Method for stacking chip particles on wafer and semiconductor device

Abstract

The invention provides a method for stacking core particles on a wafer and a semiconductor device. The method comprises the following steps of: S1, arranging the wafer in a laminating device in a manner that one surface with a circuit pattern structure faces downwards; s2, absorbing the upper surface of a wafer from top to bottom by using a wafer absorbing device, and placing the wafer in the laminating device in a manner that one surface with a circuit pattern structure faces upwards; and S3, carrying out bonding by taking the direction from bottom to top as the bonding direction from the wafer to the wafer, and completing the stacking of the core particles on the wafer. According to the invention, particle pollution introduced by intermediate processes (such as cutting, picking, overturning and the like of a chip) in processing engineering is avoided, so that the technical problems of bonding strength reduction and bonding electrical failure are greatly avoided.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor device manufacturing, and in particular relates to a method for stacking core particles on a wafer and a semiconductor device. Background Art

[0002] One of the difficulties of Die to Wafer Hybrid Bonding is the control of contamination. Compared with the process of Wafer to Wafer Hybrid Bonding, since it involves cutting, picking up, flipping and other processes of the chip, and there are more moving operations, it is inevitable that particle contamination will be introduced. When these particles fall on the bonding interface, it will cause the strength of the bond to decrease and the electrical failure of the bond. Summary of the invention

[0003] To this end, the present invention provides a method for stacking core particles on a wafer, the method comprising: step S1, placing the wafer with a side having a circuit pattern structure facing downward in a bonding device; step S2, using a wafer suction device to absorb the upper surface of the wafer from top to bottom, and placing the wafer with a side having a circuit pattern structure facing upward in the bonding device; step S3, bonding with the direction from bottom to top as the wafer to wafer bonding direction, to complete the stacking of core particles on the wafer.

[0004] Furthermore, preferably, in the chip stacking method on a wafer of the present invention, in the step S3, it further comprises: using a heating functional component of the bonding device to pre-heat the chip and the wafer bonded to the chip before bonding.

[0005] In addition, preferably, in the chip stacking method on a wafer of the present invention, in the step S3, it further includes: while aligning and bonding the chip with the wafer, heating the back side of the chip.

[0006] In addition, preferably, in the method for stacking core particles on a wafer of the present invention, in the step S3, it also includes: using a suction cup adsorbed on the back of the wafer to heat the wafer under conditions of 80°C-150°C for 10s-180s to achieve heating of only the chip bonding position.

[0007] In addition, preferably, in the method for stacking core particles on a wafer of the present invention, in the step S3, it further includes: depositing a heat absorbing material of a specific wavelength band of 50A-10000A on the bonding interface.

[0008] Furthermore, preferably, in the chip stacking method on a wafer of the present invention, the heat absorbing material in a specific wavelength band is TiN or amorphous silicon.

[0009] Furthermore, preferably, in the method for stacking core particles on a wafer of the present invention, after bonding is completed, the positions of the wafer and the chip are flipped 180°, and high-temperature annealing is performed at 300°C-500°C for 30min-180min.

[0010] In addition, the present invention also provides a semiconductor device, which is generated by obtaining core particles on a wafer using any of the above-mentioned core particle stacking methods on a wafer, and completing wafer-level stacking through a hybrid bonding process.

[0011] By utilizing the present invention, particle contamination introduced by intermediate processes in the processing engineering (such as chip cutting, picking up, flipping, etc.) is avoided, thereby largely avoiding technical problems that may cause reduction in bonding strength and electrical failure of bonding. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a flow chart showing a die stacking method on a wafer according to one embodiment of the present invention.

[0013] Figure 2 1 is a schematic diagram showing the structure of a Bernoulli non-contact pickup device in one embodiment of the present invention.

[0014] Figure 3 is a schematic diagram showing the process flow of wafer-to-wafer hybrid bonding in one embodiment of the present invention.

[0015] Figure 4 is a schematic diagram showing a wafer-to-wafer hybrid bonding process flow in one embodiment of the present invention.

[0016] Figure 5 Schematic diagram showing a machine air flow system in one embodiment of the present invention.

[0017] Figure 6 Schematic diagram showing a heating structure in a bonding apparatus according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Other embodiments or variations obtained based on the embodiments in the present application by ordinary technicians in this field without creative work are all within the scope of protection of this application.

[0019] Figure 1 is a flow chart showing a die stacking method on a wafer according to one embodiment of the present invention.

[0020] One of the difficulties of Die to Wafer Hybrid Bonding is the control of contamination. Compared with the process of Wafer to Wafer Hybrid Bonding, since it involves the cutting, picking up, flipping and other processes of the chip, and there are more moving operations, particle contamination will inevitably be introduced. When these particles fall on the bonding interface, it will cause the strength of the bond to decrease and the electrical failure of the bond. Therefore, it is very important to control the cleanliness of the surface bonding of the chip and wafer.

[0021] At present, the cleanliness of chips and wafers during bonding is mainly controlled by the following aspects:

[0022] 1. Core cutting: Laser cutting has a great thermal effect, which can easily cause recasting of the edge of the cut chip, resulting in changes in the bonding surface morphology; mechanical cutting will produce a large number of particles and cause greater pollution; therefore, plasma etching is currently used to cut the core particles using the plasma etching process before the Fab process to minimize the particle contamination introduced during the core cutting process; recasting and particle contamination will cause bubble defects (Bubble Defect) at the bonding interface.

[0023] 2. Core particle picking: The original contact core particle picking device is upgraded to a non-contact Bernoulli picking device, thereby avoiding contamination caused by contact between the equipment and the core particles; Bernoulli non-contact picking device such as Figure 1 shown.

[0024] 3. Other aspects: including optimization of the moving parts and the environment inside the entire chamber to ensure that the movement of these mechanical structures does not introduce additional particle contamination during the bonding process; optimizing the cleaning process formula or process flow of the core particles and wafer surfaces to improve the cleanliness of the surfaces of both.

[0025] Through the above-mentioned process optimization, the cleanliness of the material surface is improved, thereby ensuring the final bonding effect.

[0026] Although the current solution optimizes the cleanliness of wafer-to-wafer hybrid bonding from several aspects, there are still several problems:

[0027] 1. During the bonding process, the wafer is at the bottom with the front side facing up. The chip picking process is with the front side facing up. Therefore, after we pick up the chip, the placement device is located on the back of the chip. After the placement device absorbs the chip, we need to flip the chip, face it down, and bond it to the wafer to complete the process of placing the chip. This step involves the flip chip bonding process in which the mechanical structure of the chip and the chip clamping is flipped. Due to the mechanical rotation, particle contamination will inevitably occur, which has a great impact on the bonding interface of the chip and wafer and the cleanliness of the cavity.

[0028] 2. The bonding efficiency of the wafer-to-wafer hybrid bonding machine is low, and it usually takes tens of minutes to complete the bonding of a wafer (wafer in wafer-to-wafer hybrid bonding). In this process, there will be a robotic arm constantly picking up the core particles to the wafer for bonding. Such moving parts will generate a large number of particles. In addition, the effect of gravity will cause many particles to fall on the wafer, thereby contaminating the wafer; what is more serious is that there are corresponding gaps between the bonded wafers, and there will be circuit designs in these gaps to prepare for subsequent electrical tests. During the entire bonding process, the circuit at this position will always be exposed to the outside, and there will always be a risk of particles falling and being contaminated; in addition, the area of ​​the wafer is very large, and the probability of contamination caused by falling particles is also very high.

[0029] Figure 2 1 is a schematic diagram showing the structure of a Bernoulli non-contact pickup device in one embodiment of the present invention.

[0030] With regard to wafers (also known as bare chips, dies), the current technical solutions mainly ensure the cleanliness of the wafers by controlling the number of particles on the wafers and the particles introduced by the machine flipping device.

[0031] For wafers, the current focus is on ensuring the cleanliness of the inside of the bonding chamber, thereby reducing the number of particles falling on the wafer and controlling the cleanliness of the wafer. At the same time, the exposure time of the wafer during the entire bonding process is minimized, usually by speeding up the bonding rate, etc., to ensure the cleanliness of the wafer.

[0032] However, the above methods can only improve the pollution problem, but cannot fundamentally solve the problem.

[0033] In the present invention, the wafer-to-wafer hybrid bonding machine is divided into two parts, one part is the wafer-related equipment, and the other part is the wafer-related equipment.

[0034] The wafer equipment mainly consists of two parts: picking and placing. The picking device is responsible for picking up the wafer from the dicing tape; the placing device absorbs the wafer from the back, flips it together with the wafer, and bonds it to the wafer. In this way, the wafer is bonded, and then the above steps are repeated to bond the wafer to the wafer one by one; the wafer equipment mainly consists of a suction cup, which carries the wafer to complete the hybrid bonding of wafer to wafer. The machine position is that the wafer is located at the top with the front facing down, and the wafer is located at the bottom with the front facing up. The schematic diagram is as follows Figure 3 shown.

[0035] The present invention swaps the relative positions of the conventional chip and wafer-related equipment, with the chip located at the bottom with the front facing upward and the wafer located at the top with the front facing downward. After the chip is picked up, the placement device directly picks up the chip from the back without the need for a flipping process, and the chip is bonded face to face with the upper wafer from bottom to top. Figure 4 shown.

[0036] The advantages of the present invention are described from the following two aspects: flipping of the core particles in the flip chip and the particles falling due to gravity causing contamination:

[0037] 1. Flip chip flipping core particles: obtained by chip cutting, the core particle cutting process is to fix a whole wafer on the cutting tape, and after the cutting is completed, the film expansion process is carried out to obtain separate core particles, at this time the front circuit structure of the core particles is facing upward. Therefore, the original wafer position is in a position where the lower circuit structure is upward, which inevitably involves the process of flipping the core particles. In the flipping process, the mechanical structure involves more movement, and more particles will be generated, which will cause greater pollution to the chip, wafer structure, and cavity environment. This invention places the wafer with the upper circuit structure downward, fundamentally avoiding the flipping process, thereby reducing the pollution caused by this process.

[0038] 2. Particles fall due to gravity: Wafer-to-wafer hybrid bonding requires wafer-to-wafer alignment and bonding process. The process time for aligning and bonding each wafer is relatively long. In this way, it usually takes tens of minutes or even hours to complete the bonding of all the wafers on each wafer. In this process, since the front of the wafer is facing up, the probability of particles falling is relatively high, which will cause contamination to the surface of the wafer and affect the bonding effect. At the same time, there is a gap between the wafers bonded to the wafer, and this part also has a circuit design. This part of the circuit is exposed in the cavity from the beginning to the end of the bonding, and the static time is relatively long. The possibility of contamination caused by particle falling is greater. At the same time, since the depth and width of the gap here are relatively large, particle contamination is difficult to clean, and this part of the circuit is prone to abnormalities in the future. In addition, in the original bonding process, the wafer device needs to repeatedly align and bond mechanical movements such as above the wafer for wafer-to-wafer bonding. In this process, a large amount of particle pollution will be generated, and under the action of gravity, it is easier to cause contamination to the wafer surface. In this invention, since the wafer is located at the top with the front side facing downward, particles will not fall on the wafer due to gravity, thereby minimizing the contamination of the wafer by particles.

[0039] The method of reducing pollution of the present invention is to build an air flow system from top to bottom, with air blowing from the top and returning from the bottom, so as to better ensure that particles do not fall on the wafer. At the same time, the chip is shielded by the wafer and is also not contaminated by particles affected by gravity. The schematic diagram of the air flow system is shown in FIG. Figure 5 shown.

[0040] The present invention is not limited to the application in the process flow of chip-to-wafer hybrid bonding, but can also be applied to other chip-to-wafer, substrate and other bonding equipment optimization solutions to reduce the contamination caused by chip flipping and particles falling due to gravity.

[0041] In addition, after the chip and the wafer are aligned, they are only pre-bonded, and there are not enough covalent bonds formed between the dielectric film layers at the bonding interface, so the bonding strength is very weak. At this time, the back of the chip has no support, and our bonding device will leave after bonding to carry out the alignment and bonding process of the next chip. The chip that has just been bonded will be affected by gravity and will be displaced or even fall. Therefore, we can make the following improvements:

[0042] We can integrate a heating function on the bonding device. While aligning and bonding, we also heat the back of the chip. This can increase some hanging bonds and enhance the bonding strength to prevent displacement and falling.

[0043] We can also heat the wafer through the suction cup behind the wafer. However, we need to precisely control the heating area and heat only the chip bonding position on the wafer each time. If the entire wafer is heated each time, the wafer will be heated repeatedly, which consumes a lot of the wafer's thermal budget and affects the chip's performance. We can design the wafer's electrostatic suction cup (E Chuck) accordingly, such as equipping different areas with multiple heating coils to achieve zoned heating, as shown in the schematic diagram. Figure 6 As shown in (a) in .

[0044] We can also deposit a certain thickness of material that has a good heat absorption effect in a certain band on the bonding interface. For example, we can deposit a certain thickness of TiN. TiN absorbs light in the green band significantly and generates heat, while other common semiconductor materials do not absorb light in this band and therefore do not absorb heat. We use green light when heating chips or wafers. Therefore, we can deposit a certain thickness of film layer, and then heat it by irradiating light of a specific wavelength, so as to achieve precise heating of the bonding interface. The special film layer is as close to the bonding interface as possible, but in order to ensure the bonding effect, the introduced special film layer cannot be the bonding interface. It only plays a heating role. The schematic diagram is as follows Figure 6 As shown in (b) in .

[0045] Because the bonding force mainly depends on the part of the dielectric layer of the bonding interface (because the area occupied by Cu is less than 10%, and it also mainly plays the role of electrical connection), the annealing after bonding has two functions: the -OH active group generated by the water coated on the surface generates Si-OH with the dangling bond of the bonding interface, and the temperature rise promotes the hydrophilic bonding reaction of Si-OH+HO-Si→Si-O-Si+H2O during the bonding, thereby enhancing the bonding strength. The temperature here can be 80℃-150℃; the metal Cu grains expand due to heat, and the copper on both sides contact each other, thus forming electrical connection. Here, the internal stress of the metal is also released in advance, so that the metal expands in advance. When the subsequent thermal process is carried out, the copper continues to expand, causing damage to the hole. The subsequent process temperature varies depending on the process, with a maximum of 350℃-450℃. Therefore, to meet this requirement, the temperature needs to be between 350℃-450℃, and it cannot be lower than the subsequent process temperature to prevent the subsequent temperature from being higher, and the copper continues to expand, causing damage to the structure. Therefore, the purpose of this step is to enhance the bonding strength, not for electrical connectivity, so the temperature can be controlled at 80℃-150℃, or even lower, as long as the core particles do not move or fall off. After each chip is bonded to the wafer, a unified annealing step will be performed, which can not only achieve the expansion of the copper grains to achieve electrical connectivity, but also further enhance the bonding strength.

[0046] In summary, the process characteristics of the present invention are as follows:

[0047] (1) The overall process flow is: repeatedly heat at low temperature (80℃-150℃) to complete the bonding of each die, and after all dies are bonded, perform a high-temperature unified annealing step to complete the entire process.

[0048] (2) In each step of low-temperature heating, only the area of ​​the wafer that is bonded to the die is heated, because the dies on the wafer are isolated from each other by Scribe Lanes, so the heat will not be transmitted to other locations on the wafer.

[0049] (3) During the low-temperature bonding process, the bonding device is not removed and a certain pressure is applied to the chip to keep the position of the chip and the wafer unchanged.

[0050] (4) After the final annealing, the chip and wafer are turned over, with the wafer at the bottom and the chip at the top. This makes the relative position more stable.

[0051] Therefore, in the present invention, the relative positions of the original chip and the wafer are swapped, the wafer is located at the top, and the front circuit structure is downward; the chip is located at the bottom, and the front circuit structure is upward, and the placement device realizes the face-to-face bonding of the chip to the wafer from bottom to top, which has the following advantages:

[0052] 1. After the bonding core is picked up in this way, there is no need to flip it. It can be directly bonded face to face with the wafer from bottom to top, avoiding particle contamination caused by flipping the core.

[0053] 2. In this method, the wafer is located on the upper front with the circuit structure facing downward. Particles will not fall on the wafer due to gravity (especially in the gap between the bonded wafers, which is difficult to remove) and cause particle contamination, as in the existing machine structure.

[0054] In summary, this solution can be applied to chip-to-wafer hybrid bonding and other chip-to-panel packaging processes, eliminating the particle contamination introduced by the flip-chip process, and avoiding the contamination caused by particles falling on wafers and panels due to gravity, greatly improving the cleanliness of the overall process to meet the final packaging effect.

[0055] Beneficial effects of the present invention:

[0056] 1. The overall orientation of the bond,

[0057] It should be noted that in this article, the relationship techniques such as the first and second, etc., are that the circuit structure of the wafer is upward and the position is below; the circuit structure of the wafer is downward and the position is above;

[0058] 2. The wafer suction device sucks the wafer above the wafer, and then the bonding device is located on the back of the wafer, below the wafer;

[0059] 3. The wafer-to-wafer bonding direction is from bottom to top;

[0060] 4. The entire picking and bonding process does not involve wafer flipping;

[0061] 5. During the bonding process, the chip and the wafer bonded to the chip need to be heated in advance to provide a certain bonding strength. At this time, the bonding device also provides a certain pressure. After the low-temperature heating is completed, the bonding device will be withdrawn. To heat the wafer, only the Die part of the wafer that is bonded to the chip needs to be heated. This is low-temperature heating (80℃-150℃). Heating can be done by direct contact heating or by non-contact heating by depositing a special film layer and irradiating light of a special wavelength. After each chip is bonded to the wafer, we flip the position of the wafer and chip over, with the chip on top and the wafer on the bottom, and perform uniform annealing. The temperature is high-temperature annealing at 350℃-450℃.

[0062] The term "comprises" or "comprising" is used only to distinguish one entity or operation from another entity or operation, and does not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0063] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0064] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0065] The above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A method for stacking chips on a wafer, characterized in that: include: Step S1, placing the wafer in a bonding device with the side having the circuit pattern structure facing downward; Step S2, using a wafer suction device to suck the upper surface of the wafer from top to bottom, and placing the wafer into the bonding device with the side having the circuit pattern structure facing upward; Step S3 , bonding is performed in a direction from bottom to top as the wafer-to-wafer bonding direction, thereby completing the stacking of the core particles on the wafer.

2. The method for stacking chips on a wafer according to claim 1, characterized in that: In the step S3, it also includes: using the heating function component of the bonding device to pre-heat the chip and the wafer bonded to the chip before bonding.

3. The method for stacking chips on a wafer according to claim 2, characterized in that: The step S3 further includes: heating the back side of the chip while aligning and bonding the chip to the wafer.

4. The method for stacking chips on a wafer according to claim 2, characterized in that: In the step S3, it also includes: using a suction cup adsorbed on the back of the wafer to heat the wafer under the conditions of 80° C.-150° C. for 10s-180s, so as to heat only the chip bonding position.

5. The method for stacking chips on a wafer according to claim 2, characterized in that: In the step S3, it also includes: depositing a heat absorbing material of a specific wavelength band of 50A-10000A on the bonding interface.

6. The method for stacking chips on a wafer according to claim 5, characterized in that: The specific band heat absorption material is TiN or amorphous silicon.

7. The method for stacking chips on a wafer according to claim 2, characterized in that: After the bonding is completed, the positions of the wafer and the chip are flipped 180°, and high-temperature annealing is performed at 300° C.-500° C. for 30 min-180 min.

8. A semiconductor device, characterized in that: The semiconductor device is produced by obtaining the chip-on-wafer stacking method according to any one of claims 1 to 7 and completing wafer-level stacking through a hybrid bonding process.

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