Diffusion barrier layer for copper interconnection, copper interconnection structure and preparation method thereof
By using the tantalum-manganese alloy layer and its oxide film layer as diffusion barrier layers in the copper interconnect structure, the problems of high Cu line resistivity and electromigration failure are solved, and lower resistivity and higher anti-electromigration performance are achieved.
Patent Information
- Application Number
- CN202311212204.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-19
- Publication Date
- 2025-03-21
AI Technical Summary
In the prior art, the diffusion barrier layer for copper interconnection causes a large resistivity of the Cu line and causes electromigration failure.
The tantalum-manganese alloy layer and its oxide film layer are used as diffusion barrier layers to form a dense manganese oxide film layer through oxidation reaction, thinning the diffusion barrier layer, reducing the resistivity of Cu lines and blocking the diffusion of Cu atoms.
The thickness of the diffusion barrier layer and the resistivity of the Cu line are effectively reduced, the diffusion of Cu atoms is blocked, the electromigration of the Cu line is suppressed, and the quality of the Cu line is improved.
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Figure CN119673891A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor back-end process, and in particular relates to a diffusion barrier layer for copper interconnection, a copper interconnection structure and a preparation method thereof. Background Art
[0002] With the development of ultra-large-scale integrated circuits, low-resistivity Cu has replaced Al as the mainstream interconnect material. Although Cu wire is the most promising interconnect wire for integrated circuits, especially large-scale integrated circuits, it also has its own shortcomings: first, it can react with the semiconductor substrate (such as silicon) or the low-k dielectric layer at a temperature below 200°C to generate a high-resistance copper-silicon phase Cu3Si, which will increase the resistance of the entire interconnect system and destroy the interconnect system, eventually leading to device failure. In addition, Cu can also quickly diffuse into the semiconductor substrate (diffusion coefficient D Cu =4.7×10 -3 cm 2 ·s -1 ) causes deep well defects and reduces the minority carrier lifetime; secondly, the bonding performance between Cu and the dielectric layer is relatively poor, and the film layer and the substrate are easily peeled off. The above shortcomings will obviously limit the application of Cu interconnects in ultra-large-scale integrated circuits. The common solution is to form a diffusion barrier layer before electroplating Cu to prevent the diffusion of Cu atoms, which can also enhance the bonding strength between Cu and the dielectric layer.
[0003] As the Cu interconnect feature size is reduced to tens of nanometers, the thickness of the diffusion barrier layer also needs to be further reduced, which puts more stringent requirements on the preparation process and performance of the diffusion barrier layer. At present, the Ta / TaN double-layer structure is often used to prepare the diffusion barrier layer, but its thickness is relatively thick, occupying a large part of the volume of the Cu line, thereby increasing the resistivity of the Cu line; in addition, the diffusion barrier layer is generally prepared by physical vapor deposition (PVD), and the PVD technology has poor step coverage characteristics in smaller grooves, causing Cu atoms to diffuse in places with poor coverage, causing electromigration (EM) failure, and it is not easy to form a thin diffusion barrier layer, such as a material layer less than 1nm, and it is not easy to reduce the resistivity of the Cu line. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a diffusion barrier layer for copper interconnection, a copper interconnection structure and a preparation method thereof, so as to solve the problems in the prior art that the diffusion barrier layer for copper interconnection causes a large resistivity of the Cu line and causes electromigration failure.
[0005] To achieve the above-mentioned object and other related objects, the present invention provides a diffusion barrier layer for copper interconnection, the diffusion barrier layer comprising:
[0006] an insulating layer formed on the semiconductor substrate;
[0007] A groove extending inwardly from a surface of the insulating layer and formed in the insulating layer;
[0008] A tantalum-manganese alloy layer is formed on the inner side wall and the bottom wall of the groove;
[0009] A manganese oxide film layer covers the surface of the tantalum-manganese alloy layer and completely covers the inner surface of the groove.
[0010] Optionally, the total thickness of the tantalum-manganese alloy layer and the manganese oxide film layer is 5 nm to 10 nm, including endpoint values.
[0011] Furthermore, the manganese oxide film layer has a thickness of 0.5 nm to 5 nm, including end points.
[0012] Furthermore, the manganese oxide film layer has a thickness of 0.5 nm to 1.5 nm, including end points.
[0013] Optionally, the atomic ratio of total manganese atoms to tantalum atoms in the tantalum-manganese alloy layer and the manganese oxide film layer is 0.5% to 5%, including endpoint values.
[0014] The present invention also provides a copper interconnect structure, comprising:
[0015] A diffusion barrier as described in any one of the above;
[0016] A copper seed layer is formed on the surface of the diffusion barrier layer;
[0017] A copper electroplating layer is formed on the copper seed layer and fills the groove to form a copper interconnection structure.
[0018] The present invention also provides a method for preparing a diffusion barrier layer for copper interconnect as described in any one of the above, the preparation method comprising:
[0019] Providing a semiconductor substrate having an insulating layer formed on the surface, wherein a groove is formed extending inwardly from the surface of the insulating layer;
[0020] Depositing a tantalum-manganese alloy layer on the inner sidewall and bottom wall of the groove;
[0021] The obtained structure is placed in an oxygen-containing gas atmosphere, and the tantalum-manganese alloy layer is subjected to an oxidation reaction, so that manganese atoms are combined with oxygen atoms to form a manganese oxide film layer, so that the manganese oxide film layer covers the surface of the tantalum-manganese alloy layer and completely covers the inner surface of the groove.
[0022] Optionally, the tantalum-manganese alloy layer is deposited by a PVD process, and the tantalum-manganese alloy layer is naturally cooled by a cooling chamber in the PVD equipment to cause an oxidation reaction of the tantalum-manganese alloy layer to form the manganese oxide film layer; or the tantalum-manganese alloy layer is deposited by a CVD process.
[0023] Optionally, the manganese oxide film layer is formed by a rapid annealing process or a furnace tube process.
[0024] Furthermore, in the rapid annealing process or the furnace tube process, the temperature of the oxidation reaction is 100° C. to 350° C., and the time is 2 min to 5 min, including endpoint values.
[0025] The present invention also provides a method for preparing a copper interconnect structure, the method comprising:
[0026] Providing a diffusion barrier layer for copper interconnect as described in any one of the above;
[0027] forming the copper seed layer on the surface of the diffusion barrier layer;
[0028] The copper electroplating layer is formed on the copper seed layer by electroplating, and the copper electroplating layer is made to fill the groove to form a copper interconnection structure.
[0029] As described above, the diffusion barrier layer for copper interconnection, the copper interconnection structure and the preparation method thereof of the present invention are obtained by subjecting the tantalum-manganese alloy layer and subjecting it to oxidation reaction to obtain a manganese oxide film layer as a diffusion barrier layer. Firstly, the tantalum-manganese alloy layer is a single-layer structure, and the thickness of the manganese oxide film layer obtained by the oxidation reaction is very thin, so the thickness of the diffusion barrier layer is effectively reduced, and the resistivity of the subsequently formed Cu line is reduced; secondly, the manganese oxide film layer obtained by the oxidation reaction is dense, uniform in thickness and completely covers the inner surface of the groove, which can effectively block the diffusion of Cu atoms in the subsequent Cu line and effectively inhibit the electromigration of the Cu line; furthermore, a manganese oxide film layer with high resistance to electromigration is formed, so when the Cu line is subsequently formed, the seed layer can always select the Cu seed layer, avoiding the problem of reduced efficiency caused by the need to replace different target materials during PVD seed layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figures 1 to 6 It is a schematic diagram of the cross-sectional structure after each step in a method for preparing a copper interconnect structure according to an example of the present invention is completed.
[0031] Description of Reference Numerals
[0032] 10 Semiconductor substrate
[0033] 11 Insulation layer
[0034] 12 Grooves
[0035] 13 Tantalum-manganese alloy layer
[0036] 14 Manganese oxide film
[0037] 15 Copper seed layer
[0038] 16 Copper plating layer DETAILED DESCRIPTION
[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0040] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0041] Embodiment 1
[0042] High entropy alloys are used as diffusion barriers in the process of preparing copper interconnect structures. This is because in the existing copper interconnect technology, some single refractory metals, such as Ti, Zr, Mo and Ta, and nitrides, such as TiN and TaN, are chemically inert with copper and are often used as diffusion barriers. However, since such materials have a polycrystalline structure, more grain boundaries provide diffusion channels for copper atoms, reducing the barrier effect. While using a laminated structure, such as a Ta / TaN structure, although the grain boundaries can be extended, the grain boundaries or cross-sections are detuned, making it difficult for copper atoms to diffuse, the diffusion barrier layer of the laminated structure is usually thicker than a single-layer barrier layer, resulting in an increase in the resistivity of the Cu line. Even if the PVD method is used, on the one hand, the step coverage characteristics in smaller grooves are poor, causing Cu atoms to diffuse in places with poor coverage, causing electromigration (EM) failure, and PVD is not easy to form a thin diffusion barrier layer, such as a material layer less than 1nm, and it is not easy to reduce the resistivity of the Cu line.
[0043] Based on the above situation, this embodiment provides a diffusion barrier layer for copper interconnection, such as Figures 1 to 3 As shown, the diffusion barrier layer comprises:
[0044] An insulating layer 11 formed on the semiconductor substrate 10;
[0045] A groove 12 is formed in the insulating layer 11 and extends inward from the surface of the insulating layer 11;
[0046] like Figure 2 As shown, the tantalum-manganese alloy layer 13 is formed on the inner side wall and the bottom wall of the groove 12;
[0047] like Figure 3 As shown, the manganese oxide film layer 14 covers the surface of the tantalum-manganese alloy layer 13 and completely covers the inner surface of the groove 12; its preparation method can be formed by oxidizing the tantalum-manganese alloy layer 13 to combine manganese atoms with oxygen atoms.
[0048] As is known, the number of grooves 12 in the insulating layer 11 can be set according to actual needs, and generally there are more than one grooves 12. In the diagram of this embodiment, only one groove 12 is shown for ease of understanding, but this number cannot be used as a limitation on the scope of protection of the present invention. In addition, after the groove 12 is subsequently filled with metal, it mainly serves as an electrical interconnection to electrically connect the electronic device on its upper side with the electronic device in the semiconductor substrate 10 on its lower side, so generally the groove 12 is a through groove that passes through the insulating layer 11. Furthermore, the semiconductor substrate 10 here refers to a semiconductor substrate 10 that needs to be metal interconnected at any stage in the semiconductor process, and some other device structures may be formed therein, which is determined specifically according to the process stage it is in and the different semiconductor structures, and is not specifically limited here.
[0049] The semiconductor substrate 10 is made of conventional semiconductor materials that can be used to prepare semiconductor devices, such as commonly used silicon materials, germanium materials, sapphire materials or semiconductor-on-insulator materials, etc. The material of the insulating layer 11 is selected from conventional insulating materials. Generally, the material used by the semiconductor substrate 10 can be referred to when selecting. For example, if the material of the semiconductor substrate 10 is silicon, the material of the insulating layer 11 is selected from silicon oxide, but it is not limited thereto. The insulating layer 11 can also be selected from other dielectric materials.
[0050] Here, the manganese oxide film layer 14 covers the surface of the tantalum-manganese alloy layer 13 and completely covers the inner surface of the groove 12. It means that when the tantalum-manganese alloy layer 13 has an uneven thickness on the inner side wall and bottom wall of the groove 12 (that is, it is thick in some places and thin in some places) due to process limitations, the manganese oxide film layer 14 not only covers the surface of the thicker tantalum-manganese alloy layer 13 but also covers the surface of the thinner tantalum-manganese alloy layer 13, so that the manganese oxide film layer 14 completely covers the inner surface of the groove 12. This structural property of the manganese oxide film layer 14 is also based on the fact that it is obtained by causing the tantalum-manganese alloy layer 13 to undergo an oxidation reaction with oxygen atoms.
[0051] The diffusion barrier layer for copper interconnection of the present embodiment is obtained by subjecting the tantalum-manganese alloy layer 13 to an oxidation reaction to obtain a manganese oxide film layer as a diffusion barrier layer. Firstly, the tantalum-manganese alloy layer is a single-layer structure, and the thickness of the manganese oxide film layer obtained by the oxidation reaction is very thin, so the thickness of the diffusion barrier layer is effectively reduced, and the resistivity of the subsequently formed Cu line is reduced; secondly, the manganese oxide film layer obtained by the oxidation reaction is dense, uniform in thickness and completely covers the inner surface of the groove, which can effectively block the diffusion of Cu atoms in the subsequent Cu line and effectively inhibit the electromigration of the Cu line; furthermore, a manganese oxide film layer with high resistance to electromigration is formed, so when the Cu line is subsequently formed, the seed layer can always select the Cu seed layer, avoiding the problem of reduced efficiency caused by the need to replace different target materials during the PVD seed layer.
[0052] As a preferred example, the total thickness of the tantalum-manganese alloy layer 13 and the manganese oxide film layer 14 is 5nm to 10nm, including endpoint values, such as 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm. On this basis, the thickness of the manganese oxide film layer 14 is 0.5nm to 5nm; specifically, it can include 0.5nm, 1nm, 2nm, 3nm, 4nm, and 5nm; more preferably, the thickness of the manganese oxide film layer 14 is 0.5nm to 1.5nm, including endpoint values, such as 0.5nm, 0.7nm, 0.9nm, 1.1nm, 1.3nm, and 1.5nm.
[0053] As another preferred example, the atomic ratio of total manganese atoms to tantalum atoms in the tantalum-manganese alloy layer 13 and the manganese oxide film layer 14 is 0.5% to 5%, including endpoint values, such as 0.5%, 1.0%, 1.5%, 2.0%, 2.5%, 3.0%, 3.5%, 4.0%, 4.5%, and 5.0%.
[0054] Embodiment 2
[0055] This embodiment provides a method for preparing a diffusion barrier layer for copper interconnection, which is used to prepare the diffusion barrier layer for copper interconnection described in the first embodiment, but is not limited thereto. Other preparation methods can also be used to prepare the diffusion barrier layer for copper interconnection of the first embodiment, but relatively speaking, the preparation method of this embodiment is a more preferred preparation scheme. The preparation method includes:
[0056] like Figure 1 As shown, S1, providing a semiconductor substrate 10 with an insulating layer 11 formed on the surface, and a groove 12 extending inwardly from the surface of the insulating layer 11;
[0057] like Figure 2 As shown, S2, depositing a tantalum-manganese alloy layer 13 on the inner side wall and the bottom wall of the groove 12;
[0058] like Figure 3As shown, S3, placing the above-obtained structure in an oxygen-containing gas atmosphere, performing an oxidation reaction on the tantalum-manganese alloy layer 13, so that manganese atoms are combined with oxygen atoms to form a manganese oxide film layer 14, so that the manganese oxide film layer 14 covers the surface of the tantalum-manganese alloy layer 13 and completely covers the inner surface of the groove 12.
[0059] As described in the first embodiment, the number of grooves 12 in the insulating layer 11 can be set according to actual needs, and is generally more than one groove 12. In the diagram of this embodiment, only one groove 12 is shown for ease of understanding, but this number cannot be used as a limitation on the scope of protection of the present invention. In addition, after the groove 12 is subsequently filled with copper metal, it mainly serves as an electrical interconnection to electrically connect the electronic device on its upper side with the electronic device in the semiconductor substrate 10 on its lower side, so the groove 12 is generally a through groove that passes through the insulating layer 11. Furthermore, the semiconductor substrate 10 here refers to a semiconductor substrate 10 that needs to be metal interconnected at any stage in the semiconductor process, and some other device structures may be formed therein, which is determined specifically according to the process stage in which it is located and the different semiconductor structures, and is not specifically limited here.
[0060] The semiconductor substrate 10 is made of conventional semiconductor materials that can be used to prepare semiconductor devices, such as commonly used silicon materials, germanium materials, sapphire materials or semiconductor-on-insulator materials, etc. The material of the insulating layer 11 is selected from conventional insulating materials. Generally, the material used by the semiconductor substrate 10 can be referred to when selecting. For example, if the material of the semiconductor substrate 10 is silicon, the material of the insulating layer 11 is selected from silicon oxide, but it is not limited thereto. The insulating layer 11 can also be selected from other low-k dielectric materials.
[0061] As an example, the tantalum-manganese alloy layer 13 can be prepared by deposition using a PVD process or a CVD process.
[0062] When the tantalum-manganese alloy layer 13 is deposited and prepared by a PVD process, the manganese oxide film layer 14 can be naturally cooled by a cooling chamber in the PVD equipment to allow the tantalum-manganese alloy layer 13 to undergo an oxidation reaction to form the manganese oxide film layer 14. Natural cooling here means that when the tantalum-manganese alloy layer 13 is prepared by PVD, although there is no external heating, heat will be generated during the deposition process, so the heat is slowly cooled in the cooling chamber to promote the oxidation reaction to obtain the manganese oxide film layer 14.
[0063] In addition to the above method, the manganese oxide film layer 14 can also be formed by a rapid annealing (RTA) process or a furnace tube process. Preferably, when these two processes are used, the temperature of the oxidation reaction is selected to be between 100°C and 350°C, such as 100°C, 150°C, 200°C, 250°C or 300°C, etc., and the time is between 2min and 5min, such as 2min, 3min, 4min or 5min, etc. During the oxidation reaction, the gas atmosphere includes oxygen and a protective gas to ensure the safety of the reaction process. The protective gas generally selects an inert gas (such as argon), nitrogen or other commonly used protective gases, and the type and content of the protective gas are selected according to actual needs.
[0064] As a preferred example, the total thickness of the tantalum-manganese alloy layer 13 and the manganese oxide film layer 14 is 5nm to 10nm, including endpoint values, such as 5nm, 6nm, 7nm, 8nm, 9nm, and 10nm. On this basis, the thickness of the manganese oxide film layer 14 is 0.5nm to 5nm; specifically, it can include 0.5nm, 1nm, 2nm, 3nm, 4nm, and 5nm; more preferably, the thickness of the manganese oxide film layer 14 is 0.5nm to 1.5nm, including endpoint values, such as 0.5nm, 0.7nm, 0.9nm, 1.1nm, 1.3nm, and 1.5nm.
[0065] As another preferred example, the atomic ratio of total manganese atoms to tantalum atoms in the tantalum-manganese alloy layer 13 and the manganese oxide film layer 14 is 0.5% to 5%, including endpoint values, such as 0.5%, 1.0%, 1.5%, 2.0%, 2.5%, 3.0%, 3.5%, 4.0%, 4.5%, and 5.0%.
[0066] Embodiment 3
[0067] This embodiment provides a copper interconnect structure, which is based on the copper interconnect diffusion barrier layer of the first embodiment. The beneficial effects that can be achieved can be found in the first embodiment, and will not be described in detail in this embodiment. Figure 6 As shown, the copper interconnect structure includes:
[0068] The diffusion barrier layer described in the first embodiment and the variation of the diffusion barrier layer described in the first embodiment mainly include: an insulating layer 11 formed on a semiconductor substrate 10; a groove 12 extending inwardly from the surface of the insulating layer 11 and formed in the insulating layer 11; Figure 2 As shown, the tantalum-manganese alloy layer 13 is formed on the inner side wall and the bottom wall of the groove 12; Figure 3As shown, the manganese oxide film layer 14 covers the surface of the tantalum-manganese alloy layer 13 and completely covers the inner surface of the groove 12, and is formed by oxidizing the tantalum-manganese alloy layer 13 so that manganese atoms are combined with oxygen atoms;
[0069] A copper seed layer 15 is formed on the surface of the diffusion barrier layer;
[0070] A copper electroplating layer 16 is formed on the copper seed layer 15 and fills the groove 12 to form a copper interconnection structure.
[0071] The copper seed layer 15 provides a good growth layer for the electroplating of the copper electroplating layer 16, so that the electroplating process can be carried out evenly on the surface of the groove. The thickness of the copper seed layer 15 is generally selected according to specific needs and is not excessively limited here.
[0072] Embodiment 4
[0073] This embodiment provides a method for preparing a copper interconnect structure, which is used to prepare the copper interconnect structure described in the third embodiment, but is not limited thereto. Other preparation methods can also be used to prepare the copper interconnect structure of the third embodiment, but relatively speaking, the preparation method of this embodiment is a more preferred preparation scheme. The preparation method includes:
[0074] S1. providing a diffusion barrier layer for copper interconnect as described in Example 1;
[0075] S2, such as Figure 4 As shown, a copper seed layer 15 is formed on the surface of the diffusion barrier layer;
[0076] S3, such as Figure 6 As shown, the copper electroplating layer 16 is formed on the copper seed layer 15 by electroplating, and the copper electroplating layer 16 fills the groove 12 to form a copper interconnection structure.
[0077] As a preferred example, the method for preparing the diffusion barrier layer for copper interconnect in step S1 is preferably prepared by adopting the method for preparing the diffusion barrier layer for copper interconnect in embodiment 2.
[0078] The copper seed layer 15 is preferably prepared by a PVD process, and specific process parameters are actually adjusted according to parameters known in the art.
[0079] like Figure 5 As shown in FIG. 1 , based on the existing deposition and electroplating processes, the entire surface of the substrate is generally covered. Therefore, after the copper electroplating layer 16 is formed by electroplating, the material layer outside the groove 12 and on the surface of the insulating layer 11 needs to be removed by grinding using a CMP process. It is even possible that the insulating layer 11 and the corresponding grooves need to be ground to a preset thickness according to actual needs so that the copper interconnect structure reaches a preset height, thereby obtaining the following: Figure 6The copper interconnect structure shown.
[0080] In summary, the present invention provides a diffusion barrier layer for copper interconnection, a copper interconnection structure and a preparation method thereof, wherein a tantalum-manganese alloy layer is subjected to an oxidation reaction to obtain a manganese oxide film layer as a diffusion barrier layer. Firstly, the tantalum-manganese alloy layer is a single-layer structure, and the thickness of the manganese oxide film layer obtained by the oxidation reaction is very thin, so the thickness of the diffusion barrier layer is effectively reduced, and the resistivity of the subsequently formed Cu line is reduced; secondly, the manganese oxide film layer obtained by the oxidation reaction is dense, uniform in thickness and completely covers the inner surface of the groove, which can effectively block the diffusion of Cu atoms in the subsequent Cu line and effectively inhibit the electromigration of the Cu line; furthermore, a manganese oxide film layer with high electromigration resistance is formed, and when the Cu line is subsequently formed, the seed layer can always select the Cu seed layer, avoiding the problem of reduced efficiency caused by the need to replace different target materials during the PVD seed layer. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0081] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A diffusion barrier layer for copper interconnect, characterized in that: The diffusion barrier layer comprises: an insulating layer formed on the semiconductor substrate; A groove extending inwardly from a surface of the insulating layer and formed in the insulating layer; A tantalum-manganese alloy layer is formed on the inner side wall and the bottom wall of the groove; A manganese oxide film layer covers the surface of the tantalum-manganese alloy layer and completely covers the inner surface of the groove.
2. The diffusion barrier layer for copper interconnect according to claim 1, characterized in that: The total thickness of the tantalum-manganese alloy layer and the manganese oxide film layer is 5 nm to 10 nm, including the end value.
3. The diffusion barrier layer for copper interconnect according to claim 2, characterized in that: The thickness of the manganese oxide film layer is 0.5 nm to 5 nm, including the end value.
4. The diffusion barrier layer for copper interconnection according to claim 3, characterized in that: The thickness of the manganese oxide film layer is 0.5 nm to 1.5 nm, including the end value.
5. The diffusion barrier layer for copper interconnect according to claim 1, characterized in that: The atomic ratio of total manganese atoms to tantalum atoms in the tantalum-manganese alloy layer and the manganese oxide film layer is 0.5% to 5%, including end points.
6. A copper interconnect structure, characterized in that: The copper interconnect structure comprises: The diffusion barrier layer according to any one of claims 1 to 5; A copper seed layer is formed on the surface of the diffusion barrier layer; A copper electroplating layer is formed on the copper seed layer and fills the groove to form a copper interconnection structure.
7. A method for preparing a diffusion barrier layer for copper interconnection according to any one of claims 1 to 5, characterized in that: The preparation method comprises: Providing a semiconductor substrate having an insulating layer formed on the surface, wherein a groove is formed extending inwardly from the surface of the insulating layer; Depositing a tantalum-manganese alloy layer on the inner sidewall and bottom wall of the groove; The obtained structure is placed in an oxygen-containing gas atmosphere, and the tantalum-manganese alloy layer is subjected to an oxidation reaction, so that manganese atoms are combined with oxygen atoms to form a manganese oxide film layer, so that the manganese oxide film layer covers the surface of the tantalum-manganese alloy layer and completely covers the inner surface of the groove.
8. The method for preparing a diffusion barrier layer for copper interconnect according to claim 7, characterized in that: The tantalum-manganese alloy layer is deposited by a PVD process, and a cooling chamber in the PVD device is used for natural cooling to cause the tantalum-manganese alloy layer to undergo an oxidation reaction to form the manganese oxide film layer; or the tantalum-manganese alloy layer is deposited by a CVD process.
9. The method for preparing a diffusion barrier layer for copper interconnect according to claim 7, characterized in that: The manganese oxide film layer is formed by adopting a rapid annealing process or a furnace tube process.
10. The method for preparing a diffusion barrier layer for copper interconnect according to claim 9, characterized in that: In the rapid annealing process or the furnace tube process, the temperature of the oxidation reaction is 100° C. to 350° C., and the time is 2 min to 5 min, including the endpoint values.
11. A method for preparing a copper interconnect structure as claimed in claim 6, characterized in that: The preparation method comprises: Providing a diffusion barrier layer for copper interconnection as claimed in any one of claims 1 to 5; forming the copper seed layer on the surface of the diffusion barrier layer; The copper electroplating layer is formed on the copper seed layer by electroplating, and the copper electroplating layer is made to fill the groove to form a copper interconnection structure.