Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The first electrode layer is located on the substrate, and an electrode convex part is formed on the first electrode layer; the first dielectric layer covers the top and the side wall of the electrode convex part and the first electrode layer on the side part of the electrode convex part; the second electrode layer covers the first dielectric layer, and a first opening for exposing the first dielectric layer at the top of the electrode convex part is formed in the second electrode layer; the second dielectric layer covers the second electrode layer and the first dielectric layer exposed out of the first opening; the third electrode layer covers the second dielectric layer, a second opening exposing the top of the second dielectric layer is formed in the third electrode layer, and projections of the second opening and the first opening on the substrate are located at different positions; a first through hole interconnection structure at the first opening, wherein the first electrode layer and the third electrode layer are electrically connected through the first through hole interconnection structure; and a second through hole interconnection structure at the second opening, wherein the second electrode layer is electrically connected with the second through hole interconnection structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in materials and design in the IC industry have produced successive generations of integrated circuits. Each generation has smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing integrated circuits, and similar advances in IC processing and manufacturing are required to achieve these advances. Over the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component that can be made using a manufacturing process) has decreased.

[0003] One type of capacitor is a Metal Insulator Metal (MIM) capacitor, which is commonly used in mixed-signal devices and logic devices (such as embedded memory and RF devices). MIM capacitors are commonly used to store charge in various semiconductor devices. In order to meet the performance requirements of the device, the capacitance density of MIM capacitors is also gradually increasing.

[0004] However, the equivalent capacitance density of MIM capacitors still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a first electrode layer, located on the substrate, and having an electrode protrusion formed on the first electrode layer; a first dielectric layer, covering the top and sidewalls of the electrode protrusion, and the first electrode layer covering the side of the electrode protrusion; a second electrode layer, covering the first dielectric layer, and having a first opening formed in the second electrode layer, the first opening exposing the first dielectric layer at the top of the electrode protrusion; a second dielectric layer, covering the second electrode layer, and covering the first dielectric layer exposed by the first opening; a third electrode layer, covering the second dielectric layer, and having a second opening formed in the third electrode layer exposing the top of the second dielectric layer, the projection of the second opening on the substrate and the projection of the first opening on the substrate are located at different positions; a first through-hole interconnection structure, located at the position of the first opening, and penetrating the third electrode layer, the second dielectric layer and the first dielectric layer, the first electrode layer and the third electrode layer are electrically connected through the first through-hole interconnection structure; a second through-hole interconnection structure, located at the position of the second opening, and penetrating the second dielectric layer, the second electrode layer is electrically connected to the second through-hole interconnection structure.

[0007] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first electrode layer on the substrate, wherein an electrode protrusion is formed on the first electrode layer; forming a first dielectric layer of the first electrode layer covering the top and sidewalls of the electrode protrusion and the side of the electrode protrusion; forming a second electrode layer covering the first dielectric layer, wherein a first opening is formed in the second electrode layer, wherein the first opening exposes the first dielectric layer at the top of the electrode protrusion; forming a second dielectric layer covering the second electrode layer, wherein the second dielectric layer also covers the first dielectric layer exposed by the first opening; forming a third electrode layer covering the second dielectric layer, wherein a second opening is formed in the third electrode layer, wherein the top of the second dielectric layer is exposed, and the projection of the second opening on the substrate and the projection of the first opening on the substrate are located at different positions; forming a first through-hole interconnection structure penetrating the third electrode layer, the second dielectric layer and the first dielectric layer at the position of the first opening, wherein the first electrode layer and the third electrode layer are electrically connected through the first through-hole interconnection structure; forming a second through-hole interconnection structure penetrating the second dielectric layer at the position of the second opening, wherein the second electrode layer is electrically connected to the second through-hole interconnection structure.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] The semiconductor structure provided by the embodiment of the present invention includes the first electrode layer having an electrode protrusion; a first through-hole interconnection structure located at the position of the first opening and penetrating the third electrode layer, the second dielectric layer and the first dielectric layer, the first electrode layer and the third electrode layer are electrically connected through the first through-hole interconnection structure, and a second through-hole interconnection structure located at the position of the second opening and penetrating the second dielectric layer, the second electrode layer and the second through-hole interconnection structure are electrically connected; because the electrode protrusion is formed on the first electrode layer, the vertical distance between the first electrode layer located at the top of the electrode protrusion and the third electrode layer is small, which correspondingly reduces the distance between the first electrode layer and the third electrode layer. The first through-hole interconnect structure electrically connects the first electrode layer and the third electrode layer, and the distance between the two reduces the height of the first through-hole interconnect structure, so that the second through-hole interconnect structure does not need to penetrate the first electrode layer, and there is no need to reserve an opening in the first electrode layer for forming the second through-hole interconnect structure, that is, the area of ​​the first electrode layer is increased, and the facing area of ​​the first electrode layer and the second electrode layer is correspondingly increased, which is beneficial to increase the capacitance density of the metal-insulator-metal (MIM) capacitor formed by the first electrode layer, the second electrode layer and the third electrode layer, thereby improving the performance of the semiconductor structure.

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, an electrode protrusion is formed on the first electrode layer, and a first through-hole interconnection structure penetrating the third electrode layer, the second dielectric layer and the first dielectric layer is formed at the position of the first opening, and the first electrode layer and the third electrode layer are electrically connected through the first through-hole interconnection structure; a second through-hole interconnection structure penetrating the second dielectric layer is formed at the position of the second opening, and the second electrode layer is electrically connected to the second through-hole interconnection structure; because the electrode protrusion is formed on the first electrode layer, the vertical distance between the first electrode layer and the third electrode layer located at the top of the electrode protrusion is small, and the distance between the first electrode layer and the third electrode layer respectively electrically connected to the first through-hole interconnection structure is correspondingly reduced, that is, the height of the first through-hole interconnection structure is reduced, so that the second through-hole interconnection structure does not need to penetrate the second electrode layer, and the opening for forming the second through-hole interconnection structure does not need to be reserved in the first electrode layer, that is, the area of ​​the first electrode layer is increased, and the area directly facing the first electrode layer and the second electrode layer is correspondingly increased, which is conducive to increasing the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer, the second electrode layer and the third electrode layer, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 3 It is a schematic diagram of the structure of a semiconductor structure;

[0012] Figures 4 to 8 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 9 to 32 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] At present, the performance of semiconductor structures still needs to be improved. Now, combining a semiconductor structure, we analyze the reasons why the performance of semiconductor structures needs to be improved.

[0015] Figures 1 to 3 is a schematic diagram of a semiconductor structure; wherein, Figure 1 It is a top view. Figure 2 yes Figure 1 Cross-sectional view at BB1 position, Figure 3 yes Figure 1 Cross-sectional view at position AA1.

[0016] refer to Figures 1 to 3 The semiconductor structure includes: a substrate 10, wherein the substrate 10 includes a first positioning portion 11 and a second positioning portion 12; a first electrode layer 13, located on the substrate 10, wherein a first opening (not shown) is formed in the first electrode layer 13 above the second positioning portion 12, wherein the first opening exposes the top of the substrate 10; a first dielectric layer 14, covering the first electrode layer 13 and the substrate 10 exposed by the first opening; a second electrode layer 15, covering the first dielectric layer 14, wherein a second opening (not shown) is formed in the second electrode layer 15 above the first positioning portion 11, wherein the top of the first dielectric layer 14 is exposed; a second dielectric layer 16, covering the second electrode layer 15 and the first dielectric layer 14 exposed by the second opening a third electrode layer 17 covering the second dielectric layer 16, wherein the third electrode layer 17 above the second positioning 12 is further formed with a third opening (not shown) located above the first opening, and the third opening exposes the top of the second dielectric layer 16; a first through-hole interconnection structure 21 located at the top of the first positioning 11 and penetrating the first electrode layer 13, the first dielectric layer 14, the second dielectric layer 16 and the third electrode layer 17, wherein the first electrode layer 13 and the third electrode layer 17 are electrically connected via the first through-hole interconnection structure 21; a second through-hole interconnection structure 22 located at the top of the second positioning 12 and penetrating the first dielectric layer 14, the second electrode layer 15 and the second dielectric layer 16, wherein the second electrode layer 15 is electrically connected to the second through-hole interconnection structure 22.

[0017] It has been found that in order to make the first through-hole interconnect structure 21 only contact the first electrode layer 13 and the third electrode layer 17 but not contact the second electrode layer 15, and the second through-hole interconnect structure 22 only contact the second electrode layer 15 but not contact the first electrode layer 13 and the third electrode layer 17, it is necessary to form a first opening exposing the top of the substrate 10 in the first electrode layer 13 above the second positioning 12, form a third opening exposing the top of the second dielectric layer 16 in the third electrode layer 17 above the second positioning 12, and form a second opening exposing the top of the first dielectric layer 14 in the second electrode layer 15 above the first positioning 11, thereby reducing the facing area between the adjacent first electrode layer 13 and the second electrode layer 15, and between the second electrode layer 15 and the third electrode layer 17, and correspondingly reducing the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 13, the second electrode layer 15 and the third electrode layer 17, thereby affecting the performance of the semiconductor structure.

[0018] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a first electrode layer, located on the substrate, and an electrode protrusion is formed on the first electrode layer; a first dielectric layer, covering the top and sidewalls of the electrode protrusion, and the first electrode layer covering the side of the electrode protrusion; a second electrode layer, covering the first dielectric layer, and a first opening is formed in the second electrode layer, and the first opening exposes the first dielectric layer at the top of the electrode protrusion; a second dielectric layer, covering the second electrode layer, and covering the first dielectric layer exposed by the first opening; a third electrode layer, covering the second dielectric layer, and a second opening is formed in the third electrode layer to expose the top of the second dielectric layer, and the projection of the second opening on the substrate and the projection of the first opening on the substrate are located at different positions; a first through-hole interconnection structure, located at the position of the first opening, and penetrating the third electrode layer, the second dielectric layer and the first dielectric layer, and the first electrode layer and the third electrode layer are electrically connected through the first through-hole interconnection structure; a second through-hole interconnection structure, located at the position of the second opening, and penetrating the second dielectric layer, and the second electrode layer is electrically connected to the second through-hole interconnection structure.

[0019] The semiconductor structure provided in the embodiment of the present invention includes the first electrode layer having an electrode protrusion; a first through-hole interconnection structure located at the position of the first opening and penetrating the third electrode layer, the second dielectric layer and the first dielectric layer, the first electrode layer and the third electrode layer are electrically connected through the first through-hole interconnection structure, and a second through-hole interconnection structure located at the position of the second opening and penetrating the second dielectric layer, the second electrode layer and the second through-hole interconnection structure are electrically connected; because the electrode protrusion is formed on the first electrode layer, the vertical distance between the first electrode layer located at the top of the electrode protrusion and the third electrode layer is small, and the distance between the first electrode layer and the third electrode layer respectively electrically connected to the first through-hole interconnection structure is correspondingly reduced, that is, the height of the first through-hole interconnection structure is reduced, so that the second through-hole interconnection structure does not need to penetrate the first electrode layer, and the opening for forming the second through-hole interconnection structure does not need to be reserved in the first electrode layer, that is, the area of ​​the first electrode layer is increased, and the area directly facing the first electrode layer and the second electrode layer is correspondingly increased, which is conducive to increasing the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer, the second electrode layer and the third electrode layer, thereby improving the performance of the semiconductor structure.

[0020] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0021] Figures 4 to 8 It is a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0022] refer to Figures 4 to 8 In this embodiment, the semiconductor structure includes: a substrate 100; a first electrode layer 110, located on the substrate 100, and an electrode protrusion 115 is formed on the first electrode layer 110; a first dielectric layer 120, covering the top and sidewalls of the electrode protrusion 115, and the first electrode layer 110 covering the side of the electrode protrusion 115; a second electrode layer 130, covering the first dielectric layer 120, and a first opening 135 (such as Figure 7 ), the first opening 135 exposes the first dielectric layer 120 at the top of the electrode protrusion 115; the second dielectric layer 140 covers the second electrode layer 130 and the first dielectric layer 120 exposed by the first opening 135; the third electrode layer 150 covers the second dielectric layer 140, and the third electrode layer 150 is formed with a second opening 155 (as shown in FIG. 1 ) that exposes the top of the second dielectric layer 140 Figure 8As shown), the projection of the second opening 155 on the substrate 100 and the projection of the first opening 135 on the substrate 100 are located at different positions; the first through-hole interconnection structure 210 is located at the position of the first opening 135 and penetrates the third electrode layer 150, the second dielectric layer 140 and the first dielectric layer 120, and the first electrode layer 110 and the third electrode layer 150 are electrically connected through the first through-hole interconnection structure 210; the second through-hole interconnection structure 220 is located at the position of the second opening 155 and penetrates the second dielectric layer 140, and the second electrode layer 130 is electrically connected to the second through-hole interconnection structure 220.

[0023] in, Figure 4 is a top view, Figure 5 for Figure 4 Cross-sectional view at BB1 position, Figure 6 for Figure 4 The cross-sectional view at position AA1, Figure 7 for Figure 5 The corresponding cross-sectional view of the second opening, Figure 8 for Figure 6 A cross-sectional view of the corresponding first opening.

[0024] It should be noted that in order to clearly show the semiconductor structure, Figure 7 The fourth dielectric layer and the second through-hole interconnect structure are omitted. Figure 8 The second dielectric layer, the third electrode layer, the fourth dielectric layer and the first through-hole interconnection structure are omitted.

[0025] The substrate 100 is used to provide a process platform for forming a capacitor.

[0026] In this embodiment, the substrate 100 is used to form a MIM capacitor.

[0027] Specifically, the first electrode layer 110 , the second electrode layer 130 , and the third electrode layer 150 constitute a metal-insulator-metal capacitor.

[0028] In other embodiments, the substrate may also be used to form MOS (metal-oxide-semiconductor) capacitors, PIP (polysilicon-insulator-polysilicon) capacitors, MOM (metal-oxide-metal) capacitors, and the like.

[0029] In this embodiment, the base 100 includes a substrate 101, which is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0030] Other structures (not shown) may also be formed on the substrate 101 , such as MOS transistors, resistors, inductors, dielectric layers, metal interconnect structures, etc.

[0031] In this embodiment, an initial protrusion 105 is formed on the substrate 100 , and the first electrode layer 110 also covers the initial protrusion 105 , and a portion of the first electrode layer 110 located on the initial protrusion 105 serves as the electrode protrusion 115 .

[0032] Usually, an initial protrusion 105 is first formed on the substrate 100. Therefore, in the step of forming the first electrode layer 110, the first electrode layer 110 also covers the initial protrusion 105, so that the first electrode layer 110 can obtain the electrode protrusion 115 following the morphology of the initial protrusion 105. That is to say, in the step of forming the first electrode layer 110, the electrode protrusion 115 can be formed on the first electrode layer 110 without patterning the first electrode layer 110, thereby reducing the probability of the patterning process causing damage to the first electrode layer 110, which is beneficial to improving the quality of the first electrode layer 110, correspondingly improving the performance of the semiconductor structure, and reducing the difficulty of forming the electrode protrusion 115.

[0033] Specifically, the base 100 includes a substrate 101 and a third dielectric layer 102 located on the substrate 101 , and the third dielectric layer 102 has an initial protrusion 105 on the top.

[0034] On the one hand, the third dielectric layer 102 is used to isolate the structure (such as MOS transistors, etc.) formed above the substrate 101 from the first electrode layer 110. On the other hand, the third dielectric layer 102 can be patterned to form a raised initial protrusion 105 on the remaining thickness of the third dielectric layer 102, thereby reducing the process complexity of obtaining the initial protrusion 105.

[0035] Moreover, patterning the third dielectric layer 102 to form a raised initial protrusion 105 on the remaining thickness of the third dielectric layer 102 is also beneficial to reducing the probability of the substrate 101 being damaged and the probability of other structures between the substrate 101 and the third dielectric layer 102 being damaged, thereby improving the performance of the semiconductor structure.

[0036] It should be noted that other structures (not shown) may also be formed on the substrate 101 , such as MOS transistors, resistors, inductors, dielectric layers, metal interconnect structures, etc. Correspondingly, other structures are located between the substrate 101 and the third dielectric layer 102 .

[0037] In this embodiment, the material of the third dielectric layer 102 is silicon oxide. In other embodiments, the material of the third dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0038] It should be noted that, along the direction perpendicular to the side wall of the initial protrusion 105, the width w of the initial protrusion should not be too small or too large. Since the first opening 135 is located above the initial protrusion 105, if the width w of the initial protrusion 105 is too small, it is easy to increase the difficulty of forming the first opening 135, and correspondingly, it is easy to increase the difficulty of forming the first through-hole interconnection structure 210 at the position of the first opening 135; if the width w of the initial protrusion 105 is too large, while ensuring the number of electrode protrusions 115, it is easy to cause the occupied area of ​​the MIM capacitor to be too large, which is not conducive to the reduction of the process node. Therefore, in this embodiment, along the direction perpendicular to the side wall of the initial protrusion 105, the width w of the initial protrusion 105 ranges from 1 micron to 5 microns.

[0039] The first electrode layer 110 is used as an electrode plate of the MIM capacitor.

[0040] In this embodiment, the material of the first electrode layer 110 is a conductive material. As an example, the material of the first electrode layer 110 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0041] An electrode protrusion 115 is formed on the first electrode layer 110, so that the vertical distance between the top surfaces of the first electrode layer 110 located on the top of the electrode protrusion 115 and the third electrode layer 150 is small, and the distance between the first electrode layer 110 and the third electrode layer 150 in the first through-hole interconnection structure 210 is correspondingly reduced, that is, the height of the first through-hole interconnection structure 210 is reduced, so that the second through-hole interconnection structure 220 does not need to penetrate the first electrode layer 110, and there is no need to reserve an opening in the first electrode layer 110 for forming the second through-hole interconnection structure 220, that is, the area of ​​the first electrode layer 110 is increased, and the area facing the first electrode layer 110 and the second electrode layer 130 is correspondingly increased, which is beneficial to increase the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 110, the second electrode layer 130 and the third electrode layer 150, thereby improving the performance of the semiconductor structure.

[0042] In this embodiment, the electrode protrusions 115 are arranged in a matrix.

[0043] The electrode protrusions 115 are arranged in a matrix, so that the first openings 135 of the first dielectric layer 120 that expose the tops of the electrode protrusions 115 are also arranged in a matrix, and accordingly, the first through-hole interconnection structures 210 located at the positions of the first openings 135 are also arranged in a matrix; moreover, the electrode protrusions 115 are arranged in a matrix, so that the projections of the second openings 155 on the substrate 100 are located between the projections of adjacent electrode protrusions 115 on the substrate 100.

[0044] The first dielectric layer 120 is used as an insulating layer in forming the MIM capacitor, and is used to isolate the first electrode layer 110 from the second electrode layer 130 .

[0045] In this embodiment, the material of the first dielectric layer 120 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of high-k dielectric materials is conducive to increasing the capacitance value of the MIM capacitor and correspondingly increasing the capacitance density.

[0046] Specifically, the first dielectric layer 120 is a high-k dielectric layer formed by stacking, that is, the first dielectric layer 120 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the first dielectric layer 120 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0047] In this embodiment, the first dielectric layer 120 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer stacked together. In other embodiments, according to process requirements, the material of the dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0048] The second electrode layer 130 is used as an electrode plate of the MIM capacitor.

[0049] In this embodiment, the material of the second electrode layer 130 is a conductive material. As an example, the material of the second electrode layer 130 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0050] A first opening 135 is formed in the second electrode layer 130 , and the first opening 135 exposes the first dielectric layer 120 at the top of the electrode protrusion 115 , so as to form a first through-hole interconnection structure 210 at the position of the first opening 135 , which is in contact with the first electrode layer 110 and the third electrode layer 150 but not with the second electrode layer 130 .

[0051] It should be noted that, along the normal direction of the substrate 100, the ratio of the height h1 of the electrode protrusion 115 to the thickness h2 of the second electrode layer 130 on its side should not be too small or too large. If the ratio of the height h1 of the electrode protrusion 115 to the thickness h2 of the second electrode layer 130 on its side is too small or too large, it is easy to cause the height difference between the first through-hole interconnection structure 210 formed at the position of the first opening 135 and the second through-hole interconnection structure 220 formed at the position of the second opening 155 to be too large, thereby easily increasing the process difficulty of forming the first through-hole interconnection structure 210 and the second through-hole interconnection structure 220. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the height h1 of the electrode protrusion 115 accounts for 80% to 95% of the thickness h2 of the second electrode layer 130 on its side.

[0052] The second dielectric layer 140 is used as an insulating layer in forming the MIM capacitor, and is used to isolate the second electrode layer 130 and the third electrode layer 150 .

[0053] In this embodiment, the material of the second dielectric layer 140 is a high-k dielectric material. The reason for selecting the high-k dielectric material as the material of the second dielectric layer 140 is similar to the reason for selecting the high-k dielectric material as the material of the first dielectric layer 120 , so it will not be repeated here.

[0054] Specifically, the second dielectric layer 140 is a high-k dielectric layer formed by stacking, that is, the second dielectric layer 140 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the second dielectric layer 140 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0055] As an example, the second dielectric layer 140 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer stacked. In other embodiments, according to process requirements, the material of the dielectric layer can also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0056] The third electrode layer 150 is used as an electrode plate of the MIM capacitor.

[0057] In this embodiment, the material of the third electrode layer 150 is a conductive material. As an example, the material of the second electrode layer 130 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0058] In this embodiment, the second openings 155 are arranged in a matrix, and along the column direction of the matrix, the projections of the electrode protrusions 115 on the substrate 100 and the projections of the second openings 155 on the substrate 100 are arranged alternately, and along the row direction of the matrix, the projections of the electrode protrusions 115 on the substrate 100 and the projections of the second openings 155 on the substrate 100 are staggered. Here, the column direction and the row direction are perpendicular to each other.

[0059] Along the column direction of the matrix, the projection of the electrode protrusion 115 on the substrate 100 and the projection of the second opening 155 on the substrate 100 are arranged alternately, and along the row direction of the matrix, the projection of the electrode protrusion 115 on the substrate 100 and the projection of the second opening 155 on the substrate 100 are staggered, that is, along the diagonal direction of the matrix, the electrode protrusion 115 and the second opening 155 are arranged alternately, so that the first through-hole interconnection structure 210 corresponding to the electrode protrusion 115 and the second through-hole interconnection structure 220 corresponding to the second opening 155 are arranged alternately in the direction along the diagonal direction of the matrix.

[0060] In this embodiment, the semiconductor structure further includes: a fourth dielectric layer 160 covering the third electrode layer 150 and the second dielectric layer 140 exposed by the second opening 155 ; the first through-hole interconnect structure 210 and the second through-hole interconnect structure 220 are both located in the fourth dielectric layer 160 .

[0061] The fourth dielectric layer 160 is used to provide a process basis for forming the first through-hole interconnection structure 210 and the second through-hole interconnection structure 220 , and is also used to achieve electrical isolation between the first through-hole interconnection structure 210 and the second through-hole interconnection structure 220 .

[0062] Specifically, the material of the fourth dielectric layer 160 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0063] The first through-hole interconnection structure 210 is used to electrically connect the first electrode layer 110 and the third electrode layer 150, thereby loading the first electrical signal to the first electrode layer 110 and the third electrode layer 150. The second through-hole interconnection structure 220 is used to electrically connect the second electrode layer 130, thereby loading the second electrical signal to the second electrode layer 130.

[0064] Since the electrode protrusion 115 is formed on the first electrode layer 110, the vertical distance between the first electrode layer 110 located on the top of the electrode protrusion 115 and the third electrode layer 150 is small, and the distance between the first electrode layer 110 and the third electrode layer 150, which are respectively electrically connected to the first through-hole interconnection structure 210, is correspondingly reduced, that is, the height of the first through-hole interconnection structure 210 is reduced, so that the second through-hole interconnection structure 220 does not need to penetrate the first electrode layer 110, and there is no need to reserve an opening in the first electrode layer 110 for forming the second through-hole interconnection structure 220, that is, the area of ​​the first electrode layer 110 is increased, and the facing area of ​​the first electrode layer 110 and the second electrode layer 130 is correspondingly increased, which is beneficial to increase the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 110, the second electrode layer 130 and the third electrode layer 150, thereby improving the performance of the semiconductor structure.

[0065] It should be noted that a first electrical signal is loaded to the first electrode layer 110 and the third electrode layer 150 through the first through-hole interconnection structure 210, and a second electrical signal is loaded to the second electrode layer 130 through the second through-hole interconnection structure 220, so that there is a potential difference between the first electrode layer 110 and the second electrode layer 130, and at the same time, there is a potential difference between the second electrode layer 130 and the third electrode layer 150, so that the first electrode layer 110, the second electrode layer 130 and the third electrode layer 150 constitute a MIM capacitor.

[0066] Specifically, the material of the first via interconnect structure 210 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride. The material of the second via interconnect structure 220 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.

[0067] In this embodiment, the second openings 155 are arranged in a matrix, and along the column direction of the matrix, the projections of the electrode protrusions 115 on the substrate 100 and the projections of the second openings 155 on the substrate 100 are arranged alternately, and along the row direction of the matrix, the projections of the electrode protrusions 115 on the substrate 100 and the projections of the second openings 155 on the substrate 100 are staggered. Accordingly, the first through-hole interconnection structures 210 and the second through-hole interconnection structures 220 are arranged alternately in the direction along the diagonal line of the matrix.

[0068] The first through-hole interconnection structures 210 and the second through-hole interconnection structures 220 are alternately arranged in the direction along the diagonal line of the matrix, so that the comb-teeth portions of the first rewiring structure and the comb-teeth portions of the second rewiring structure are arranged crosswise.

[0069] In this embodiment, the first through-hole interconnection structure 210 is also located in the first electrode layer 110 of the first partial thickness.

[0070] The first through-hole interconnect structure 210 is also located in the first partial thickness of the first electrode layer 110 , which is beneficial to ensure the contact effect between the first through-hole interconnect structure 210 and the first electrode layer 110 , thereby ensuring the electrical connection performance between the first through-hole interconnect structure 210 and the first electrode layer 110 .

[0071] It should be noted that, along the normal direction of the top surface of the substrate 100, the ratio of the thickness of the first portion to the thickness of the first electrode layer 110 should not be too small or too large. If the ratio is too small, it is easy to ensure that the contact effect between the first through-hole interconnection structure 210 and the first electrode layer 110 is poor; if the ratio is too large, it is easy to increase the probability of over-etching the first electrode layer 110, that is, to increase the probability of the first through-hole interconnection structure 210 passing through the first electrode layer 110, thereby increasing the probability of the first through-hole interconnection structure 210 being electrically connected to the structure. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the thickness of the first portion accounts for 50% to 70% of the thickness of the first electrode layer.

[0072] In this embodiment, the second through hole interconnection structure 220 is also located in the second partial thickness of the first electrode layer.

[0073] The second through-hole interconnect structure 220 is also located in the second partial thickness of the second electrode layer 130 , which is beneficial to ensure the contact effect between the second through-hole interconnect structure 220 and the second electrode layer 130 , thereby ensuring the electrical connection performance between the second through-hole interconnect structure 220 and the second electrode layer 130 .

[0074] It should be noted that, along the normal direction of the top surface of the substrate 100, the ratio of the thickness of the second portion to the thickness of the second electrode layer 130 should not be too small or too large. If the ratio is too small, it is easy to ensure that the contact effect between the second through-hole interconnection structure 220 and the second electrode layer 130 is poor; if the ratio is too large, it is easy to increase the probability of over-etching the second electrode layer 130, that is, to increase the probability of the second through-hole interconnection structure 220 passing through the second electrode layer 130, thereby increasing the probability of the second through-hole interconnection structure 220 electrically connecting to the first electrode layer 110. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 100, the thickness of the second portion accounts for 50% to 70% of the thickness of the second electrode layer 130.

[0075] In this embodiment, the semiconductor structure also includes: a rewiring structure 170, located above the first through-hole interconnection structure 210 and the second through-hole interconnection structure 220, the rewiring structure 170 includes a first rewiring structure 171 and a second rewiring structure 172, the first rewiring structure 171 and the second rewiring structure 172 both include a comb handle 175 and a comb tooth portion 176 connected to the comb handle 175; the comb tooth portion 176 of the first rewiring structure 171 and the comb tooth portion 176 of the second rewiring structure 172 are cross-arranged; and the first rewiring structure 171 is connected to the first through-hole interconnection structure 210, and the second rewiring structure 172 is connected to the second through-hole interconnection structure 220.

[0076] The rewiring structure 170 can rewire the first through-hole interconnect structure 210 and the second through-hole interconnect structure 220, and is also convenient for loading the first electrical signal to the first electrode layer 110 and the third electrode layer 150 through the first rewiring structure 171, and loading the second electrical signal to the second electrode layer 130 through the second rewiring structure 172.

[0077] The first rewiring structure 171 and the second rewiring structure 172 both include a comb handle 175 and a comb tooth portion 176 connected to the comb handle 175, and the comb tooth portion 176 of the first rewiring structure 171 and the comb tooth portion 176 of the second rewiring structure 172 are cross-arranged, which is beneficial for simultaneously loading electrical signals to each first through-hole interconnection structure 210 or second through-hole interconnection structure 220 electrically connected thereto through the comb handle 175, and saves the area of ​​the first rewiring structure 171 and the second rewiring structure 172, and correspondingly saves the area of ​​the rewiring structure 170, thereby helping to reduce process costs.

[0078] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 9 to 32 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0079] refer to Figures 9 to 11 , providing a substrate 500.

[0080] in, Fig. 9 is a top view, Fig.10 for Fig. 9 Cross-sectional view at BB1 position, Fig.11 for Fig. 9 Cross-sectional view at position AA1.

[0081] The substrate 500 is used to provide a process platform for forming a capacitor.

[0082] In this embodiment, the substrate 500 is used to form a MIM capacitor.

[0083] Specifically, the first electrode layer, the second electrode layer and the third electrode layer formed subsequently constitute a metal-insulator-metal capacitor.

[0084] In other embodiments, the substrate may also be used to form MOS (metal-oxide-semiconductor) capacitors, PIP (polysilicon-insulator-polysilicon) capacitors, MOM (metal-oxide-metal) capacitors, and the like.

[0085] In this embodiment, the base 500 includes a substrate 501, which is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0086] Other structures (not shown) may also be formed on the substrate 501 , such as MOS transistors, resistors, inductors, dielectric layers, metal interconnect structures, etc.

[0087] In this embodiment, in the step of providing the substrate 500 , an initial protrusion 505 is formed on the substrate 500 .

[0088] An initial protrusion 505 is first formed on the substrate 500, so that in the subsequent step of forming the first electrode layer, the first electrode layer covers the initial protrusion 505, and the first electrode layer located on the initial protrusion 505 serves as the electrode protrusion. That is to say, in the step of forming the first electrode layer, there is no need to pattern the first electrode layer, and the electrode protrusion can be formed on the first electrode layer, thereby reducing the probability of the patterning process causing damage to the first electrode layer, which is beneficial to improving the quality of the first electrode layer, correspondingly improving the performance of the semiconductor structure, and also reducing the difficulty of forming the electrode protrusion.

[0089] Specifically, in the step of providing the base 500, the base 500 includes a substrate 501 and a third dielectric layer 502 located on the substrate 501; before forming the first electrode layer on the base 500, the third dielectric layer 502 is patterned to form a raised initial protrusion 505 on the remaining thickness of the third dielectric layer 502.

[0090] On the one hand, the third dielectric layer 502 is used to isolate the structure (such as MOS transistor, etc.) formed above the substrate 501 from the first electrode layer. On the other hand, the third dielectric layer 502 can be patterned to form a raised initial protrusion 505 on the remaining thickness of the third dielectric layer 502, thereby reducing the process complexity of obtaining the initial protrusion 105.

[0091] Moreover, patterning the third dielectric layer 502 to form a raised initial protrusion 505 on the remaining thickness of the third dielectric layer 502 is also beneficial to reducing the probability of the substrate 501 being damaged and the probability of other structures located between the substrate 501 and the third dielectric layer 502 being damaged, thereby improving the performance of the semiconductor structure.

[0092] It should be noted that other structures (not shown) may also be formed on the substrate 501 , such as MOS transistors, resistors, inductors, dielectric layers, metal interconnect structures, etc. Correspondingly, the other structures are located between the substrate 501 and the third dielectric layer 502 .

[0093] In this embodiment, the material of the third dielectric layer 502 is silicon oxide. In other embodiments, the material of the third dielectric layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0094] It should be noted that, along the direction perpendicular to the side wall of the initial protrusion 505, the width W of the initial protrusion should not be too small or too large. Since the subsequent first opening is located above the initial protrusion 505, if the width W of the initial protrusion 505 is too small, it is easy to increase the difficulty of forming the first opening subsequently, and it is easy to increase the difficulty of forming the first through-hole interconnection structure at the position of the first opening; if the width W of the initial protrusion 505 is too large, it is easy to cause the occupied area of ​​the MIM capacitor to be too large while ensuring the number of electrode protrusions, which is not conducive to the reduction of process nodes. Therefore, in this embodiment, along the direction perpendicular to the side wall of the initial protrusion 505, the width W of the initial protrusion 505 ranges from 1 micron to 5 microns.

[0095] refer to Figure 12 to Figure 13 A first electrode layer 510 is formed on the substrate 500 , and an electrode protrusion 515 is formed on the first electrode layer 510 .

[0096] in, Fig.12 for Fig.10 Schematic diagram of the structure after forming the first electrode layer, Fig.13 for Fig.11 Schematic diagram of the structure after forming the first electrode layer.

[0097] The first electrode layer 510 is used as an electrode plate of the MIM capacitor.

[0098] In this embodiment, the material of the first electrode layer 510 is a conductive material. As an example, the material of the first electrode layer 510 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0099] An electrode protrusion 515 is formed on the first electrode layer 510, so that the vertical distance between the top surface of the first electrode layer 510 located on the top of the electrode protrusion 515 and the subsequently formed third electrode layer is small, and the distance between the first electrode layer 510 and the third electrode layer in the first through-hole interconnection structure is correspondingly reduced, that is, the height of the first through-hole interconnection structure formed subsequently is reduced, so that the second through-hole interconnection structure formed subsequently does not need to penetrate the second electrode layer, and there is no need to reserve an opening in the first electrode layer 510 for forming the second through-hole interconnection structure, that is, the area of ​​the first electrode layer 510 is increased, and the area facing the first electrode layer 510 and the subsequently formed second electrode layer is correspondingly increased, which is beneficial to increase the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 510, the second electrode layer and the third electrode layer, thereby improving the performance of the semiconductor structure.

[0100] Correspondingly, in this embodiment, in the step of forming the first electrode layer 510 , the first electrode layer 510 also covers the initial protrusion 505 , and the portion located on the initial protrusion 505 serves as the electrode protrusion 515 .

[0101] In this embodiment, in the step of forming the first electrode layer 510 , the electrode protrusions 515 are arranged in a matrix.

[0102] In the step of forming the first electrode layer 510, the electrode protrusions 515 are arranged in a matrix, so that the first openings subsequently formed according to the electrode protrusions 515 are also arranged in a matrix, and the first through-hole interconnection structure formed at the first opening position is also arranged in a matrix; moreover, the electrode protrusions 515 are arranged in a matrix, which also makes it easier for the projection of the second opening on the substrate 500 to be located between the projections of adjacent electrode protrusions 515 on the substrate 500.

[0103] refer to Figure 14 to Figure 15 , forming a first dielectric layer 520 of the first electrode layer 510 covering the top and side walls of the electrode protrusion 515 and the side of the electrode protrusion 515 .

[0104] in, Fig.14 for Fig.12 Schematic diagram of the structure after forming the first dielectric layer, Fig.15 for Fig.13 Schematic diagram of the structure after forming the first dielectric layer.

[0105] The first dielectric layer 520 is used as an insulating layer in forming the MIM capacitor, and is used to isolate the first electrode layer 510 from the second electrode layer formed subsequently.

[0106] In this embodiment, the material of the first dielectric layer 520 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of high-k dielectric materials is conducive to increasing the capacitance value of the MIM capacitor and correspondingly increasing the capacitance density.

[0107] Specifically, the first dielectric layer 520 is a high-k dielectric layer formed by stacking, that is, the first dielectric layer 520 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the first dielectric layer 520 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0108] In this embodiment, the first dielectric layer 520 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer stacked together. In other embodiments, according to process requirements, the material of the dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0109] refer to Fig.16 and Fig.17 , forming a second electrode layer 530 covering the first dielectric layer 520 , wherein a first opening 535 is formed in the second electrode layer 530 , and the first opening 535 exposes the first dielectric layer 520 on the top of the electrode protrusion 515 .

[0110] in, Fig.16 for Fig.14 Schematic diagram of the structure after forming the second electrode layer, Fig.17 for Fig.15 Schematic diagram of the structure after forming the second electrode layer.

[0111] The second electrode layer 530 is used as an electrode plate of the MIM capacitor.

[0112] In this embodiment, the material of the second electrode layer 530 is a conductive material. As an example, the material of the second electrode layer 530 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0113] A first opening 535 is formed in the second electrode layer 530 , so as to facilitate the subsequent formation of a first through-hole interconnection structure at the position of the first opening 535 that contacts only the first electrode layer and the third electrode layer but does not contact the second electrode layer 530 .

[0114] In this embodiment, the step of forming the second electrode layer 530 includes: forming a second electrode material layer (not shown) covering the first dielectric layer 520; patterning the second electrode material layer to form a first opening 535 exposing the first dielectric layer 520 at the position of the electrode protrusion 515, and the remaining second electrode material layer serves as the second electrode layer 530.

[0115] It should be noted that, along the normal direction of the substrate 500, the ratio of the height H1 of the electrode protrusion 515 to the thickness H2 of the second electrode layer 530 on its side should not be too small or too large. If the ratio of the height H1 of the electrode protrusion 515 to the thickness H2 of the second electrode layer 530 on its side is too small or too large, it is easy to cause the height difference between the first through-hole interconnection structure formed at the first opening 535 position and the second through-hole interconnection structure formed at the second opening position to be too large, thereby easily increasing the difficulty of the subsequent process of forming the first through-hole interconnection structure and the second through-hole interconnection structure. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the height H1 of the electrode protrusion 515 accounts for 80% to 95% of the thickness H2 of the second electrode layer 530 on its side.

[0116] refer to Fig.18 and Fig.19 , forming a second dielectric layer 540 covering the second electrode layer 530 , and the second dielectric layer 540 also covers the first dielectric layer 520 exposed by the first opening 535 .

[0117] in, Fig.18 for Fig.16 Schematic diagram of the structure after forming the second dielectric layer, Fig.19 for Fig.17 Schematic diagram of the structure after forming the second dielectric layer.

[0118] The second dielectric layer 540 is used as an insulating layer in forming the MIM capacitor, and is used to isolate the second electrode layer 530 from the subsequently formed third electrode layer.

[0119] In this embodiment, the material of the second dielectric layer 540 is a high-k dielectric material. The reason for selecting the high-k dielectric material as the material of the second dielectric layer 540 is similar to the reason for selecting the high-k dielectric material as the material of the first dielectric layer 520, so it will not be repeated here.

[0120] Specifically, the second dielectric layer 540 is a high-k dielectric layer formed by stacking, that is, the second dielectric layer 540 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the second dielectric layer 540 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0121] As an example, the second dielectric layer 540 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer stacked. In other embodiments, according to process requirements, the material of the dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0122] refer to Figure 20 to Figure 21 , forming a third electrode layer 550 covering the second dielectric layer 540, wherein the third electrode layer 550 is formed with a second opening 555 exposing the top of the second dielectric layer 540, and the projection of the second opening 555 on the substrate 500 and the projection of the first opening 535 on the substrate 500 are located at different positions. Here, the column direction is perpendicular to the row direction.

[0123] in, Fig. 20 for Fig.18 Schematic diagram of the structure after forming the third electrode layer, Fig.21 for Fig.19 Schematic diagram of the structure after forming the third electrode layer.

[0124] The third electrode layer 550 is used as an electrode plate of the MIM capacitor.

[0125] In this embodiment, the material of the third electrode layer 550 is a conductive material. As an example, the material of the second electrode layer 130 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0126] In this embodiment, in the step of forming the third electrode layer 550, the second openings 555 are arranged in a matrix, and along the column direction of the matrix, the projection of the electrode protrusion 515 on the substrate 500 and the projection of the second openings 555 on the substrate 500 are arranged alternately, and along the row direction of the matrix, the projection of the electrode protrusion 515 on the substrate 500 and the projection of the second openings 555 on the substrate 500 are staggered.

[0127] Along the column direction of the matrix, the projection of the electrode protrusion 515 on the substrate 500 and the projection of the second opening 555 on the substrate 500 are arranged alternately, and along the row direction of the matrix, the projection of the electrode protrusion 515 on the substrate 500 and the projection of the second opening 555 on the substrate 500 are staggered, that is, along the diagonal direction of the matrix, the electrode protrusion 515 and the second opening 555 are arranged alternately, so that the first through-hole interconnection structure corresponding to the electrode protrusion 515 and the second through-hole interconnection structure corresponding to the second opening 555 formed subsequently are arranged alternately in the direction along the diagonal direction of the matrix.

[0128] refer to Figure 22 to Figure 23 In this embodiment, after forming the third electrode layer 550 and before forming the first through-hole interconnection structure and the second through-hole interconnection structure, the formation method further includes: forming a fourth dielectric layer 560 covering the third electrode layer 550, and the fourth dielectric layer 560 also covers the second dielectric layer 540 exposed by the second opening 555.

[0129] in, Fig. 22 for Fig. 20 Schematic diagram of the structure after forming the fourth dielectric layer, Fig.23 for Fig.21 Schematic diagram of the structure after forming the fourth dielectric layer.

[0130] The fourth dielectric layer 560 is used to provide a process basis for the subsequent formation of the first through-hole interconnection structure and the second through-hole interconnection structure, and is also used to achieve electrical isolation between the first through-hole interconnection structure and the second through-hole interconnection structure.

[0131] Specifically, the material of the fourth dielectric layer 560 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0132] refer to Figures 24 to 31 At the position of the first opening 535, a first through-hole interconnection structure 610 is formed that penetrates the third electrode layer 550, the second dielectric layer 540 and the first dielectric layer 520, and the first electrode layer 510 and the third electrode layer 550 are electrically connected through the first through-hole interconnection structure 610; at the position of the second opening 555, a second through-hole interconnection structure 620 is formed that penetrates the second dielectric layer 540, and the second electrode layer 530 is electrically connected to the second through-hole interconnection structure 620.

[0133] in, Fig.24 yes Fig. 22 A schematic diagram of the structure after forming the second initial through hole, Fig.25 for Fig.23 A schematic diagram of the structure after forming the first initial through hole, Fig.26 yes Fig.24 A schematic diagram of the structure after forming the second through hole, Fig. 27 for Fig.25 A schematic diagram of the structure after forming the first through hole, Fig.28 yes Fig.26 A schematic diagram of the structure after removing the second electrode layer of a second portion of thickness, Fig.29 yes Fig. 27 A schematic diagram of the structure after removing the first electrode layer of a first portion of thickness, Fig.30 yes Fig.28 A schematic diagram of the structure after forming the second through-hole interconnection structure, Fig.31 yes Fig.29 Schematic diagram of the structure after forming the first through-hole interconnection structure.

[0134] The first through-hole interconnection structure 610 is used to electrically connect the first electrode layer 510 and the third electrode layer 550, thereby loading the first electrical signal to the first electrode layer 510 and the third electrode layer 550. The second through-hole interconnection structure 620 is used to electrically connect the second electrode layer 530, thereby loading the second electrical signal to the second electrode layer 530.

[0135] Since the electrode protrusion 515 is formed on the first electrode layer 510, the vertical distance between the first electrode layer 510 located on the top of the electrode protrusion 515 and the third electrode layer 550 is small, and the distance between the first electrode layer 510 and the third electrode layer 550, which are respectively electrically connected to the first through-hole interconnection structure 610, is correspondingly reduced, that is, the height of the first through-hole interconnection structure 610 is reduced, so that the second through-hole interconnection structure 620 does not need to penetrate the second electrode layer 530, and there is no need to reserve an opening in the first electrode layer 510 for forming the second through-hole interconnection structure 620, that is, the area of ​​the first electrode layer 510 is increased, and the area directly facing the first electrode layer 510 and the second electrode layer 530 is correspondingly increased, which is beneficial to increase the capacitance density of the metal-insulator-metal capacitor formed by the first electrode layer 510, the second electrode layer 530 and the third electrode layer 550, thereby improving the performance of the semiconductor structure.

[0136] It should be noted that a first electrical signal is loaded to the first electrode layer 510 and the third electrode layer 550 through the first through-hole interconnection structure 610, and a second electrical signal is loaded to the second electrode layer 530 through the second through-hole interconnection structure 620, so that there is a potential difference between the first electrode layer 510 and the second electrode layer 530, and at the same time, there is a potential difference between the second electrode layer 530 and the third electrode layer 550, so that the first electrode layer 510, the second electrode layer 530 and the third electrode layer 550 constitute a MIM capacitor.

[0137] Specifically, the material of the first via interconnect structure 610 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride. The material of the second via interconnect structure 620 includes one or more of aluminum, copper, titanium nitride, cobalt, and tantalum nitride.

[0138] In this embodiment, along the column direction of the matrix, the projection of the electrode protrusion 515 on the substrate 500 and the projection of the second opening 555 on the substrate 500 are arranged alternately, and along the row direction of the matrix, the projection of the electrode protrusion 515 on the substrate 500 and the projection of the second opening 555 on the substrate 500 are staggered. Accordingly, the first through-hole interconnection structure 610 and the second through-hole interconnection structure 620 are arranged alternately in the direction along the diagonal line of the matrix.

[0139] The first through-hole interconnection structures 610 and the second through-hole interconnection structures 620 are alternately arranged in the direction along the diagonal line of the matrix, so that the comb-teeth portions of the first rewiring structure and the comb-teeth portions of the second rewiring structure are arranged crosswise.

[0140] In this embodiment, the steps of forming the first through-hole interconnection structure 610 and the second through-hole interconnection structure 620 include: forming a first through-hole 611 penetrating the fourth dielectric layer 560, the third electrode layer 550, the second dielectric layer 540 and the first dielectric layer 520 at the position of the first opening 535, and forming a second through-hole 621 penetrating the fourth dielectric layer 560 and the second dielectric layer 540 at the position of the second opening 555; filling the first through-hole 611 to form the first through-hole interconnection structure 610 (such as Fig.31 ), fill the second through hole 621 to form the second through hole interconnection structure 620 (as shown in Fig.30 shown).

[0141] First, a first through hole 611 penetrating the fourth dielectric layer 560, the third electrode layer 550, the second dielectric layer 540 and the first dielectric layer 520, and a second through hole 621 penetrating the fourth dielectric layer 560 and the second dielectric layer 540 are formed, and then the first through hole 611 is filled to form the first through hole interconnection structure 610, and the second through hole 621 is filled to form the second through hole interconnection structure 620, which is conducive to reducing the difficulty of forming the first through hole interconnection structure 610 and the second through hole interconnection structure 620, thereby improving the quality of the first through hole interconnection structure 610 and the second through hole interconnection structure 620.

[0142] In this embodiment, before forming the first through-hole interconnection structure 610 and the second through-hole interconnection structure 620, a fourth dielectric layer covering the third electrode layer is formed, and the fourth dielectric layer also covers the second dielectric layer exposed by the second opening. Accordingly, in the step of forming the first through-hole 611 and the second through-hole 621, both the first through-hole 611 and the second through-hole 621 need to penetrate the fourth dielectric layer 560.

[0143] In this embodiment, the steps of forming the first through hole 611 and the second through hole 621 include: taking the second dielectric layer 540 as the stop position, forming a first initial through hole 615 (such as a through hole 615) penetrating the fourth dielectric layer 560 and the third electrode layer 550 at the position of the first opening 535. Fig.25 At the position of the second opening 555, a second initial through hole 625 (as shown in FIG. 5 ) penetrating the fourth dielectric layer 560 is formed. Fig.24 ); With the first electrode layer 510 as the stop position, the second dielectric layer 540 and the first dielectric layer 520 at the bottom of the first initial through hole 615 are removed to form the first through hole 611 (as shown in Fig. 27 As shown), with the second electrode layer 530 as the stop position, the second dielectric layer 540 at the bottom of the second initial through hole 625 is removed to form the second through hole 621 (as shown Fig.26 shown).

[0144] Forming the first initial through hole 615 and the second initial through hole 625 first and then forming the first through hole 611 and the second through hole 621 is beneficial to reducing the difficulty of forming the first through hole 611 and the second through hole 621, thereby improving the quality of the first through hole 611 and the second through hole 621, and correspondingly improving the quality of the first through hole interconnection structure 610 and the second through hole interconnection structure 620.

[0145] The first initial through hole 615 and the second initial through hole 625 are formed with the second dielectric layer 540 as the stop position, so that the first initial through hole 615 and the second initial through hole 625 are formed in the same step, thereby reducing the process steps for forming the first initial through hole 615 and the second initial through hole 625 and saving process costs.

[0146] The first through hole 611 is located at the position of the first opening 535 at the top of the electrode protrusion 515, that is, the vertical distance from the bottom of the first initial through hole 615 to the first electrode layer 510 is less different from the vertical distance from the bottom of the second initial through hole 625 to the second electrode layer 530, which is convenient for forming the first through hole 611 and the second through hole 621 in the same step, which is correspondingly conducive to reducing the process steps and saving process costs. In addition, since the materials of the first electrode layer 510 and the second electrode layer 530 are both conductive materials, and the materials of the first dielectric layer 520 and the second dielectric layer 540 are both high-k dielectric materials, it is easy to make the etching selectivity of the first dielectric layer 520 and the first electrode layer 510 less different from the etching selectivity of the second dielectric layer 540 and the second electrode layer 530, thereby further facilitating the formation of the first through hole 611 and the second through hole 621 in the same step.

[0147] It should be noted that the etching selectivity ratio of the third electrode layer 550 to the second dielectric layer 540, and the etching selectivity ratio of the fourth dielectric layer 560 to the second dielectric layer 540 should not be too small. If the etching selectivity ratio of the third electrode layer 550 to the second dielectric layer 540, and the etching selectivity ratio of the fourth dielectric layer 560 to the second dielectric layer 540 are too small, it is not easy to control the etching depth of the first initial through hole 615 and the second initial through hole 625, so that the size and morphology of the first initial through hole 615 and the second initial through hole 625 are not good, and the size and morphology of the first through hole 611 and the second through hole 621 are not good. Therefore, in this embodiment, in the step of forming the first initial through hole 615 and the second initial through hole 625, the etching selectivity ratio of the third electrode layer 550 to the second dielectric layer 540 is greater than 800, and the etching selectivity ratio of the fourth dielectric layer 560 to the second dielectric layer 540 is greater than 800.

[0148] It should also be noted that the etching selectivity ratio of the first dielectric layer 520 to the first electrode layer 510, and the etching selectivity ratio of the second dielectric layer 540 to the second electrode layer 530 should not be too small. If the etching selectivity ratio of the first dielectric layer 520 to the first electrode layer 510, and the etching selectivity ratio of the second dielectric layer 540 to the second electrode layer 530 are too small, it is not easy to control the etching depth of the first through hole 611 and the second through hole 621, so that the size and morphology of the first through hole 611 and the second through hole 621 are likely to be poor. Therefore, in this embodiment, in the step of forming the first through hole 611 and the second through hole 621, the etching selectivity ratio of the first dielectric layer 520 to the first electrode layer 510 is greater than 800, and the etching selectivity ratio of the second dielectric layer 540 to the second electrode layer 530 is greater than 800.

[0149] In this embodiment, the process of forming the first initial through hole 615 and the second initial through hole 625 includes an anisotropic etching process, and the process of forming the first through hole 611 and the second through hole 621 includes an anisotropic etching process.

[0150] The anisotropic etching process has the characteristics of anisotropic etching, the etching is directional, the etching accuracy is high, and the control over the cross-section is better, which is beneficial to improve the size accuracy and morphology accuracy of the first initial through hole 615, the second initial through hole 625, the first through hole 611 and the second through hole 621 in the process of etching to form the first initial through hole 615, the second initial through hole 625, the first through hole 611 and the second through hole 621.

[0151] As an example, the first initial through hole and the second initial through hole are formed by an anisotropic dry etching process, and the first through hole and the second through hole are formed by an anisotropic dry etching process.

[0152] In this embodiment, the first initial through hole 615 and the second initial through hole 625 are formed by an anisotropic dry etching process.

[0153] It should be noted that in the step of forming the first initial through hole 615 and the second initial through hole 625 by using an anisotropic dry etching process, the process time should not be too short or too long. If the process time is too short, it is easy to cause the first initial through hole 615 or the bottom of the second initial through hole 625 to have the residue of the fourth dielectric layer 560; if the process time is too long, it is easy to cause the problem of over-etching, so that the effect of improving the dimensional accuracy and morphological accuracy of the first initial through hole 615 and the second initial through hole 625 is not good. Therefore, in this embodiment, the process time ranges from 30 seconds to 45 seconds.

[0154] In this embodiment, the first through hole 611 and the second through hole 621 are formed by an anisotropic dry etching process.

[0155] It should be noted that in the step of forming the first through hole 611 and the second through hole 621 by using an anisotropic dry etching process, the process time should not be too short or too long. If the process time is too short, it is easy to cause the first dielectric layer 520 to remain at the bottom of the first through hole 611, or the second dielectric layer 540 to remain at the bottom of the second through hole 621; if the process time is too long, it is easy to cause the problem of over-etching, so that the effect of improving the dimensional accuracy and morphological accuracy of the first through hole 611 and the second through hole 621 is not good. Therefore, in this embodiment, the process time ranges from 30 seconds to 45 seconds.

[0156] In this embodiment, during the process of forming the first through hole 611, the first electrode layer 510 (eg, a first portion of the thickness) is removed. Fig.29 In the process of forming the second through hole 621, the second electrode layer 530 of the second portion of thickness is also removed (as shown in FIG. Fig.28 shown).

[0157] In the process of forming the first through hole 611, the first portion of the thickness of the first electrode layer 510 is also removed, and in the process of forming the second through hole 621, the second portion of the thickness of the second electrode layer 530 is also removed, which is beneficial to ensure the contact effect between the first through hole 611 and the first electrode layer 510, that is, the contact effect between the first through hole interconnection structure 610 and the first electrode layer 510, and the contact effect between the second through hole 621 and the second electrode layer 530, that is, the contact effect between the second through hole interconnection structure 620 and the second electrode layer 530, thereby ensuring the electrical connection performance between the first through hole interconnection structure 610 and the first electrode layer 510, and the electrical connection performance between the second through hole interconnection structure 620 and the second electrode layer 530.

[0158] Correspondingly, in the step of forming the first through-hole interconnection structure 610, the first through-hole interconnection structure 610 is also located in the first electrode layer of the first partial thickness; in the step of forming the second through-hole interconnection structure 620, the second through-hole interconnection structure 620 is also located in the first electrode layer of the second partial thickness.

[0159] Specifically, the process of removing the first portion of the thickness of the first electrode layer 510 and removing the second portion of the thickness of the second electrode layer 530 includes an anisotropic etching process.

[0160] The anisotropic etching process has higher etching accuracy, which is beneficial for controlling the etching depth and reducing the probability of over-etching problems.

[0161] As an example, an anisotropic dry etching process is used to remove the first portion of the thickness of the first electrode layer and to remove the second portion of the thickness of the second electrode layer.

[0162] In this embodiment, in the steps of removing the first electrode layer of the first portion thickness and removing the second electrode layer of the second portion thickness by using an anisotropic dry etching process, the process time should not be too short or too long. If the process time is too short, it is easy to ensure that the surface of the first electrode layer 510 and the second electrode layer 530 is not exposed; if the process time is too long, it is easy to reduce the effect of over-etching. Therefore, in this embodiment, the process time ranges from 30 seconds to 45 seconds.

[0163] In this embodiment, along the normal direction of the top surface of the substrate 500, the ratio of the thickness of the first portion to the thickness of the first electrode layer 510 should not be too small or too large. If the ratio is too small, it is easy to ensure that the contact effect between the first through-hole interconnection structure 610 and the first electrode layer 510 is poor; if the ratio is too large, it is easy to increase the probability of over-etching the first electrode layer 510, that is, the probability of the first through-hole 611 penetrating the first electrode layer 510 is increased, and the probability of the first through-hole interconnection structure 610 penetrating the first electrode layer 510 is also increased, thereby increasing the probability of the first through-hole interconnection structure 610 being electrically connected to the structure. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the thickness of the first portion accounts for 50% to 70% of the thickness of the first electrode layer 510. Accordingly, in the step of forming the first through-hole interconnection structure 610, the first through-hole interconnection structure 610 is also located in the first electrode layer 510 with a thickness of 50% to 70%.

[0164] In this embodiment, along the normal direction of the top surface of the substrate 500, the ratio of the thickness of the second part to the thickness of the second electrode layer 530 should not be too large or too small. If the ratio is too small, it is easy to ensure that the contact effect between the second through-hole interconnection structure 620 and the second electrode layer 530 is not good; if the ratio is too large, it is easy to increase the probability of over-etching the second electrode layer 530, that is, the probability of the second through hole 621 penetrating the second electrode layer 530 is increased, and the probability of the second through-hole interconnection structure 620 penetrating the second electrode layer 530 is also increased, thereby increasing the probability of the second through-hole interconnection structure 620 electrically connecting the first electrode layer 110. The effect of reducing the over-etching problem is not good. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the thickness of the second part accounts for 50% to 70% of the thickness of the second electrode layer 530. Accordingly, in the step of forming the second through-hole interconnection structure 620, the second through-hole interconnection structure 620 is also located in the second electrode layer 530 with a thickness of 50% to 70%.

[0165] refer to Fig.32 , Fig.32It is a top view. In this embodiment, after the first through-hole interconnect structure 610 and the second through-hole interconnect structure 620 are formed, the forming method further includes: forming a rewiring structure 570 above the first through-hole interconnect structure 610 and the second through-hole interconnect structure 620, the rewiring structure 570 including a first rewiring structure 571 and a second rewiring structure 572, the first rewiring structure 571 and the second rewiring structure 572 both including a comb handle portion (not marked) and a comb tooth portion (not marked) connected to the comb handle portion; the comb tooth portion of the first rewiring structure 571 and the comb tooth portion of the second rewiring structure 572 are cross-arranged; and the first rewiring structure 571 is connected to the first through-hole interconnect structure 610, and the second rewiring structure 572 is connected to the second through-hole interconnect structure 620.

[0166] The rewiring structure 570 can rewire the first through-hole interconnect structure 610 and the second through-hole interconnect structure 620, and is also convenient for loading the first electrical signal to the first electrode layer 510 and the third electrode layer 550 through the first rewiring structure 571, and loading the second electrical signal to the second electrode layer 530 through the second rewiring structure 572.

[0167] The first rewiring structure 571 and the second rewiring structure 572 both include a comb handle 575 and a comb tooth portion 576 connected to the comb handle 575, and the comb tooth portion 576 of the first rewiring structure 571 and the comb tooth portion 576 of the second rewiring structure 572 are cross-arranged, which is beneficial for simultaneously loading electrical signals to each first through-hole interconnection structure 610 or second through-hole interconnection structure 620 electrically connected thereto through the comb handle 575, and saves the area of ​​the first rewiring structure 571 and the second rewiring structure 572, and correspondingly saves the area of ​​the rewiring structure 570, thereby helping to reduce process costs.

[0168] It should be noted that the semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0169] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A first electrode layer is located on the substrate, and an electrode protrusion is formed on the first electrode layer; A first dielectric layer covering the top and side walls of the electrode protrusion and the first electrode layer covering the side of the electrode protrusion; a second electrode layer covering the first dielectric layer, wherein a first opening is formed in the second electrode layer, and the first opening exposes the first dielectric layer on the top of the electrode protrusion; a second dielectric layer covering the second electrode layer and the first dielectric layer exposed by the first opening; a third electrode layer covering the second dielectric layer, wherein a second opening exposing the top of the second dielectric layer is formed in the third electrode layer, and a projection of the second opening on the substrate and a projection of the first opening on the substrate are located at different positions; a first through-hole interconnection structure, located at the position of the first opening and penetrating the third electrode layer, the second dielectric layer and the first dielectric layer, wherein the first electrode layer and the third electrode layer are electrically connected via the first through-hole interconnection structure; The second through-hole interconnection structure is located at the position of the second opening and penetrates the second dielectric layer. The second electrode layer is electrically connected to the second through-hole interconnection structure.

2. The semiconductor structure according to claim 1, wherein: An initial protrusion is formed on the substrate, the first electrode layer also covers the initial protrusion, and a portion of the first electrode layer located on the initial protrusion serves as the electrode protrusion.

3. The semiconductor structure according to claim 2, wherein: Along a direction perpendicular to the sidewall of the initial protrusion, the width of the initial protrusion ranges from 1 micron to 5 microns.

4. The semiconductor structure according to claim 2, characterized in that The base comprises a substrate and a third dielectric layer located on the substrate, wherein the top of the third dielectric layer has an initial protrusion.

5. The semiconductor structure according to claim 1, wherein: Along the normal direction of the top surface of the substrate, the height of the electrode protrusion accounts for 80% to 95% of the thickness of the second electrode layer on its side.

6. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a fourth dielectric layer covering the third electrode layer and the second dielectric layer exposed by the second opening; The first through-hole interconnect structure and the second through-hole interconnect structure are both located in the fourth dielectric layer.

7. The semiconductor structure according to claim 1 or 6, characterized in that: The electrode protrusions are arranged in a matrix; The second openings are arranged in a matrix, and along the column direction of the matrix, the projections of the electrode protrusions on the substrate and the projections of the second openings on the substrate are arranged alternately, and along the row direction of the matrix, the projections of the electrode protrusions on the substrate and the projections of the second openings on the substrate are staggered; The semiconductor structure also includes: a rewiring structure, located above the first through-hole interconnection structure and the second through-hole interconnection structure, the rewiring structure includes a first rewiring structure and a second rewiring structure, the first rewiring structure and the second rewiring structure both include a comb handle and a comb tooth portion connected to the comb handle; the comb tooth portion of the first rewiring structure and the comb tooth portion of the second rewiring structure are cross-arranged; and the first rewiring structure is connected to the first through-hole interconnection structure, and the second rewiring structure is connected to the second through-hole interconnection structure.

8. The semiconductor structure according to claim 1, wherein: The first through-hole interconnect structure is also located in a first portion of the thickness of the first electrode layer, and along the normal direction of the top surface of the substrate, the first portion of the thickness accounts for 50% to 70% of the thickness of the second electrode layer; The second through hole interconnection structure is also located in a second portion of the thickness of the second electrode layer, and along the normal direction of the top surface of the substrate, the second portion of the thickness accounts for 50% to 70% of the thickness of the second electrode layer.

9. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first electrode layer on the substrate, wherein an electrode protrusion is formed on the first electrode layer; forming a first dielectric layer of the first electrode layer covering the top and side walls of the electrode protrusion and the side of the electrode protrusion; forming a second electrode layer covering the first dielectric layer, wherein a first opening is formed in the second electrode layer, and the first opening exposes the first dielectric layer on the top of the electrode protrusion; forming a second dielectric layer covering the second electrode layer, wherein the second dielectric layer also covers the first dielectric layer exposed by the first opening; forming a third electrode layer covering the second dielectric layer, wherein a second opening is formed in the third electrode layer to expose the top of the second dielectric layer, and a projection of the second opening on the substrate and a projection of the first opening on the substrate are located at different positions; At the position of the first opening, a first through-hole interconnection structure is formed that penetrates the third electrode layer, the second dielectric layer and the first dielectric layer, and the first electrode layer and the third electrode layer are electrically connected through the first through-hole interconnection structure; A second through-hole interconnection structure penetrating the second dielectric layer is formed at the position of the second opening, and the second electrode layer is electrically connected to the second through-hole interconnection structure.

10. The method for forming a semiconductor structure according to claim 9, wherein: In the step of providing the substrate, an initial convex portion is formed on the substrate; In the step of forming the first electrode layer, the first electrode layer also covers the initial protrusion, and a portion of the first electrode layer located on the initial protrusion serves as the electrode protrusion.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing the substrate, the substrate comprises a substrate and a third dielectric layer located on the substrate; Before forming the first electrode layer on the substrate, the third dielectric layer is patterned to form a raised initial protrusion on the remaining thickness of the third dielectric layer.

12. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming the first electrode layer, the electrode protrusions are arranged in a matrix; In the step of forming the third electrode layer, the second openings are arranged in a matrix, and along the column direction of the matrix, the projections of the electrode protrusions on the substrate and the projections of the second openings on the substrate are arranged alternately, and along the row direction of the matrix, the projections of the electrode protrusions on the substrate and the projections of the second openings on the substrate are staggered; After forming the first through-hole interconnection structure and the second through-hole interconnection structure, the forming method further includes: forming a rewiring structure above the first through-hole interconnection structure and the second through-hole interconnection structure, the rewiring structure including the first rewiring structure and the second rewiring structure, the first rewiring structure and the second rewiring structure both including a comb handle portion and a comb tooth portion connected to the comb handle portion; the comb tooth portion of the first rewiring structure and the comb tooth portion of the second rewiring structure are cross-arranged; and the first rewiring structure is connected to the first through-hole interconnection structure, and the second rewiring structure is connected to the second through-hole interconnection structure.

13. The method for forming a semiconductor structure according to claim 9 or 12, characterized in that: After forming the third electrode layer and before forming the first through-hole interconnection structure and the second through-hole interconnection structure, the forming method further includes: forming a fourth dielectric layer covering the third electrode layer, the fourth dielectric layer also covering the second dielectric layer exposed by the second opening; The steps of forming the first through-hole interconnection structure and the second through-hole interconnection structure include: forming a first through-hole penetrating the fourth dielectric layer, the third electrode layer, the second dielectric layer and the first dielectric layer at the first opening position, and forming a second through-hole penetrating the fourth dielectric layer and the second dielectric layer at the second opening position; The first through-hole is filled to form the first through-hole interconnection structure, and the second through-hole is filled to form the second through-hole interconnection structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: The steps of forming the first through hole and the second through hole include: taking the second dielectric layer as the stop position, forming a first initial through hole penetrating the fourth dielectric layer and the third electrode layer at the first opening position; forming a second initial through hole penetrating the fourth dielectric layer at the second opening position; With the first electrode layer as the stop position, the second dielectric layer and the first dielectric layer at the bottom of the first initial through hole are removed to form the first through hole; with the second electrode layer as the stop position, the second dielectric layer at the bottom of the second initial through hole is removed to form the second through hole.

15. The method for forming a semiconductor structure according to claim 14, wherein: In the step of forming the first initial through hole and the second initial through hole, the etching selectivity ratio of the third electrode layer to the second dielectric layer is greater than 800, and the etching selectivity ratio of the fourth dielectric layer to the second dielectric layer is greater than 800; In the step of forming the first through hole and the second through hole, an etching selectivity ratio of the first dielectric layer to the first electrode layer is greater than 800, and an etching selectivity ratio of the second dielectric layer to the second electrode layer is greater than 800.

16. The method for forming a semiconductor structure according to claim 14, wherein: The process of forming the first preliminary through hole and the second preliminary through hole includes an anisotropic etching process, and the process of forming the first through hole and the second through hole includes an anisotropic etching process.

17. The method for forming a semiconductor structure according to claim 13, wherein: In the process of forming the first through hole, a first portion of the thickness of the first electrode layer is also removed; During the process of forming the second through hole, a second portion of the thickness of the second electrode layer is also removed.

18. The method for forming a semiconductor structure according to claim 17, wherein: The process of removing the first portion of the thickness of the first electrode layer and removing the second portion of the thickness of the second electrode layer comprises an anisotropic etching process.

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