Data packet copying method and system for data packet processing pipeline

Abstract

The invention relates to the field of data packet replication, in particular to a data packet replication method and system for a data packet processing pipeline. According to the method, only one part of the data packet needs to be cached, meanwhile, the data packet header vector is analyzed from the data packet and the user-defined general data structure and input into the data packet processing assembly line, and when the data packet header vector is input into the copying module, the copying frequency is obtained by querying the flow table according to the copying identification field; the data packet header vector is subjected to linear-speed copy output through the copy enabling field and the copy frequency, the copy index field is arranged in an inverted order, and finally the data packet header vector and data are recombined through inverse analysis to achieve linear-speed copy output of the data packet. The high-performance data packet copying method is realized, logic resources and storage resources for copying and storing the data packet are reduced, the copying module can flexibly adjust the position in the assembly line, parameterization and linear speed processing of each module are realized, the flexibility and the expandability are realized, and the data packet copying method is suitable for large-scale popularization and application. And network functions and technologies with data packet copying requirements can be met.

Description

Technical Field

[0001] The present invention is applied to the field of FPGA acceleration and data packet replication, and relates to a scenario where data packet replication is required when FPGA performs high-speed data packet processing, and in particular to a data packet replication method and system for a data packet processing pipeline. Background Art

[0002] In the packet processing pipeline, it is usually necessary to go through the matching process and execute the action of the matching result. This structure that executes the corresponding action after matching is called a match action unit (MAU). Different behaviors are achieved by executing different actions of each unit, which involves matching and changing some fields in the packet header vector (PHV) of the packet. Since the storage resources of FPGA chips are relatively scarce, in the process of using FPGA for packet processing, for network functions with replication requirements, such as multicast, caching, redundant transmission, etc., if the data packets are cached in multiple data channels, the consumption of resources will inevitably be huge, and the one-to-many different data channels will also add additional branching logic and back pressure logic, increase the design complexity of the module, and thus consume more logic resources of the chip. This leads to the design of adding a MAU specifically for copying PHVs to the multi-level MAUs in the pipeline. In the packet processing pipeline, the data packet is input into the packet cache module, and the packet header and custom fields form a PHV input pipeline processing. The PHV is copied and updated when passing through the replication module, and the multi-level MAU is cooperated with. The replication information is input into the packet cache before the PHV enters the reverse parsing. The packet cache outputs data of the same cache space multiple times, and reverse parsing is performed with the PHV to achieve the purpose of copying the packet. This can reduce the resource usage of the cached data packet and simplify the replication logic, realizing high-performance packet replication, which is of great significance for the processing of packet replication using FPGA.

[0003] Among the related patents, Chinese patent CN201811644018.X ("Data transmission method and device based on MAC layer data packet replication") replicates the target data packet into multiple copies at the media intervention control MAC layer, and stores the remaining target data packets in the buffer of the MAC layer, increasing the resource occupation of the buffer; Chinese patent CN201210274379.6 ("Multicast message replication method and device") replicates the cache address of the message, reads the corresponding message through the port scheduling cache address and outputs it, but it needs to obtain the total number of replications corresponding to the cache address, and the occupied resources will increase with the increase of the cache address, and only supports multicast replication, and cannot support other types of data packets; Chinese patent CN201210491806.6 ("Data packet fast replication method, data packet reading method") replicates the data packet by segment, and does not replicate the data segment that is the same as the corresponding segment of the original data packet or the corresponding segment of other data packet copies, but this method needs to store the data segments of different generated data packet copies, which occupies additional resources, and judging whether the data segments are the same and reading the data segments will consume additional logic and time. Summary of the invention

[0004] The purpose of the present invention is to address the defects of low data packet replication performance, large resource occupation and lack of flexibility in data packet processing pipelines that require data packet replication. It is necessary to propose a universal data packet replication method to achieve high-performance data packet replication while reducing the occupation of logical resources and storage resources, thereby realizing different network functions with replication requirements.

[0005] To achieve the above-mentioned purpose, the present invention proposes a data packet replication method for a data packet processing pipeline, wherein the method only needs to cache a copy of the data packet, and at the same time, parse the data packet and a custom general data structure to obtain a data packet header vector and input it into the data packet processing pipeline, and when inputting the data packet replication module, query the flow table according to the replication identification field to obtain the number of replications, and output the line-speed replication of the data packet header vector by replicating the enable field and the number of replications, and set the replication index field in reverse order, and finally reorganize the data packet header vector and data through inverse parsing to realize the line-speed replication output of the data packet.

[0006] To achieve the above object, the present invention is implemented through the following technical solutions.

[0007] The present invention proposes a data packet replication method for a data packet processing pipeline, wherein the data packet processing pipeline includes a multi-stage matching action unit; the method includes:

[0008] After the data packet enters the data packet processing pipeline, a copy of the data packet is cached; at the same time, the data packet header vector is parsed through a custom data structure and input into the data packet processing pipeline;

[0009] At any position in the data packet processing pipeline, according to the copy identification field and the copy enable field set by a matching action unit at a certain level before the position, the data packet header vector is copied, and the copied data packet header vector is output in reverse order according to the number of copies;

[0010] The copied data packet header vector and the data obtained from the cached data packet are parsed, and the parsed data packet is output to the data packet processing pipeline to complete the copying of the data packet.

[0011] As one of the improvements of the above technical solution, the data packet header vector is copied according to the copy identification field and the copy enable field set by a matching action unit at a certain level before the position, and the copied data packet header vector is output in reverse order according to the number of copies, which specifically includes:

[0012] Extracting the copy identification field and the copy enable field in the data packet header vector set by a matching action unit at a certain level before the position;

[0013] Use the replication flag field as the key value to query the flow table, obtain the replication count, and replicate the data packet header vector according to the replication count;

[0014] Determine whether to copy the data packet header vector according to the copy enable field;

[0015] While copying the data packet header vector, the copy index field is set, and the copied data packet header vector is output to the next level matching action unit in reverse order according to the number of copies.

[0016] As one of the improvements of the above technical solution, the copy identification field, the copy enable field, the flow table mask and the copy index field are all stored in the data packet header vector.

[0017] As one of the improvements of the above technical solution, the step of copying the data packet header vector according to the number of copies specifically includes:

[0018] Output a copy of the original packet header vector, build a counter at the same time, and enter the number of copies into the counter;

[0019] The corresponding number of data packet header vectors are copied according to the value of the counter. Each time a data packet header vector is copied, the counter is reduced by 1; if the number of copies is 0, no copying is performed.

[0020] As one of the improvements of the above technical solution, when copying the data packet header vector, the next data packet header vector is blocked until the current data packet header vector is copied.

[0021] As one of the improvements of the above technical solution, the counter is updated synchronously with the number of replications, and the counter value is the same as the number of replications. During replication, the counter is decremented, and the replication index field is also decremented. When the counter is 0, it stops blocking the next data packet header vector.

[0022] As one of the improvements of the above technical solution, the blocking of the next data packet header vector is achieved through a counter and back pressure logic control, specifically: when the counter is greater than 0, the input signal of the next data packet header vector cannot reach a handshake agreement with the action unit, and the next data packet header vector is back pressed.

[0023] As one of the improvements of the above technical solution, the parsing of the copied data packet header vector and the cached data packet specifically includes:

[0024] Determine the corresponding packet length field and the copy index field according to the copied data packet header vector;

[0025] Output the corresponding cached data packet according to the packet length field and the copy index field;

[0026] Combine the packet header vector with the cached packet and perform reverse parsing.

[0027] As one of the improvements of the above technical solution, the copied data packet header vector is output at line speed.

[0028] The present invention also designs a data packet replication system for a data packet processing pipeline, the system comprising: a data packet parsing module, a data packet replication module, a data packet cache module and a data reverse parsing module; wherein the data packet replication module is placed at any position in the data packet processing pipeline, and comprises a key value extraction submodule and an action unit submodule; a matching action unit at a certain level before the data packet replication module is provided with a replication identification field and a replication enable field in a data packet header vector;

[0029] The data packet parsing module is used to generate a data packet header vector after the data packet is input into the data packet processing pipeline, and input the data packet into the matching action units at each level, and store the data packet into the data packet buffer module;

[0030] The key value extraction submodule is used to extract the replication identification field as a key value to query the flow table and obtain the number of replications;

[0031] The action unit submodule is used to determine the number of times the data packet header vector is copied according to the number of copies, to set the copy index field when copying the data packet header vector, and to output the data packet header vector in reverse order according to the number of copies to the matching action unit after the data packet copy module; and to block the next data packet header vector when copying the data packet header vector until the current data packet header vector is copied;

[0032] The data packet buffer module is used to output the data packet in the buffer space corresponding to the data packet header vector;

[0033] The data packet reverse parsing module is used to combine and parse the data packet header vector and the cached data packet, and output the data packet to the data packet processing pipeline.

[0034] Compared with the prior art, the present invention has the following advantages:

[0035] 1. The present invention only needs to copy PHV. PHV is not input at line speed before entering the copy module because PHV corresponds to one data packet and the copy module copies and outputs PHV at line speed, thereby achieving high-performance copying.

[0036] 2. The packet replication module set at any position of the packet processing pipeline as the first-level MAU of the packet processing pipeline can flexibly adjust its position in the pipeline and decouple from the previous and next MAUs, thereby improving flexibility;

[0037] 3. The data packet cache module in the system of the present invention only caches the data packet once, which reduces resource usage;

[0038] 4. The present invention can realize the duplication of data packets of different bit widths, flexibly adjust the bit width according to the board scenarios of different resources, thereby changing the performance, and has universality and portability; it can realize the duplication and modification of PHVs of different bit widths, and since PHVs can also be customized, it has flexibility and scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the implementation system of the present invention;

[0040] Figure 2 It is a working diagram of the data packet duplication module of the present invention;

[0041] Figure 3 It is a work flow chart of the implementation system of the present invention. DETAILED DESCRIPTION

[0042] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0043] Example 1

[0044] The purpose of the present invention is to provide a method for replicating PHV in a data packet processing pipeline, thereby improving the performance of data packet replication and reducing the occupation of logic resources and storage resources.

[0045] The method of the present invention comprises:

[0046] When the PHV enters the data packet duplication module, the duplication identification field and duplication enable field have been set by the first-level MAU before the data packet duplication module.

[0047] The replication identification field is used as a key value to obtain the number of replications by querying the flow table in the data packet replication module.

[0048] The data packet replication module determines the number of replications of the data packet header vector according to the number of replications.

[0049] The data packet replication module replicates the data packet header vector according to the replication number.

[0050] As an improvement to the above method, the data packet header vector is copied according to the number of copies; specifically:

[0051] The data packet replication module first outputs a copy of the original PHV and inputs the number of copies into a counter. The data packet replication module replicates the PHV according to the value of the counter. Each time a copy of the PHV is made, the counter is reduced by 1.

[0052] When the data packet replication module replicates the PHV, it also sets the replication index field and outputs it in reverse order according to the number of replications.

[0053] As an improvement to the above method, the setting of the copy index field is completed in reverse order through a counter, and the value of the copy index field is assigned by the counter.

[0054] When the data packet replication module replicates a PHV, it will block the next PHV until the current PHV is replicated.

[0055] As an improvement of the above method, the blocking of the next PHV is controlled by a counter and back pressure logic. When the counter is greater than 0, the input signal of the next PHV cannot reach a handshake agreement with the action unit and is thus back pressured.

[0056] Before the PHV is reverse parsed, the packet length field and the copy index field are input into the data packet cache module to achieve data copy output.

[0057] As an improvement of the above method, the PHV copied by the copy module corresponds to the same data packet cache space as the original PHV.

[0058] As an improvement to the above method, the copy identification field, the copy enable field and the copy index field are all stored in a data packet header vector.

[0059] PHV and data are reverse parsed to achieve the copy output of the data packet.

[0060] Example 2

[0061] The technical solution of the present invention is now described in detail with reference to the accompanying drawings.

[0062] Figure 1 This is a schematic diagram of the implementation system of the present invention. This schematic diagram shows the positions of the data packet parsing module, matching action units at various levels, data packet replication module, data packet reverse parsing module, and data packet cache module in the entire pipeline architecture and the relationship between the modules. After the data packet passes through the data packet parsing module, it is divided into two paths. One path is the PHV signal, which will pass through each level of MAU, participate in matching and execute corresponding actions, and the other path is the original data packet, which will enter the remaining space of the data packet cache. As one of the first-level MAUs, the data packet replication module can flexibly adjust its position in each level of MAU, but there will be a first-level MAU before the data packet replication module to set the corresponding fields for the PHV to cooperate with the normal operation of the data packet replication module. Before the PHV inputs the reverse parsing of the data packet, it will also extract the relevant fields and input them into the data packet cache module, so that the data packet cache module outputs the corresponding data.

[0063] Figure 2 This is a working diagram of the data packet replication module of the present invention. The specific steps are as follows:

[0064] Step 1: After power-on and board reset, the controller sends a flow table configuration signal to the flow table in the data packet replication module, where the matching domain of the flow table is the replication identification field of the PHV, and the corresponding matching result of each table entry is the number of replications, which can be 0.

[0065] Step 2: PHV enters the data packet replication module, and the replication identification field and replication enable field in the current PHV have been set in the matching action unit before the data packet replication module. Among them, the replication identification field is used to match the flow table of the data packet replication module, and the replication enable field is used to enable the replication action.

[0066] Step 3: One path of PHV is input into the data packet header vector queue, and the other path is input into the key value selection module. Since the information stored in PHV will cause a large bus width, using the BRAM resources of the FPGA chip to store PHV will cause a lot of resource waste. Therefore, the shift register resources can be used to form an SRL FIFO as the data packet header vector queue. The key value selection module extracts the copy identification field in PHV and outputs it. The bit width and position of the copy identification field in PHV can be customized by the user.

[0067] Step 4: Copy the identification field and input it into the flow table for matching. If the table entry is hit, the hit signal is set to 1, the valid signal is set to 1, and the result is output together with the number of copies. If the table entry is not hit, the hit signal is set to 0, and the valid signal is set to 1 for output.

[0068] Step 5: If the valid signal on the main interface side of the packet header vector queue is 1 and the back pressure signal on the PHV on the slave interface side of the matching action unit is 1, that is, the main interface side of the packet header vector queue and the PHV on the slave interface side of the matching action unit have reached a handshake condition, and the main interface side of the flow table and the matching slave interface side of the matching action unit have reached a handshake condition, then the hit signal, the number of copies and the packet header vector are synchronously input to the matching action unit. If one of the valid signal on the main interface side of the packet header vector queue, the back pressure signal on the PHV on the slave interface side of the matching action unit, the valid signal on the main interface side of the flow table and the matching slave interface side back pressure signal of the matching action unit is 0, then nothing is done.

[0069] Step 6: The matching action unit first determines the hit signal. If the hit signal is 1, the copy enable is 1, and the number of copies is greater than 0, the number of copies is entered into the counter and the original PHV is output. The value of the counter affects the two sets of back pressure signals from the interface side of the matching action unit through the back pressure logic. When the value of the counter is greater than 0, the two sets of back pressure signals from the interface side will definitely be 0. Then, according to the value of the counter, the corresponding number of PHVs are output. Each time a PHV is output, the copy index field in the PHV is set to the value of the current counter, and the counter is reduced by 1 until the counter is reduced to 0. If the hit signal is 1 and the number of copies is equal to 0, only the original PHV is output. If the hit signal is 1 but the copy enable is 0, only the original PHV is output. If the hit signal is 0, the output port field of the PHV is set, and the corresponding data packet is sent to the controller, so as to notify the controller to update the flow table in time.

[0070] Figure 3 The following is a workflow diagram of the implementation system of the present invention. Combined with the system schematic diagram and the replication module workflow diagram, the workflow of the implementation system of the present invention is now described in detail:

[0071] (1) The data packet enters the data packet parsing module. The data packet parsing module calculates the packet length in the last frame of data entering. If the remaining space in the data packet cache can cache the data packet of the corresponding packet length, the data packet is input into the data packet cache module, and the packet length information is extracted and combined with the custom data structure to form the PHV input pipeline. If the remaining space in the data packet cache is insufficient, the data packet is back-pressed after the remaining space is full, and the data packet continues to be input when there is remaining space in the data packet cache.

[0072] (2) The PHV enters the pipeline, participates in matching and executes corresponding actions through each level of MAU. Before entering the packet replication module, the replication identification field and replication enable field in the PHV have been set by the MAU before the packet replication module.

[0073] (3) The PHV enters the packet replication module and matches the flow table of the packet replication module. If the flow table is not hit, or if the flow table is hit but replication is not required, the PHV is not replicated and the original PHV enters the lower-level MAU. If the flow table is hit and replication is required, the PHV that has not entered the matching action unit is back-pressed, and the matching action unit executes the action of replicating the PHV and modifying the replication index field in reverse order according to the number of replications, and the replicated PHV is output at line speed.

[0074] (4) Before entering the data packet reverse parsing module, the PHV inputs the packet length field and the copy index field in the PHV into the data packet cache module. The data packet cache module outputs the data of the corresponding space according to the packet length field and repeatedly outputs the data according to the copy index field.

[0075] (5) PHV and data enter the packet reverse parsing module and reassemble the data packets for line-speed output.

[0076] In the prior art, in the packet processing pipeline, a packet is copied and output in multiple copies. If a one-input-multiple-output replication method is adopted, more bus resources are required, and more storage resources are used to cache the packets. However, in an FPGA-based packet processing scenario, FPGA resources are scarce, and packet-level replication will consume more logic resources and storage resources, and high-performance replication cannot be achieved.

[0077] Compared with the above problems existing in the prior art, the advantages of the present invention are: a high-performance data packet replication method is implemented in the data packet processing pipeline, which reduces the logical resources and storage resources for replicating and storing data packets. At the same time, the data packet replication module, as one of the first-level matching action units in the pipeline, is decoupled from the matching action units at all levels and the data packet cache, and can flexibly adjust its position in the pipeline. At the same time, each module realizes parameterization and line-speed processing, has flexibility and scalability, and can meet network functions and technologies with data packet replication requirements, such as multicast, caching, redundant transmission, etc.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A data packet replication method for a data packet processing pipeline, wherein the data packet processing pipeline comprises a multi-stage matching action unit; the method comprises: After the data packet enters the data packet processing pipeline, a copy of the data packet is cached; at the same time, the data packet header vector is parsed through a custom data structure and input into the data packet processing pipeline; At any position in the data packet processing pipeline, according to the copy identification field and the copy enable field set by a matching action unit at a certain level before the position, the data packet header vector is copied, and the copied data packet header vector is output in reverse order according to the number of copies; The copied data packet header vector and the data obtained from the cached data packet are parsed, and the parsed data packet is output to the data packet processing pipeline to complete the copying of the data packet.

2. The data packet replication method of the data packet processing pipeline according to claim 1, characterized in that: The method of duplicating the data packet header vector according to the duplication identification field and the duplication enable field set by a matching action unit at a certain level before the position, and outputting the duplicated data packet header vector in reverse order according to the number of duplications, specifically includes: Extracting the copy identification field and the copy enable field in the data packet header vector set by a matching action unit at a certain level before the position; Use the replication flag field as the key value to query the flow table, obtain the replication count, and replicate the data packet header vector according to the replication count; Determine whether to copy the data packet header vector according to the copy enable field; While copying the data packet header vector, the copy index field is set, and the copied data packet header vector is output to the next level matching action unit in reverse order according to the number of copies.

3. The data packet replication method of the data packet processing pipeline according to claim 2, characterized in that: The copy identification field, the copy enable field, the flow table mask and the copy index field are all stored in the data packet header vector.

4. The data packet replication method of the data packet processing pipeline according to claim 2, characterized in that: The step of duplicating the data packet header vector according to the number of duplications specifically includes: Output a copy of the original packet header vector, build a counter at the same time, and enter the number of copies into the counter; The corresponding number of data packet header vectors are copied according to the value of the counter. Each time a data packet header vector is copied, the counter is reduced by 1; if the number of copies is 0, no copying is performed.

5. The data packet replication method of the data packet processing pipeline according to claim 4, characterized in that: When copying the data packet header vector, the next data packet header vector is blocked until the current data packet header vector is copied.

6. The data packet replication method of the data packet processing pipeline according to claim 5, characterized in that: The counter is updated synchronously with the number of replications, and the counter value is the same as the number of replications. During replication, the counter is decremented, and the replication index field is also decremented. When the counter is 0, the next data packet header vector is stopped from being blocked.

7. The data packet replication method of the data packet processing pipeline according to claim 6, characterized in that: The blocking of the next data packet header vector is achieved through counter and back pressure logic control, specifically: when the counter is greater than 0, the input signal of the next data packet header vector cannot reach a handshake agreement with the action unit, and the next data packet header vector is back pressured.

8. The data packet replication method of the data packet processing pipeline according to claim 1, characterized in that: The parsing of the copied data packet header vector and the cached data packet specifically includes: Determine the corresponding packet length field and the copy index field according to the copied data packet header vector; Output the corresponding cached data packet according to the packet length field and the copy index field; Combine the packet header vector with the cached packet and perform reverse parsing.

9. The data packet replication method of the data packet processing pipeline according to any one of claims 1 to 8, characterized in that: The replicated packet header vector is output at line rate.

10. A data packet replication system for a data packet processing pipeline, characterized in that: The system comprises: a data packet parsing module, a data packet duplication module, a data packet caching module and a data reverse parsing module; wherein the data packet duplication module is placed at any position in the data packet processing pipeline, and comprises a key value extraction submodule and an action unit submodule; a certain level of matching action unit before the data packet duplication module is provided with a duplication identification field and a duplication enable field in a data packet header vector; The data packet parsing module is used to generate a data packet header vector after the data packet is input into the data packet processing pipeline, and input the data packet into the matching action units at each level, and store the data packet into the data packet buffer module; The key value extraction submodule is used to extract the replication identification field as a key value to query the flow table and obtain the number of replications; The action unit submodule is used to determine the number of times the data packet header vector is copied according to the number of copies, to set the copy index field when copying the data packet header vector, and to output the data packet header vector in reverse order according to the number of copies to the matching action unit after the data packet copy module; and to block the next data packet header vector when copying the data packet header vector until the current data packet header vector is copied; The data packet buffer module is used to output the data packet in the buffer space corresponding to the data packet header vector; The data packet reverse parsing module is used to combine and parse the data packet header vector and the cached data packet, and output the data packet to the data packet processing pipeline.

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