Signal channel, module substrate including signal channel, and semiconductor system

Abstract

A signal channel, a module substrate including the signal channel, and a semiconductor system are disclosed. A signal channel according to an embodiment of the present disclosure includes a plurality of signal lines disposed on a plurality of layers spaced apart from each other in a first direction and connecting a first point and a second point to each other. A plurality of segments are defined between a first point and a second point. A first signal line disposed on a first layer of the plurality of layers in a first section of the plurality of sections is electrically connected to a second signal line disposed on a second layer of the plurality of layers in a second section of the plurality of sections.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0125791 filed in the Korean Intellectual Property Office on September 20, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to semiconductors, and more particularly, to a signal channel, a module substrate including the signal channel, and a semiconductor system including the signal channel. Background Art

[0003] When signal lines on multiple layers of a module substrate are used as signal channels to increase throughput, the signal channels may have different characteristics from each other due to differences in specifications of the various signal lines. Different characteristics between signal channels included in the same channel group may result in differences in single-bit response characteristics (or single-bit response characteristics) and crosstalk response characteristics of the signal channels. Summary of the invention

[0004] A signal channel for solving such a technical goal according to an embodiment of the present disclosure includes: a plurality of signal lines, which are arranged on a plurality of layers spaced apart from each other in a first direction and connect a first point and a second point to each other, wherein a plurality of segments are arranged between the first point and the second point, wherein a first signal line on a first layer of the plurality of layers in a first segment among the plurality of segments is electrically connected to a second signal line on a second layer of the plurality of layers in a second segment among the plurality of segments.

[0005] A module substrate according to an embodiment of the present disclosure includes: a substrate body including a dielectric material and including a plurality of layers spaced apart from each other in a first direction; and a plurality of signal lines arranged on the plurality of layers, connecting a first point and a second point and having a loop structure, wherein a plurality of segments are arranged between the first point and the second point, and a first signal line on a first layer of the plurality of layers in a first segment of the plurality of segments is electrically connected to a second signal line on a second layer of the plurality of layers in a second segment of the plurality of segments.

[0006] A semiconductor system according to an embodiment of the present disclosure includes: a plurality of stacked memory dies; a buffer die below the plurality of memory dies; a memory controller; and an interposer including a plurality of signal lines connecting a first point of the memory controller and a second point of the buffer die, wherein a plurality of segments are set between the first point and the second point, and a first signal line on a first layer of the plurality of layers set in a first segment of the plurality of segments is electrically connected to a second signal line on a second layer of the plurality of layers set in a second segment of the plurality of segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a semiconductor system according to an embodiment of the present disclosure.

[0008] Figure 2 is a cross-sectional view of a semiconductor system according to an embodiment of the present disclosure.

[0009] Figure 3 It is a schematic diagram of the signal channel.

[0010] Figure 4 yes Figure 3 A cross-sectional view of a signal channel.

[0011] Figure 5 is a schematic diagram of a signal channel according to an embodiment of the present disclosure.

[0012] Fig. 6A , Figure 6B and Figure 6C is a cross-sectional view of a signal channel according to an embodiment of the present disclosure.

[0013] Figure 7 It is a schematic diagram of the signal channel.

[0014] Figure 8 yes Figure 7 A cross-sectional view of a signal channel.

[0015] Fig. 9 and Fig.10 It is shown by Figure 7 A graph of the signal measured through the signal channel.

[0016] Fig.11 is a schematic diagram of a signal channel according to an embodiment of the present disclosure.

[0017] Fig.12 is a table representing signal lines allocated to signal channels according to an embodiment of the present disclosure.

[0018] Fig.13A and Fig. 13B Signal lines allocated to signal channels according to an embodiment of the present disclosure are shown.

[0019] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D is a cross-sectional view of a signal channel according to an embodiment of the present disclosure.

[0020] Fig.15 A method of connecting signal lines according to an embodiment of the present disclosure is shown.

[0021] Fig.16 and Fig.17 It is shown by Fig.12A graph of the signal measured through the signal channel.

[0022] Fig.18A and Fig.18B is a heat map showing the similarity of signal channel responses according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In the following detailed description, specific embodiments of the present invention have been shown and described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0024] Although each of the accompanying drawings may represent one or more specific embodiments of the present disclosure drawn to scale so that relative lengths, thicknesses, and angles can be inferred therefrom, it should be understood that the present invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​may be changed within the spirit and scope of the present disclosure, for example, to allow for manufacturing limitations, etc. Throughout the specification and drawings, the same reference numerals may designate the same elements. In the flowcharts described with reference to the accompanying drawings, the order of operations may be changed, several operations may be merged, some operations may be divided, and specific operations may not be performed.

[0025] In this specification, unless an explicit expression such as "one" or "single" is used, an expression described in the singular may be interpreted as singular or plural. In this specification, terms including ordinal numbers (such as first, second, etc.) may be used to describe various elements, but the elements are not necessarily limited by the terms. Terms are used to distinguish one element from another.

[0026] Figure 1 is an exemplary block diagram of a semiconductor system according to an embodiment of the present disclosure.

[0027] Reference Figure 1 , the semiconductor system 100 includes a memory device 110 and a memory controller 120 .

[0028] The memory device 110 and the memory controller 120 are electrically connected through a memory interface, and thus signals can be exchanged through the memory interface. In an embodiment of the present disclosure, the memory device 110 and the memory controller 120 can send and receive DQ signals to each other using a serial interface method. The memory controller 120 can access the memory device 110 according to a request from an external host to the semiconductor system 100. The memory controller 120 can communicate with the host through various protocols. For example, the memory controller 120 can communicate with the external host through a parallel interface. In an embodiment of the present disclosure, the memory controller 120 can communicate with the host through a serial interface.

[0029] The memory device 110 includes a memory cell array 111 and an interface circuit 112. The memory cell array 111 includes a plurality of memory cells electrically connected to a plurality of rows and a plurality of columns. The interface circuit 112 may receive a signal sent from outside the memory device 110 (i.e., a memory controller 120, etc.), or may output a signal from the memory device 110 to the outside. For example, the interface circuit 112 may receive data sent from the memory controller 120, and may store the data in the memory cell array 111 or output the data stored in the memory cell array 111 to the memory controller 120. The interface circuit 112 may include a transmitter 113 and a receiver 114.

[0030] The transmitter 113 may output a signal generated by the memory device 110. The transmitter 113 may generate a multi-level signal based on a logic state including a plurality of bits. For example, the transmitter 113 may use a PAM4 signaling method (or other types of multi-level signaling methods) to generate a signal having an amplitude corresponding to the logic state. The transmitter 113 may receive data using a single input line. In an embodiment of the present disclosure, the transmitter 113 may generate a binary level signal (e.g., a non-return to zero (NRZ) signal). The transmitter 113 may generate a multi-level signal using single-ended signaling. The transmitter 113 may receive data from the memory cell array 111 and output a data input / output signal based on the data. The transmitter 113 may output a signal in parallel through a signal channel 130. When the transmitter 113 outputs a signal to the signal channel 130 in parallel, a transition caused by the signal may occur in the signal channel 130. For example, when a transition occurs in a channel adjacent to a target channel, the signal transmission of the target channel may be interrupted. Such a phenomenon may be referred to as crosstalk. The transmitter 113 of the memory device 110 is then equivalent to the transmitter 122 of the memory controller 120 , and therefore, the description of the transmitter 122 of the memory controller 120 refers to the above description.

[0031] The signal channel 130 may be a path through which the memory device 110 and the memory controller 120 are physically or electrically connected. For example, the signal channel 130 may be implemented using a through silicon via (also referred to as a through silicon via, TSV), a trace, or a coaxial cable. In an embodiment of the present disclosure, each signal channel 130 may be a trace disposed in an interposer disposed between the memory cell array 111 and the memory controller 120. When the number of signal channels 130 increases, the amount of data transmitted to the memory device 110 (i.e., data throughput) may be increased without increasing the data transmission speed. In order to increase the number of signal channels 130, signal lines disposed on several layers within the interposer may be used as the signal channels 130. In an embodiment of the present disclosure, each signal channel 130 may include signal lines on several layers in the interposer. The length of each signal line included in each signal channel 130 on the layer may be substantially equal. For example, one of the signal channels 130 may include a first signal line on a first layer in the interposer and a second signal line on a second layer in the interposer different from the first layer. In this case, the length of the first signal line and the length of the second signal line may be substantially equal. Each signal channel 130 may be referred to as a wide system interface. In an embodiment of the present disclosure, one or more of the signal channels 130 may have a unidirectional direction, or one or more of the signal channels 130 may be bidirectional.

[0032] The receiver 114 may determine the logic state of the symbol expression of the multi-level signal received using the signal channel 130. In some cases, the receiver 114 may determine the amplitude of the received multi-level signal. Based on the determined amplitude, the receiver 114 may determine the logic state expressed by the multi-level signal. The receiver 114 may output data using a signal output line. In an embodiment of the present disclosure, the receiver 114 may decode a binary level signal (e.g., an NRZ signal). For example, the receiver 114 may receive a DQ signal provided from the memory controller 120, and generate data by decoding the received DQ. The receiver 114 may output the generated data to the memory cell array 111. Since the receiver of the memory device 110 is substantially equivalent to the receiver 123 of the memory controller 120, the description of the receiver 123 of the memory controller 120 will refer to the above description.

[0033] The memory controller 120 may control the memory operation of the memory device 110 by providing a control signal to the memory device 110. The control signal may include a command and an address. In some embodiments, the memory controller 120 may control the memory operation (such as access, reading, or writing to the memory cell array 111) by providing a command and an address to the memory device 110. According to a read operation, data may be sent from the memory cell array 111 to the memory controller 120 as a DQ signal, and according to a write operation, data may be sent from the memory controller 120 to the memory cell array 111 as a DQ signal.

[0034] The command may include an activation command, a read / write command, and a refresh command. The activation command may be a command for changing a target row of the memory cell array 111 to an active state to write data into the memory cell array 111 or read data from the memory cell array 111. In response to the activation command, the memory cells of the target row may be activated (e.g., driven). The read / write command may be a command for operating a read or write operation in the target memory cell of the row changed to the active state. The refresh command may be a command for performing a refresh operation in the memory cell array 111.

[0035] The interface circuit 121 of the memory controller 120 may output data as DQ to the memory device 110 or receive DQ output from the memory device 110. The interface circuit 121 may include a transmitter 122 and a receiver 123.

[0036] The memory device 110 may be a semiconductor device-based storage device. In an embodiment of the present disclosure, the memory device 110 may include a dynamic random access memory (DRAM). In an embodiment of the present disclosure, the memory device 110 may include other volatile memory devices or non-volatile memory devices in which the transmitter 113 or the receiver 114 is used.

[0037] In the following, reference will be made to Figure 2 The structure of the semiconductor system 100 is described.

[0038] Figure 2 is a schematic diagram of a semiconductor system according to an embodiment of the present disclosure.

[0039] Reference Figure 2, the semiconductor system 200 includes a memory controller 220 and a memory device 210. The semiconductor system 200 may further include an interposer 230 connecting the memory controller 220 and the memory device 210. The memory device 210 and the memory controller 220 may be disposed on the interposer 230. The memory controller 220 and the memory device 210 may be placed on the same plane (for example, their respective lower surfaces and / or their respective upper surfaces may be aligned in the horizontal direction). Such a structure of the semiconductor system 200 may be referred to as a 2.5-dimensional (D) packaging structure. The semiconductor system 200 may further include a packaging substrate 240 provided with the interposer 230.

[0040] The memory device 210 may be a high bandwidth memory (HBM) device. The memory device 210 may provide more bandwidth for data transfer per unit of power used in the memory device 210. The memory device 210 may be a DRAM device.

[0041] The memory device 210 may include a buffer die (or a base die) 214 and at least one of core dies (or memory dies, decks) 211a to 211d disposed on the buffer die 214. Signal transmission between the buffer die 214 and the core dies 211a to 211d may be performed through various through silicon vias (TSVs) 213. For example, first bumps 212 may be formed between the stacked core dies 211a to 211d and between the core die 211a and the buffer die 214, respectively, and TSVs 213 penetrating the core dies 211a to 211d may be formed between the first bumps 212.

[0042] The second bump 215 may be disposed between the memory device 210 and the interposer 230. In an embodiment of the present disclosure, the buffer die 214 and the interposer 230 may be combined using the second bump 215.

[0043] The buffer die 214 may include a plurality of buffers electrically connected to the signal line 231. The plurality of buffers may output signals output to the signal channel through the signal line 231.

[0044] The third bump 221 may be disposed between the memory controller 220 and the interposer 230. The first bump 212, the second bump 215, and the third bump 221 may be micro bumps. The memory controller 220 may output a signal to the memory device 210 through the signal line 231. For example, the memory controller 220 may send a command signal and an address signal to the memory device 210 through the signal line 231, and may exchange a DQ signal with the memory device 210. The memory controller 220 may be included in a graphics processing unit (GPU) die, a central processing unit (CPU) die, or a system on chip (SoC) die.

[0045] The interposer 230 may include a plurality of layers L1 to L4 and a signal line 231 disposed on the plurality of layers L1 to L4. The fourth bump 233 may be disposed on a lower surface of the interposer 230 (eg, between the interposer 230 and the package substrate 240).

[0046] The signal lines 231 may each be used as a signal channel. The signal channels may form a signal channel group. A signal channel group may be formed by signal lines 231 adjacent to each other. Signal lines 231 adjacent to each other may be arranged on multiple layers L1 to L4. For example, eight data signal channels that output 8-bit data signals may form a signal channel group, and each data signal channel may be formed by signal lines on different layers L1 to L4. However, there may be differences in specifications (e.g., differences in physical arrangement and / or settings) between the various signal lines 231 on multiple layers L1 to L4. Therefore, the signal transmission characteristics between the signal channels are different due to the different specifications of the signal lines 231. The different characteristics between the signal channels included in the same signal channel group result in differences in the single-bit response characteristics and crosstalk response characteristics of the signal channels. For example, due to the difference in specifications between the signal line arranged on layer L1 and transmitting the DQ0 signal and the signal line arranged on layer L3 and transmitting the DQ1 signal, a difference in response characteristics between the DQ0 signal and the DQ1 signal may occur. Reference will be made to Figure 3 and Figure 4 Signal channels and signal lines according to embodiments of the present disclosure are described.

[0047] Figure 3 is a schematic diagram of a signal channel 300, and Figure 4 yes Figure 3 A cross-sectional view of a signal channel.

[0048] Reference Figure 3 , the signal channel group may include three signal channels CH0, CH1, and CH2. The signal channels CH0, CH1, and CH2 are single-ended channels, and they may electrically connect the first points SP0, SP1, and SP2 and the second points EP0, EP1, and EP2 to each other. One signal channel (CH0, CH1, or CH2) may be implemented by one signal line (310a, 310b, or 310c), respectively. Figure 3 , it is assumed that the signal lines 310a, 310b, and 310c between the first points SP0, SP1, and SP2 and the second points EP0, EP1, and EP2 have specific specifications. The signal lines 310a, 310b, and 310c may have different specifications. Therefore, a difference in response characteristics may occur between signals transmitted through the signal channels CH0, CH1, and CH2.

[0049] Refer to Figure 4, signal lines 420, 421, and 422 that transmit signals may be disposed on a plurality of layers L1 and L2 in the interposer 400. For example, the signal line 420 corresponding to the channel CH0 may be disposed on the layer L1, and the signal lines 421 and 422 corresponding to the channels CH1 and CH2 may be disposed on the layer L2. Reference lines 411, 412, 413, and 414 to which a reference voltage is applied may be disposed on a plurality of layers L1 and L2 within the interposer 400. The signal lines 420, 421, and 422 and the reference lines 411, 412, 413, and 414 may extend along the Y-axis direction. The reference lines 411, 412, 413, and 414 may be disposed around the signal lines 420, 421, and 422 that form one signal channel group. For example, on the same layer L1, the reference lines 411 and 412 may be disposed around the signal line 420 in the X-axis direction. For example, on the same layer L1, the signal line 420 may be disposed between the reference lines 411 and 412. On the same layer L2, the reference lines 413 and 414 may be disposed around the signal lines 421 and 422 in the X-axis direction. For example, on the same layer L2, the signal lines 421 and 422 may be disposed between the reference lines 413 and 414. The reference voltage applied to the reference lines 411, 412, 413, and 414 may be a ground voltage GND.

[0050] The interposer 400 may further include a first reference plate 410 to which a reference voltage is applied above the layers L1 and L2, and a second reference plate 415 to which a reference voltage is applied below the layers L1 and L2. The first reference plate 410 and the second reference plate 415 are formed of a metal to which a reference voltage is applied, and a space between the first reference plate 410 and the second reference plate 415 may be filled with one or more dielectrics. The reference voltage applied to the first reference plate 410 and the second reference plate 415 may be a ground voltage GND. In an embodiment of the present disclosure, the interposer 400 may not include the first reference plate 410 and the second reference plate 415, or may include only one of the first reference plate 410 and the second reference plate 415.

[0051] The signal line 420 may form capacitive couplings Cg1, Ct1, and Cx1 with the first reference plate 410, the reference lines 411 and 412, and the signal lines 421 and 422, respectively. The signal line 421 may form capacitive couplings Cg2, Ct2, Ct3, Cx1, and Cx2 with the second reference plate 415, the reference lines 412 and 414, and the signal lines 420 and 422, respectively. The signal line 422 may form capacitive couplings Cg2, Ct2, Ct3, Cx1, and Cx2 with the second reference plate 415, the reference lines 411 and 413, and the signal lines 420 and 421, respectively. The thickness d1 of the signal line 420 and the reference lines 411 and 412 on the layer L1 in the Z-axis direction and the thickness d2 of the signal lines 421 and 422 and the reference lines 413 and 414 on the layer L2 in the Z-axis direction may be different from each other. The widths of the reference lines 412 and 414 and the signal lines 420 and 422 in the X-axis direction may be different from each other. The distance e1 between the signal line 420 and the first reference plate 410 and the distance e2 between the signal lines 421 and 422 and the second reference plate 415 may be different from each other. For example, since the signal lines 420, 421 and 422 have different thicknesses and / or widths, the resistivities of the signal lines 420, 421 and 422 may be different from each other. In addition, the signal line 420 and the signal line 422 may have different capacitance values ​​according to the capacitive coupling formed with the adjacent reference lines, signal lines and / or reference plates. Due to the difference in the specifications of the signal lines 420, 421 and 422, a difference in response characteristics may occur between the signals transmitted through the signal channels CH0, CH1 and CH2.

[0052] In an embodiment of the present disclosure, three signal channels CH0, CH1 and CH2 in a signal channel group may be implemented by signal lines having a cyclic structure. As used herein, the phrase "cyclic structure" may indicate that signal lines are twisted and / or woven with each other so that they exhibit a repeated arrangement in which they take turns to occupy relative positions. The signal lines having a cyclic structure in the signal channel group may include signal lines included in a closed plane having a maximum area among three or more signal lines among the signal lines of the signal channel group. For example, in the case where three signal lines 420, 421 and 422 on an XZ plane are points on a plane, a closed plane may be formed by a virtual straight line including two of the three points. Since the closed plane has the largest area, the three signal lines 420, 421 and 422 included in the closed plane may have a cyclic structure. The closed plane may be a closed figure composed of virtual straight lines. Since a closed plane is formed by virtual straight lines connecting specific points of signal lines on the XZ plane, if a signal channel group includes four or more signal lines and three of the four or more signal lines are not located on a virtual straight line, multiple closed planes can be formed.

[0053] In one embodiment, in a signal channel, one signal channel implemented using a signal line having a loop structure may include signal lines 231 on a plurality of layers L1 to L4. For example, the signal channel may include a signal line disposed on layer L1, a signal line disposed on layer L2, a signal line disposed on layer L3, and a signal line disposed on layer L4. For example, each of the signal lines 231 may be electrically connected to each of the other signal lines 231 at a plurality of connection portions 232. In addition, at least one of the signal lines 231 may be electrically connected in the plurality of connection portions 232 to a signal line disposed on a different layer among the signal lines 231. For example, in the connection portion 232, among the signal lines 231, the signal line disposed on layer L1 may be electrically connected to the signal line disposed on layer L2, the signal line disposed on layer L2 may be electrically connected to the signal line disposed on layer L3, the signal line disposed on layer L3 may be electrically connected to the signal line disposed on layer L4, and the signal line disposed on layer L4 may be electrically connected to the signal line disposed on layer L1. For example, the position of the signal line corresponding to each signal channel may be changed in the connection portion 232. Although it has been described above that the signal lines 231 arranged on the four layers L1 to L4 are electrically connected to different signal lines respectively in the connecting portion 232, some signal lines may not be electrically connected to different signal lines. In some embodiments, the signal lines included in one signal channel may have substantially the same length. Since each signal channel includes at least one signal line with different specifications, substantially equivalent response characteristics of signals transmitted through the signal channels can be obtained. For example, when all signal channels implemented with signal lines having a cyclic structure in one signal channel group include all signal lines having equal lengths on which all signal channels can be arranged, the difference in response characteristics that may occur due to the difference in signal line specifications between one signal channel and another signal channel can be minimized.

[0054] The package substrate 240 may be combined with other components using one or more solder balls 241 .

[0055] Figure 5 is a schematic diagram of a signal channel 500 according to an embodiment of the present disclosure.

[0056] Reference Figure 5 , the signal channel group may include three signal channels CH0, CH1, and CH2 implemented with a signal line having a loop structure. The signal channels CH0, CH1, and CH2 may be single-ended channels, and the first points SP0, SP1, and SP2 may be electrically connected to the second points EP0, EP1, and EP2. Figure 5, it is assumed that the signal lines 510a, 510b, and 510c between the first points SP0, SP1, and SP2 and the second points EP0, EP1, and EP2 have specific specifications. The signal lines 510a, 510b, and 510c may have different specifications. A plurality of sections 530a, 530b, and 530c may be provided between the first points SP0, SP1, and SP2 and the second points EP0, EP1, and EP2. In an embodiment of the present disclosure, the number of the plurality of sections 530a, 530b, and 530c may be an integer multiple of the number of the signal lines 510a, 510b, and 510c having a cyclic structure.

[0057] One signal channel CH0, CH1 or CH2 may be implemented with a plurality of signal lines 510a, 510b and 510c. For example, the signal channel CH0 connecting the first point SP0 and the second point EP0 may include a first signal line 510a electrically connected to the first point SP0 in the first section 530a, a second signal line 510b in the second section 530b, and a third signal line 510c in the third section 530c. The third signal line 510c of the third section 530c may be electrically connected back to the second point EP0. The length P1 of the first section 530a, the length P2 of the second section 530b, and the length P3 of the third section 530c may be substantially equal. For example, the length of each of the three signal lines included in the first signal channel CH0 may be substantially equal to each other. The connecting portions 520a, 520b, and 520c may be arranged in response to the sections 530a, 530b, and 530c, respectively. In each of the connection parts 520a, 520b, and 520c, each of the signal lines 510a, 510b, and 510c may be electrically connected to different signal lines 510a, 510b, and 510c. For example, in the connection part 520a, the first signal line 510a may be electrically connected to the second signal line 510b, the second signal line 510b may be electrically connected to the third signal line 510c, and the third signal line 510c may be electrically connected to the first signal line 510a. The length M1 of each of the connection parts 520a, 520b, and 520c may be shorter than the lengths P1, P2, and P3 of the corresponding sections 530a, 530b, and 530c.

[0058] Each of the signal channels CH0, CH1, and CH2 implemented with a signal line having a loop structure includes at least one of the signal lines 510a, 510b, and 510c having different specifications, so that substantially equivalent response characteristics of signals transmitted through the signal channels CH0, CH1, and CH2 can be obtained. When the signal channels CH0, CH1, and CH2 implemented with a signal line having a loop structure and included in one signal channel group each include "signal lines 510a, 510b, and 510c corresponding to the signal channels CH0, CH1, and CH2 having equal lengths P1, P2, and P3," a difference in response characteristics that may occur due to a difference in signal line specifications between one signal channel and another signal channel can be minimized. Fig. 6A , Figure 6B and Figure 6C describe Figure 5 The structure of the signal channel.

[0059] Fig. 6A , Figure 6B and Figure 6C A cross-sectional view of a signal channel according to an embodiment of the present disclosure is shown.

[0060] exist Fig. 6A , Figure 6B and Figure 6C , the XZ plane of the signal channels in each section 530a, 530b, and 530c is shown by a cross-sectional view. For example, Fig. 6A A cross-sectional view of the XZ plane of the interposer 600a including the signal channels CH0, CH1 and CH2 in the section 530a is shown, Figure 6B A cross-sectional view of the XZ plane of the interposer 600b including the signal channels CH0, CH1 and CH2 in the section 530b is shown, and Figure 6C A cross-sectional view of an XZ plane of interposer 600 c including signal channels CH0 , CH1 , and CH2 in section 530 c is shown.

[0061] Reference Fig. 6A , signal lines 620a, 621a, and 622a that transmit signals may be disposed on layers L1 and L2 in the interposer 600a. Reference lines 611, 612, 613, and 614 may be disposed around the signal lines 620a, 621a, and 622a that form one signal channel group. For example, the reference lines 611 and 612 may be disposed around the signal line 620a in the X-axis direction on the same layer L1, and the signal lines 621a and 622a may be disposed between the reference lines 613 and 614 on the same layer L2. The interposer 600a may include a first reference plate 610 to which a reference voltage is applied above the layers L1 and L2, and a second reference plate 615 to which a reference voltage is applied below the layers L1 and L2.

[0062] In the section 530 a , the signal channel CH0 may include a first signal line 620 a , the signal channel CH1 may include a second signal line 621 a , and the signal channel CH2 may include a third signal line 622 a .

[0063] Reference Figure 6B , in the section 530b, the signal channel CH0 may include the second signal line 621b, the signal channel CH1 may include the third signal line 622b, and the signal channel CH2 may include the first signal line 620b.

[0064] Reference Figure 6C , in the section 530c, the signal channel CH0 may include the third signal line 622c, the signal channel CH1 may include the first signal line 620c, and the signal channel CH2 may include the second signal line 621c.

[0065] In one embodiment, each of the signal channels CH0, CH1, and CH2 may include signal lines 620a, 621b, 622c or 620b, 621c, 622a or 620c, 621a, 622b on multiple layers (L1 and L2). Therefore, according to an embodiment of the present disclosure, substantially equivalent response characteristics of signals transmitted through the signal channels CH0, CH1, and CH2 may be obtained.

[0066] Figure 7 is a schematic diagram of the signal channel, and Figure 8 yes Figure 7 A cross-sectional view of a signal channel.

[0067] Reference Figure 7 , the signal channel group may include nine signal channels CH0 to CH8. The signal channels CH0 to CH8 may be single-ended channels, respectively, and may electrically connect the first points SP0 to SP8 and the second points EP0 to EP8 to each other, respectively. One signal channel (CH0, ..., or CH8) may be implemented by one signal line (710a, ..., or 710i). Figure 7 , it is assumed that each of the signal lines 710a to 710i between the first points SP0 to SP8 and the second points EP0 to EP8 has a specific specification. The signal lines 710a to 710i may have different specifications. Therefore, a difference in response characteristics may occur between signals transmitted through the signal channels CH0 to CH8.

[0068] Reference Figure 8, signal lines 820 to 828 transmitting signals may be disposed on a plurality of layers L1, L2, and L3 in the interposer 800. For example, signal lines 820 to 822 corresponding to channels CH0 to CH2, respectively, may be disposed on layer L1, signal lines 823 to 825 corresponding to channels CH7, CH8, and CH3, respectively, may be disposed on layer L2, and signal lines 826 to 828 corresponding to channels CH6, CH5, and CH4, respectively, may be disposed on layer L3. Reference lines 811 to 816 to which reference voltages are applied may be disposed on layers L1, L2, and L3 in the interposer 800. The signal lines 820 to 828 and the reference lines 811 to 816 may extend in the Y-axis direction. The reference lines 811 to 816 may be disposed around the signal lines 820 to 828 forming one signal channel group. For example, the reference lines 811 and 812 may be disposed around the signal lines 820 and 822 in the X-axis direction on the same layer L1, the reference lines 813 and 814 may be disposed around the signal lines 823 and 825 in the X-axis direction on the same layer L2, and the reference lines 815 and 816 may be disposed around the signal lines 826 and 828 in the X-axis direction on the same layer L3. For example, on the same layer L1, L2, or L3, the signal lines 820, 821, and 822, or the signal lines 823, 824, and 825, or the signal lines 826, 827, and 828 may be disposed between the reference lines 811 and 812, between the reference lines 813 and 814, or between the reference lines 815 and 816. The reference voltage applied to the reference lines 811 to 816 may be a ground voltage GND.

[0069] The interposer 800 may include a first reference plate 810 to which a reference voltage is applied above the layers L1, L2, and L3, and a second reference plate 817 to which a reference voltage is applied below the layers L1, L2, and L3. The first reference plate 810 and the second reference plate 817 may be formed of a metal to which a reference voltage is applied, and a space between the first reference plate 810 and the second reference plate 817 may be filled with one or more dielectrics. The reference voltage applied to the first reference plate 810 and the second reference plate 817 may be a ground voltage GND.

[0070] The signal line 820 may form capacitive couplings Cg11, Ct11, Cx12, Ct11, Cx22, and Cx12 with the first reference plate 810, the reference lines 811 and 813, and the signal lines 821, 823, and 824. The signal line 823 may form capacitive couplings Cx12, Ct22, Cx23, Cx22, Cx12, Ct22, Cx33, and Cx23 with the reference lines 811, 813, and 815, and the signal lines 820, 821, 824, 826, and 827. The signal line 826 may form capacitive couplings Cg33, Cx23, Ct33, Cx33, Cx23, and Ct33 with the second reference plate 817, the reference lines 813 and 815, and the signal lines 823, 824, and 827.

[0071] In an embodiment of the present disclosure, nine signal channels CH0 to CH8 in a signal channel group may be implemented by a signal line having a loop structure. The signal line having a loop structure in the signal channel group may include a signal line included in a closed plane having the largest area among the closed planes formed by three or more signal lines in the signal channel group. For example, in the case where nine signal lines 820 to 828 on the XZ plane are points on the plane, a closed plane may be formed by a virtual straight line including two of the eight points. Since the closed plane formed by the eight signal lines 820, ..., 823, 825, ..., 828 has the largest area among the closed planes, the eight signal lines 820, ..., 823, 825, ..., 828 may have a loop structure.

[0072] At least one of the thickness h1 of the signal lines 820, 821, and 822 and the reference lines 811 and 812 in the Z-axis direction on the layer L1, the thickness h2 of the signal lines 823, 824, and 825 and the reference lines 813 and 814 in the Z-axis direction on the layer L2, and the thickness h3 of the signal lines 826, 827, and 828 and the reference lines 815 and 816 in the Z-axis direction on the layer L3 may be different from the other two thicknesses. For example, since the signal lines 820, ..., and 828 have different thicknesses, the signal lines 820, ..., and 828 may have different resistivities. The distance g1 between the signal lines 820, 821, and 822 and the first reference plate 810 in the Z-axis direction and the distance g4 between the signal lines 826, 827, and 828 and the second reference plate 817 in the Z-axis direction may be different from each other. The distance g2 between the signal lines 820, 821, and 822 and the signal lines 823, 824, and 825 in the Z-axis direction and the distance g3 between the signal lines 823, 824, and 825 and the signal lines 826, 827, and 828 in the Z-axis direction may be different from each other. For example, the signal lines 820, 821, 822 or 823, 824, 825 or 826, 827, 828 may have different capacitance values ​​according to the capacitive coupling formed with the adjacent reference lines, signal lines, and / or reference plates. Due to the difference in specifications of these signal lines 820, ..., and 828, a difference in response characteristics may occur between the signals transmitted through the signal channels CH0, ..., and CH8. Referring to Fig. 9 and Fig.10 Describe the differences in response characteristics of signal channels CH0, ..., and CH8.

[0073] Fig. 9 and Fig.10 is through Figure 7 A graph of the signal measured through the signal channel.

[0074] Reference Fig. 9 , single bit responses 910 and crosstalk responses 920 of channels CH0, ..., and CH7 excluding channel CH8 are shown. It can be observed that the single bit responses 910 of channels CH0, ..., and CH7 have large differences from each other. In addition, it can be observed that the crosstalk responses 920 of channels CH0, ..., and CH7 also have various deviations. These differences may occur due to differences in specifications between signal lines 820, ..., 823, 825, ..., and 828 corresponding to each of channels CH0, ..., and CH7 and differences in capacitance values ​​due to capacitive coupling with surrounding lines and boards.

[0075] Reference Fig.10, showing a single bit response 1010 and a crosstalk response 1020 of channel CH8. The crosstalk response 1020 represents the response characteristics due to the crosstalk effect between channel CH8 and other channels CH0, ..., and CH7. It can be observed from the graph that due to the crosstalk effect occurring between channel CH8 and other channels CH0, ..., and CH7 due to "differences in specifications of other channels CH0, ..., CH7 affecting channel CH8 and differences in capacitance values ​​caused by capacitive coupling between channel CH8 and other channels CH0, ..., and CH7", there is a large difference in the response characteristics.

[0076] Since the single bit responses 910 between channels CH0, ... and CH7 are different, it is difficult to use CH0, ... and CH7 as a single channel group, and it is difficult to apply a crosstalk removal scheme based on the similarity of crosstalk responses, where the similarity of crosstalk responses is based on the deviation of crosstalk response 920 and the deviation of crosstalk response 1020.

[0077] According to the present disclosure, a signal channel may include signal lines 820, ..., 823, 825, ..., and 828 on a plurality of layers L1 to L3. The signal lines 820, ..., 823, 825, ..., and 828 included in one signal channel may have substantially equal lengths. Since each of the signal channels CH0, ..., and CH7 includes at least one of the signal lines 820, ..., 823, 825, ..., and 828 having different specifications, substantially equivalent response characteristics of signals transmitted through the signal channels CH0, ..., and CH7 may be obtained. For example, in one signal channel group, all signal channels CH0, ..., and CH7 having a cyclic structure include all signal lines 820, ..., 823, 825, ..., and 828 of the same length in which the signal channels CH0, ..., and CH7 may be set, and the difference in response characteristics that may occur due to the difference in signal line specifications between one signal channel and another signal channel may be minimized.

[0078] Fig.11 is a schematic diagram of a signal channel 1100 according to an embodiment of the present disclosure.

[0079] Reference Fig.11 , the signal channel group may include nine signal channels CH0, ... and CH8. The nine signal channels CH0, ... CH8 are Figure 8 An example of signal channels CH0 to CH8. Signal channels CH0, ..., and CH8 may be single-ended channels, respectively, and the first points SP0, ..., and SP8 may be electrically connected to the second points EP0, ..., and EP8. Fig.11, it is assumed that the signal lines 1110a, ..., and 1110i between the first points SP0, ..., and SP8 and the second points EP0, ..., and EP8 have specific specifications. The signal lines 1110a, ..., and 1110i may have different specifications. A plurality of sections 1130a, ..., and 1130h may be provided between the first points SP0, ..., and SP8 and the second points EP0, ..., and EP8. In an embodiment of the present disclosure, the number of the plurality of sections 1130a, ..., and 1130h may be an integer multiple of the number of the signal lines 1110a, ..., and 1110h having a cyclic structure.

[0080] The signal channel group may include eight signal channels CH0, ... and CH7 implemented with signal lines having a loop structure. One signal channel among the eight signal channels CH0, ... and CH7 implemented with signal lines having a loop structure may be implemented with multiple signal lines 1110a, ... and 1110h. For example, the signal channel CH0 may include a first signal line 1110a in the first segment 1130a, a fourth signal line 1110d in the second segment 1130b, a seventh signal line 1110g in the third segment 1130c, a second signal line 1110b in the fourth segment 1130d, a fifth signal line 1110e in the fifth segment 1130e, an eighth signal line 1110h in the sixth segment 1130f, a third signal line 1110c in the seventh segment 1130g, and a sixth signal line 1110f in the eighth segment 1130h. This will refer to Fig.12 Give a description.

[0081] Fig.12 is a table representing signal lines allocated to signal channels according to an embodiment of the present disclosure.

[0082] exist Fig.12 In the example, R1 to R8 represent Fig.11 , and 1130h, and L0 to L8 represent a plurality of signal lines 1110a, ..., and 1110i. It is assumed that the number of the plurality of signal lines 1110a, ..., and 1110i is the same as the number of channels CH0, ..., and CH8 electrically connected to the first points SP0, ..., and SP8.

[0083] Reference Fig.12 Each of the eight signal channels CH0, ..., and CH7 implemented with the signal line having a loop structure may include a plurality of signal lines L0 to L7 in sections R1 to R8. On the XZ plane, the signal lines 1110a, ..., and 1110h corresponding to the signal lines L0 to L7 may be arranged on the outline of the closed plane in a clockwise direction.

[0084] In an embodiment of the present disclosure, when the number of signal channels implemented with a signal line having a cyclic structure is N and one channel includes a signal line of a first segment and a signal line of a second segment adjacent to the first segment, the signal line of the second segment may be located at the Ath line of the contour of a closed plane formed by the signal line having a cyclic structure starting from the signal line of the first segment. Here, A is a positive integer and may be a value other than 1 that maximizes the magnitude of the (NA) value among values ​​coprime to N. For example, when N is 8, A may be 3, and when N is 12, A may be 5.

[0085] exist Fig.12 In the example of , N is 8, so it can be observed that the difference between the number of signal lines in the first segment and the number of signal lines in the second segment adjacent to the first segment is 3. For example, the signal line L0 of the first segment R1 can be electrically connected to the signal line L3 of the second segment R2, which is located third in the clockwise direction along the outline of the closed plane.

[0086] In the embodiment of the present disclosure, in the case of a signal channel implemented with a signal line having a loop structure, the signal line of the second section electrically connected to the signal line of the first section may be the Ath signal line arranged along the outline of the closed plane formed by the signal line having a loop structure starting from the signal line of the first section in the clockwise direction or the counterclockwise direction. This will refer to Fig.13A and Fig. 13B Give a description.

[0087] Fig.13A and Fig. 13B Signal lines allocated to signal channels according to an embodiment of the present disclosure are shown.

[0088] Fig.13A and Fig. 13B A method of electrically connecting a signal line electrically connected to one channel to another signal line between two adjacent segments is shown. Fig.13A and Fig. 13B In FIG. 1 , a plurality of signal lines 1310a, ... and 1310i correspond to Fig.12 L0 to L8.

[0089] like Fig.13AAs shown in (1300a), in the case of signal channels CH0, ... and CH7 implemented with signal lines having a loop structure, the signal line of the second segment electrically connected to the signal line of the first segment may be the Ath signal line in the clockwise direction along the outline of the closed plane formed by the signal channels implemented with the signal lines having a loop structure starting from the signal line of the first segment. For example, the signal line 1310a electrically connected to the channel CH0 may be electrically connected to the signal line 1310d in the adjacent segment. The signal line 1310a of the first segment may be electrically connected to the signal line 1310d of the second segment, which is located at the third in the clockwise direction along the outline of the closed plane formed by the signal channels CH0, ... and CH7.

[0090] like Fig. 13B As shown in (1300b), in the case of signal channels CH0, ... and CH7 implemented with signal lines having a loop structure, the signal line of the second segment electrically connected to the signal line of the first segment may be the Ath signal line in the counterclockwise direction along the outline of the closed plane formed by the signal channel implemented with the signal line having a loop structure starting from the signal line of the first segment. For example, the signal line 1310a electrically connected to the channel CH0 may be electrically connected to the signal line 1310f in the adjacent segment. The signal line 1310a of the first segment may be electrically connected to the signal line 1310f of the second segment, which is located at the third signal line in the counterclockwise direction along the outline of the closed plane formed by the signal channels CH0, ... and CH7.

[0091] Return to reference Fig.11, the lengths K1, ..., and K8 of the sections 1130a, ..., and 1130h may be substantially equal to each other. For example, the lengths K1, ..., and K8 of the eight signal lines included in the first signal channel CH0 may be substantially equal. The connecting portions 1120a, ..., and 1120h may be arranged corresponding to the plurality of sections 1130a, ..., and 1130h, respectively. In each of the connecting portions 1120a, ..., and 1120h, each of the signal lines 1110a, ..., and 1110h may be electrically connected to different signal lines 1110a, ..., and 1110h. For example, in the connection portion 1120a, the first signal line 1110a may be electrically connected to the fourth signal line 1110d, the second signal line 1110b may be electrically connected to the fifth signal line 1110e, the third signal line 1110c may be electrically connected to the sixth signal line 1110f, the fourth signal line 1110d may be electrically connected to the seventh signal line 1110g, the fifth signal line 1110e may be electrically connected to the eighth signal line 1110h, the sixth signal line 1110f may be electrically connected to the first signal line 1110a, the seventh signal line 1110g may be electrically connected to the second signal line 1110b, and the eighth signal line 1110h may be electrically connected to the third signal line 1110c. The length J1 of each of the connection portions 1120a, ..., and 1120h may be very short compared to the lengths K1, ..., and K8 of the corresponding sections 1130a, 1130b, ..., and 1130h.

[0092] Since each of the signal channels CH0, ..., and CH7 implemented with the signal line having a loop structure includes at least one of the signal lines 1110a, ..., and 1110h having a difference in specification, substantially equivalent response characteristics of signals transmitted through the signal channels CH0, ..., and CH7 can be obtained. When the signal channels CH0, ..., and CH7 implemented with the signal line having a loop structure and included in one signal channel group each include the signal lines 1110a, ..., and 1110h corresponding to the signal channels CH0, ..., and CH7 having equal lengths K1, ..., and K8, a difference in response characteristics that may occur due to a difference in the specification of the signal line between one signal channel and another signal channel can be minimized.

[0093] Will refer to Fig.14A , Fig. 14B , Fig. 14C and Fig.14D describe Fig.11 The structure of the signal channel.

[0094] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D is a cross-sectional view of a signal channel according to an embodiment of the present disclosure.

[0095] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D Shown in cross-sectional view Fig.11 The XZ plane of the signal channel in one connection portion (e.g., 1120a). For example, Fig.14A , Fig. 14B , Fig. 14C and Fig.14D It may be a cross-sectional view showing the XZ plane according to the distance from the first points SP0, ... and SP8. For example, Fig.14A is a cross-sectional view of a portion 1400a adjacent to the first points SP0, ..., and SP8, Fig.14D It is a cross-sectional view of a portion 1400d which is farthest away from the first points SP0, ..., and SP8.

[0096] A signal line included in a signal channel in a connection portion may be electrically connected to the Ath signal line in a clockwise or counterclockwise direction along the outline of a closed plane formed by the signal channel implemented with the signal line having a loop structure. In one embodiment, for example, in a connection portion, the signal line included in a signal channel and the Ath signal line may be electrically connected through the A signal lines along the outline of the closed plane having the largest area. In a connection portion, a signal channel and the Ath signal line may be electrically connected through the A signal lines arranged along the outline of the closed plane. In an embodiment of the present disclosure, when A is 2 or greater, a signal line may be repeatedly electrically connected to the first signal line located in a clockwise or counterclockwise direction along the outline of the closed plane (i.e., the signal line adjacent along the outline of the closed plane) to connect the signal line of the first section with the signal line of the second section. For example, since A is 3, in the connecting portion connecting the signal line of the first segment and the signal line of the second segment, a signal line can be repeatedly electrically connected three times to the first signal line located in the clockwise or counterclockwise direction along the outline of the closed plane (i.e., the signal line adjacent along the outline of the closed plane).

[0097] like Fig.14A As shown in , the signal channel CH0 may include a signal line 1420 in a portion 1400a adjacent to the first points SP0, . . . , and SP8 in the connection portion.

[0098] like Fig. 14B As shown in FIG. 14 , in a next portion 1400b of the portion 1400a, the signal channel CH0 may include a signal line 1421. The signal line 1420 may be electrically connected to the signal line 1421 located first in a clockwise direction along an outline of a closed plane.

[0099] Will refer to Fig.15 describe Fig.14A and Fig. 14B Connection of signal lines in.

[0100] Fig.15 A method of connecting signal lines according to an embodiment of the present disclosure is exemplarily shown.

[0101] like Fig.15 As shown in (1500), part of the connection portion 1510 may be arranged FIG. 14A to FIG. 14B between the portion 1400a and the portion 1400b, and the plurality of signal lines 1520a, ..., and 1528a may be electrically connected to the plurality of signal lines 1520b, ..., and 1528b.

[0102] In the partial connection portion 1510, the signal line 1520a corresponding to the signal channel CH0 may be electrically connected to the first signal line 1521b in the clockwise direction along the outline of the closed plane. In the partial connection portion 1510, the signal line 1521a corresponding to the signal channel CH1 may be electrically connected to the first signal line 1522b in the clockwise direction along the outline of the closed plane. In the partial connection portion 1510, the signal line 1522a corresponding to the signal channel CH2 may be electrically connected to the first signal line 1525b in the clockwise direction along the outline of the closed plane. The signal line 1522a and the signal line 1525b may be electrically connected to each other through the via 1511. In the partial connection portion 1510, the signal line 1525a corresponding to the signal channel CH3 may be electrically connected to the first signal line 1528b in the clockwise direction along the outline of the closed plane. The signal line 1525a and the signal line 1528b may be electrically connected to each other through the via 1512. In the partial connection portion 1510, a signal line 1528a corresponding to a signal channel CH4 may be electrically connected to a first signal line 1527b in a clockwise direction along the outline of a closed plane. In the partial connection portion 1510, a signal line 1527a corresponding to a signal channel CH5 may be electrically connected to a first signal line 1526b in a clockwise direction along the outline of a closed plane. In the partial connection portion 1510, a signal line 1526a corresponding to a signal channel CH6 may be electrically connected to a first signal line 1523b in a clockwise direction along the outline of a closed plane. The signal line 1526a and the signal line 1523b may be electrically connected to each other through a via 1513. In the partial connection portion 1510, a signal line 1523a corresponding to a signal channel CH7 may be electrically connected to a first signal line 1520b in a clockwise direction along the outline of a closed plane. The signal line 1523a and the signal line 1520b may be electrically connected to each other through a via 1514.

[0103] As described above, one signal line may be electrically connected to a signal line adjacent in a clockwise direction or a counterclockwise direction in the partial connection portion 1510. The above connection method is merely an example for realizing connection between signal lines in the connection portion (e.g., 1120a), and in the present disclosure, connection between signal lines may be realized in various ways other than the above method.

[0104] Then, if Fig. 14C As shown in FIG. 14 , in a next portion 1400c of the portion 1400b, the signal channel CH0 may include a signal line 1422. The signal line 1421 may be electrically connected to the signal line 1422 located first in a clockwise direction along the outline of the closed plane.

[0105] like Fig.14D As shown in FIG. 14 , in the next portion 1400d of the portion 1400c, the signal channel CH0 may include a signal line 1425. The signal line 1422 may be electrically connected to the signal line 1425 located first in the clockwise direction along the outline of the closed plane.

[0106] As a result, in the connection portion, the signal line 1420 may be electrically connected to the third signal line 1425 in the clockwise direction along the outline of the closed plane formed by the signal lines 1420 , . . . , 1423 , 1425 , . . . , 1428 of the loop structure.

[0107] Fig.16 and Fig.17 It is shown by Fig.12 A graph of the signal measured through the signal channel.

[0108] Reference Fig.16 , single bit responses 1610 and crosstalk responses 1620 of CH0, ..., and CH7 excluding channel CH8 are shown. It can be observed that the single bit responses 1610 of channels CH0, ..., and CH7 have substantially equivalent characteristics. In addition, it can be observed that the crosstalk responses 1620 of channels CH0, ..., and CH7 are classified into several groups having substantially equivalent characteristics. Therefore, channels CH0, ..., and CH7 can be used as one channel group, and a crosstalk removal scheme based on the similarity of the crosstalk responses can be applied.

[0109] Reference Fig.17 , a single bit response 1710 and a crosstalk response 1720 of a channel CH8 are shown. The crosstalk response 1720 represents the response characteristics caused by the crosstalk effect between the channel CH8 and other channels CH0, ... and CH7. It can be observed that the crosstalk response 1720 has substantially the same characteristics. Therefore, a crosstalk removal scheme based on the similarity of the crosstalk response can be applied.

[0110] Fig.18A and Fig.18B A heat map illustrating the similarity of signal channel responses according to an embodiment of the present disclosure is shown.

[0111] Fig.18A Shown according to reference Figure 7 The response similarity of the signal channels of the described comparative examples, and Fig.18B Shown according to reference Fig.11 The described embodiments signal channels similarity.

[0112] like Fig.18A and Fig.18B As shown in , the horizontal and vertical axes represent the response numbers between the nine signal channels and the nine signal channels, and the shading in the figure represents the similarity between the responses. Fig.18A and Fig.18B In the graph of FIG. 1 , when the horizontal axis x=0, the color change in the area corresponding to the value of the vertical axis y indicates the similarity between "the response between the channel CH0 and the channel CH0" and "the response between one of the nine channels CH0, ... and CH8 and one of the nine channels CH0, ... and CH8 (i.e., 81 responses)". Among the responses between signal channels, the response between the same two channels may be a single bit response, and the response between two different channels may be a crosstalk response.

[0113] Reference Fig.18A , the similarity of responses can be divided into 13 groups. For example, the deviation of the similarity of responses is different. Fig.18B , the similarity of the response can be classified into 6 groups. For example, the deviation of the similarity of the response is small. Therefore, it is easy to apply the crosstalk removal scheme based on the similarity of the crosstalk response to the signal channel according to the present disclosure.

[0114] According to the present disclosure, signal channels have crosstalk response characteristics classified into several groups similar to substantially equivalent single bit response characteristics, and thus signal lines having different specifications disposed in multiple layers can be used as signal channel groups for high throughput.

[0115] Although the embodiments of the present invention have been described in detail above, the present invention is not necessarily limited to the embodiments set forth herein, and various modifications and adjustments made by those skilled in the art using the basic concept of the present invention also fall within the scope of the present invention.

Claims

1. A signal channel, comprising: a plurality of signal lines disposed on a plurality of layers, wherein each of the plurality of signal lines is spaced apart from each other in a first direction and connects a first point and a second point to each other, wherein a plurality of segments are defined between a first point and a second point, and Wherein, a first signal line among the multiple signal lines is arranged on a first layer among the multiple layers in a first segment among the multiple segments, and is electrically connected to a second signal line among the multiple signal lines arranged on a second layer among the multiple layers in a second segment among the multiple segments.

2. The signal channel according to claim 1, wherein: The plurality of signal wires include three or more signal wires twisted or braided together.

3. The signal channel according to claim 2, wherein: The three or more signal lines twisted or braided together include: three or more signal lines included in a first closed plane having a largest area among closed planes formed by the three or more signal lines twisted or braided together.

4. The signal channel according to claim 3, wherein: The number of the three or more signal lines twisted or braided together is N, the second signal line is arranged at the Ath line along the contour of the first closed plane starting from the first signal line, A is a positive integer, and is a value other than 1 among values ​​coprime to N that maximizes the magnitude of the (NA) value.

5. The signal channel according to claim 4, wherein: The second signal line is disposed at the Ath line along the outline of the first closed plane starting from the first signal line in the clockwise direction or the counterclockwise direction.

6. The signal channel according to claim 4, wherein: In the connection portion between the first section and the second section, the first signal line and the second signal line are electrically connected through A signal lines along the outline of the first closed plane.

7. The signal channel according to claim 2, wherein: The number of the plurality of sections is an integer multiple of the number of the three or more signal lines twisted or braided together.

8. The signal channel according to claim 2, wherein: The lengths of the plurality of sections are equal to each other.

9. The signal channel according to claim 1, wherein: In a connection portion between the first section and the second section, the first signal line is electrically connected to the second signal line through a via connecting the first layer and the second layer.

10. The signal channel according to claim 1, wherein: The first signal line and the second signal line have different specifications.

11. The signal channel according to claim 1, wherein: Thicknesses of the first signal line and the second signal line in the first direction and / or widths of the first signal line and the second signal line in a second direction intersecting the first direction are different from each other.

12. The signal channel according to claim 1, further comprising: A first reference plate, to which a reference voltage is applied, is disposed above the first layer.

13. The signal channel according to claim 1, further comprising: A second reference plate, to which a reference voltage is applied, is disposed below the second layer.

14. The signal channel according to any one of claims 1 to 13, further comprising: A plurality of first reference lines and / or a plurality of second reference lines, wherein the plurality of first reference lines are arranged in the first layer close to the first signal lines and are applied with reference voltages, and the plurality of second reference lines are arranged in the second layer close to the second signal lines and are applied with reference voltages.

15. A module substrate, comprising: a substrate body including a dielectric material and including a plurality of layers spaced apart from each other in a first direction; as well as a plurality of signal lines disposed on the plurality of layers, wherein the plurality of signal lines electrically connect the first point and the second point to each other, and wherein the plurality of signal lines are twisted or braided with each other, wherein a plurality of segments are defined between a first point and a second point, and Among them, a first signal line among the multiple signal lines arranged on a first layer among the multiple layers in a first segment among the multiple segments is electrically connected to a second signal line among the multiple signal lines arranged on a second layer among the multiple layers in a second segment among the multiple segments.

16. The module substrate according to claim 15, wherein: The plurality of signal lines twisted or braided together include three or more signal lines included in a first closed plane having a largest area among closed planes formed by the three or more signal lines.

17. The module substrate according to claim 16, wherein: The number of the plurality of signal lines twisted or braided together is N, the second signal line is arranged at the Ath line along the contour of the first closed plane starting from the first signal line, A is a positive integer, and is a value other than 1 among values ​​coprime to N that maximizes the value of (NA).

18. The module substrate according to claim 17, wherein: The second signal line is disposed at the Ath line along the outline of the first closed plane starting from the first signal line in the clockwise direction or the counterclockwise direction.

19. The module substrate according to claim 17, wherein: In the connection portion between the first section and the second section, the first signal line and the second signal line are electrically connected through A signal lines along the outline of the first closed plane.

20. A semiconductor system comprising: multiple stacked memory dies; a buffer die disposed below the plurality of stacked memory dies; Memory controller; as well as an interposer including a plurality of signal lines electrically connecting a first point of the memory controller and a second point of the buffer die to each other, wherein a plurality of segments are defined between a first point and a second point, and Among them, a first signal line among the multiple signal lines arranged on a first layer among multiple layers in a first segment among the multiple segments is electrically connected to a second signal line among the multiple signal lines arranged on a second layer among the multiple layers in a second segment among the multiple segments.

Images