Semiconductor device and data storage system including same

Abstract

The invention provides a semiconductor device and a data storage system including the same. A semiconductor device includes: a stacked structure including gate electrodes spaced apart from each other in a first direction in a first region and a second region; a separation region in the first region and the second region, extending through the stacked structure and extending in a second direction perpendicular to the first direction; a plurality of channel structures extending through the stack structure in the cell region of the first region; a plurality of dummy channel structures in the buffer region of the first region extending through the stack structure; and a plurality of support structures in the second region extending through the stack structure. The first region and the second region are sequentially arranged in the second direction. The partition region includes a first partition region and a second partition region adjacent to each other in the third direction. The dummy channel structure includes a first dummy group and a second dummy group having different lengths between the first partition region and the second partition region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a data storage system including the semiconductor device. Background Art

[0002] Semiconductor devices capable of storing high-capacity data are generally needed in data storage systems that require data storage. Therefore, methods for increasing the data storage capacity of semiconductor devices are being studied. For example, a semiconductor device including three-dimensionally arranged storage cells instead of two-dimensionally arranged storage cells has been proposed as one of the methods for increasing the data storage capacity of a semiconductor device. Summary of the invention

[0003] An aspect of the present disclosure is to provide a semiconductor device having an improved manufacturing process and having improved electrical characteristics and reliability.

[0004] According to one aspect of the present disclosure, a semiconductor device includes: a stacked structure, in a first region and a second region, including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of a substrate; a plurality of separation regions, in the first region and the second region, extending through the stacked structure and extending in a second direction perpendicular to the first direction; a plurality of channel structures, in a cell region of the first region, extending through the stacked structure; a plurality of dummy channel structures, in a buffer region of the first region, extending through the stacked structure; and a plurality of support structures, in the second region, extending through the stacked structure. The first region and the second region are sequentially arranged in the second direction, and the plurality of separation regions include first separation regions and second separation regions adjacent to each other in a third direction perpendicular to the first direction and the second direction. Between the first separation region and the second separation region, the plurality of dummy channel structures include a first dummy group and a second dummy group, the first dummy group being adjacent to the cell region and including first dummy channel structures sequentially arranged in the third direction, and the second dummy group being adjacent to the second region and including second dummy channel structures sequentially arranged in the third direction. The first length of the first dummy group in the third direction is longer than the second length of the second dummy group in the third direction.

[0005] According to another aspect of the present disclosure, a semiconductor device includes: a stacked structure, in a first region and a second region, and including gate electrodes and interlayer insulating layers alternately stacked in a first direction; a plurality of separation regions extending through the stacked structure; a plurality of channel structures extending through the stacked structure in a cell region of the first region; a plurality of dummy vertical structures extending through the stacked structure in a buffer region of the first region; a plurality of first support structures extending through the stacked structure in a boundary region of the second region; a contact plug connected to a contact region of the gate electrode in a connection region of the second region; and a plurality of second support structures extending through the stacked structure in a connection region of the second region. The cell region of the first region, the buffer region of the first region, the boundary region of the second region, and the connection region of the second region are sequentially arranged in the second direction. The plurality of separation regions include a first separation region and a second separation region adjacent to each other in a third direction perpendicular to the first direction and the second direction. Between a first central axis of the first separation region extending in the second direction and a second central axis of the second separation region extending in the second direction, a distance between a first dummy vertical structure adjacent to the first separation region and the first central axis among the plurality of dummy vertical structures increases from a region adjacent to the cell region of the first region to a region adjacent to the boundary region of the second region.

[0006] According to one aspect of the present disclosure, a data storage system includes: a semiconductor memory device including a first semiconductor structure including a circuit element, a second semiconductor structure on a surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element; a controller electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device. The second semiconductor structure includes: a stacked structure in a first region and a second region and including gate electrodes and interlayer insulating layers alternately stacked in a first direction; a plurality of separation regions extending through the stacked structure; a plurality of channel structures extending through the stacked structure in a cell region of the first region; a plurality of dummy vertical structures extending through the stacked structure in a buffer region of the first region; a plurality of first support structures extending through the stacked structure in a boundary region of the second region; a contact plug connected to a contact region of the gate electrode in a connection region of the second region; and a plurality of second support structures extending through the stacked structure in a connection region of the second region. The cell region of the first region, the buffer region of the first region, the boundary region of the second region, and the connection region of the second region are arranged sequentially in the second direction. The plurality of separation regions include first separation regions and second separation regions adjacent to each other in a third direction perpendicular to the first direction and the second direction. Between a first central axis extending along the second direction of the first separation region and a second central axis extending along the second direction of the second separation region, a distance between a first dummy vertical structure adjacent to the first separation region among the multiple dummy vertical structures and the first central axis increases from an area adjacent to a unit area of ​​the first region to an area adjacent to a boundary area of ​​the second region.

[0007] According to the present disclosure, when an opening is formed by an etching process for separating regions, some embodiments can prevent or reduce defects caused by over-etching, which is caused when etching is biased toward the dummy channel structure due to the asymmetry of the Coulomb force between the dummy channel structure and the support structure. That is, the dummy channel structure near the boundary region between the dummy channel structure and the support structure can be arranged relatively far away from the separation region, thereby reducing or minimizing over-etching. The deformation of the separation region caused by over-etching can be reduced or minimized so as not to affect the channel structure, thereby reducing or preventing leakage current and improving the yield of the semiconductor device.

[0008] In addition, by expanding the width of the separation region corresponding to the boundary between the dummy channel structure and the support structure, the electric field concentration can be alleviated to reduce or prevent the occurrence of the over-etching region, and the area without the vertical structure between the dummy channel structure and the separation region can be reduced or minimized, thereby reducing the risk of stacking structure collapse or preventing the stacking structure collapse. Therefore, a semiconductor device with improved reliability and yield can be provided.

[0009] Various advantages and effects of embodiments of the inventive concept are not limited to the foregoing and may be more easily understood in the course of describing specific example embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic plan view of a semiconductor device according to an example embodiment;

[0012] FIG. 2A to FIG. 2C is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0013] Figure 3A and Figure 3B yes Figure 1 and Figure 2A an enlarged cross-sectional view of a portion of;

[0014] Figures 4 to 8 is a schematic plan view of a semiconductor device according to an example embodiment;

[0015] Fig. 9 is a schematic cross-sectional view of a semiconductor device according to an example embodiment;

[0016] FIG. 10A to FIG. 10K and Fig.11 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment;

[0017] Fig.12 is a schematic diagram of a data storage system including a semiconductor device according to an example embodiment;

[0018] Fig.13 is a schematic perspective view of a data storage system including a semiconductor device according to an example embodiment; and

[0019] Fig.14 is a cross-sectional view schematically illustrating a semiconductor package according to an example embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings. Hereinafter, it will be understood that expressions such as "on ... ", "above ... ", "up", "below ... ", "under ... ", "down" and "side" may be indicated based on the accompanying drawings, and in some cases may be indicated by reference numerals and referred to separately. Throughout the various aspects, the same reference numerals in the accompanying drawings indicate the same or similar functions. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. It should be noted that aspects described with respect to one embodiment may be incorporated into different embodiments, although not specifically described thereto. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0021] Figure 1 is a schematic plan view of a semiconductor device according to an example embodiment, FIG. 2A to FIG. 2C is a schematic cross-sectional view of a semiconductor device according to example embodiments.

[0022] FIG. 2A to FIG. 2C are respectively along Figure 1 Cross-sectional views taken along cutting lines II', II-II' and III-III'. Figure 3A and Figure 3B is a partially enlarged view illustrating a partial region of a semiconductor device according to example embodiments. Figure 3A It is shown Figure 1 A magnified view of area "A" Figure 3B It is shown Figure 2A Magnified view of area "B". Figure 1 It is schematically shown from FIG. 2A to FIG. 2C A plan view of the semiconductor device at an angle of the lower portion of the upper horizontal insulating layer to show the arrangement of each vertical structure, FIG. 2A to FIG. 2C A planar structure on an upper horizontal insulating layer is shown.

[0023] Reference Figures 1 to 3B , the semiconductor device 100 may include a peripheral circuit region PERI and a memory cell region CELL, the peripheral circuit region PERI is a first semiconductor structure including a first substrate 201, and the memory cell region CELL is a second semiconductor structure including a second substrate 101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. On the contrary, in example embodiments, the memory cell region CELL may be disposed below the peripheral circuit region PERI in the Z direction.

[0024] The semiconductor device 100 may include a first region R1 and a second region R2 in a space formed by an X direction, a Y direction, and a Z direction.

[0025] The first region R1 of the semiconductor device 100 may include a cell region R1a and a first boundary region R1b adjacent to the cell region R1a in the X direction, wherein the channel structure CH (which is configured to penetrate or extend through the stacked structure of the gate electrode 130) is arranged in a zigzag or matrix shape in the cell region R1a, and the dummy channel structure DCH (which is configured to penetrate or extend through the stacked structure of the gate electrode 130) is formed in a plurality of columns in the first boundary region R1b.

[0026] The second region R2 of the semiconductor device 100 may include a second boundary region R2b adjacent to the first boundary region R1b in the X direction and a connection region R2a adjacent to the second boundary region R2b in the X direction, in which the first support structures SH1 arranged to penetrate or extend through the stacked structure of the gate electrode 130 among the support structures SH in the second boundary region R2b are arranged in a zigzag or matrix arrangement, and in the connection region R2a, the second support structures SH2 arranged to penetrate or extend through the stacked structure of the gate electrode 130 form a plurality of matrices. The contact plug 170 may be arranged between the second support structures SH2 in the connection region R2a.

[0027] In other words, in the semiconductor device 100, the cell region R1a, the first boundary region R1b, the second boundary region R2b and the connection region R2a are arranged sequentially in the X direction, and the boundary region Rb including the first boundary region R1b and the second boundary region R2b can be arranged between the cell region R1a in which the channel structure CH is set and the connection region R2a in which the contact plug 170 is set.

[0028] The peripheral circuit region PERI of the semiconductor device 100 may include a first substrate 201 in the first region R1 and the second region R2, a source / drain region 205 and a device isolation layer 210 in the first substrate 201, and a circuit element 220, a circuit contact plug 270, a circuit wiring line 280 and a peripheral region insulating layer 290 arranged on the first substrate 201.

[0029] The first substrate 201 may have an upper surface extending in the X direction and the Y direction. The active region may be defined in the first substrate 201 by the device isolation layer 210. The source / drain region 205 including impurities may be disposed in a portion of the active region. The first substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0030] The circuit elements 220 may include planar transistors. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The source / drain regions 205 may be disposed on both sides of the circuit gate electrode 225 in the first substrate 201.

[0031] The circuit contact plug 270 and the circuit wiring line 280 may form a circuit wiring structure electrically connected to the circuit element 220 and the source / drain region 205. The circuit contact plug 270 may have a cylindrical shape, and the circuit wiring line 280 may have a linear or linear shape. The circuit contact plug 270 and the circuit wiring line 280 may include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), etc., and each component may also include a diffusion barrier. However, in example embodiments, the number and arrangement of the layers of the circuit contact plug 270 and the circuit wiring line 280 may be variously changed.

[0032] The peripheral region insulating layer 290 may be disposed on the first substrate 201 to be on the circuit element 220 and to at least partially cover the circuit element 220. The peripheral region insulating layer 290 may be formed of an insulating material and may include one or more insulating layers.

[0033] The memory cell region CELL of the semiconductor device 100 may include a second substrate 101 in a first region R1 and a second region R2, gate electrodes 130 stacked on the second substrate 101, an interlayer insulating layer 120 alternately stacked with the gate electrodes 130, a channel structure CH and a dummy channel structure DCH arranged in the first region R1 to penetrate or extend through the stacked structure of the gate electrodes 130, a support structure SH arranged in the second region R2 to penetrate or extend through the stacked structure of the gate electrodes 130, a first separation region MS1 ​​and a second separation region MS2a and MS2b extending to penetrate the stacked structure of the gate electrodes 130, and a contact plug 170 connected to a contact region 130P of the gate electrode 130 in the second region R2 and extending in a vertical direction (i.e., Z direction).

[0034] The channel structure CH that penetrates or extends through the stacked structure of the gate electrode 130 can be arranged in a zigzag or matrix shape in the cell region R1a of the first region R1, and the dummy channel structure DCH that penetrates or extends through the stacked structure of the gate electrode 130 in the first boundary region R1b can be arranged by forming multiple columns.

[0035] Among the support structures SH of the stacked structure penetrating or extending through the gate electrode 130 in the second region R2, in the second boundary region R2b, the first support structures SH1 may be arranged in a zigzag or matrix arrangement, and in the connection region R2a, the second support structures SH2 may be arranged by forming a plurality of matrices. The contact plugs 170 may be arranged between the second support structures SH2.

[0036] The memory cell region CELL may further include: a substrate insulating layer 121, at the same level as the second substrate 101; a first horizontal conductive layer 102 and a second horizontal conductive layer 104, arranged below the gate electrode 130 in the first region R1 (in the Z direction); a horizontal insulating layer 110, arranged below the gate electrode 130 in the second region R2 (in the Z direction); a through-via 175, extending from the memory cell region CELL to the peripheral circuit region PERI; a channel structure CH; a dummy channel structure DCH; a supporting structure SH, including a first supporting structure SH1 and a second supporting structure SH2; and a cell region insulating layer 190, on the contact plug 170 and the gate electrode 130 and at least partially covering the contact plug 170 and the gate electrode 130.

[0037] The cell region R1a of the semiconductor device 100 is a region in which the gate electrode 130 is vertically stacked and the channel structure CH is set, and may be a region in which a memory cell is set. The first boundary region R1b of the semiconductor device 100 may be a buffer region in which a dummy channel structure DCH is set. The dummy channel structure DCH has substantially the same configuration as the channel structure CH, and may be an electrically floating structure so as not to be used as the channel structure CH. Therefore, the dummy channel structure DCH may not be used as a memory cell. The second boundary region R2b of the semiconductor device 100 is a boundary region in which the first support structure SH1 is set, and may be used as a buffer region. The connection region R2a is a region for electrically connecting a memory cell to the peripheral circuit region PERI, and an electrical connection between the contact region 130P of the gate electrode 130 and the peripheral circuit region PERI may be performed by a contact plug 170. To this end, the gate electrode 130 may extend to different lengths, but the embodiments of the present disclosure are not limited thereto.

[0038] As described above, in at least one direction (eg, in the X direction), the second region R2 may be disposed at one end of the first region R1, specifically, the unit region R1a, the first boundary region R1b, the second boundary region R2b, and the connection region R2a may be disposed in sequence.

[0039] The second substrate 101 has a plate shape and may function as at least a portion of a common source line of the semiconductor device 100 .

[0040] The second substrate 101 may have an upper surface extending in the X direction and the Y direction. The second substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, and / or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, and / or silicon-germanium. The second substrate 101 may also include impurities. The second substrate 101 may be provided as a polycrystalline semiconductor layer (such as a polycrystalline silicon layer) or an epitaxial layer.

[0041] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be sequentially stacked and disposed on the upper surface of the first region R1 of the second substrate 101. The first horizontal conductive layer 102 may not extend into the second region R2 of the second substrate 101, and the second horizontal conductive layer 104 may extend into the second region R2. The first horizontal conductive layer 102 may be used as a part of a common source line of the semiconductor device 100, for example, used as a common source line together with the second substrate 101. Figure 3B As shown in the enlarged view of FIG. 1 , the first horizontal conductive layer 102 may be directly connected to the channel layer 140 around the channel layer 140 .

[0042] The second horizontal conductive layer 104 may contact the second substrate 101 in a boundary between the first region R1 and the second region R2 where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not provided. The second horizontal conductive layer 104 may be bent in the boundary between the first region R1 and the second region R2 while being on and at least partially covering an end of the first horizontal conductive layer 102 or the horizontal insulating layer 110 and extending onto the second substrate 101.

[0043] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material, such as polysilicon. In this example, at least the first horizontal conductive layer 102 may be a layer doped with impurities of the same conductivity type as the second substrate 101, and the second horizontal conductive layer 104 may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102. However, the material of the second horizontal conductive layer 104 is not limited to a semiconductor material, and may be replaced by an insulating layer.

[0044] The horizontal insulating layer 110 may be disposed on the second substrate 101 at the same level as the first horizontal conductive layer 102 in the Z direction in at least a portion of the second region R2. The horizontal insulating layer 110 may include first horizontal insulating layers 111 and second horizontal insulating layers 112 alternately stacked in the second region R2 of the second substrate 101. The horizontal insulating layer 110 may be a layer that remains after a portion of the horizontal insulating layer 110 is replaced with the first horizontal conductive layer 102 in a manufacturing process of the semiconductor device 100.

[0045] The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide and / or silicon oxynitride. The first horizontal insulating layer 111 and the second horizontal insulating layer 112 may include different insulating materials. For example, the first horizontal insulating layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of a different material from the interlayer insulating layer 120.

[0046] The substrate insulating layer 121 may be disposed to penetrate the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 in the connection region R2a of the second region R2. The substrate insulating layer 121 may be further disposed in the first region R1 or the second region R2, for example, in a region in which the through via 175 is disposed. The lower surface of the substrate insulating layer 121 may be coplanar with the lower surface of the second substrate 101, or may be disposed at a level lower than the lower surface of the second substrate 101 in the Z direction. The substrate insulating layer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon carbide, and / or silicon oxynitride.

[0047] The gate electrodes 130 may be spaced apart from each other in a vertical direction (Z direction) on the second substrate 101 to form a stacked structure. The gate electrode 130 may include a lower gate electrode 130L forming a gate of a ground selection transistor, a storage gate electrode 130M forming a plurality of memory cells, and a first upper gate electrode 130U1 and a second upper gate electrode 130U2 on the storage gate electrode 130M. The number of storage gate electrodes 130M forming a memory cell may be determined according to the capacity of the semiconductor device 100. According to an example embodiment, one or two or more upper gate electrodes and lower gate electrodes (130U1, 130U2, and 130L) may be provided and may have the same or different structure as the storage gate electrode 130M. In an example embodiment, the second upper gate electrode 130U2 may form a string selection transistor, and the first upper gate electrode 130U1 may form an erase transistor used in an erase operation using a gate induced drain leakage current (GIDL) phenomenon. The erase transistor may even be included in the lower portion of the lower gate electrode, but the embodiments of the present disclosure are not limited thereto.

[0048] Furthermore, some of the gate electrodes 130 (eg, the memory gate electrode 130M adjacent to the first upper gate electrode 130U1 or the lower gate electrode 130L) may be dummy gate electrodes.

[0049] like Figure 1As shown, the gate electrodes 130 may be arranged to be separated from each other in the Y direction by the first separation regions MS1 extending continuously in the first region R1 and the second region R2. The gate electrodes 130 between a pair of first separation regions MS1 may form a memory block, but the range of the memory block is not limited thereto. Some gate electrodes 130 (e.g., the memory gate electrodes 130M) may respectively form a layer in a memory block.

[0050] The gate electrodes 130 may be stacked in the first region R1 and the second region R2 spaced apart from each other in the vertical direction (Z direction), and may extend from the first region R1 to the second region R2 at different lengths to form a step structure GP having a step shape in a portion of the second region R2 (e.g., the connection region R2a). The gate electrode 130 may even be arranged to have a structure that is stepped with each other in the Y direction. Through the step structure, the lower gate electrode 130 may extend longer than the upper gate electrode 130, and therefore, the gate electrode 130 may have regions where its upper surface is exposed upward from the interlayer insulating layer 120 and other gate electrodes 130, respectively, and these regions may be referred to as contact regions 130P. In each gate electrode 130, the contact region 130P may be a region including the end of the gate electrode 130 in the X direction. The contact region 130P may correspond to a region of the uppermost gate electrode 130 disposed in each region among the gate electrodes 130 that form a stacked structure in the connection region R2a of the second region R2. The gate electrodes 130 may be connected to the contact plugs 170 in the contact regions 130P, respectively. The gate electrode 130 may have an increased thickness in the contact regions 130P.

[0051] The gate electrode 130 may include a metal material such as tungsten (W). According to an example embodiment, the gate electrode 130 may include polysilicon and / or a metal silicide material. In an example embodiment, the gate electrode 130 may further include a diffusion barrier, for example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0052] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may be disposed to be spaced apart from each other in a direction perpendicular to the upper surface of second substrate 101 and extend in the X direction. Interlayer insulating layers 120 may include insulating materials such as silicon oxide or silicon nitride.

[0053] The first separation region MS1 ​​and the second separation regions MS2a and MS2b may be arranged to penetrate or extend through at least a portion of the gate electrode 130 and extend in the X direction. The first separation region MS1 ​​and the second separation regions MS2a and MS2b may be arranged in parallel with each other. The first separation region MS1 ​​and the second separation regions MS2a and MS2b may penetrate all gate electrodes 130 stacked on the second substrate 101, and further penetrate or extend through the first horizontal conductive layer 102 and the second horizontal conductive layer 104 and the horizontal insulating layer 110 at the bottom, thereby contacting the second substrate 101. The first separation region MS1 ​​extends into one in the X direction, and the second separation region MS2 may extend intermittently between a pair of first separation regions MS1 or may be arranged only in a partial region. For example, the second central separation region MS2a may extend into one in the first region R1, and may pass through the second boundary region R2b of the second region R2 and extend intermittently in the X direction in the connection region R2a. The second auxiliary separation region MS2b may be provided only in a portion of the second region R2, for example, in the connection region R2a, may be spaced apart from the second central separation region MS2a by a predetermined distance, and may face the second central separation region MS2a and extend in the X direction. The first separation region MS1 ​​and the second central separation region MS2a extend continuously within the first region R1 and the second boundary region R2b without interruption. However, in the example embodiment, the arrangement order and number of the first separation region MS1 ​​and the second separation regions MS2a and MS2b are not limited to Figure 1 Arrangement order and quantity shown.

[0054] The separation insulating layer 105 may be disposed in the first separation region MS1 ​​and the second separation regions MS2a and MS2b. Due to the high aspect ratio, the separation insulating layer 105 may have a shape whose width decreases toward the second substrate 101, but the present disclosure is not limited thereto, and the separation insulating layer 105 may have a side surface perpendicular to the upper surface of the second substrate 101. The lower surface of the separation insulating layer 105 may contact the second substrate 101.

[0055] The upper separation region SS may extend in the X direction between the first separation region MS1 ​​and the second separation regions MS2a and MS2b adjacent to each other. The upper separation region SS may be disposed in a portion of the second region R2 as well as in the first region R1. The upper separation region SS may penetrate or extend through the second upper gate electrode 130U2 disposed at the uppermost portion among the gate electrodes 130. Figure 2B As shown, the upper separation region SS may divide the second upper gate electrode 130U2 in the Y direction.

[0056] The upper separation regions SS may include upper separation insulating layers, respectively. The upper separation insulating layers may include an insulating material, such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0057] Each channel structure CH may form a memory cell string, and may be spaced apart from each other while forming rows and columns in the cell region R1a of the first region R1. The channel structure CH may be arranged in a zigzag shape in one direction in the XY plane. The channel structure CH may be symmetrically arranged in the cell region R1a in the X direction about the first separation region MS1 ​​or the second central separation region MS2a. For example, when the channel structure CH disposed between two first separation regions MS1 and second central separation regions MS2a spaced apart from each other in the Y direction has an odd number of columns, the arrangement of the channel structures CH on both sides may be identical to each other with each of the first separation regions MS1 or the second central separation regions MS2a as an axis, and the channel structures CH on both sides of the same arrangement may be symmetrical to each other in the X direction about the first separation region MS1 ​​or the second central separation region MS2a.

[0058] When the channel structure CH arranged between two first separation regions MS1 or second central separation regions MS2a spaced apart from each other along the Y direction has an even number of columns, the arrangements of the channel structures CH on both sides with each of the first separation regions MS1 or the second central separation regions MS2a as an axis may be different from each other, and the channel structures CH on both sides with different arrangements may form a mirror pair that are symmetrical to each other about the first separation region MS1 ​​or the second central separation region MS2a.

[0059] Each channel structure CH may include vertically stacked first, second, and third channel structures CH1, CH2, and CH3, which may have a pillar shape and may be connected to each other, and which may be connected to each other through a conductive connection pad CP.

[0060] The first and second channel structures CH1 and CH2 may have inclined side surfaces that become narrower as they approach the second substrate 101 depending on their aspect ratios.

[0061] The first channel structure CH1 and the upper second channel structure CH2 may have a bent portion due to a width difference in a connection region. However, according to example embodiments, the number of channel structures stacked in the Z direction may be variously changed.

[0062] Each of the first channel structure CH1 and the upper second channel structure CH2 may include a channel layer 140 disposed in a channel hole, a gate dielectric layer 145, a channel buried insulating layer 150, and a channel pad 155. Figure 3B As shown in the enlarged view of , the channel layer 140 may be formed in a ring shape at least partially surrounding the channel buried insulating layer 150 therein in the XY plane, but according to an example embodiment, the channel layer 140 may have a column shape such as a column or a prism without the channel buried insulating layer 150. The channel layer 140 may be connected to the first horizontal conductive layer 102 at the bottom. The channel layer 140 may include a semiconductor material such as polycrystalline silicon and / or single crystal silicon.

[0063] The gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer sequentially stacked from the channel layer 140. The tunneling layer may tunnel charges to the charge storage layer and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trap layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high dielectric constant (high κ) dielectric material, or a combination thereof. In example embodiments, at least a portion of the gate dielectric layer 145 may extend along the gate electrode 130 in a horizontal direction (eg, a Y direction).

[0064] The channel pad 155 may be disposed only on an upper end of the top second channel structure CH2. The channel pad 155 may include, for example, doped polysilicon.

[0065] The channel layer 140, the gate dielectric layer 145, and the channel buried insulating layer 150 may be connected to each other between the first channel structure CH1 and the second channel structure CH2. An upper interlayer insulating layer 125 having a relatively large thickness may be disposed between the first channel structure CH1 and the second channel structure CH2. However, in example embodiments, the thickness and shape of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may be variously changed.

[0066] The third channel structures CH3 may penetrate or extend through the second upper gate electrode 130U2 and extend in the Z direction, and may be connected to the second channel structures CH2, respectively. The third channel structures CH3 may be disposed on the second channel structures CH2, respectively, and may be offset from the second channel structures CH2 in a horizontal direction (eg, Y direction), but the present disclosure is not limited thereto.

[0067] Although not specifically shown, each third channel structure CH3 may include an upper channel layer, an upper gate dielectric layer, an upper channel buried insulating layer, and an upper channel pad disposed in the upper channel hole. The upper channel layer may be formed into a ring that at least partially surrounds the upper channel buried insulating layer therein in the XY plane. The upper channel layer may be connected to a connection pad CP at the bottom and may be electrically connected to the channel layer 140 of the second channel structure CH2 through the connection pad CP.

[0068] The above description of each of the channel layer 140, the gate dielectric layer 145, the channel buried insulating layer 150 and the channel pad 155 may be equally applied to the materials of the upper channel layer, the upper gate dielectric layer, the upper channel buried insulating layer and the upper channel pad. The connection pad CP may include a conductive material, such as polysilicon.

[0069] The dummy channel structure DCH is a dummy channel that substantially does not form a memory cell string, and may be referred to as a dummy vertical structure or a support structure.

[0070] The dummy channel structure DCH has the same structure as the channel structure CH, and may be arranged to be spaced apart from each other while forming a plurality of columns in the first boundary region R1b of the first region R1. The dummy channel structure DCH may be arranged in the XY plane in the form of columns sequentially formed in the Y direction. A plurality of dummy channel structures DCH forming each column of the dummy channel structure DCH may be defined as an i-th dummy group DGi (i=1, ..., n).

[0071] The i th dummy group DGi may include dummy channel structures DCHi disposed at both ends in the Y direction, and a distance between the dummy channel structures DCHi at both ends of the i th dummy group DGi may be defined as a length (da, . . . , db) of the i th dummy group DGi.

[0072] The minimum distance between the dummy channel structure DCHi (i=1, ..., n) at either end of the i-th dummy group DGi and the first separation region MS1 ​​or the second central separation region MS2a adjacent to the dummy channel structure DCHi at one end can be defined as the separation distance di (i=1, 2, ..., n) between the i-th dummy group DGi and the separation regions MS1 and MS2a.

[0073] The dummy channel structure DCH may be provided such that, between two separation regions MS1 and MS2a adjacent to each other in the Y direction, a separation distance di (i=1, 2, . . . , n) between the i-th dummy group DGi and the separation regions MS1 and MS2a is variable.

[0074] More specifically, refer to Figure 3A The minimum distance from a center line (center axis) l1 extending in the X direction along the center of the width of the first separation region MS1 ​​or the second central separation region MS2a in the Y direction to the center of the dummy channel structure DCHi at one end of each i-th dummy group DGi can be defined as a separation distance di, and the separation distance di can increase as it approaches the second boundary region R2b (that is, as it approaches the support structure SH).

[0075] In the first boundary region R1b, the separation distance di may increase as it approaches the second boundary region R2b from the cell region R1a, and the change in the separation distance di may be satisfied simultaneously in the dummy channel structures DCHi at both ends. That is, in one dummy group DGi, the separation distance di of the dummy channel structure DCHi at one end may be equal to the separation distance di of the dummy channel structure DCHi at the other end, and the arrangement of the dummy channel structures DCH may be as follows: Figure 1 The one shown is a trapezoid.

[0076] As for the length of a dummy group DGi, due to the change in the separation distance di of the dummy channel structure DCH, the length da of the first dummy group DG1 close to the cell region R1a can be the longest, and the length db of the last nth column (i.e., the nth dummy group DGn close to the second boundary region R2b) can be the shortest, and the length of the dummy group DGi can be reduced as any one of the dummy groups DGi between the first dummy group DG1 and the nth dummy group DGn approaches the nth dummy group DGn.

[0077] The separation distance di of each dummy group DGi may gradually increase from the unit region R1a to the second boundary region R2b. The gradual increase may be defined as the trapezoidal hypotenuse having a constant inclination angle θ1 relative to the center line l1 of the first separation region MS1 ​​or the second central separation region MS2a. That is, the change amount of the separation distance di-1 of the previous dummy group DGi-1 and the separation distance di of the current dummy group DGi may be the same as the change amount of the separation distance di of the current dummy group DGi and the separation distance di+1 of the next dummy group DGi+1.

[0078] Furthermore, a relationship between the separation distances d1 to dn of the plurality of dummy groups DG1 to DGn may be defined according to distances between the plurality of dummy groups DG1 to DGn in the X direction.

[0079] That is, a ratio of a difference di-d1 between the separation distances of the first dummy group DG1 and the i-th dummy group DGi with respect to the distance between the first dummy group DG1 and the i-th dummy group DGi in the X direction may be equal to a ratio of a difference dn-di between the separation distances of the n-th dummy group DGn and the i-th dummy group DGi with respect to the distance between the n-th dummy group DGn and the i-th dummy group DGi in the X direction. The ratios regarding the separation distances of the dummy groups DG1 to DGn may be applied identically to the lengths (da, ..., db) of the dummy groups DG1 to DGn.

[0080] When the length of each dummy group DGi decreases at the same rate, such as Figure 1 As shown, the numbers of dummy channel structures DCH forming each dummy group DGi may be the same as each other, and intervals Ii (i=1, . . . , n) between the dummy channel structures DCH of each dummy group DGi may decrease toward the second boundary region R2b.

[0081] That is, the interval between the dummy channel structures DCH may gradually decrease such that the interval I1 between the dummy channel structures DCH of the first dummy group DG1 is the largest and the distance In between the dummy channel structures DCH of the last dummy group DGn (eg, n=6) is the smallest.

[0082] The dummy channel structure DCHn at one end of the last dummy group DGn is disposed to have a maximum separation distance dn from the first separation region MS1 ​​or the second central separation region MS2a adjacent thereto and may be disposed to have a separation distance dn greater than a reference distance disposed between the separation insulating layer 105 and the first support structure SH1.

[0083] The reference distance may vary depending on the width of the first separation region MS1 ​​or the second central separation region MS2a in the Y direction, and may be a distance in which at least 180 nm is added to 1 / 2 of the width in the Y direction, in some embodiments at least 190 nm is added to 1 / 2 of the width in the Y direction, and in other embodiments at least 192 nm is added to 1 / 2 of the width in the Y direction. That is, the dummy channel structure DCHn at one end of the last dummy group DGn may be disposed to be spaced apart from the outer side surface of the first separation region MS1 ​​or the second central separation region MS2a adjacent thereto by at least 180 nm, by 190 nm or more in some embodiments, and by 192 nm or more in other embodiments.

[0084] In this way, when the dummy channel structure DCH is arranged to form an opening for separating the regions MS1 and MS2a between the conductive channel layer and the non-conductive support structure SH, plasma over-etching due to electric field concentration caused by the difference in conductivity between the conductive channel layer and the non-conductive insulating layer can be reduced or minimized.

[0085] In the first boundary region R1b, the dummy channel structures DCH disposed on both sides in the Y direction with the first separation region MS1 ​​or the second central separation region MS2a in the X direction as an axis may be symmetrical to each other. For example, the dummy channel structure DCH between the first separation region MS1 ​​and the second central separation region MS2a adjacent to each other is arranged to have a trapezoidal shape, and the dummy channel structure DCH opposite to each other with the first separation region MS1 ​​or the second central separation region MS2a in the X direction as an axis may also be arranged to have a trapezoidal shape, and the two trapezoidal arrangements may be symmetrical to each other with the first separation region MS1 ​​or the second central separation region MS2a in the X direction as an axis.

[0086] Arrangements of the channel structures CH and the dummy channel structures DCH between two adjacent first and second center separation regions MS1 and MS2 a may be different from each other.

[0087] like Figure 1 As shown, the channel structures CH may be arranged in a zigzag pattern in one direction, and the dummy channel structures DCH may form multiple columns in the Y direction and may be arranged in a trapezoidal shape. In addition, the density of the channel structures CH may be greater than the density of the dummy channel structures DCH.

[0088] The shape and internal configuration of each dummy channel structure DCH may be the same as those of the channel structure CH, but the size of the dummy channel structure DCH may be greater than that of the channel structure CH.

[0089] Specifically, the diameter w2 or the maximum width of the dummy channel structure DCH may be greater than the diameter w1 or the maximum width of the channel structure CH.

[0090] For example, the diameter w2 of the dummy channel structure DCH may be 90 to 100 nm, and in some embodiments, 95 nm, and the diameter w1 of the channel structure CH may be 80 to 90 nm, and in some embodiments, 85 nm, but embodiments of the present disclosure are not limited thereto.

[0091] The dummy channel structure DCH may include first and second dummy channel structures vertically stacked in the Z direction, and its shape may be described as being the same as those of the first and second channel structures CH1 and CH2 , but embodiments of the present disclosure are not limited thereto.

[0092] The support structure SH disposed in the second region R2 may include a first support structure SH1 disposed in the second boundary region R2b and a second support structure SH2 disposed in the connection region R2a.

[0093] The first supporting structure SH1 and the second supporting structure SH2 may have the same configuration, but the embodiments of the present disclosure are not limited thereto.

[0094] The first support structures SH1 disposed in the second boundary region R2 b close to the first boundary region R1 b in the X-direction may form rows and columns and may be spaced apart from each other.

[0095] In the second boundary region R2b, the contact plug 170 may not be provided, the gate electrode 130 may not be formed to have a stepped portion, and similar to the first boundary region R1b, the second boundary region R2b may include a structure in which all gate electrodes 130 are stacked in the Z direction.

[0096] The boundary region Rb including the first boundary region R1b and the second boundary region R2b may be a buffer region between the contact plug 170 and the channel structure CH used as a memory cell. The first support structure SH1 in the second boundary region R2b and the second support structure SH2 in the connection region R2a may have different arrangements.

[0097] like Figure 1 As shown, the first support structures SH1 may be disposed in a zigzag or matrix arrangement in the second boundary region R2b, and their respective intervals may be the same as each other.

[0098] The separation distance between the first region R1 and the second region R2 (specifically, the separation distance dn from the first separation region MS1 ​​or the second central separation region MS2a to the last dummy group DGn between the first boundary region R1b and the second boundary region R2b) may be greater than the separation distance from the first separation region MS1 ​​or the second central separation region MS2a to the first support structure SH1 adjacent to the first boundary region R1b, but the embodiments of the present disclosure are not limited thereto.

[0099] The plurality of first support structures SH1 may be symmetrical to each other with the first separation region MS1 ​​or the second central separation region MS2a in the X direction as an axis (center line li).

[0100] In the connection region R2a of the second region R2, the second support structures SH2 may be spaced apart from each other while forming rows and columns. Figure 1As shown in the plan view of FIG. 1 , the second support structure SH2 may be disposed to surround each contact plug 170 in four directions. However, in example embodiments, the arrangement form of the second support structure SH2 may be variously changed.

[0101] Between the adjacent first separation regions MS1 and the second central separation regions MS2a, the arrangement of the first support structures SH1 and the arrangement of the second support structures SH2 adjacent to the first support structures SH1 in the X direction may be different from each other, and the second support structures SH2 may be arranged at a higher density, but the embodiments of the present disclosure are not limited thereto.

[0102] Arrangements of the channel structures CH, the dummy channel structures DCH, and the first support structures SH1 between two adjacent first separation regions MS1 or second central separation regions MS2 a may be different from each other.

[0103] The first and second supporting structures SH1 and SH2 may have a pillar shape and may have inclined side surfaces that become narrower as they approach the second substrate 101 depending on an aspect ratio.

[0104] The support structure SH may include two vertically stacked support structures. The support structure SH may have a form in which a lower support structure and an upper support structure are connected, and may have a curved portion due to a width difference in a connection area. However, according to example embodiments, the number of support structures stacked in the Z direction may be variously changed. The diameter or maximum width of the first support structure SH1 and the second support structure SH2 may be greater than the diameter or maximum width of the dummy channel structure DCH. The first support structure SH1 and the second support structure SH2 may have a circular, elliptical, or similar shape in the XY plane.

[0105] The first support structure SH1 and the second support structure SH2 may have an internal structure different from the internal structure of the channel structure CH or the dummy channel structure DCH. Since the first support structure SH1 and the second support structure SH2 do not include a channel layer, they may not include a conductive material and may include a support insulating layer disposed in each support hole. The support insulating layer may include, for example, silicon oxide, silicon nitride and / or silicon oxynitride as an insulating material.

[0106] The contact plug 170 may be connected to the contact region 130P of the gate electrode 130 disposed at the uppermost portion in the connection region R2a. The contact plug 170 may have a shape corresponding to the channel structure CH. Each contact plug 170 includes a lower region and an upper region that penetrate or extend through the stacked structure, respectively, and may have a curved portion whose width changes discontinuously under the upper horizontal insulating layer 191. The lower region may further penetrate the substrate insulating layer 121. The lower region and the upper region may have a cylindrical shape whose width decreases toward the first substrate 201 due to the aspect ratio. Each contact plug 170 may also include a landing region whose width is expanded under the substrate insulating layer 121. However, in some example embodiments, the contact plug 170 may not include a landing region.

[0107] The contact plug 170 may penetrate or extend through at least a portion of the cell region insulating layer 190 and may be connected to each contact region 130P of the gate electrode 130 exposed at the top. The contact plug 170 may penetrate or extend through the gate electrode 130 below the contact region 130P and penetrate or extend through the second horizontal conductive layer 104, the horizontal insulating layer 110, and the second substrate 101, and may be connected to the circuit wiring line 280 in the peripheral circuit region PERI. The contact plug 170 may be spaced apart from the gate electrode 130 below the contact region 130P by the contact insulating layer 160. The contact plug 170 may be spaced apart from the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 by the substrate insulating layer 121.

[0108] Each contact plug 170 may have a shape that extends horizontally in the contact region 130P. The contact plug 170 may include a vertical extension portion 170V extending in the Z direction and a horizontal extension portion 170H extending horizontally from the vertical extension portion 170V to contact the gate electrode 130. The horizontal extension portion 170H may be disposed along the periphery of the vertical extension portion 170V, and its entire side surface may be surrounded by the gate electrode 130. The distance from the side surface of the vertical extension portion 170V to the end of the horizontal extension portion 170H may be less than the distance from the side surface of the vertical extension portion 170V to the outer surface of the contact insulation layer 160. The contact plug 170 may be spaced apart from the gate electrode 130 (that is, the gate electrode 130 that is not electrically connected) below the contact region 130P by the contact insulation layer 160.

[0109] The contact plug 170 may include one or more conductive materials such as tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some example embodiments, the contact plug 170 may include a barrier layer extending along side and bottom surfaces thereof, or may have an air gap therein.

[0110] The contact insulating layer 160 may be disposed under the contact region 130P in the Z direction to at least partially surround the side surface of each contact plug 170 in the XY plane. The contact insulating layer 160 may be disposed around each contact plug 170 to be spaced apart from each other in the Z direction. The contact insulating layer 160 may be disposed at substantially the same level as each gate electrode 130. The contact insulating layer 160 may include an insulating material, such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0111] The upper contact plug 173 may be connected to the second upper gate electrode 130U2. Unlike the contact plug 170, the upper contact plug 173 may not penetrate the second upper gate electrode 130U2. The upper contact plug 173 may be provided to partially recess the second upper gate electrode 130U2 from its upper surface, or may be provided to be connected to its upper surface. The upper contact plug 173 may include a conductive material, and may include the same material as the contact plug 170, but the embodiments of the present disclosure are not limited thereto.

[0112] The through via 175 may be disposed outside the second substrate 101 and may extend to the peripheral circuit region PERI by penetrating or extending through the memory cell region CELL. The upper wiring structure 180 may be configured to connect the upper circuit wiring 183 of the memory cell region CELL to the circuit wiring line 280 of the peripheral circuit region PERI. However, according to example embodiments, in an area where the sacrificial insulating layer 118 not replaced by the gate electrode 130 remains, the through via 175 may be configured to penetrate or extend through a stacked structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120. The shape of the through via 175 may be formed to have a curved portion in the same manner as the contact plug 170. The through via 175 may include one or more conductive materials such as tungsten (W), copper (Cu), aluminum (Al) and alloys thereof.

[0113] The cell region insulating layer 190 may be disposed on and at least partially cover the second substrate 101, the gate electrode 130 on the second substrate 101, and the peripheral region insulating layer 290. The cell region insulating layer 190 may be formed of an insulating material, or may be formed of a plurality of insulating layers.

[0114] An upper horizontal insulating layer 191 may be further formed on the cell region insulating layer 190. The upper horizontal insulating layer 191 may be disposed on the channel structure CH, the dummy channel structure DCH, and the support structure SH. The upper horizontal insulating layer 191 may be disposed at a level higher than the stack structure and the cell region insulating layer 190 in the Z direction. The upper horizontal insulating layer 191 may have a conformal thickness and may be disposed to extend in the X direction and the Y direction. The thickness of the upper horizontal insulating layer 191 may be substantially the same as or less than the thickness of the gate electrode 130. The upper horizontal insulating layer 191 may include a material different from that of the cell region insulating layer 190. The upper horizontal insulating layer 191 may include a material having an etching selectivity relative to the cell region insulating layer 190. For example, the upper horizontal insulating layer 191 may include one or more nitride-based materials, such as silicon nitride and silicon oxynitride. The connection pad CP may penetrate or extend through the upper horizontal insulating layer 191 to be connected to the channel structure CH. The connection pad CP may be a structure at least partially filled in a plurality of holes having shapes such as a circle, an ellipse, and a polygon. In the Z direction (which is a vertical direction), the connection pad CP may partially overlap with the second channel structure CH2. A partial area of ​​each second channel structure CH2 may overlap with the connection pad CP, and the remaining area may overlap with the upper horizontal insulating layer 191. That is, on a plane, the center of the connection pad CP may be spaced apart from the center of each second channel structure CH2.

[0115] The first insulating layer 192 may be disposed on an upper surface of the upper horizontal insulating layer 191. The first insulating layer 192 may have a thickness greater than that of the upper horizontal insulating layer 191. The first insulating layer 192 may include a material having an etching selectivity with respect to the upper horizontal insulating layer 191. The first insulating layer 192 may include, for example, silicon oxide.

[0116] The second upper gate electrode 130U2 (that is, the upper electrode) may be provided on the first insulating layer 192. The second upper gate electrode 130U2 may partially overlap the stacked structure in the Z direction. The second upper gate electrode 130U2 may be disposed on the first region R1. According to example embodiments, the second upper gate electrode 130U2 may extend to the second region R2 and may be disposed on some support structures SH.

[0117] The second upper gate electrode 130U2 may be divided into a plurality of second upper gate electrodes 130U2 by the upper separation region SS. The separated second upper gate electrodes 130U2 may be spaced apart from each other in the Y direction with the upper separation region SS interposed therebetween. Each of the separated second upper gate electrodes 130U2 may include a string selection line.

[0118] The second insulating layer 193 and the third insulating layer 194 may be sequentially stacked on the second upper gate electrode 130U2. The second insulating layer 193 and the third insulating layer 194 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0119] The upper separation region SS may extend in the X direction between the first separation region MS1 ​​and the second separation region MS2a adjacent to each other. The upper separation region SS may be disposed to penetrate or extend through the second upper gate electrode 130U2 and extend in the X direction. The upper separation region SS may penetrate or extend through the upper gate electrode 130U2 and extend into the first insulating layer 192. A lower surface of the upper separation region SS may be disposed at a higher level than the upper horizontal insulating layer 191 in the Z direction.

[0120] An upper separation insulating layer may be disposed in the upper separation region SS. In an example embodiment, the upper separation insulating layer may include an insulating material such as silicon oxide. However, according to example embodiments, the upper separation region SS may include at least a portion of the material of the third channel structure CH3. For example, each upper separation region SS may include a buried semiconductor pattern and a barrier.

[0121] The third channel structure CH3 and the connecting pad CP may not be set on the dummy channel structure DCH in the first region R1, and the stacked structure of the upper horizontal insulating layer 191, the first insulating layer 192, the second upper gate electrode 130U2, and the second and third insulating layers 193 and 194 may be set on the dummy channel structure DCH in the first boundary region R1b where the dummy channel structure DCH is set.

[0122] Therefore, the configuration of the dummy channel structure DCH may be the same as or similar to that of the channel structure CH, and may be set to a floating state (in which electrical conduction is blocked) so that the dummy channel structure DCH cannot be used as a memory cell.

[0123] The upper separation region SS may extend from the cell region R1a to the first boundary region R1b where the dummy channel structure DCH is disposed, but since the upper separation region SS is not disposed at the same level as the dummy channel structure DCH in the Z direction, the degree of freedom of arrangement of the dummy channel structure DCH may be increased.

[0124] The upper wiring structure 180 may include a conductive material and may be electrically connected to the upper channel structure CH3. The upper wiring structure 180 may include an upper contact plug 181 and an upper circuit wiring 183. The upper contact plug 181 may penetrate or extend through the third upper insulating layer 194 to contact the upper surface of the third channel structure CH3, each contact plug 170, and the through-via 175. The upper circuit wiring 183 may be disposed on the upper contact plug 181 and the third upper insulating layer 194. Some of the upper circuit wirings 183 may be bit lines in contact with the contact plugs 181. The bit lines may extend in the Y direction perpendicular to the X direction, and the upper separation region SS extends in the X direction. According to the circuit design, a multilayer plug may be disposed between the upper circuit wiring 183 and the upper contact plug 181, but the embodiments of the present disclosure are not limited thereto.

[0125] Figures 4 to 8 is a schematic plan view of a semiconductor device according to example embodiments.

[0126] Reference Figure 4 In the semiconductor device 100a, the dummy channel structures DCH of the first boundary region R1b may form a plurality of columns and may be spaced apart from each other. The dummy channel structures DCH may be arranged to form a plurality of columns in the Y direction in the XY plane, and the dummy channel structures DCH in each column may be defined as a dummy group DGi. Each dummy group DGi may include dummy channel structures DCHi at both ends thereof, and may be arranged to simultaneously change the separation distance di between the dummy channel structures DCHi at each end thereof and the first separation region MS1 ​​or the second central separation region MS2a adjacent thereto.

[0127] Specifically, refer to Figure 4 , a separation distance di from a center line l1 extending in the X direction along the center of the width of the first separation region MS1 ​​or the second central separation region MS2a in the Y direction to the dummy channel structure DCHi at one end of the dummy group DGi may increase as the distance from the second boundary region R2b decreases.

[0128] In the first boundary region R1b, each separation distance di of the first dummy group DG1 to the nth dummy group DGn increases as the distance from the second boundary region R2b decreases, and the separation distance di can be simultaneously satisfied in the dummy channel structures DCHi at both ends, so the shape of the dummy channel structure DCH can form a trapezoid, such as Figure 4 That is, the separation distance di from the dummy channel structure DCHi at one end in one column may be the same as the separation distance di from the dummy channel structure DCHi at the other end.

[0129] The separation distance di of each dummy group DGi may gradually increase from the cell region R1a to the second boundary region R2b. The gradual increase may be considered that the trapezoidal hypotenuse has a constant inclination angle θ1 relative to the center line l1 of the first separation region MS1 ​​or the second central separation region MS2a.

[0130] Furthermore, a relationship between the separation distances d1 to dn of the plurality of dummy groups DG1 to DGn may be defined according to distances between the plurality of dummy groups DG1 to DGn in the X direction.

[0131] That is, a ratio of a difference di-d1 between the separation distances of the first dummy group DG1 and the i-th dummy group DGi to the distance in the X direction between the first dummy group DG1 and the i-th dummy group DGi may be equal to a ratio of a difference dn-di between the separation distances of the n-th dummy group DGn and the i-th dummy group DGi to the distance in the X direction between the n-th dummy group DGn and the i-th dummy group DGi.

[0132] In this manner, when the length of each dummy group DGi is reduced at the same rate, intervals between the dummy channel structures DCH in each column in the Y direction are identical to each other, and the number of dummy channel structures DCH forming each dummy group DGi can be reduced.

[0133] That is, when the first dummy group DG1 has nine dummy channel structures DCH, the next dummy group DG2 may be set such that the number of dummy channel structures DCH decreases by one.

[0134] The dummy channel structure DCHi at one end of the last dummy group DGn may be disposed to have a maximum separation distance from the separation regions MS1 and MS2 a and may be disposed to have a distance greater than a reference distance between the separation insulating layer 105 and the first support structure SH1 .

[0135] The dummy channel structures DCH may be symmetrically disposed in the first boundary region R1 b with the separation regions MS1 and MS2 a in the X direction as an axis.

[0136] Reference Figure 5 , in the semiconductor device 100b, in the first boundary region R1b, a separation distance di from a center line l1 extending in the X direction along the center of the width of the first separation region MS1 ​​or the second central separation region MS2a in the Y direction to the dummy channel structure DCHi at one end of each dummy group DGi may increase as the distance from the second boundary region R2b decreases.

[0137] The dummy channel structure DCH may be configured to have a shape such as Figure 5The separation distance di at one end of the dummy group DGi may be the same as the separation distance di at the other end of the dummy group DGi.

[0138] When the separation distance di of each dummy group DGi increases at the same rate, the intervals Ii (i=1, 2, . . . , n) between the dummy channel structures DCH and the number of dummy channel structures DCH of each dummy group DGi in the Y direction may vary.

[0139] That is, when the first dummy group DG1 has nine dummy channel structures DCH and the interval I1 between the dummy channel structures DCH in the Y direction has a first value, the number of dummy channel structures DCH of the second dummy group DG2 is nine as in the first dummy group DG1, but the interval I2 between the dummy channel structures DCH in the Y direction may satisfy a second value smaller than the first value. Therefore, the length of the second dummy group DG2 may be smaller than the length of the first dummy group DG1.

[0140] In the third dummy group DG3 , the dummy channel structures DCH may be reduced to eight, and an interval I3 between the dummy channel structures DCH may satisfy the first value.

[0141] In this manner, the example in which the number of dummy channel structures DCH decreases and the example in which the interval between the dummy channel structures DCH decreases may be repeated, thereby gradually decreasing the length of the dummy group DGi toward the second boundary region R2 b.

[0142] In this example, the inclination angle θ2 of the separation distance di may have a value greater than Figure 4 The smaller the value of the inclination angle θ1 of the separation distance di.

[0143] Therefore, the separation distance di between the dummy channel structure DCHi at both ends and the separation regions MS1 and MS2a can meet the reference distance or more, and at the same time, the area without vertical structure between the dummy channel structure DCHi at both ends and the adjacent separation regions MS1 and MS2a can be reduced or minimized.

[0144] Reference Figure 6 In the semiconductor device 100c, the dummy channel structures DCH of the first boundary region R1b may form a plurality of columns and may be spaced apart from each other, and a separation distance di between each dummy group DGi and a center line l1 extending in the X direction along the center of the width of the separation regions MS1 and MS2a in the Y direction may increase rapidly as the distance from the second boundary region R2b decreases.

[0145] The separation distance di of each dummy group DGi can increase at different ratios, and the ratio of the separation distance di of the dummy group DGi close to the cell region R1a can be very small, and as the dummy group DGi approaches the second boundary region R2b, the ratio can increase rapidly. When the intervals Ii in the Y direction between the dummy channel structures DCH of each dummy group DGi are the same as each other, the number of dummy channel structures DCH of each dummy group DGi can decrease rapidly as it approaches the second boundary region R2b. That is, when there are nine dummy channel structures DCH in the first dummy group DG1 and the second dummy group DG2, the number of dummy channel structures DCH that are reduced when the distance from the second boundary region R2b is reduced can increase rapidly to two or three.

[0146] In other embodiments, when the intervals Ii between the dummy channel structures DCH of each dummy group DGi in the Y direction are different from each other, the intervals Ii between the dummy channel structures DCH of each dummy group DGi can be rapidly reduced as the distance from the second boundary region R2b decreases. In addition, as the intervals Ii between the dummy channel structures DCH of each dummy group DGi in the Y direction and the number of dummy channel structures DCH change to reduce the distance from the second boundary region R2b, the ratio of the separation distance di can be rapidly increased. Therefore, the arrangement of the dummy channel structures DCH in the first boundary region R1b can have a bell shape, but the embodiments of the present disclosure are not limited thereto.

[0147] Since the separation distance di has a large value only in a portion close to the second boundary region R2 b , an area without a vertical structure can be reduced or minimized while ensuring a reference distance from the separation regions MS1 and MS2 a .

[0148] Reference Figure 7 In the semiconductor device 100d, each of the separation regions MS1 and MS2a including the first separation region MS1 ​​and the second central separation region MS2a may include an expansion portion Mw extending in the X direction by having a first width in the Y direction and having a second width greater than the first width.

[0149] The expansion portion Mw may be disposed between the first boundary region R1b and the second boundary region R2b, specifically, in the boundary region Rb in which the dummy channel structure DCH and the first support structure SH1 are disposed.

[0150] The extension portion Mw may have a variable width and may be Figure 7As shown, the extension portion Mw may have a shape in which its width increases to produce a maximum width in the last column of the dummy channel structure DCH (ie, in a region facing the dummy group DGn having the shortest length), and its width gradually decreases toward the second boundary region R2b.

[0151] For example, the expansion portion Mw may have a stepped structure that gradually increases in width, and the expansion portion Mw may decrease again in a stepped manner when passing through the maximum width portion toward the second boundary region R2b. In other embodiments, the expansion portion Mw may have a curved surface and may have an elliptical shape with an increased width, but embodiments of the present disclosure are not limited thereto.

[0152] In this example, Figure 1 , Figure 4 , Figure 5 and Figure 6 Any one of the above can be applied to the arrangement of the dummy channel structure DCH. In this way, the separation distance di of the last dummy group DGn close to the first support structure SH1 can satisfy the reference distance or more from the center line l1 of the width of the first separation region MS1 ​​or the second central separation region MS2a, and at the same time, the distance between the outer side of the separation insulating layer 105 of the extension part Mw and the dummy channel structure DCH arranged to correspond to the extension part Mw with an increased width can satisfy the predetermined distance or less. Therefore, the area without a vertical structure can be reduced or minimized to prevent or reduce the risk of collapse, and at the same time, when forming an opening for the first separation region MS1 ​​or the second central separation region MS2a, the aspect ratio can be reduced to alleviate plasma over-etching.

[0153] A separation distance dn from a dummy channel structure DCHn at one end of the nth dummy group DGn adjacent to an extended portion Mw of one of the first separation region MS1 ​​and the second central separation region MS2a to the first separation region MS1 ​​or the second central separation region MS2a may be less than a minimum distance between the first separation region MS1 ​​or the second central separation region MS2a and a channel structure CH at one end adjacent thereto in the cell region R1a.

[0154] Reference Figure 8 In the semiconductor device 100e, among the first separation region MS1 ​​and the second separation regions MS2a and MS2b, a separation insulating layer 105 forming the first separation region MS1 ​​and the second central separation region MS2a extending from the first region R1 to the second region R2 may have a protrusion RD protruding from the side surface to the dummy channel structure DCH between the first region R1 and the second region R2 (specifically, between the first boundary region R1b and the second boundary region R2b).

[0155] The protrusion RD may be a structure formed by bending the separation insulating layer 105 toward the dummy channel structure DCH, but the separation insulating layer 105 may be a structure extending in the X direction and partially protruding from a side surface thereof.

[0156] The protrusion RD may be disposed at a lower portion of a side surface of the separation insulating layer 105 on the second substrate 101 , ie, under the upper interlayer insulating layer 125 , but is not limited thereto.

[0157] The size of the protrusion RD (specifically, the farthest distance from the outer side surface of the separation insulating layer 105 to the outer surface of the protrusion RD) may be about 195 nm or less, 192 nm or less in some embodiments, and 170 nm or less in other embodiments. The protrusion RD may have a length corresponding to at least one gate electrode 130 below the upper interlayer insulating layer 125, but the embodiments of the present disclosure are not limited thereto. The farthest point of the outer surface of the protrusion RD may be biased toward the dummy channel structure DCH, but the embodiments of the present disclosure are not limited thereto.

[0158] In the case where the first separation region MS1 ​​and the second separation region MS2a in the X direction are used as the axis, the channel structures CH provided on both sides in the Y direction may be symmetrical with respect to the first separation region MS1 ​​and any one of the second separation regions MS2a and MS2b. In addition, in the case where the first separation region MS1 ​​and the second separation region MS2a in the X direction are used as the axis, the dummy channel structures DCH provided on both sides in the Y direction may be symmetrical for one of the first separation region MS1 ​​and the second separation region MS2a. In addition, in the case where the first separation region MS1 ​​and the second separation region MS2a in the X direction are used as the axis, the first support structures SH1 provided on both sides in the Y direction may be symmetrical for one of the first separation region MS1 ​​and the second separation region MS2a.

[0159] The dummy channel structures DCH of the first boundary region R1b may form a plurality of columns in the Y direction and may be spaced apart from each other, and separation distances di of the plurality of dummy groups DGi from a center line l1 extending in the X direction along the center of the width of the separation regions MS1 and MS2a in the Y direction may all be the same as each other.

[0160] The intervals of the dummy channel structures DCH of each dummy group DGi may be the same, the number of the dummy channel structures DCH may be the same, the dummy channel structures DCH may be arranged in a matrix, and the distance from the dummy channel structure DCH at one end of the last dummy group DGn to the protrusion RD may meet a reference value or greater.

[0161] The reference value may be at least 180 nm or more, 190 nm or more in some embodiments, and 192 nm or more in other embodiments, but the embodiments of the present disclosure are not limited thereto.

[0162] Some protrusions RD may be formed by ensuring symmetrical arrangement of the channel structure CH and the dummy channel structure DCH and a separation distance di between the dummy channel structure DCH and the first and second separation regions MS1, MS2a, and MS2b being equal to or greater than a reference value, but the protrusion RD may be reduced or minimized so as not to cause device defects such as the occurrence of leakage current.

[0163] Fig. 9 is a schematic cross-sectional view of a semiconductor device 100 f according to example embodiments. Fig. 9 Shown corresponding to Figure 2A cross section.

[0164] Reference Fig. 9 The semiconductor device 100f may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded by a wafer bonding method.

[0165] For the above reference Figures 1 to 3B The description of the peripheral circuit region PERI described can be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 may also include a first bonding path 295, a first bonding metal layer 298, and a first bonding insulating layer 299 as a bonding structure. The first bonding path 295 may be arranged above the circuit wiring line 280 in the Z direction at the uppermost part and may be connected to the circuit wiring line 280. At least a portion of the first bonding metal layer 298 may be connected to the first bonding path 295 on the first bonding path 295. The first bonding metal layer 298 may be connected to the second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298 may provide an electrical connection path according to the bonding between the first semiconductor structure S1 and the second semiconductor structure S2 together with the second bonding metal layer 198. Some of the first bonding metal layer 298 may not be connected to the circuit wiring line 280 of the lower part and may be provided only for bonding. The first bonding path 295 and the first bonding metal layer 298 may include a conductive material, such as copper (Cu). The first bonding insulating layer 299 may be arranged around the first bonding metal layer 298. The first bonding insulating layer 299 may serve as a diffusion barrier for the first bonding metal layer 298 , and may include one or more insulating materials, for example, SiN, SiON, SiCN, SiOC, SiOCN, and / or SiO.

[0166] Unless otherwise specified, the above references Figures 1 to 3BThe description of the memory cell region CELL described may be applied to the second semiconductor structure S2. The second semiconductor structure S2 may include an upper circuit wiring 183 as a cell wiring structure, and may also include a second bonding via 196, a second bonding metal layer 198, and a second bonding insulating layer 199 as a bonding structure. The second semiconductor structure S2 may also include a passivation layer 106 on the upper surface of the second substrate 101 and the upper surface of the substrate insulating layer 121 and at least partially covering the upper surface of the second substrate 101 and the upper surface of the substrate insulating layer 121.

[0167] The upper circuit wiring 183 may be connected to the upper contact plug 181. However, in example embodiments, the number and arrangement of layers of plugs and wiring lines forming the cell wiring structure may be variously changed. The upper circuit wiring 183 may be formed of a conductive material and may include, for example, one or more of tungsten (W), aluminum (Al), and / or copper (Cu).

[0168] The second bonding via 196 and the second bonding metal layer 198 may be disposed below the upper circuit wiring 183 in the Z direction. The second bonding via 196 may connect the upper circuit wiring 183 to the second bonding metal layer 198, and the second bonding metal layer 198 may be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 may be bonded and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 196 and the second bonding metal layer 198 may include a conductive material, such as copper (Cu). The second bonding insulating layer 199 may include, for example, one or more of SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN.

[0169] The first semiconductor structure S1 and the second semiconductor structure S2 can be bonded by bonding the first bonding metal layer 298 to the second bonding metal layer 198 and bonding the first bonding insulating layer 299 to the second bonding insulating layer 199. The bonding of the first bonding metal layer 298 and the second bonding metal layer 198 can be, for example, copper (Cu)-copper (Cu) bonding, and the bonding of the first bonding insulating layer 299 and the second bonding insulating layer 199 can be, for example, dielectric-dielectric bonding, such as SiCN-SiCN bonding. The first semiconductor structure S1 and the second semiconductor structure S2 can be bonded by a hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0170] The passivation layer 106 may be disposed on the upper surface of the second substrate 101 and may protect the semiconductor device 100f. The passivation layer 106 may include one or more insulating materials, such as silicon oxide, silicon nitride, and / or silicon carbide. The substrate insulating layer 121 may be widely disposed in the connection region R2a to be on the upper end of the contact plug 170 and at least partially cover the upper end of the contact plug 170. However, in example embodiments, the substrate insulating layer 121 may have various arrangements within the range of electrically separating the contact plug 170 from the second substrate 101.

[0171] In this example embodiment, the second semiconductor structure S2 may not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (see Figure 2A ). The first channel structure CHf may be directly connected to the second substrate 101 in a state where the channel layer 140 is exposed through its upper end. However, the electrical connection form of the first channel structure CHf and the common source line may be variously changed in example embodiments, and the first channel structure and the source structure may have the same Figure 2A The same structure as the example implementation is shown.

[0172] Figure 2A , FIG. 10A to FIG. 10K and Fig.11 is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. FIG. 10A to FIG. 10K is corresponding to Figure 2A The cross section, Fig.11 is corresponding to Figure 2C cross section.

[0173] Reference Figure 2A and Fig. 10A A peripheral circuit region PERI including a circuit element 220 and a circuit wiring structure may be formed on the first substrate 201, and a second substrate 101, a horizontal insulating layer 110, a second horizontal conductive layer 104 and a substrate insulating layer 121 may be formed on the peripheral circuit region PERI.

[0174] First, a device isolation layer 210 may be formed in the first substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the first substrate 201. The device isolation layer 210 may be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 may be formed of silicon oxide, and the circuit gate electrode 225 may be formed of at least one of polysilicon and metal silicide, but the embodiments of the present disclosure are not limited thereto. Next, a spacer layer 224 and a source / drain region 205 may be formed on both sidewalls of the circuit gate dielectric layer 222 and both sidewalls of the circuit gate electrode 225. According to an example embodiment, the spacer layer 224 may be formed of a plurality of layers. Next, the source / drain region 205 may be formed by performing an ion implantation process.

[0175] The circuit contact plug 270 of the circuit wiring structure may be formed by forming a portion of the peripheral region insulating layer 290, then partially etching and removing the formed peripheral region insulating layer 290, and burying a conductive material in the removed portion. The circuit wiring line 280 may be formed, for example, by depositing a conductive material and then patterning it.

[0176] The peripheral region insulating layer 290 may be formed of a plurality of insulating layers. The peripheral region insulating layer 290 may be partially formed in each operation of forming the circuit wiring structure, may be partially formed in the upper portion of the uppermost circuit wiring line 280, and may be finally formed on the circuit element 220 and the circuit wiring structure and at least partially cover the circuit element 220 and the circuit wiring structure.

[0177] Next, refer to Fig. 10B On the peripheral circuit region PERI, a second substrate 101 provided with a memory cell region CELL, a horizontal insulating layer 110, a second horizontal conductive layer 104 and a substrate insulating layer 121 can be formed, and sacrificial insulating layers 118 and interlayer insulating layers 120 can be alternately stacked to form a lower stacked structure and form a first vertical sacrificial layer 116a and a first contact sacrificial layer 119a.

[0178] The second substrate 101 may be formed on the peripheral region insulating layer 290. The second substrate 101 may be formed of, for example, polysilicon, and may be formed through a CVD process. The polysilicon forming the second substrate 101 may include impurities.

[0179] When forming the second substrate 101, the landing pad 171 may be formed together on the uppermost circuit wiring line 280. The landing pad 171 may be formed in which the contact plug 170 (see FIG. 1 ) is disposed. Figure 2A). First, before forming the second substrate 101, an opening may be formed by partially removing the peripheral region insulating layer 290 from the uppermost circuit wiring line 280. When forming the second substrate 101, the landing pad 171 may be formed by at least partially filling the opening with a material forming the second substrate 101. The opening may be formed, for example, together with a ground path for connecting the second substrate 101 and the circuit wiring structure.

[0180] The first horizontal insulating layer 111 and the second horizontal insulating layer 112 forming the horizontal insulating layer 110 may be alternately stacked on the second substrate 101. The horizontal insulating layer 110 may be partially formed by a subsequent process. Figure 2A The first horizontal insulating layer 111 may include a material different from that of the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the subsequent sacrificial insulating layer 118. The horizontal insulating layer 110 may be partially removed from some regions (e.g., the second region R2) through a patterning process.

[0181] The second horizontal conductive layer 104 may be formed on the horizontal insulating layer 110 and may contact the second substrate 101 in a region where the horizontal insulating layer 110 is removed. Therefore, the second horizontal conductive layer 104 may be bent along an end of the horizontal insulating layer 110, and may be on and at least partially cover the end of the horizontal insulating layer 110, and extend onto the second substrate 101.

[0182] The substrate insulating layer 121 may be formed to include a contact plug 170 (see FIG. Figure 2A ) penetrates or extends through the second substrate 101 in some areas of the area. The substrate insulating layer 121 can be formed by partially removing the second substrate 101, the horizontal insulating layer 110 and the second horizontal conductive layer 104, and then burying the insulating material in the removed portion. After the insulating material is embedded, a planarization process can be further performed using a chemical mechanical polishing (CMP) process. Therefore, the upper surface of the substrate insulating layer 121 can be substantially coplanar with the uppermost surface of the second horizontal conductive layer 104.

[0183] Next, a first channel structure CH1 (see FIG. 1 ) may be provided on the second horizontal conductive layer 104 and the substrate insulating layer 121. Figure 2A ) to form a lower stacking structure.

[0184] The sacrificial insulating layer 118 may be at least partially replaced by the gate electrode 130 (see Figure 2A) is replaced by a portion of the interlayer insulating layer 118. The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120. For example, the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may be formed of silicon oxide and / or silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, such as, for example, silicon oxide, silicon carbide, and / or silicon nitride. According to example embodiments, the thickness of the interlayer insulating layer 120 may not all be the same. In addition, the thickness of the interlayer insulating layer 120 and the sacrificial insulating layer 118 and the number of layers formed may be changed in various ways from those shown in the drawings.

[0185] Interlayer insulating layers 120 and sacrificial insulating layers 118 forming a lower stack structure are alternately stacked on the second horizontal conductive layer 104 .

[0186] The gate contact region 130P may be formed by repeatedly performing photolithography and etching processes on the sacrificial insulating layer 118 and the interlayer insulating layer 120. The gate contact region 130P may be formed in the connection region R2a of the second region R2, and may be formed to include a region in which the sacrificial insulating layer 118 at the upper portion extends shorter than the sacrificial insulating layer 118 at the lower portion. In the gate contact region 130P, an asymmetric step structure GP may be formed so that the upper surfaces and ends of the plurality of sacrificial insulating layers 118 are exposed upward. However, in example embodiments, the specific shape of the gate contact region 130P may be variously changed. A sacrificial insulating layer 118 may be further formed on the step structure GP of the gate contact region 130P, thereby allowing the sacrificial insulating layer 118 disposed in the uppermost portion of each region to have a relatively thick thickness.

[0187] Next, a cell region insulating layer 190 may be formed on the lower stack structure and at least partially cover a lower portion of the lower stack structure, and a first vertical sacrificial layer 116 a penetrating or extending through the lower stack structure may be formed.

[0188] The first vertical sacrificial layer 116a may be formed in the first region R1 and the second boundary region R2b at a position corresponding to the first channel structure CH1, the lower portion of the dummy channel structure DCH, and the lower portion of the support structure SH. The first contact sacrificial layer 119a may be formed in the connection region R2a at a position corresponding to the contact plug 170 (see Figure 2A) corresponding to a position. The first vertical sacrificial layer 116a and the first contact sacrificial layer 119a may be formed simultaneously. The first vertical sacrificial layer 116a and the first contact sacrificial layer 119a may be formed by forming a first hole that penetrates or extends through the lower stacked structure, then depositing a sacrificial layer material in the first hole, and performing a planarization process. The first hole may include a hole corresponding to the first channel structure CH1, the dummy channel structure DCH, the support structure SH, and the contact plug 170. The first vertical sacrificial layer 116a and the first contact sacrificial layer 119a may include, for example, TiN and / or polysilicon.

[0189] Reference Fig. 10C A sacrificial insulating layer 118 and an interlayer insulating layer 120 of an upper stack structure may be alternately stacked on the lower stack structure, a step structure GP having a step shape may be formed, an upper unit area insulating layer 190 may be formed, and a second vertical sacrificial layer 116b and a second contact sacrificial layer 119b may be formed.

[0190] Each configuration of the upper stack structure may be formed in the same manner as the method of forming the lower stack structure.

[0191] The second vertical sacrificial layers 116b may be formed to be connected to the first vertical sacrificial layers 116a, respectively. The second contact sacrificial layers 119b may be formed to be connected to the first contact sacrificial layers 119a, respectively. The second vertical sacrificial layers 116b and the second contact sacrificial layers 119b may be formed by depositing the same material (e.g., polysilicon) as the first vertical sacrificial layers 116a.

[0192] Reference Fig. 10D , first and second channel structures CH1 and CH2 penetrating or extending through the lower and upper stack structures and a dummy channel structure DCH may be formed.

[0193] The first and second channel structures CH1 and CH2 may be formed by removing the first and second vertical sacrificial layers 116a and 116b and forming hole-shaped channel holes and sequentially depositing at least a portion of the gate dielectric layer 145 , the channel layer 140 , the channel buried insulating layer 150 , and the channel pad 155 in the channel holes.

[0194] The gate dielectric layer 145 may be formed to have a substantially uniform thickness using an ALD or CVD process. In this operation, all or part of the gate dielectric layer 145 may be formed, and a portion extending vertically to the second substrate 101 along the first channel structure CH1 and the second channel structure CH2 may be formed in this operation. The channel layer 140 may be formed on the gate dielectric layer 145 in the channel hole. The channel buried insulating layer 150 may be formed to at least partially fill the channel hole and may be an insulating material. The channel pad 155 may be formed of a conductive material (e.g., polysilicon). The dummy channel structure DCH may also be formed into the same shape as the first channel structure CH1 and the second channel structure CH2 by removing the first vertical sacrificial layer 116a and the second vertical sacrificial layer 116b.

[0195] After forming the channel structure CH and the dummy channel structure DCH, the support structure SH of the second region R2 may also be formed in a similar manner (see Figure 1 and Figure 2A ). Specifically, the support structure SH may be formed by removing the first vertical sacrificial layer 116a and the second vertical sacrificial layer 116b and forming a support hole, and then at least partially filling the support hole with a supporting insulating layer.

[0196] Reference Fig. 10E , the first contact hole OH may be formed by removing the first contact sacrificial layer 119a and the second contact sacrificial layer 119b.

[0197] The first contact hole OH may be formed by selectively removing the first contact sacrificial layer 119a and the second contact sacrificial layer 119b and further removing the exposed landing pad 171. The circuit wiring line 280 may be exposed through the bottom surface of the first contact hole OH. In some example embodiments, the landing pad 171 may not be removed in this operation, but may be removed in a subsequent operation.

[0198] Reference Fig.10F and Fig.11 , an initial contact insulating layer 160P and a vertical sacrificial layer 195 may be formed in the first contact hole OH, and the sacrificial insulating layer 118 may be removed.

[0199] First, the sacrificial insulating layer 118 exposed through the first contact hole OH may be partially removed. A contact tunnel portion may be formed by removing a predetermined length of the sacrificial insulating layer 118 from the periphery of the first contact hole OH. The contact tunnel portion is formed to have a relatively short length in the uppermost sacrificial insulating layer 118, and may be formed to have a relatively long length in the sacrificial insulating layer 118 therebelow.

[0200] Specifically, initially, on the contrary, the contact tunnel portion may be formed to be relatively long in the uppermost sacrificial insulating layer 118. This may be because the uppermost sacrificial insulating layer 118 includes a region having a relatively faster etching rate than the sacrificial insulating layer 118 below it. Next, a separate sacrificial layer may be formed in the first contact hole OH and the contact tunnel portion. The sacrificial layer may be formed of a material having an etching rate lower than that of the sacrificial insulating layer 118. Next, a portion of the sacrificial layer and a portion of the sacrificial insulating layer 118 may be removed, in which case the sacrificial layer may be retained in the uppermost portion, and the sacrificial layer may be removed to partially remove the sacrificial insulating layer 118 in the lower portion. Therefore, in the end, the contact tunnel portion may be formed to have a relatively short length in the uppermost sacrificial insulating layer 118.

[0201] The initial contact insulating layer 160P may be formed by depositing an insulating material in the first contact hole OH and the contact tunnel portion. The initial contact insulating layer 160P may be formed on the sidewall of the first contact hole OH and may at least partially fill the contact tunnel portion. In the uppermost sacrificial insulating layer 118, the initial contact insulating layer 160P may not completely fill the contact tunnel portion.

[0202] The vertical sacrificial layer 195 may at least partially fill the first contact hole OH and at least partially fill the uppermost contact tunnel portion. The vertical sacrificial layer 195 may include a material different from that of the initial contact insulating layer 160P and may include, for example, polysilicon.

[0203] Next, if Fig.11 As shown, the first separation area MS1 and the second separation areas MS2a and MS2b (see Figure 1 ) is formed at a position of the second substrate 101 by penetrating or extending through the sacrificial insulating layer 118 and the interlayer insulating layer 120. Next, an etch-back process may be performed while forming a separate sacrificial spacer layer in the opening OP, and in the first region R1, the horizontal insulating layer 110 may be selectively removed, and a portion of the exposed first gate dielectric layer 145 may also be removed. After forming the first horizontal conductive layer 102 by depositing a conductive material in a region where the horizontal insulating layer 110 has been removed, the sacrificial spacer layer may be removed within the opening. Through this operation, the first horizontal conductive layer 102 may be formed in the first region R1.

[0204] During etching in the process of forming the opening OP, charged ions in plasma may be concentrated toward the dummy channel structure DCH according to the difference in Coulomb force between the dummy channel structure DCH and the support structure SH, which may cause defects such as over-etching toward the dummy channel structure DCH.

[0205] Since the dummy channel structure DCH includes a conductive channel layer and the first support structure SH1 does not include a conductive material, this etching asymmetry is caused by the difference in conductivity. However, in this example embodiment, the channel structure CH and the dummy channel structure DCH can be symmetrically arranged about the center line l1 of the width of the first separation region MS1 ​​and the second central separation region MS2a, and since the dummy channel structure DCH is arranged by forming a column, they can be arranged so that the separation distance di between the dummy channel structure DCH at one end of each column and the separation regions MS1 and MS2a increases as the distance from the first support structure SH1 decreases. Therefore, the separation distance di between the dummy channel structure DCH at one end and the separation regions MS1 and MS2a increases as it approaches the second boundary region R2b in the first boundary region R1b, and the influence of the dummy channel structure DCH on the conductive channel layer can be weakened to disperse the electric field. Due to the electric field dispersion, the protrusion generated by bending the side surface of the opening OP in the Y direction can be reduced or minimized, thereby preventing or reducing the risk of defects such as leakage current.

[0206] Next, the sacrificial insulating layer 118 may be selectively removed from the interlayer insulating layer 120 , the second horizontal conductive layer 104 , and the initial contact insulating layer 160P, for example, using wet etching.

[0207] Reference Figure 10G , a gate electrode 130 may be formed.

[0208] The gate electrode 130 may be formed by depositing a conductive material in a region where the sacrificial insulating layer 118 has been removed. The conductive material may include metal, polysilicon, and / or metal silicide materials. In some example embodiments, a portion of the first gate dielectric layer 145 may be formed first before forming the gate electrode 130.

[0209] After forming the gate electrode 130, a gate separation insulating layer 105 may be formed in the opening formed to correspond to the first separation region MS1 ​​(see Figure 2B ).

[0210] Reference Fig. 10H , an upper horizontal insulating layer 191 and a connection pad CP may be formed, a second upper gate electrode 130U2 may be formed, and a third channel structure CH3 penetrating or extending through the second upper gate electrode 130U2 may be formed.

[0211] The upper horizontal insulating layer 191 may be formed on the second channel structure CH2, the dummy channel structure DCH, and the support structure SH. The connection pad CP may be patterned on the second channel structure CH2 to connect to the channel pad 155 of the second channel structure CH2, or may be formed by partial conversion of the upper horizontal insulating layer 191. Next, a first insulating layer 192 may be formed, and a second upper gate electrode 130U2 may be patterned and formed. The second upper gate electrode 130U2 may include a material different from that of the other gate electrodes 130, but the present disclosure is not limited thereto. For example, the second upper gate electrode 130U2 may include polysilicon. Next, a second insulating layer 193 may be further formed.

[0212] In order to form the third channel structure CH3, an upper channel hole penetrating or extending through the second upper gate electrode 130U2 may be first formed, and then an upper gate dielectric layer, an upper channel layer, an upper channel buried layer, and an upper channel pad may be sequentially formed, thereby forming the third channel structure CH3. Each layer may be formed in the same manner as the first channel structure CH1 and the second channel structure CH2. The upper channel layer 140U may be formed to be connected to the connection pad CP at its lower end.

[0213] Reference Fig.10I , a first opening OP1 and a second opening OP2 may be formed.

[0214] The first opening OP1 and the second opening OP2 may be formed to penetrate or extend through at least a portion of the second insulating layer 193. The first opening OP1 may be formed to at least partially expose the second upper gate electrode 130U2, and the second opening OP2 may penetrate or extend through the second insulating layer 193 and the upper horizontal insulating layer 191 so that the vertical sacrificial layer 195 may be at least partially exposed. The first opening OP1 and the second opening OP2 may be formed simultaneously or may be formed by separate processes.

[0215] Reference Fig.10J , the vertical sacrificial layer 195 exposed through the second opening OP2 may be removed, and a portion of the initial contact insulating layer 160P may be removed to form a second contact hole OH′.

[0216] The vertical sacrificial layer 195 may be selectively removed relative to the interlayer insulating layer 120 and the gate electrode 130. After removing the vertical sacrificial layer 195, a portion of the exposed initial contact insulating layer 160P may also be removed. In this case, all of the initial contact insulating layer 160P may be removed from the contact region 130P (see FIG. Figure 2A) The uppermost gate electrode 130 corresponding to the initial contact insulating layer 160P is removed, and a remaining contact insulating layer 160 may be formed thereunder. In the contact region 130P, when the first gate dielectric layer 145 is exposed after the initial contact insulating layer 160P is removed, the first gate dielectric layer 145 may also be removed, thereby at least partially exposing the side surface of the gate electrode 130.

[0217] Reference Figure 10K , the contact plug 170 and the upper contact plug 173 may be formed.

[0218] The contact plug 170 and the upper contact plug 173 may be formed by depositing a conductive material in the second contact hole OH′ and the first and second openings OP1 and OP2. The contact plug 170 may be formed to have a horizontal extension portion 170H extending horizontally from the contact region 130P (see FIG. 1 ). Figure 2A ), thereby being physically and electrically connected to the gate electrode 130. The upper contact plug 173 may be deposited together with the contact plug 170, or may be deposited in a separate process. The through via 175 may also be formed by the same process.

[0219] Next, let’s refer to Figure 2A , an upper contact plug 181 connected to an upper end of the contact plug 170 and an upper end of the third channel structure CH3 may be formed, and an upper circuit wiring 183 (including a bit line) may be formed on the third insulating layer 194 or the cell region insulating layer 190 , thereby forming the semiconductor device 100 .

[0220] Fig.12 is a schematic diagram of a data storage system including a semiconductor device according to example embodiments.

[0221] Reference Fig.12 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be a solid state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0222] The semiconductor device 1100 may be a nonvolatile memory device, such as the one described above with reference to Figures 1 to 9The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an example embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL between the bit line BL and the common source line CSL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR.

[0223] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary depending on example embodiments.

[0224] In example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0225] In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation of erasing data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0226] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through the first connection wiring 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S.

[0227] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through the input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0228] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . According to example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , in which case the controller 1200 may control the plurality of semiconductor devices 1100 .

[0229] The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware and may control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. Through the NAND interface 1221, a control command for controlling the semiconductor device 1100, data to be recorded to the memory cell transistor MCT of the semiconductor device 1100, and data read from the memory cell transistor MCT of the semiconductor device 1100 may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0230] Fig.13 is a schematic perspective view of a data storage system including a semiconductor device according to an example embodiment.

[0231] Reference Fig.13 , a data storage system 2000 according to an example embodiment of the present disclosure may include a main board 2001, and a controller 2002, one or more semiconductor packages 2003, and a DRAM 2004 mounted on the main board 2001. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 formed on the main board 2001.

[0232] The mainboard 2001 may include a connector 2006 including a plurality of pins connected to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host according to any one of the interfaces of a universal serial bus (USB), a peripheral component interconnect high speed (PCI-Express), a serial advanced technology attachment (SATA), and M-Phy for universal flash memory (UFS). In an example embodiment, the data storage system 2000 may operate with power supplied from an external host through the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) configured to distribute power supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0233] The controller 2002 may record data in the semiconductor package 2003 or read data from the semiconductor package 2003 , and may increase the operation speed of the data storage system 2000 .

[0234] The DRAM 2004 may be a buffer memory for alleviating the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a high-speed cache memory and may provide a space for temporarily storing data during a control operation of the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0235] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 on the package substrate 2100 and on the semiconductor chip 2200 and the connection structure 2400 and at least partially covering the semiconductor chip 2200 and the connection structure 2400.

[0236] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.12 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the above reference Figures 1 to 9 A semiconductor device is described.

[0237] In example embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input / output pad 2210 and the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other using a bonding wire manner, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other through a connection structure including a through silicon via (TSV), instead of the bonding wire type connection structure 2400.

[0238] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer different from the main board 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through wiring formed on the interposer.

[0239] Fig.14 is a cross-sectional view schematically illustrating a semiconductor package according to example embodiments. Fig.14 Show Fig.13 An example embodiment of a semiconductor package 2003 is shown conceptually. Fig.13 The semiconductor package 2003 is cut along the cutting line IV-IV'.

[0240] Reference Fig.14 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate main body 2120, a package upper pad 2130 (see FIG. 213 ) disposed on the upper surface of the package substrate main body 2120, and a package upper pad 2130 (see FIG. 214 ). Fig.13), a lower pad 2125 disposed on or exposed through the lower surface of the package substrate main body 2120, and an internal wiring 2135 electrically connecting the package upper pad 2130 and the lower pad 2125 in the package substrate main body 2120. The lower pad 2125 can be connected to the conductive connector 2800 as shown in FIG. Fig.13 A wiring pattern 2005 of a main board 2001 of a data storage system 2000 is shown.

[0241] Each semiconductor chip 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 penetrating or extending through the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see FIG. 2 ). Fig.12 ) of the contact plug 3235. As mentioned above Figures 1 to 9 As described above, the plurality of gate electrodes 130 in each semiconductor chip 2200 may be commonly connected to one contact plug 170 .

[0242] Each semiconductor chip 2200 may include a through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may be disposed outside the gate stack structure 3210 and may be further disposed to penetrate or extend through the gate stack structure 3210. Each semiconductor chip 2200 may also include an input / output pad 2210 electrically connected to the peripheral wiring 3110 of the first structure 3100 (see FIG. Fig.13 ).

[0243] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0244] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0126471 filed on September 21, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a stacked structure including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region and the second region; a plurality of separation regions, in the first region and the second region, extending through the stacked structure and extending in a second direction perpendicular to the first direction; a plurality of channel structures extending through the stacked structure in a cell region of the first region; a plurality of dummy channel structures extending through the stacked structure in a buffer region of the first region; as well as a plurality of support structures extending through the stacked structure in the second region, wherein the first area and the second area are arranged sequentially in the second direction, wherein the plurality of separation regions include a first separation region and a second separation region adjacent to each other in a third direction perpendicular to the first direction and the second direction, wherein, between the first separation region and the second separation region, the plurality of dummy channel structures include a first dummy group and a second dummy group, the first dummy group being adjacent to the cell region and including first dummy channel structures sequentially arranged in the third direction, the second dummy group being adjacent to the second region and including second dummy channel structures sequentially arranged in the third direction, and A first length of the first dummy group in the third direction is longer than a second length of the second dummy group in the third direction. 2 . The semiconductor device according to claim 1 , wherein a distance between the first separation region and the second dummy group is equal to a distance between the second separation region and the second dummy group.

3. The semiconductor device according to claim 1 , wherein between the first separation region and the second separation region, the plurality of dummy channel structures further include a third dummy group, the third dummy group being between the first dummy group and the second dummy group and including third dummy channel structures sequentially arranged in the third direction, and A third length of the third dummy group in the third direction is shorter than the first length of the first dummy group in the third direction, and is longer than the second length of the second dummy group in the third direction. 4 . The semiconductor device according to claim 3 , wherein the number of the first dummy channel structures in the first dummy group, the number of the second dummy channel structures in the second dummy group, and the number of the third dummy channel structures in the third dummy group are different from each other.

5. The semiconductor device according to claim 3, wherein a ratio of a difference between a distance between the first separation region and the second dummy group in the third direction and a distance between the first separation region and the third dummy group in the third direction to a distance between the second dummy group and the third dummy group in the second direction is equal to a ratio of a difference between the distance between the first separation region and the third dummy group in the third direction and a distance between the first separation region and the first dummy group in the third direction to a distance between the first dummy group and the third dummy group in the second direction.

6. The semiconductor device according to claim 3, wherein a ratio of a difference between a distance between the first separation region and the second dummy group in the third direction and a distance between the first separation region and the third dummy group in the third direction to a distance between the second dummy group and the third dummy group in the second direction is different from a ratio of a difference between the distance between the first separation region and the third dummy group in the third direction and a distance between the first separation region and the first dummy group in the third direction to a distance between the first dummy group and the third dummy group in the second direction. 7 . The semiconductor device according to claim 1 , wherein a first interval between adjacent first dummy channel structures in the first dummy channel structures in the third direction is greater than a second interval between adjacent second dummy channel structures in the second dummy channel structures in the third direction.

8. The semiconductor device according to claim 1, wherein at least one of the first separation region and the second separation region has a first width in the cell region of the first region and has a second width greater than the first width in a boundary region between the first region and the second region.

9. The semiconductor device according to claim 8, wherein in the boundary region between the first region and the second region, at least one of the first separation region and the second separation region has an expansion portion, a width of the expansion portion increases and then decreases in a direction away from the unit region of the first region, and a portion of the expansion portion has the second width. 10 . The semiconductor device according to claim 8 , wherein in the third direction, a minimum distance between the first separation region and the second dummy channel structure of the second dummy group is shorter than a minimum distance between the first separation region and the plurality of channel structures. 11 . The semiconductor device according to claim 9 , wherein in the buffer region, a width of the expansion portion gradually increases with increasing distance from the cell region in the second direction. 12 . The semiconductor device according to claim 1 , wherein the channel structure and the dummy channel structure include a first material, and the support structure does not include the first material.

13. The semiconductor device according to claim 1, wherein each of the channel structures has a first width, At least one of the plurality of dummy channel structures has a second width greater than the first width, and At least one of the plurality of support structures has a third width greater than the second width. 14 . The semiconductor device according to claim 1 , wherein with one of the separation regions extending in the second direction as an axis, the channel structure is disposed symmetrically about the axis. 15 . The semiconductor device according to claim 1 , wherein between the first separation region and the second separation region, an arrangement of the plurality of channel structures is different from an arrangement of the plurality of dummy channel structures.

16. A semiconductor device comprising: A stacked structure in the first region and the second region and including gate electrodes and interlayer insulating layers alternately stacked in a first direction; a plurality of partitioned regions extending through the stacked structure; a plurality of channel structures extending through the stacked structure in a cell region of the first region; a plurality of dummy vertical structures extending through the stacked structure in a buffer region of the first region; a plurality of first support structures extending through the stacked structure in a boundary region of the second region; a contact plug connected to the contact region of the gate electrode in the connection region of the second region; as well as a plurality of second support structures extending through the stacked structure in the connection region of the second region, wherein the unit area of ​​the first area, the buffer area of ​​the first area, the boundary area of ​​the second area and the connection area of ​​the second area are arranged in sequence in the second direction, wherein the plurality of partition regions include a first partition region and a second partition region adjacent to each other in a third direction perpendicular to the first direction and the second direction, and Wherein, between a first central axis of the first separation region extending along the second direction and a second central axis of the second separation region extending along the second direction, a distance between a first dummy vertical structure adjacent to the first separation region among the multiple dummy vertical structures and the first central axis increases from an area adjacent to the unit area of ​​the first region to an area adjacent to the boundary area of ​​the second region.

17. The semiconductor device according to claim 16, wherein the channel structure comprises a channel layer, wherein the dummy vertical structure comprises a dummy channel layer, wherein the channel layer and the dummy channel layer include a first material, and The first supporting structure and the second supporting structure include a supporting insulating layer and do not include the first material. 18 . The semiconductor device of claim 16 , wherein a width of the channel structure is smaller than a width of the dummy vertical structure, and the width of the dummy vertical structure is smaller than widths of the first support structure and the second support structure.

19. The semiconductor device according to claim 16, wherein between the first center axis of the first separation region extending along the second direction and the second center axis of the second separation region extending along the second direction, the arrangement of the multiple dummy vertical structures is different from the arrangement of the multiple channel structures and the arrangement of the multiple first support structures.

20. A data storage system comprising: A semiconductor memory device comprising a first semiconductor structure including a circuit element, a second semiconductor structure on a surface of the first semiconductor structure, and an input / output pad electrically connected to the circuit element; a controller electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device, The second semiconductor structure comprises: A stacked structure in the first region and the second region and including gate electrodes and interlayer insulating layers alternately stacked in a first direction; a plurality of partitioned regions extending through the stacked structure; a plurality of channel structures extending through the stacked structure in a cell region of the first region; a plurality of dummy vertical structures extending through the stacked structure in a buffer region of the first region; a plurality of first support structures extending through the stacked structure in a boundary region of the second region; a contact plug connected to the contact region of the gate electrode in the connection region of the second region; and a plurality of second support structures extending through the stacked structure in the connection region of the second region, wherein the unit area of ​​the first area, the buffer area of ​​the first area, the boundary area of ​​the second area and the connection area of ​​the second area are arranged in sequence in the second direction, wherein the plurality of partition regions include a first partition region and a second partition region adjacent to each other in a third direction perpendicular to the first direction and the second direction, and Wherein, between a first central axis of the first separation region extending along the second direction and a second central axis of the second separation region extending along the second direction, a distance between a first dummy vertical structure adjacent to the first separation region among the multiple dummy vertical structures and the first central axis increases from an area adjacent to the unit area of ​​the first region to an area adjacent to the boundary area of ​​the second region.

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