Preparation method of novel power device and power device
By etching the substrate surface of the SGT MOSFET device to form a trench and forming a step-shaped gate region at the bottom of the trench, the problem of excessive Vds stress at the fast shutdown is solved, and the stability of the device is improved.
Patent Information
- Application Number
- CN202411975000.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-03-21
AI Technical Summary
The Vds stress of SGT MOSFET devices is too high when they are shut down, resulting in the risk of the device being easily broken down, damaged or even burned.
By etching on the first surface of the substrate, a shielded gate structure is formed at the bottom of the trench, and a step-shaped gate region is formed on the shielded gate structure, increasing the relative area between the gate polysilicon and the substrate, and reducing the Vds stress under fast shutdown.
It effectively reduces the stress of Vds under fast shutdown of SGT MOSFET devices, improves device stability, and reduces the risk of breakdown and damage.
Smart Images
Figure CN119677124A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a preparation method of a novel power device and a power device. Background Art
[0002] Shielded Gate Trench (SGT) MOSFET device is an innovative trench power MOSFET with low on-resistance, low switching loss, and superior frequency characteristics. It can be used in core power key components such as mobile phone fast charging, motor drive and power management system. In addition, with the rise of electric vehicles, the demand for medium and low voltage MOSFET is increasing. SGT MOSFET helps improve system efficiency and power density in motor control and power battery systems.
[0003] In SGT MOSFET, by connecting the shield electrode to the source electrode, this design achieves the function of shielding the gate and drift region, thereby reducing the Miller capacitance and gate charge of the device and accelerating the switching speed of the device. However, this also causes the device to have excessive Vds stress under fast shutdown, resulting in the risk of device breakdown, damage or even burning. Summary of the invention
[0004] The present application provides a novel method for preparing a power device and a power device, which can solve the problem of excessive Vds stress during fast shutdown of an SGT MOSFET device, thereby improving the stability of the device.
[0005] In order to achieve the above objectives, this application adopts the following technical solutions: In a first aspect of the embodiments of the present application, a method for preparing a novel power device is provided, the method comprising: Etching a plurality of grooves on the first surface of the substrate; forming a shielding gate structure at the bottom of the trench; forming a gate region on the shielding gate structure, wherein the gate region comprises a gate oxide layer and gate polysilicon located on the gate oxide layer, and a channel between the gate polysilicon and the substrate is in a step shape; forming a source region in the substrate below the gate oxide layer; A drain is formed on the second surface of the substrate.
[0006] As a possible implementation manner, forming a shielding gate structure at the bottom of the trench includes: Oxidizing the bottom of the trench, the sidewalls of the trench and the surface of the trench opening to obtain a corresponding oxide layer, and then filling the trench with polysilicon; The polysilicon is etched to expose the gate polysilicon region, thereby obtaining the shielding gate structure.
[0007] As a possible implementation manner, forming a gate region on the shielding gate structure includes: After etching two side walls of the trench located in the area above the shielding gate structure into step shapes, after forming a dielectric layer on the shielding gate structure, the dielectric layer in each trench, the two step-shaped side walls of each trench and the connecting surface between two adjacent trenches are connected to form an etched surface; After a gate oxide layer is formed on the etched surface, gate polysilicon is filled in two trenches with stepped sidewalls on the gate oxide layer to form the gate region.
[0008] As a possible implementation manner, etching two side walls of the trench located in the area above the shielding gate structure into a step shape includes: After the oxide layer on the surface of the trench opening is ground, the two side walls of the trench located in the area above the shielding gate structure are etched into a step shape using photoresist.
[0009] As a possible implementation manner, forming a source region in the substrate under the gate oxide layer includes: A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.
[0010] As a possible implementation manner, after forming a source region in the substrate under the gate oxide layer, the method further includes: After forming a passivation layer on the gate oxide layer, an etching hole is formed in the passivation layer to obtain a hole etching surface, wherein the etching hole is connected to the source region.
[0011] As a possible implementation manner, after the etching hole is formed in the passivation layer to obtain the hole etching surface, the method further includes: A metal electrode is formed on the surface of the hole etching, and the metal electrode is connected to the source region through the etching hole.
[0012] As a possible implementation manner, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.
[0013] In a second aspect of an embodiment of the present application, a power device is provided, the power device comprising: a substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a plurality of grooves; A shielding grid structure, wherein the shielding grid structure is located at the bottom of the groove; A gate region, the gate region is located on the shielding gate structure, the gate region includes a gate oxide layer and gate polysilicon located on the gate oxide layer, and a channel between the gate polysilicon and the substrate is in a step shape; A source region, located in the substrate below the gate oxide layer; The drain is located on the second surface of the substrate.
[0014] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: The preparation method of the novel power device provided in the embodiment of the present application is characterized in that a plurality of grooves are formed by etching on the first surface of the substrate; a shielding gate structure is formed at the bottom of the groove; a gate region is formed on the shielding gate structure, the gate region includes a gate oxide layer and a gate polysilicon located on the gate oxide layer, and a channel between the gate polysilicon and the substrate is in a step shape; a source region is formed in the substrate under the gate oxide layer; a drain is formed on the second surface of the substrate, and by preparing the channel between the gate polysilicon and the substrate to be in a step shape, the relative area between the gate polysilicon and the substrate can be increased, the gate-drain capacitance can be increased, and the Vds stress under fast shutdown can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A flow chart of a method for preparing a novel power device provided in an embodiment of the present application; Figure 2 A schematic diagram of a longitudinal section of a power device provided in an embodiment of the present application.
[0016] Reference numerals: 1- oxide layer, 2- shielding gate polysilicon, 3- gate polysilicon, 4- source region, 5- passivation layer, 6- gate oxide layer, 7- metal electrode, 8- drain, 9- dielectric layer. DETAILED DESCRIPTION
[0017] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0018] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
[0019] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.
[0020] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0021] The present application provides a method for preparing a novel power device, such as Figure 1 As shown, the method comprises the following steps: Step 101, etching a first surface of a substrate to form a plurality of grooves; Step 102, forming a shielding gate structure at the bottom of the trench; Step 103, forming a gate region on the shielding gate structure, wherein the gate region includes a gate oxide layer and gate polysilicon located on the gate oxide layer, and a channel between the gate polysilicon and the substrate is in a step shape; Step 104, forming a source region in the substrate under the gate oxide layer; Step 105: forming a drain on the second surface of the substrate.
[0022] The substrate is used as a carrier of the power device and mainly plays a supporting role. The substrate can be made of silicon, germanium or germanium silicon. In this embodiment, the substrate is preferably made of silicon, which is the most common, cheap and stable semiconductor material.
[0023] The substrate has a first surface and a second surface opposite to each other, wherein the first surface can be understood as the front side of the substrate, and the second surface can be understood as the back side of the substrate. The gate region and the source region in the device structure are formed on the first surface. The drain in the device structure is formed on the second surface of the substrate.
[0024] Optionally, step 102 of forming a shielding gate structure at the bottom of the trench includes: Oxidizing the bottom of the trench, the sidewalls of the trench and the surface of the trench opening to obtain a corresponding oxide layer, and then filling the trench with polysilicon; The polysilicon is etched to expose the gate polysilicon region, thereby obtaining the shielding gate structure.
[0025] The trench above the shielding gate structure is used to form a gate region.
[0026] Optionally, step 103 of forming a gate region on the shielding gate structure includes: After etching two side walls of the trench located in the area above the shielding gate structure into step shapes, after forming a dielectric layer on the shielding gate structure, the dielectric layer in each trench, the two step-shaped side walls of each trench and the connecting surface between two adjacent trenches are connected to form an etched surface; After a gate oxide layer is formed on the etched surface, gate polysilicon is filled in the trenches with two stepped sidewalls to form the gate region.
[0027] Optionally, etching two sidewalls of the trench located in the area above the shielding gate structure into a step shape includes: After grinding the oxide layer on the surface of the trench opening, photoresist is used to etch two side walls of the trench located above the shielding gate structure into a step shape.
[0028] Optionally, the step 104 of forming a source region in the substrate under the gate oxide layer includes: A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.
[0029] The first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.
[0030] Optionally, after forming a source region in the substrate under the gate oxide layer in step 104, the method further includes: After forming a passivation layer on the gate oxide layer, an etching hole is formed in the passivation layer to obtain a hole etching surface, wherein the etching hole is connected to the source region.
[0031] Furthermore, after forming the etching hole in the passivation layer to obtain the hole etching surface, the method further comprises: A metal electrode is formed on the surface of the hole etching, and the metal electrode is connected to the source region through the etching hole.
[0032] The preparation method of the novel power device provided in the embodiment of the present application is characterized in that a plurality of grooves are formed by etching on the first surface of the substrate; a shielding gate structure is formed at the bottom of the groove; a gate region is formed on the shielding gate structure, the gate region includes a gate oxide layer and a gate polysilicon located on the gate oxide layer, and a channel between the gate polysilicon and the substrate is in a step shape; a source region is formed in the substrate under the gate oxide layer; a drain is formed on the second surface of the substrate, and by preparing the channel between the gate polysilicon and the substrate to be in a step shape, the relative area between the gate polysilicon and the substrate can be increased, the gate-drain capacitance can be increased, and the Vds stress under fast shutdown can be reduced.
[0033] The present application also provides a power device, the power device comprising: a substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a plurality of grooves; A shielding grid structure, wherein the shielding grid structure is located at the bottom of the groove; A gate region, the gate region is located on the shielding gate structure, the gate region includes a gate oxide layer 6 and a gate polysilicon 3 located on the gate oxide layer 6, and a channel between the gate polysilicon 3 and the substrate is in a step shape; A source region 4 is located in the substrate below the gate oxide layer 6; The drain electrode 8 is located on the second surface of the substrate.
[0034] Optionally, the shielding grid structure includes: An oxide layer 1, wherein the oxide layer 1 is formed on the bottom of the trench, the sidewalls of the trench and the surface of the trench opening; Polycrystalline silicon 2, the polycrystalline silicon 2 is located at the bottom of the trench, and the oxide layer 1 is included between the polycrystalline silicon 2 and the substrate.
[0035] Optionally, power devices include: An etched surface, wherein the etched surface is formed by connecting the dielectric layer 9 in each trench, the two stepped side walls of each trench and the connecting surface between two adjacent trenches after etching the two side walls of the trench located in the area above the shielding gate structure into a step shape and forming a dielectric layer 9 on the shielding gate structure; The gate region is formed by forming a gate oxide layer 6 on the etching surface and then filling a gate polysilicon 3 in a trench with two stepped sidewalls.
[0036] The power device comprises: A passivation layer 5, wherein the passivation layer 5 is located on the gate oxide layer 6; The hole etching surface is a surface after an etching hole is formed in the passivation layer 5 , and the etching hole is connected to the source region 4 .
[0037] The power device further comprises: A metal electrode 7 is formed on the hole etching surface, and the metal electrode 7 is connected to the source region 7 through the hole etching surface.
[0038] The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.
[0039] Regarding the specific limitations of the power device, reference may be made to the limitations of the method for preparing the power device in the embodiments of the present application, and no further details will be given here.
[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
[0041] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the above claims, any one of the claimed embodiments may be used in any combination. The information disclosed in this background technology section is intended only to deepen the understanding of the overall background technology of the present application and should not be regarded as an admission or in any form of implication that the information constitutes prior art known to those skilled in the art.
Claims
1. A method for preparing a novel power device, characterized in that: The method comprises: Etching a plurality of grooves on the first surface of the substrate; forming a shielding gate structure at the bottom of the trench; forming a gate region on the shielding gate structure, wherein the gate region comprises a gate oxide layer and gate polysilicon located on the gate oxide layer, and a channel between the gate polysilicon and the substrate is in a step shape; forming a source region in the substrate below the gate oxide layer; A drain is formed on the second surface of the substrate.
2. The method according to claim 1, characterized in that The shielding gate structure is formed at the bottom of the trench, comprising: Oxidizing the bottom of the trench, the sidewalls of the trench and the surface of the trench opening to obtain a corresponding oxide layer, and then filling the trench with polysilicon; The polysilicon is etched to expose the gate polysilicon region, thereby obtaining the shielding gate structure.
3. The method according to claim 1, characterized in that The forming of a gate region on the shielding gate structure comprises: After etching two side walls of the trench located in the area above the shielding gate structure into a step shape, and forming a dielectric layer on the shielding gate structure, the dielectric layer in each trench, the two step-shaped side walls of each trench and the connecting surface between two adjacent trenches constitute an etched surface; After a gate oxide layer is formed on the etched surface, gate polysilicon is filled in two trenches with stepped sidewalls on the gate oxide layer to form the gate region.
4. The method according to claim 3, characterized in that The step of etching two sidewalls of the trench located in the area above the shielding gate structure into a step shape comprises: After grinding the oxide layer on the surface of the trench opening, photoresist is used to etch two side walls of the trench located above the shielding gate structure into a step shape.
5. The method according to claim 1, characterized in that: The forming of a source region in the substrate under the gate oxide layer comprises: A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.
6. The method according to claim 1, characterized in that After forming a source region in the substrate under the gate oxide layer, the method further comprises: After forming a passivation layer on the gate oxide layer, an etching hole is formed in the passivation layer to obtain a hole etching surface, wherein the etching hole is connected to the source region.
7. The method according to claim 6, characterized in that After the etching holes are formed in the passivation layer to obtain the hole etching surface, the method further comprises: A metal electrode is formed on the surface of the hole etching, and the metal electrode is connected to the source region through the etching hole.
8. The method according to claim 5, characterized in that The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.
9. A power device, characterized in that: The power device comprises: a substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a plurality of grooves; A shielding grid structure, wherein the shielding grid structure is located at the bottom of the groove; A gate region, the gate region is located on the shielding gate structure, the gate region includes a gate oxide layer and gate polysilicon located on the gate oxide layer, and a channel between the gate polysilicon and the substrate is in a step shape; A source region, located in the substrate below the gate oxide layer; The drain is located on the second surface of the substrate.