Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: forming a first gate structure, a second gate structure and an interlayer dielectric layer on a substrate, and enabling the interlayer dielectric layer to cover the substrate at two sides of the first gate structure and the substrate at two sides of the second gate structure, the width of the section of the first gate structure in the direction perpendicular to the surface of the substrate is larger than that of the section of the second gate structure in the direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than that of the second gate structure; forming a surface filling layer covering the first gate structure and the second gate structure on the interlayer dielectric layer; thinning the surface filling layer to expose the first gate structure; and etching the first gate structure to enable the surface of the first gate structure to be flush with the surface of the second gate structure. According to the invention, the height difference between the first gate structure and the second gate structure is reduced or eliminated, and the process window of the subsequent process is increased.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the planarization process (Chemical Mechanical Polishing, CMP) of the interlayer dielectric (ILD), due to the different polishing rates of different materials and the differences in the polishing rates corresponding to the parts with different pattern densities in the interlayer dielectric layer, the polishing rate corresponding to the part with a large gate in the interlayer dielectric layer is slower, resulting in a higher gate height (Gate height) at the large gate, resulting in a height difference between the large gate and the surrounding structures, which may even affect the process window (Windows) of subsequent processes in severe cases. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof to reduce the height difference between different gate structures in the interlayer dielectric layer.

[0004] In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0005] Providing a substrate, on which a first gate structure, a second gate structure and an interlayer dielectric layer are formed, wherein the interlayer dielectric layer covers the substrate on both sides of the first gate structure and the substrate on both sides of the second gate structure, the width of the cross section of the first gate structure along a direction perpendicular to the surface of the substrate is greater than the width of the cross section of the second gate structure along a direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than the surface of the second gate structure;

[0006] forming a surface filling layer on the interlayer dielectric layer, wherein the surface filling layer covers a surface of the first gate structure and a surface of the second gate structure;

[0007] Thinning the surface filling layer to expose the first gate structure;

[0008] The first gate structure is etched so that a surface of the first gate structure is flush with a surface of the second gate structure.

[0009] In one embodiment, after etching the first gate structure, the method for manufacturing a semiconductor device further includes:

[0010] The remaining surface filling layer is removed.

[0011] In one embodiment, the material of the surface filling layer includes a photosensitive material with a dielectric constant between 3.0 and 5.0.

[0012] In one embodiment, the material of the surface filling layer includes polyimide material.

[0013] In one embodiment, the surface filling layer is formed by a spin coating process.

[0014] In one of the embodiments, the surface filling layer is exposed to light to remove the remaining surface filling layer.

[0015] In one embodiment, the formation process of the first gate structure, the second gate structure and the interlayer dielectric layer includes:

[0016] forming a gate material layer on the substrate;

[0017] forming a gate dielectric layer on the gate material layer;

[0018] Performing patterning on the gate material layer and the gate dielectric layer to form the first gate structure and the second gate structure;

[0019] forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer extends to and covers the first gate structure and the second gate structure;

[0020] The interlayer dielectric layer is planarized to expose the first gate structure and the second gate structure.

[0021] In one of the embodiments, a grinding rate of the gate dielectric layer during the planarization process is lower than a grinding rate of the interlayer dielectric layer during the planarization process.

[0022] In one embodiment, the planarization process is performed using a chemical mechanical polishing process.

[0023] In a second aspect, the present application also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method as described above.

[0024] The unexpected effect of the present application is: forming a surface filling layer to cover the surface of the first gate structure and the surface of the second gate structure, thinning the surface filling layer to expose the first gate structure, and then etching the first gate structure to make the surface of the first gate structure flush with the surface of the second gate structure, thereby reducing or eliminating the height difference between the first gate structure and the second gate structure, so as to increase the process window of the subsequent process. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A flowchart of a method for manufacturing a semiconductor device provided in one embodiment of the present application.

[0027] Figure 2 A schematic structural diagram corresponding to the step of providing a substrate in a method for manufacturing a semiconductor device provided in an embodiment of the present application, and forming a first gate structure, a second gate structure and an interlayer dielectric layer on the substrate.

[0028] Figure 3 A schematic structural diagram corresponding to the step of planarizing an interlayer dielectric layer in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0029] Figure 4 A schematic structural diagram corresponding to the step of forming a surface filling layer on an interlayer dielectric layer in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0030] Figure 5 This is a structural schematic diagram corresponding to the step of thinning the surface filling layer in the method for manufacturing a semiconductor device provided in one embodiment of the present application.

[0031] Figure 6 A structural schematic diagram corresponding to the step of etching a first gate structure in a method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0032] Figure 7 A schematic structural diagram corresponding to the step of removing a surface filling layer in a method for manufacturing a semiconductor device provided in one embodiment of the present application.

[0033] Description of the accompanying drawings: 100 - substrate; 101 - gate material layer; 102 - gate dielectric layer; 110 - interlayer dielectric layer; 120 - surface filling layer; G1 - first gate structure; G2 - second gate structure. DETAILED DESCRIPTION

[0034] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0037] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0038] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] Figure 1 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. Figure 1 One embodiment of the present application provides a method for manufacturing a semiconductor device, including steps S01 to S04.

[0040] Step S01: providing a substrate, on which a first gate structure, a second gate structure and an interlayer dielectric layer are formed, wherein the interlayer dielectric layer covers the substrate on both sides of the first gate structure and the substrate on both sides of the second gate structure, the width of the cross section of the first gate structure along a direction perpendicular to the surface of the substrate is greater than the width of the cross section of the second gate structure along a direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than the surface of the second gate structure.

[0041] See also Figure 2 In one embodiment, the width of the cross section of the first gate structure G1 along the direction perpendicular to the surface of the substrate 100 is D1, and the width of the cross section of the second gate structure G2 along the direction perpendicular to the surface of the substrate 100 is D2, and the width D1 of the first gate structure G1 is greater than the width D2 of the second gate structure G2, that is, D1>D2, so the pattern size corresponding to the first gate structure G1 is also significantly greater than the pattern size corresponding to the second gate structure G2. Correspondingly, since the pattern density is smaller when the pattern size is larger, the pattern density (Pattern Density) corresponding to the first gate structure G1 is significantly smaller than the pattern density corresponding to the second gate structure G2.

[0042] See also Figure 3In one embodiment, the first gate structure G1 and the second gate structure G2 are exposed by depositing an interlayer dielectric layer 110 on the first gate structure G1, the second gate structure G2 and the substrate 100, and then performing a planarization process on the interlayer dielectric layer 110. Since the grinding rates of the regions with different pattern densities in the interlayer dielectric layer 110 are also different, there is a difference between the grinding rate corresponding to the region where the first gate structure G1 is located and the grinding rate corresponding to the region where the second gate structure G2 is located. Since the pattern density (PatternDensity) corresponding to the first gate structure G1 is significantly smaller than the pattern density corresponding to the second gate structure G2, the grinding rate corresponding to the region where the first gate structure G1 is located is smaller than the grinding rate corresponding to the region where the second gate structure G2 is located.

[0043] It should be noted that the grinding rate corresponding to the area where the first gate structure G1 is located is lower than the grinding rate corresponding to the area where the second gate structure G2 is located. Therefore, when part of the interlayer dielectric layer 110 above the second gate structure G2 is completely ground and the surface of the second gate structure G2 is exposed, part of the interlayer dielectric layer 110 above the first gate structure G1 may not be completely removed; then, in the process of continuing the planarization process until part of the interlayer dielectric layer 110 above the first gate structure G1 is also completely removed and the surface of the first gate structure G1 is exposed, at most part of the structure of the second gate structure G2 away from the substrate 100 will also be removed in the planarization process. At this time, the height of the remaining second gate structure G2 (i.e., the cross-sectional height H2 of the second gate structure G2 along the direction perpendicular to the surface of the substrate 100) is significantly smaller than the height of the first gate structure G1 (i.e., the cross-sectional height H1 of the first gate structure G1 along the direction perpendicular to the surface of the substrate 100), i.e., H1>H2.

[0044] However, the height difference between the first gate structure G1 and the second gate structure G2 will have a negative impact on the subsequent process. For example, the height difference between the first gate structure G1 and the second gate structure G2 will reduce the process window of the subsequent process, thereby affecting the performance and stability of the semiconductor device. Therefore, it is necessary to reduce or eliminate the height difference between the first gate structure G1 and the second gate structure G2 through steps S02 to S04.

[0045] Step S02: forming a surface filling layer on the interlayer dielectric layer, wherein the surface filling layer covers a surface of the first gate structure and a surface of the second gate structure.

[0046] See also Figure 4In one embodiment, the surface filling layer 120 can be prepared by using a material with good filling performance, leveling performance and dielectric performance, so as to ensure that the surface filling layer 120 can fill the relatively low part of the combined surface composed of the surface of the interlayer dielectric layer 110, the surface of the first gate structure G1 and the surface of the second gate structure G2, and has a high surface flatness (that is, to ensure that the surface of the surface filling layer 120 has a high flatness). Optionally, the material of the surface filling layer 120 includes a photosensitive material with a dielectric constant between 3.0 and 5.0.

[0047] It should be noted that, since the height H2 of the second gate structure G2 in step S02 is significantly smaller than the height H1 of the first gate structure G1, the surface filling layer 120 will preferentially fill the surface of the second gate structure G2 under the action of gravity; at the same time, since the surface filling layer 120 has a high leveling performance, the surface of the surface filling layer 120 finally formed has a high flatness and will not inherit the unevenness existing in the above-mentioned combined surface.

[0048] Step S03: thinning the surface filling layer to expose the first gate structure.

[0049] Step S04: etching the first gate structure to make the surface of the first gate structure flush with the surface of the second gate structure.

[0050] See also Figure 5 In one of the embodiments, since the surface of the surface filling layer 120 is flat and the surface of the first gate structure G1 is higher than the surface of the second gate structure G2, the thickness of the surface filling layer 120 above the first gate structure G1 is less than the thickness of the surface filling layer above the second gate structure G2. During the thinning process of step S03, since the etching rate of each part of the surface filling layer 120 is the same, when the surface filling layer 120 above the first gate structure G1 is completely removed, part of the surface filling layer 120 is still covered above the second gate structure G2. Then, during the etching process of the first gate structure G1, the surface filling layer 120 will continue to be etched until the surface of the first gate structure G1 and the surface of the second gate structure G2 are flush, and the etching process will end.

[0051] It should be noted that, since the height of the first gate structure G1 is higher than the height of the second gate structure G2 after step S01, in the thinning process adopted in step S03, as the surface filling layer 120 is thinned, the first gate structure G1 will inevitably be exposed before the second gate structure G2. It can be seen that step S03 and step S04 can realize the self-aligned etching process of the first gate structure G1 without preparing a mask, thereby saving the process cost and process time of preparing the mask and simplifying the process flow.

[0052] The manufacturing method of the semiconductor device as described above forms a surface filling layer to cover the surface of the first gate structure and the surface of the second gate structure, and then etches the surface filling layer and a portion of the first gate structure to make the surface of the first gate structure flush with the surface of the second gate structure, thereby reducing or eliminating the height difference between the first gate structure and the second gate structure, so as to increase the process window of the subsequent process.

[0053] Continue reading Figure 2 In one embodiment, the material of the substrate 100 is a silicon (Si) substrate, and an isolation trench structure (not marked in the figure) is formed in the substrate 100, and the isolation trench structure is formed in the substrate 100 on both sides of the first gate structure G1 and / or the second gate structure G2. In other embodiments of the present application, the material of the substrate 100 can also be silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, or other semiconductor materials formed by III / V compounds, etc. The substrate 100 can also be a stacked structure composed of the above semiconductor materials, or silicon on insulator, stacked silicon on insulator, silicon germanium on insulator, and germanium on insulator, etc. The material of the substrate 100 can be selected according to the type of semiconductor device, and the present application does not make specific restrictions on this.

[0054] See also Figure 2 In one embodiment, the formation process of the first gate structure G1, the second gate structure G2 and the interlayer dielectric layer 110 includes: forming a gate material layer 101 on a substrate 100; forming a gate dielectric layer 102 on the gate material layer 101; patterning the gate material layer 101 and the gate dielectric layer 102 to form the first gate structure G1 and the second gate structure G2; forming an interlayer dielectric layer 110 on the substrate 100, and the interlayer dielectric layer 110 extends and covers the first gate structure G1 and the second gate structure G2; and planarizing the interlayer dielectric layer 110 to expose the first gate structure G1 and the second gate structure G2. Optionally, the gate material layer 101 and the gate dielectric layer 102 are patterned by photolithography and etching processes.

[0055] In one embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process. Figure 2 and Figure 3In one embodiment, the gate dielectric layer 102 is also ground during the planarization process, and the grinding rate in the gate dielectric layer 102 is less than the grinding rate of the interlayer dielectric layer 110 during the planarization process, so as to reduce the thickness of the gate dielectric layer 102 removed during the planarization process, thereby reducing the height difference between the first gate structure G1 and the second gate structure G2. Optionally, the material of the gate dielectric layer 102 includes silicon nitride, and the material of the interlayer dielectric layer 110 includes silicon oxide.

[0056] See also Figure 4 In one embodiment, the material of the surface filling layer 120 includes a polyimide material. Since the polyimide material has good dielectric properties, filling properties and leveling properties, the surface filling layer 120 made of the polyimide material can well fill the combined surface formed by the surface of the first gate structure G1, the surface of the second gate structure G2 and the surface of the interlayer dielectric layer 110, while ensuring that the surface of the surface filling layer 120 is flat for subsequent process steps. In one embodiment, the surface filling layer 120 is formed by a spin coating process to improve the surface flatness of the surface filling layer 120.

[0057] In other embodiments of the present application, other materials with good dielectric properties, filling properties and leveling properties can also be selected to prepare the surface filling layer 120. It is only necessary to ensure that the surface filling layer 120 can keep the surface of the surface filling layer 120 smooth while filling and covering the above-mentioned combined surface. The present application does not impose any restrictions on this.

[0058] See also Figure 5 In one embodiment, a plasma etching process is used to thin the surface filling layer 120 so as to expose the first gate structure G1. Optionally, the process gas of the plasma etching process includes oxygen and a protective gas (the protective gas is usually an inert gas, such as helium). In other embodiments of the present application, other commonly used process methods may also be used to thin the surface filling layer 120, and the present application does not limit this.

[0059] See also Figure 6 In one embodiment, a dry etching process is used to etch the first gate structure G1. Optionally, the process gas of the dry etching process includes carbon tetrafluoride (CF4) and a protective gas (the protective gas is usually an inert gas, such as helium). In other embodiments of the present application, other commonly used process methods may also be used to etch the first gate structure G1, and the present application does not limit this.

[0060] It should be noted that in the manufacturing method of the semiconductor device provided in the present application, the portion of the first gate structure G1 that is removed in the etching process corresponding to step S04 is the gate dielectric layer 102, and the portion of the second gate structure G2 that is removed in the planarization process corresponding to step S01 is the gate dielectric layer 102, that is, after the planarization process and the etching process of the first gate structure G1, there is still a remaining gate dielectric layer 102 on the gate material layer 101 in the first gate structure G1 and the second gate structure G2, so as to ensure that the first gate structure G1 and the second gate structure G2 function normally, thereby improving the yield and stability of the semiconductor device.

[0061] In one embodiment, the height of the first gate structure G1 can be controlled by controlling the process time of the etching process of step S04, and the etching process is stopped when the surface of the first gate structure G1 is flush with the surface of the second gate structure G2. In other embodiments of the present application, the timing of stopping the etching process can be controlled by controlling other process parameters of the etching process of step S04, and it is only necessary to ensure that the surface of the first gate structure G1 is flush with the surface of the second gate structure G2 after the etching is completed.

[0062] See also Figure 6 In one of the embodiments, since the surface filling layer 120 is not completely removed after etching the first gate structure G1, there is still residual surface filling layer 120 on the surfaces of the interlayer dielectric layer 110 and the second gate structure G2. Therefore, the manufacturing method of the semiconductor device proposed in the present application also includes step S05.

[0063] Step S05: removing the remaining surface filling layer.

[0064] See also Figure 7 In one embodiment, when the surface filling layer 120 is a polyimide layer, the surface filling layer 120 can be exposed using an I-Line to remove the remaining surface filling layer 120, so as to facilitate the smooth progress of subsequent processes. In other embodiments of the present application, other photosensitive materials can also be used to form the surface filling layer 120, so as to remove the remaining surface filling layer 120 through exposure.

[0065] The present application also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above. Figure 7The semiconductor device prepared by the above-mentioned semiconductor device manufacturing method includes: a substrate 100, a first gate structure G1, a second gate structure G2 and an interlayer dielectric layer 110, wherein the first gate structure G1 and the second gate structure G2 are both located on the substrate 100, and the surface of the first gate structure G1 is flush with the surface of the second gate structure G2, and the interlayer dielectric layer 110 is located on the substrate 100 on both sides of the first gate structure G1 and the second gate structure G2.

[0066] In one embodiment, the first gate structure G1 and the second gate structure G2 both include a gate material layer 101 located on a substrate 100 and a gate dielectric layer 102 located on the gate material layer 101. Optionally, the substrate 100 is, for example, a silicon substrate; the material of the gate dielectric layer 102 is, for example, silicon nitride; and the material of the interlayer dielectric layer 110 is, for example, silicon oxide. In other embodiments of the present application, the materials of different film layers and structures in the semiconductor device can be selected according to actual needs, and the present application does not limit this.

[0067] It should be noted that, since the surface of the first gate structure G1 is flush with the surface of the second gate structure G2 , the semiconductor device has a larger process window during subsequent process steps, thereby helping to improve the yield and stability of the semiconductor device.

[0068] The unexpected effect of the present application is: forming a surface filling layer covering the first gate structure and the second gate structure, thinning the surface filling layer and exposing the first gate structure, and then etching the first gate structure to make the surface of the first gate structure flush with the surface of the second gate structure, thereby reducing or eliminating the height difference between the first gate structure and the second gate structure, so as to increase the process window of the subsequent process.

[0069] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0070] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a first gate structure, a second gate structure and an interlayer dielectric layer are formed, wherein the interlayer dielectric layer covers the substrate on both sides of the first gate structure and the substrate on both sides of the second gate structure, the width of the cross section of the first gate structure along a direction perpendicular to the surface of the substrate is greater than the width of the cross section of the second gate structure along a direction perpendicular to the surface of the substrate, and the surface of the first gate structure is higher than the surface of the second gate structure; forming a surface filling layer on the interlayer dielectric layer, wherein the surface filling layer covers a surface of the first gate structure and a surface of the second gate structure; Thinning the surface filling layer to expose the first gate structure; The first gate structure is etched so that a surface of the first gate structure is flush with a surface of the second gate structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: After etching the first gate structure, the method for manufacturing the semiconductor device further includes: The remaining surface filling layer is removed.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that: The material of the surface filling layer includes a photosensitive material with a dielectric constant between 3.0 and 5.

0.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The material of the surface filling layer includes polyimide material.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: The surface filling layer is formed by a spin coating process.

6. The method for manufacturing a semiconductor device according to claim 3, wherein: The surface filling layer is exposed to light to remove the remaining surface filling layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The formation process of the first gate structure, the second gate structure and the interlayer dielectric layer includes: forming a gate material layer on the substrate; forming a gate dielectric layer on the gate material layer; Performing patterning on the gate material layer and the gate dielectric layer to form the first gate structure and the second gate structure; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer extends to and covers the first gate structure and the second gate structure; The interlayer dielectric layer is planarized to expose the first gate structure and the second gate structure.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The grinding rate of the gate dielectric layer during the planarization process is lower than the grinding rate of the interlayer dielectric layer during the planarization process.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The planarization process is performed by using a chemical mechanical polishing process.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

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