Half-bridge chip and manufacturing method of half-bridge chip

Abstract

The invention discloses a half-bridge chip and a manufacturing method of the half-bridge chip. The half-bridge chip comprises a plurality of miniature half-bridge units formed on a substrate, and the plurality of miniature half-bridge units are arranged in parallel to form a half-bridge circuit structure; the miniature half-bridge unit comprises a first transistor, a second transistor and a capacitor, and a series circuit structure formed by connecting the first transistor and the second transistor in series is arranged in parallel with the capacitor. An upper tube, a lower tube and a capacitor of a traditional half-bridge chip are divided into a plurality of miniature half-bridge units in proportion, and due to the fact that the miniature half-bridge units are connected in parallel, according to the parallel connection principle of inductors, the loop inductance of the half-bridge chip composed of the half-bridge units is obviously smaller than that of the traditional half-bridge chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chips, and in particular to a half-bridge chip and a method for manufacturing the half-bridge chip. Background Art

[0002] Half-bridge is a common circuit structure in the field of power electronics. It consists of two transistors connected in series and is widely used in topologies such as Boost, Buck, LLC, and DAB. Figure 1 , is a schematic diagram of a conventional half-bridge circuit, and the dotted line is the power loop. The drain DH of the upper tube QH of the half-bridge is connected to the high voltage VDC, and the source SL of the lower tube QL is connected to the power ground PGND. A bypass or decoupling capacitor C is also connected in parallel in the circuit. There is parasitic inductance in the power loop (shown by the dotted line). Under high current and high frequency working conditions, the parasitic inductance will cause current and voltage spikes, affecting the efficiency, reliability, and EMI (Electromagnetic Interference) of the power supply. In the Buck circuit, refer to Figure 2 , VSW represents the switch node, which is the inductor connection end. Using discrete devices to build a half-bridge circuit on a PCB (Printed Circuit Board) has good flexibility. However, due to the large package size of the device and the wiring restrictions of the PCB, the geometric size of its power loop (shown by the dotted line) is large, so the parasitic inductance is large. In a multi-layer PCB, the upper tube, lower tube, and capacitor can be arranged in a straight line on the surface of the PCB, and then the lower layer Cu can be used for parallel wiring to form a current loop to achieve the purpose of flux cancellation and reduce the parasitic inductance of the loop. However, due to the large size of the device and the thick PCB dielectric, the parasitic inductance is still large.

[0003] To further reduce the parasitic inductance of the power loop, refer to Figure 3 , based on the package separation device, the power loop capacitor is omitted, SW represents the switch node electrode, HG represents the upper tube gate electrode, and LG represents the lower tube gate electrode. The power loop is shown as a dotted line, and its size is smaller than Figure 2 PCB half-bridge power circuit.

[0004] Further, refer to Figure 4 , Schematic diagram of a conventional integrated half-bridge chip, omitting the power loop capacitor, and the power loop is shown as a dotted line. The upper tube, lower tube, or capacitors are packaged into independent modules. Since the bare device size is small, the package wiring accuracy is higher than that of PCB, and the dielectric thickness is relatively thin, so LGA (Land Grid Array, grid array packaging) and other packages are used. The power loop size is much smaller than the PCB half bridge, and a smaller power loop parasitic inductance can be obtained than the PCB half bridge.

[0005] Since the chip processing precision is higher than the packaging and the dielectric layer thickness is thinner, integrating the half-bridge on the same substrate can further reduce the size of the power circuit and reduce the parasitic inductance. However, for a half-bridge with certain voltage and resistance specifications, its device size cannot be further reduced due to the influence of material properties and process level limitations. Therefore, the power circuit size cannot be reduced and the parasitic inductance cannot be further reduced. Summary of the invention

[0006] The object of the present invention is to provide a half-bridge chip and a method for manufacturing the half-bridge chip, so as to overcome the shortcomings of the prior art.

[0007] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes: The first aspect of the present invention provides a half-bridge chip, comprising a plurality of micro half-bridge units formed on a substrate, wherein the plurality of micro half-bridge units are arranged in parallel to form a half-bridge circuit structure; the micro half-bridge unit comprises a first transistor, a second transistor and a capacitor, and a series circuit structure formed by the first transistor and the second transistor being connected in series is arranged in parallel with the capacitor.

[0008] In some more specific embodiments, the first transistor and the second transistor are both formed by processing a semiconductor layer and are distributed along a first direction. The semiconductor layer is grown on the surface of the substrate, and the first direction is parallel to the surface of the substrate.

[0009] Furthermore, the first transistor and the second transistor are electrically isolated from each other via an isolation structure, wherein the isolation structure includes an ion implantation region or a trench structure formed in the semiconductor layer. Alternatively, the source (SH) of the first transistor (QH) and the drain (DL) of the second transistor (QL) are combined into one electrode (SW).

[0010] In some more specific implementations, the first transistor, the second transistor and the capacitor are distributed along a first direction.

[0011] In some more specific implementations, the capacitor and the first transistor and / or the second transistor are stacked in a second direction, and the second direction is perpendicular to the surface of the substrate.

[0012] Further, one of the capacitors is stacked on the first transistor and the second transistor in one of the micro half-bridge units, and two electrodes of the capacitor are electrically connected to the first transistor and the second transistor respectively; Alternatively, one capacitor is stacked on multiple first transistors and / or multiple second transistors, and one electrode of the capacitor is electrically connected to the first transistor in one micro half-bridge unit, and the other electrode is electrically connected to the second transistor in another micro half-bridge unit.

[0013] Furthermore, an insulating layer is distributed between the capacitor and the first transistor and the second transistor, and the capacitor is electrically connected to the first transistor and the second transistor respectively through a conductive through-hole structure formed in the insulating layer.

[0014] In some more specific implementations, the current loops in adjacent micro half-bridge units are in opposite directions.

[0015] In some more specific embodiments, a plurality of the micro half-bridge units are symmetrically distributed on the surface of the substrate.

[0016] In some more specific embodiments, the first transistor or the second transistor comprises a depletion-mode HEMT or an enhancement-mode HEMT.

[0017] In some more specific implementations, the first transistor or the second transistor has a p-type gate structure or a MIS gate structure.

[0018] In some more specific embodiments, the capacitor includes a capacitor having a MIM or SIS structure; and / or the breakdown voltage of the capacitor is higher than the bias voltage of the half-bridge circuit structure.

[0019] A second aspect of the present invention provides a method for manufacturing a half-bridge chip, the manufacturing method is based on the half-bridge chip, and the manufacturing method comprises: Growing a semiconductor epitaxial structure on the surface of the substrate, wherein the semiconductor epitaxial structure includes a buffer layer, a channel layer, and a barrier layer; Processing a plurality of first transistors and a plurality of second transistors distributed along a first direction in the semiconductor epitaxial structure, wherein adjacent transistors are electrically isolated from each other, and the first direction is parallel to the surface of the substrate; Disposing at least one capacitor on the substrate; Connecting each of the first transistors in series with a corresponding second transistor to form a series circuit structure, and connecting the series circuit structure in parallel with a capacitor to form a half-bridge circuit structure; A plurality of the half-bridge circuit structures are arranged in parallel to form a half-bridge circuit structure.

[0020] Furthermore, an insulating layer and the capacitor are sequentially arranged on the semiconductor layer, and the capacitor is electrically connected to the corresponding first transistor and the second transistor through a conductive through-hole structure formed in the insulating layer.

[0021] Furthermore, the half-bridge circuit structure is packaged.

[0022] Compared with the prior art, the advantages of the present invention include at least: First, in a half-bridge chip provided by the present invention, the upper tube, lower tube, and capacitor of a traditional half-bridge chip are split into multiple micro half-bridge units in proportion, so that the power loop size of each micro half-bridge unit is smaller than the power loop size of a traditional half-bridge chip, further reducing the parasitic inductance. At the same time, since multiple micro half-bridge units are connected in parallel, according to the parallel principle of inductance, the loop inductance of the half-bridge chip composed of multiple micro half-bridge units will be significantly smaller than that of the traditional half-bridge chip.

[0023] Second, in a half-bridge chip provided by the present invention, the capacitor and the first transistor and the second transistor are stacked in the second direction, which can save chip area and more efficiently improve integration and performance.

[0024] Third, in a half-bridge chip provided by the present invention, the magnetic field directions of the power circuits of two adjacent micro half-bridge units are opposite, and the circuit flows are opposite, thereby offsetting the overall magnetic flux. Moreover, the magnetic multipole moment composed of multiple micro half-bridge units has significantly reduced radiation compared to the magnetic monopole moment of a traditional half-bridge chip.

[0025] Fourthly, in a half-bridge chip provided by the present invention, the capacitor is a multilayer capacitor having a MIM or SIS structure, which can increase the capacitance per unit area.

[0026] Fifth, in a half-bridge chip provided by the present invention, a plurality of the micro half-bridge units are connected in parallel to form a two-dimensional symmetrical structure, and the currents of any two rows or columns of micro half-bridge units are symmetrical about the center line between the two rows or columns, further canceling out the magnetic flux, and the wiring is relatively simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of a conventional half-bridge circuit in the prior art; Figure 2 is based on Figure 1 A schematic diagram of a structure in which a half bridge is formed on a PCB using discrete components in the prior art; Figure 3 It is a schematic diagram of the structure of a conventional half-bridge circuit based on a separation device in the prior art, omitting the power loop capacitor; Figure 4It is a conventional integrated half-bridge chip, omitting the structural diagram of the power loop capacitor; Figure 5 is a schematic structural diagram of a half-bridge chip provided by an embodiment of the present invention; Figure 6 This is a schematic diagram of the power loop signal of a conventional half-bridge chip; Figure 7 is a schematic diagram of a power loop signal of a half-bridge chip provided by an embodiment of the present invention; Figure 8 is a schematic structural diagram of a multi-layer micro half-bridge unit provided by an embodiment of the present invention; Fig. 9 is a schematic structural diagram of a micro half-bridge unit provided by an embodiment of the present invention; Fig.10 is based on Fig. 9 Schematic diagram of power loop signals of a conventional half-bridge chip; Fig.11 is based on Fig. 9 A schematic diagram of a power loop signal of a half-bridge chip of the present invention; Fig.12 is a schematic diagram of a power circuit and a magnetic field of adjacent micro half-bridge units provided by an embodiment of the present invention; Fig.13 is a schematic diagram of the structure of a capacitor provided by an embodiment of the present invention; Fig.14 is a schematic structural diagram of a plurality of micro half-bridge units connected in one dimension in parallel according to an embodiment of the present invention; Fig.15 This is another schematic diagram of a structure of multiple micro half-bridge units connected in one dimension in parallel provided by an embodiment of the present invention; Fig.16 is a top view of a plurality of micro half-bridge units connected in one dimension in parallel according to an embodiment of the present invention; Fig.17 yes Fig.16 A partial side view of a plurality of micro half-bridge units connected in one dimension in parallel; Fig.18 This is another schematic diagram of a structure of multiple micro half-bridge units connected in one dimension in parallel provided by an embodiment of the present invention; Fig.19 is a schematic structural diagram of a plurality of micro half-bridge units connected in two dimensions in parallel according to an embodiment of the present invention; Fig. 20 It is a schematic diagram of another structure of multiple micro half-bridge units connected in two dimensions in parallel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0029] refer to Figure 5 This embodiment provides a half-bridge chip, including a plurality of micro half-bridge units formed on a substrate, wherein the plurality of micro half-bridge units are arranged in parallel to form a half-bridge circuit structure. The micro half-bridge unit includes a first transistor, a second transistor and a capacitor, and a series circuit structure formed by the first transistor and the second transistor in series is arranged in parallel with the capacitor.

[0030] Specifically, Figure 5 GH is the gate of the first transistor, GL is the gate of the second transistor, C is a capacitor, DH is the drain of the first transistor, SH is the source of the first transistor, DL is the drain of the second transistor, and SL is the source of the second transistor. The drain DH of the first transistor is connected to the bias voltage VDC, the source SH of the first transistor is connected to the drain DL of the second transistor, and the source SL of the second transistor is grounded.

[0031] In the traditional half-bridge chip architecture, two transistors usually occupy a large chip area, and the capacitor element may also occupy a relatively large area. By splitting the two transistors and capacitors in the traditional half-bridge chip into multiple micro half-bridge units based on the principle that the ratio of the on-state resistance value of the transistor to the capacitance value of the capacitor remains unchanged, the power loop size of each micro half-bridge unit can be smaller than the power loop size of the traditional half-bridge chip.

[0032] refer to Figure 6-Figure 7 , Figure 6 The dotted line in the middle is the power loop of the existing half-bridge chip, where D represents the longitudinal dimension of the conventional half-bridge power loop, and W represents the transverse dimension of the loop. Generally, the larger the D and W, the larger the parasitic inductance. Figure 7 The dotted line portion represents the power loop of the micro half-bridge unit in the present application, where d represents the longitudinal dimension of the micro half-bridge power loop in the plane, and w represents the lateral dimension in the plane. Each micro half-bridge unit is a complete half-bridge circuit structure. Among them, the voltage specification of each micro half-bridge unit, the threshold of the first transistor gate GH, the threshold of the second transistor gate GL, the driving voltage range, and other electrical parameters are the same as the specifications of the conventional half-bridge chip. Therefore, when all the micro half-bridge units are connected in parallel, their equivalent on-resistance, parasitic capacitance, capacitance C and other parameters are equal to those of the traditional half-bridge chip, while the equivalent inductance is significantly lower than that of the traditional half-bridge.

[0033] In other words, the power loop geometry of conventional half-bridge chips (see Figure 6D and W in the circuit are large, resulting in large parasitic inductance. In the present application, the power loop size of each micro half-bridge unit is smaller than the power loop size of the existing half-bridge chip. It can be clearly concluded that the micro half-bridge unit of the present application reduces the geometric size of the power loop (see Figure 7 At the same time, since multiple micro half-bridge units are connected in parallel, according to the parallel principle of inductance, the loop inductance of the new half-bridge chip composed of multiple micro half-bridge units will be significantly smaller than that of the traditional conventional half-bridge chip.

[0034] In some embodiments, the first transistor and the second transistor are both formed by processing a semiconductor layer and are distributed along a first direction. The semiconductor layer is grown on a surface of the substrate, and the first direction is parallel to the surface of the substrate.

[0035] Preferably, the first transistor and the second transistor are electrically isolated from each other via an isolation structure, wherein the isolation structure includes an ion implantation region or a trench structure formed in the semiconductor layer. Alternatively, the source (SH) of the first transistor (QH) and the drain (DL) of the second transistor (QL) are combined into one electrode (SW).

[0036] Preferably, the first transistor, the second transistor and the capacitor are distributed along a first direction. The first direction here can be understood as a direction parallel to the substrate.

[0037] Generally, the sizes of all micro half-bridge units can be set to be the same. However, in actual chip design, multiple micro half-bridge units of different sizes and areas can also be used.

[0038] In this technical solution, a new half-bridge chip is proposed, which can break through the limitations of PCB, conventional integrated half-bridge module and conventional half-bridge chip in the above-mentioned background technology and effectively reduce the power loop inductance.

[0039] In some implementations, the capacitor, the first transistor, and the second transistor are stacked in a second direction.

[0040] More preferably, one of the capacitors is stacked on the first transistor and the second transistor in one of the micro half-bridge units, and two electrodes of the capacitor are electrically connected to the first transistor and the second transistor respectively.

[0041] In this solution, the second direction is perpendicular to the surface of the substrate. The capacitor is stacked between the first transistor and the second transistor, and the two electrodes of the capacitor are electrically connected to the first transistor and the second transistor respectively, which can save the area of ​​the half-bridge chip and improve the integration and performance more efficiently, that is, it takes up less space, and the chip structure can be more compact and smaller. It should be noted that the method of stacking the capacitor and the first transistor and the second transistor in the second direction is not limited to the solution here.

[0042] In another stacking arrangement, a capacitor is stacked on a plurality of the first transistors and a plurality of the second transistors, and one electrode of the capacitor is electrically connected to a first transistor in one of the micro half-bridge units, and the other electrode is electrically connected to a second transistor in another of the micro half-bridge units.

[0043] refer to Figure 8 The micro half-bridge unit further includes a buffer layer, a channel layer, and a barrier layer from the substrate upward.

[0044] refer to Fig. 9 , the capacitor is arranged on the first layer; the transistor is arranged below the first layer and located on the second layer; the drain of the first transistor, the gate of the first transistor, the source of the first transistor, the drain of the second transistor, the gate of the second transistor, and the source of the second transistor are distributed in sequence from left to right on the second layer, wherein an isolation zone is arranged between the source of the first transistor and the drain of the second transistor, and the capacitor is connected to the drain (DH) of the first transistor and the source (SL) of the second transistor, the conductive (metal) layer includes a first conductive layer, a second conductive layer, and a third conductive layer, the first conductive layer is located at the top (corresponding to the C+ electrode of the capacitor C), the second conductive layer is located below the first conductive layer (corresponding to the electrode C- of the capacitor C), and the third conductive layer is located on the surface of the transistor (corresponding to the transistor electrode). Fig. 9 The unfilled areas (blank areas) shown represent dielectric layers, which are located between all conductive layers or embedded in the trenches and are made of insulating materials.

[0045] The half-bridge structure based on HEMT includes two different HEMT devices on the same substrate. The first transistor and the second transistor are HEMT devices. Since HEMT is a horizontal device, the electrodes are on the same side, which is easier to use for making half-bridge chips. Among them, the first transistor and the second transistor can be made on the same wafer. The first transistor and the second transistor are processed together, and the capacitor C is above the first transistor and the second transistor. A flat capacitor structure is formed by two layers of conductive materials and one layer of dielectric material. It can be understood that the wafer can be a MOSFET, LDMOS made of materials such as silicon and SiC, or a HEMT (High electron mobility transistor) based on gallium nitride. HEMT devices based on gallium nitride are used for description here. Since HEMT is a horizontal device, the electrodes are on the same side, which is easier to use for making half-bridge chips. An isolation zone can be added between the two HEMT devices, including but not limited to etching trenches and ion implantation. The gate of the HEMT device can be either a pGaN gate or a MIS gate.

[0046] In some embodiments, the first transistor or the second transistor includes a depletion-mode HEMT or an enhancement-mode HEMT.

[0047] In some embodiments, reference Fig. 9 The capacitor is connected to the first transistor and the second transistor through a through hole to form a first power loop. The dimensions of the first power loop include the in-plane longitudinal direction d (i.e. Figure 7 The dimension d in the direction perpendicular to the substrate (i.e., the height of the medium in the half bridge) is represented by h, where d ranges from 1um to 100um and h ranges from 10nm to 1000nm.

[0048] Preferably, reference Fig.11 In the capacitor stacked half-bridge structure, with the same voltage and resistance specifications, the conventional half-bridge chip surface size (defined by D, W, and Figure 5 The same as in the figure, which is the size in the substrate plane, where H is the height of the conventional half-bridge perpendicular to the substrate or PCB) and the novel half-bridge chip composed of many micro half-bridges in the present application. And the height H of the conventional half-bridge perpendicular to the substrate or PCB is not less than h in the novel half-bridge (see Figure 7 , Fig. 9 and Fig.11 ).

[0049] When all micro half-bridge units have the same structure and size, the number of micro half-bridges is approximately D / d to N. Even if H=h, in the first-order approximation, the power loop inductance of the conventional half-bridge chip is N*N times that of the new half-bridge chip.

[0050] It can be concluded that the size of the power loop is determined by the horizontal size d and the vertical size h. It can be seen that the HEMT device determines the minimum value of d, which is approximately equal to the Pitch value of the HEMT (i.e., the length of two HEMT units, which is approximately twice the source-drain ohmic contact distance in the HEMT). In practical applications, the design can be simplified to take a larger value of d. The dielectric strength of the dielectric material and the voltage on the HEMT device determine the minimum value of h, and it is necessary to ensure that the HEMT device does not break down.

[0051] refer to Fig.10 , based on Fig. 9 Schematic diagram of power loop signals of a conventional half-bridge chip and a half-bridge chip of the present invention. Fig.10 The dotted line portion is the power loop of the existing half-bridge chip. It can be intuitively concluded that the power loop of the existing half-bridge chip has a large geometric size, resulting in a large parasitic inductance. Fig.11 The dotted line portion is the power loop of the capacitor stacked half-bridge, and the power loop size of each half-bridge unit is smaller than the power loop size of the existing half-bridge chip. It can be clearly concluded that the present application reduces the geometric size of the power loop and further reduces the parasitic inductance. Since the capacitor is stacked on the transistor, the area of ​​the chip can be reduced. At the same time, since multiple half-bridge units are connected in parallel, according to the parallel principle of inductance, the loop inductance of the capacitor stacked half-bridge chip composed of multiple half-bridge units will be significantly smaller than the traditional half-bridge chip.

[0052] In some embodiments, an insulating layer is disposed between the capacitor and the first transistor and the second transistor, and the capacitor is electrically connected to the first transistor and the second transistor respectively through a conductive via structure formed in the insulating layer.

[0053] In some embodiments, reference Fig.12 , the current loops in adjacent micro half-bridge units are in opposite directions.

[0054] A plurality of the micro half-bridge units are symmetrically distributed on the surface of the substrate.

[0055] In this solution, the current loops in adjacent micro half-bridge units are in opposite directions, which can further reduce electromagnetic radiation and the intensity of coupling with external electromagnetic fields. The dotted line is the power loop of the half-bridge unit, the arrow indicates the flow direction of the power loop current, and the center circle indicates the magnetic field direction of the power loop. As can be seen from the figure, the magnetic field directions of the power loops of the two adjacent half-bridge units are opposite, and the circuit flows in opposite directions, thereby offsetting the overall magnetic flux. Moreover, the magnetic multipole moment composed of multiple half-bridge units has significantly reduced radiation compared to the magnetic monopole moment of the traditional half-bridge chip.

[0056] In some embodiments, reference Fig.13The capacitor includes a capacitor having a MIM or SIS structure. Preferably, the breakdown voltage of the capacitor is higher than the bias voltage of the half-bridge circuit structure.

[0057] In this solution, the capacitor adopts a multilayer capacitor structure, which can increase the capacitance per unit area. Specifically, the capacitor is made using a CMOS (Complementary Metal-Oxide-Semiconductor) compatible process, including MIM or SIS structure. Among them, M can be a metal such as Ti, Al, TiN; S can be a semiconductor such as polysilicon; I can be a dielectric material such as Si3N4, Al2O3, HfO2. Among them, MIM (Metal-Insulator-Metal, board-level capacitor), the capacitance value is relatively accurate, and the capacitance value will not change with the bias voltage.

[0058] In some embodiments, reference Figure 14-15 , the arrow direction indicates the direction of the current in the transistor channel. Along the direction of the transistor channel current in the half-bridge unit, a plurality of the half-bridge units are connected in parallel to form a one-dimensional linear structure.

[0059] Exemplary, reference Figure 16-Figure 17 . Fig.16 It is a top view of the one-dimensional parallel connection between two adjacent half-bridge units. Fig.17 for Fig.13 A partial side view of two adjacent half-bridge units connected in parallel, with the dotted line being the power loop. The capacitor is stacked on top of the HEMT device, and the graphics are metal layers and through holes, while the dielectric, epitaxial layer, and substrate are omitted. The first micro half-bridge unit and the second micro half-bridge unit each include two transistors, the drain DH of the first transistor is connected to the bias voltage VDC, the source SH of the first transistor is connected to the drain DL of the second transistor, the source SL of the second transistor is grounded PGND, and SW represents the switch node electrode. Fig.17 In the figure, the left dotted line loop is the first power loop, and the right dotted line loop is the second power loop.

[0060] Exemplary, reference Fig.18 , is a top view of another one-dimensional parallel connection between two adjacent micro half-bridge units. The capacitor is stacked on top of the HEMT device, and the graphics are metal layers and through holes, while the dielectric, epitaxial layer, and substrate are omitted. There is also a wiring layer between the capacitor and the HEMT device. The wiring layer is responsible for connecting each micro half-bridge unit in parallel and deriving the lumped electrode to achieve compatibility with traditional half-bridge applications.

[0061] In some embodiments, reference Fig.19, multiple micro half-bridge units are connected in parallel to form a two-dimensional structure, and the direction of the arrow indicates the direction of the current in the transistor channel. Among them, the current direction between two adjacent micro half-bridge units is staggered; in specific implementation, Fig. 9 The micro half-bridge units shown in the figure can be placed by alternating the directions. Fig. 9 The power loop in is shown as the dotted line. The direction of the current is consistent with that shown by the dotted line, which is equivalent to a small current loop. According to Ampere's law, a magnetic field will be generated. When the directions of adjacent current loops are opposite, the magnetic fields of the two current loops will have a mutual cancellation effect.

[0062] From the perspective of magnetic multipoles, the current loop (i.e., power loop) of a single conventional half-bridge is equivalent to a large magnetic dipole, while the new half-bridge based on multiple micro half-bridges is equivalent to a magnetic multipole; the magnetic field generated by the magnetic multipoles decays faster with distance, so the electromagnetic coupling between the new half-bridge and the outside world will also be reduced.

[0063] More preferably, refer to Fig. 20 , a plurality of the half-bridge units are connected in parallel to form a two-dimensional symmetrical structure, and the direction of the arrow indicates the direction of the current in the transistor channel. Among them, the current direction of any two rows or columns of the micro half-bridge units is symmetrical about the center line between the two rows or columns. In this embodiment, from the perspective of flux cancellation and wiring, the flux can be further cancelled, and the wiring is relatively simple.

[0064] This embodiment also provides a method for preparing the half-bridge chip. The specific method includes: Growing a semiconductor epitaxial structure on the surface of the substrate, wherein the semiconductor epitaxial structure includes a buffer layer, a channel layer, and a barrier layer; Processing a plurality of first transistors and a plurality of second transistors distributed along a first direction in the semiconductor epitaxial structure, wherein adjacent transistors are electrically isolated from each other, and the first direction is parallel to the surface of the substrate; Disposing at least one capacitor on the substrate; Connecting each of the first transistors in series with a corresponding second transistor to form a series circuit structure, and connecting the series circuit structure in parallel with a capacitor to form a half-bridge circuit structure; Arranging a plurality of the half-bridge circuit structures in parallel to form a half-bridge circuit structure; The half-bridge circuit structure is packaged.

[0065] In summary, in the fields of server power supply, photovoltaic inverter, etc., the current is usually large and the switching frequency is high, so the inductance of the power loop of the half-bridge circuit is required to be extremely small. The present invention proposes a new half-bridge chip and a method for manufacturing a half-bridge chip, which can break through the limitations of the above-mentioned PCB, conventional integrated half-bridge module, and conventional half-bridge chip, and effectively reduce the inductance of the power loop.

[0066] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A half-bridge chip, characterized in that: It includes a plurality of micro half-bridge units formed on a substrate, wherein the plurality of micro half-bridge units are arranged in parallel to form a half-bridge circuit structure; the micro half-bridge unit includes a first transistor, a second transistor and a capacitor, and a series circuit structure formed by the first transistor and the second transistor being connected in series is arranged in parallel with the capacitor.

2. The half-bridge chip according to claim 1, characterized in that: The first transistor and the second transistor are both formed by processing a semiconductor layer and distributed along a first direction. The semiconductor layer grows on the surface of the substrate. The first direction is parallel to the surface of the substrate, and / or the first transistor, the second transistor and the capacitor are distributed along the first direction.

3. The half-bridge chip according to any one of claims 1-2, characterized in that: The capacitor and the first transistor and / or the second transistor are stacked in a second direction, and the second direction is perpendicular to the surface of the substrate.

4. The half-bridge chip according to claim 3, characterized in that: One of the capacitors is stacked on the first transistor and the second transistor in one of the micro half-bridge units, and two electrodes of the capacitor are electrically connected to the first transistor and the second transistor respectively; Alternatively, one capacitor is stacked on multiple first transistors and / or multiple second transistors, and one electrode of the capacitor is electrically connected to the first transistor in one micro half-bridge unit, and the other electrode is electrically connected to the second transistor in another micro half-bridge unit.

5. The half-bridge chip according to claim 3, characterized in that: An insulating layer is disposed between the capacitor and the first transistor and / or the second transistor, and the capacitor is electrically connected to the first transistor and the second transistor respectively through a conductive through-hole structure formed in the insulating layer.

6. The half-bridge chip according to any one of claims 1-2, characterized in that: The current loops in adjacent micro half-bridge units are in opposite directions; And / or, a plurality of the micro half-bridge units are symmetrically distributed on the surface of the substrate.

7. The half-bridge chip according to any one of claims 1-2, characterized in that: The first transistor or the second transistor includes a depletion-mode HEMT or an enhancement-mode HEMT.

8. The half-bridge chip according to any one of claims 1-2, characterized in that: The first transistor or the second transistor has a p-type gate structure or a MIS gate structure.

9. The half-bridge chip according to any one of claims 1-2, characterized in that: The capacitor includes a capacitor having a MIM or SIS structure; and / or a breakdown voltage of the capacitor is higher than a bias voltage of the half-bridge circuit structure.

10. A method for manufacturing a half-bridge chip, characterized in that: include: Growing a semiconductor epitaxial structure on the surface of the substrate, wherein the semiconductor epitaxial structure includes a buffer layer, a channel layer, and a barrier layer; Processing a plurality of first transistors and a plurality of second transistors distributed along a first direction in the semiconductor epitaxial structure, wherein adjacent transistors are electrically isolated from each other, and the first direction is parallel to the surface of the substrate; Disposing at least one capacitor on the substrate; Connecting each of the first transistors in series with a corresponding second transistor to form a series circuit structure, and connecting the series circuit structure in parallel with a capacitor to form a half-bridge circuit structure; A plurality of the half-bridge circuit structures are arranged in parallel to form a half-bridge circuit structure.

11. The manufacturing method according to claim 10, characterized in that: Specifically include: An insulating layer and the capacitor are sequentially disposed on the semiconductor layer, and the capacitor is electrically connected to the corresponding first transistor and the second transistor through a conductive through-hole structure formed in the insulating layer.

12. The manufacturing method according to claim 10, characterized in that: Also includes: The half-bridge circuit structure is packaged.

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