Image sensor and forming method of image sensor

Abstract

The invention discloses an image sensor and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a pixel region and a peripheral region; forming a groove in the pixel area; a first gate structure is formed in the groove and comprises a first gate layer, first ions are arranged in the first gate layer, and the top surface of the first gate layer is higher than the surface of the substrate; forming a peripheral gate structure material layer on the substrate and the first gate structure, wherein the peripheral gate structure material layer comprises a peripheral gate material layer; ion implantation is carried out on a partial region of the peripheral gate material layer on the peripheral region, so that the peripheral gate material layer on the peripheral region forms a peripheral gate layer, and doped ions are arranged in the peripheral gate layer; and after carrying out ion implantation on a partial region of the peripheral gate material layer on the peripheral region, etching the peripheral gate material layer on the substrate and the first gate structure, forming a first side wall on the side wall of the first gate layer higher than the surface of the substrate, and forming a peripheral gate structure including the peripheral gate layer on the peripheral region. The performance of the image sensor is improved.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and in particular to an image sensor and a method for forming the image sensor. Background Art

[0002] In recent years, complementary metal oxide semiconductor (CMOS) image sensors have been widely used in many fields, such as security monitoring, automotive, consumer electronics, medical equipment, etc. The consumer electronics field has put forward higher requirements for the high resolution of complementary metal oxide semiconductor image sensors, and small-size pixels have been continuously developed. As the pixel size continues to shrink, the distance between the photodiode (PD) and the transistor is gradually reduced, and the risk of punch-through between the photodiode and the transistor is also increasing. In addition, as the pixel size decreases, the full well capacity of each pixel will also decrease. Therefore, it is hoped that more full well capacity can be obtained by utilizing deeper semiconductor areas. Combining the above points, vertical transfer transistors were developed.

[0003] However, the application of vertical transfer transistors in the field of image sensors still needs to be improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide an image sensor and a method for forming the image sensor, so as to improve the performance of the image sensor.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming an image sensor, comprising: providing a substrate, the substrate comprising a pixel area and a peripheral area; forming a groove in the pixel area; forming a first gate structure in the groove, the first gate structure comprising a first gate layer, the first gate layer having first ions, and the top surface of the first gate layer being higher than the surface of the substrate; forming a peripheral gate structure material layer on the substrate and the first gate structure, the peripheral gate structure material layer comprising a peripheral gate material layer; performing ion implantation on a partial area of ​​the peripheral gate material layer on the peripheral area so that the peripheral gate material layer on the peripheral area is formed into a peripheral gate layer, the peripheral gate layer having doped ions; after performing ion implantation on a partial area of ​​the peripheral gate material layer on the peripheral area, etching the peripheral gate material layer on the substrate and the first gate structure, forming a first sidewall on the sidewall of the first gate layer higher than the surface of the substrate, and forming a peripheral gate structure on the peripheral area, the peripheral gate structure comprising the peripheral gate layer.

[0006] Optionally, the first gate structure further includes: a first gate dielectric layer located on the sidewall surface and the bottom surface of the groove, and the first gate layer is located on the surface of the first gate dielectric layer.

[0007] Optionally, the method for forming the first gate structure includes: forming a gate dielectric material layer on the substrate surface, the side wall surface and the bottom surface of the groove; forming a gate material layer on the gate dielectric material layer; etching back the gate material layer until the surface of the gate dielectric material layer is exposed, and forming a first gate layer in the groove; after forming the first gate layer, removing the gate dielectric material layer on the substrate surface, and forming a first gate dielectric layer on the side wall surface and the bottom surface of the groove.

[0008] Optionally, the material of the gate material layer includes pre-doped polysilicon; the formation process of the gate material layer includes a chemical vapor deposition process and an in-situ doping process, and the reaction gas for forming the gate material layer includes a gas containing first ions.

[0009] Optionally, the material of the gate material layer includes undoped polysilicon; and before etching back the gate material layer, the method further includes: implanting a first ion into the gate material layer.

[0010] Optionally, the peripheral region includes a first region and a second region, the doped ions include second ions or third ions, and ion implantation is performed on a peripheral gate material layer in an upper portion of the peripheral region, including: implanting second ions into the peripheral gate material layer on the first region to form a first peripheral gate layer having second ions therein; implanting third ions into the peripheral gate material layer on the second region to form a second peripheral gate layer having third ions therein, and the second ions and third ions have different conductivity types; removing the peripheral gate material layer on the substrate, forming a first peripheral gate structure on the first region, and forming a second peripheral gate structure on the second region.

[0011] Optionally, the peripheral gate structure material layer also includes: a peripheral gate dielectric layer located on the substrate and the first gate structure, and the peripheral gate material layer is located on the peripheral gate dielectric layer; the peripheral gate structure includes: a peripheral gate dielectric layer located on the peripheral region and a peripheral gate layer located on the peripheral gate dielectric layer.

[0012] Optionally, it also includes: forming a second side wall on the side wall of the peripheral gate structure and the side wall of the first side wall; forming a dielectric structure on the peripheral gate structure, the first gate structure and the substrate; forming a first connecting structure on the first gate structure, the first connecting structure is electrically connected to the first gate layer; forming a second connecting structure on the peripheral gate structure, the second connecting structure is electrically connected to the peripheral gate layer, and the first connecting structure and the second connecting structure are located in the dielectric structure.

[0013] Correspondingly, the technical solution of the present invention also provides an image sensor, comprising: a substrate, the substrate comprising a pixel area and a peripheral area; a groove located in the pixel area; a first gate structure located in the groove, the first gate structure comprising a first gate layer, the first gate layer having first ions, and the top surface of the first gate layer is higher than the surface of the substrate; a peripheral gate structure located on the peripheral area, the peripheral gate structure comprising a peripheral gate layer, the peripheral gate layer having doped ions; a first side wall located on the side wall of the first gate layer above the surface of the substrate, the material of the first side wall being the same as the intrinsic material of the peripheral gate layer.

[0014] Optionally, the first gate structure further includes: a first gate dielectric layer located on the sidewall surface and the bottom surface of the groove, and the first gate layer is located on the surface of the first gate dielectric layer.

[0015] Optionally, the first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

[0016] Optionally, it also includes: a second side wall located on the side wall of the peripheral gate structure and the side wall of the first side wall; a dielectric structure located on the peripheral gate structure, the first gate structure and the substrate; a first connection structure located on the first gate structure, the first connection structure is electrically connected to the first gate layer; a second connection structure located on the peripheral gate structure, the second connection structure is electrically connected to the peripheral gate layer, and the first connection structure and the second connection structure are located in the dielectric structure.

[0017] Optionally, the peripheral gate structure further includes: a peripheral gate dielectric layer located on the substrate and the first gate structure, and the peripheral gate layer is located on the peripheral gate dielectric layer.

[0018] Optionally, the peripheral region includes a first region and a second region, the doped ions include second ions or third ions, and the peripheral gate structure includes: a first peripheral gate structure located on the first region, the first peripheral gate structure including a peripheral gate dielectric layer and a first peripheral gate layer located on the peripheral gate dielectric layer, the first peripheral gate layer having second ions therein; a second peripheral gate structure located on the second region, the second peripheral gate structure including a peripheral gate dielectric layer and a second peripheral gate layer located on the peripheral gate dielectric layer, the second peripheral gate layer having third ions therein, and the second ions and the third ions have different conductivity types.

[0019] Optionally, the conductivity type of the second ions includes N-type or P-type, and the conductivity type of the third ions includes N-type or P-type; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.

[0020] Optionally, a height range of a top surface of the first gate layer above a surface of the substrate is greater than or equal to 0.05 micrometers and less than or equal to 0.2 micrometers.

[0021] Optionally, the material of the first gate layer includes polysilicon; the material of the peripheral gate layer includes polysilicon.

[0022] Correspondingly, the technical solution of the present invention also provides a method for forming an image sensor, comprising: providing a substrate, the substrate comprising a pixel region and a peripheral region; forming a first groove and a second groove in the pixel region; forming a first gate structure in the first groove, the first gate structure comprising a first gate layer, the first gate layer having first ions, and the top surface of the first gate layer being higher than the surface of the substrate; forming a second gate structure in the second groove, the second gate structure comprising a second gate layer, the second gate layer having first ions, and the top surface of the second gate layer being higher than the surface of the substrate; forming a peripheral gate structure material layer on the substrate, the first gate structure, and the second gate structure, The peripheral gate structure material layer includes a peripheral gate material layer; ion implantation is performed on a partial area of ​​the peripheral gate material layer on the peripheral region, so that the peripheral gate material layer on the peripheral region is formed into a peripheral gate layer, and the peripheral gate layer has doped ions; after ion implantation is performed on a partial area of ​​the peripheral gate material layer on the peripheral region, the peripheral gate material layer on the substrate, the first gate structure and the second gate structure are etched to form a first side wall on the side wall of the first gate layer higher than the substrate surface, and a second side wall is formed on the side wall of the second gate layer higher than the substrate surface, and the adjacent first side walls and second side walls are merged together to form a peripheral gate structure on the peripheral region, and the peripheral gate structure includes the peripheral gate layer.

[0023] Optionally, the first gate structure also includes: a first gate dielectric layer located on the side wall surface and the bottom surface of the first groove, and the first gate layer is located on the surface of the first gate dielectric layer; the second gate structure also includes: a second gate dielectric layer located on the side wall surface and the bottom surface of the second groove, and the second gate layer is located on the surface of the second gate dielectric layer.

[0024] Optionally, the first gate structure and the second gate structure are formed simultaneously, and the method for forming the first gate structure and the second gate structure includes: forming a gate dielectric material layer on the substrate surface, the first groove sidewall surface, the second groove sidewall surface and the bottom surface; forming a gate material layer on the gate dielectric material layer; etching back the gate material layer until the surface of the gate dielectric material layer is exposed, forming a first gate layer in the first groove, and forming a second gate layer in the second groove; after forming the first gate layer and the second gate layer, removing the gate dielectric material layer on the substrate surface, forming a first gate dielectric layer on the first groove sidewall surface and the bottom surface, and forming a second gate dielectric layer on the second groove sidewall surface and the bottom surface.

[0025] Optionally, the material of the gate material layer includes pre-doped polysilicon; the formation process of the gate material layer includes a chemical vapor deposition process and an in-situ doping process, and the reaction gas for forming the gate material layer includes a gas containing first ions.

[0026] Optionally, the material of the gate material layer includes undoped polysilicon; and before etching back the gate material layer, the method further includes: implanting a first ion into the gate material layer.

[0027] Optionally, the peripheral region includes a first region and a second region, the doped ions include second ions or third ions, and ion implantation is performed on a peripheral gate material layer in an upper portion of the peripheral region, including: implanting second ions into the peripheral gate material layer on the first region to form a first peripheral gate layer having second ions therein; implanting third ions into the peripheral gate material layer on the second region to form a second peripheral gate layer having third ions therein, and the second ions and third ions have different conductivity types; removing the peripheral gate material layer on the substrate, forming a first peripheral gate structure on the first region, and forming a second peripheral gate structure on the second region.

[0028] Optionally, the peripheral gate structure material layer also includes: a peripheral gate dielectric layer located on the substrate and the first gate structure, and the peripheral gate material layer is located on the peripheral gate dielectric layer; the peripheral gate structure includes: a peripheral gate dielectric layer located on the peripheral region and a peripheral gate layer located on the peripheral gate dielectric layer.

[0029] Optionally, it also includes: forming a third sidewall on the sidewall of the peripheral gate structure, the first sidewall sidewall and the second sidewall sidewall; forming a dielectric structure on the peripheral gate structure, the first gate structure, the second gate structure and the substrate; forming a first connecting structure on the first gate structure and the second gate structure, the first connecting structure is electrically connected to the first gate layer and the second gate layer, and the first connecting structure is also located on the merged first sidewall and the second sidewall; forming a second connecting structure on the peripheral gate structure, the second connecting structure is electrically connected to the peripheral gate layer, and the first connecting structure and the second connecting structure are located in the dielectric structure.

[0030] Correspondingly, the technical solution of the present invention also provides an image sensor, including: a substrate, the substrate including a pixel area and a peripheral area; a first groove and a second groove located in the pixel area; a first gate structure located in the first groove, the first gate structure including a first gate layer, the first gate layer having first ions, and the top surface of the first gate layer is higher than the substrate surface; a second gate structure located in the second groove, the second gate structure including a second gate layer, the second gate layer having first ions, and the top surface of the second gate layer is higher than the substrate surface; a peripheral gate structure located on the peripheral area, the peripheral gate structure including a peripheral gate layer, the peripheral gate layer having doped ions; a first sidewall located on the sidewall of the first gate layer above the substrate surface, the material of the first sidewall is the same as the intrinsic material of the peripheral gate layer; a second sidewall located on the sidewall of the second gate layer above the substrate surface, the adjacent first sidewall and second sidewall are merged together, and the material of the second sidewall is the same as the intrinsic material of the peripheral gate layer.

[0031] Optionally, the first gate structure also includes: a first gate dielectric layer located on the side wall surface and the bottom surface of the first groove, and the first gate layer is located on the surface of the first gate dielectric layer; the second gate structure also includes: a second gate dielectric layer located on the side wall surface and the bottom surface of the second groove, and the second gate layer is located on the surface of the second gate dielectric layer.

[0032] Optionally, the material of the first gate layer and the second gate layer includes polysilicon; and the material of the peripheral gate layer includes polysilicon.

[0033] Optionally, the first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

[0034] Optionally, it also includes: a third sidewall located on the sidewall of the peripheral gate structure, the sidewall of the first sidewall and the sidewall of the second sidewall; a dielectric structure located on the peripheral gate structure, the first gate structure, the second gate structure and the substrate; a first connecting structure located on the first gate structure and the second gate structure, the first connecting structure being electrically connected to the first gate layer and the second gate layer, and the first connecting structure being also located on the merged first sidewall and the second sidewall; a second connecting structure located on the peripheral gate structure, the second connecting structure being electrically connected to the peripheral gate layer, and the first connecting structure and the second connecting structure being located within the dielectric structure.

[0035] Optionally, the peripheral gate structure further includes: a peripheral gate dielectric layer located on the substrate and the first gate structure, and the peripheral gate layer is located on the peripheral gate dielectric layer.

[0036] Optionally, the peripheral region includes a first region and a second region, the doped ions include second ions or third ions, and the peripheral gate structure includes: a first peripheral gate structure located on the first region, the first peripheral gate structure including a peripheral gate dielectric layer and a first peripheral gate layer located on the peripheral gate dielectric layer, the first peripheral gate layer having second ions therein; a second peripheral gate structure located on the second region, the second peripheral gate structure including a peripheral gate dielectric layer and a second peripheral gate layer located on the peripheral gate dielectric layer, the second peripheral gate layer having third ions therein, and the second ions and the third ions have different conductivity types.

[0037] Optionally, the conductivity type of the second ions includes N-type or P-type, and the conductivity type of the third ions includes N-type or P-type; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.

[0038] Optionally, the height range of the top surface of the first gate layer above the surface of the substrate is greater than or equal to 0.05 microns and less than or equal to 0.2 microns; the height range of the top surface of the second gate layer above the surface of the substrate is greater than or equal to 0.05 microns and less than or equal to 0.2 microns.

[0039] Optionally, there is a distance between the second gate structure and the first gate structure; the range of the distance is: 0.05 microns to 0.2 microns.

[0040] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0041] The present invention provides a method for forming an image sensor, which first forms a first gate structure in a groove in a pixel area, and then forms a peripheral gate structure on a peripheral area. The process of forming the first gate structure in a substrate and the process of forming the peripheral gate structure on the substrate can be integrated into one process flow, thereby reducing the manufacturing process cost; in addition, the process of forming the first gate structure is separated from the process of forming the peripheral gate structure, which can achieve separate regulation of the first ion concentration in the first gate layer, facilitate adjustment of the threshold voltage of the first gate structure, and achieve precise control of device performance.

[0042] Furthermore, a first side wall is formed on the side wall of the first gate layer that is higher than the surface of the substrate, and the first side wall is formed by etching the peripheral gate material layer, so that when a first connection structure electrically connected to the first gate structure is subsequently formed, the process window for forming the first connection structure can be increased, thereby avoiding the situation where the first connection structure falls on the substrate when the position deviation is large, causing a short circuit in the first gate structure; in addition, the first side wall is formed in the process of forming the peripheral gate layer, and there is no need to add additional process flows, thereby saving costs.

[0043] Furthermore, in another method for forming an image sensor of the present invention, a first side wall is formed on a side wall of a first gate layer that is higher than the surface of a substrate, and a second side wall is formed on a side wall of a second gate layer that is higher than the surface of the substrate, and adjacent first side walls and second side walls are merged together, so that when a first connecting structure electrically connected to the first gate structure and the second gate structure is subsequently formed, the process window for forming the first connecting structure can be increased, and the risk of the first connecting structure being connected to the substrate can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figures 1 to 10 is a structural schematic diagram of a formation process of an image sensor in one embodiment of the present invention;

[0045] Figures 11 to 13 It is a structural schematic diagram of a formation process of an image sensor in another embodiment of the present invention. DETAILED DESCRIPTION

[0046] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0047] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figures 1 to 10 It is a structural schematic diagram of the formation process of the image sensor in one embodiment of the present invention.

[0049] Please refer to Figure 1, providing a substrate 100, wherein the substrate 100 includes a pixel region A and a peripheral region. The pixel region A is a region where pixel devices are formed, and the peripheral region is a region where peripheral devices are formed.

[0050] In this embodiment, the peripheral region includes a first region I and a second region II.

[0051] In this embodiment, a photosensitive structure 101 is provided in the pixel area A, and the photosensitive structure 101 includes a photodiode.

[0052] In this embodiment, the substrate 100 is made of silicon.

[0053] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0054] Please refer to Figure 1 and Figure 2 , a groove 104 is formed in the pixel area A.

[0055] In this embodiment, the bottom of the groove 104 contacts the photosensitive structure 101 , or the bottom of the groove 104 is located in the photosensitive structure 101 , so that the first gate structure formed subsequently controls the photosensitive structure 101 .

[0056] The method for forming the groove 104 includes: forming a mask structure (refer to Figure 1 ), the mask structure includes a hard mask layer 102 and a photoresist layer 103 located on the hard mask layer 102, the photoresist layer 103 exposes a portion of the surface of the hard mask layer 102 on the pixel area A; the hard mask layer 102 and the pixel area A are etched using the photoresist layer 103 as a mask to form a groove 104 in the pixel area A.

[0057] The hard mask layer 102 is used to transfer the pattern of the photoresist layer 103 to the pixel area A. The photoresist layer 103 is naturally consumed during the etching process.

[0058] In this embodiment, the material of the hard mask layer 102 includes silicon nitride. The process of etching the hard mask layer 102 and the pixel region A includes a dry etching process.

[0059] Next, a first gate structure is formed in the groove 104 . The first gate structure includes a first gate layer. The first gate layer has first ions. The top surface of the first gate layer is higher than the surface of the substrate.

[0060] In this embodiment, the first gate structure further includes: a first gate dielectric layer located on the sidewall surface and the bottom surface of the groove, and the first gate layer is located on the surface of the first gate dielectric layer. Figure 3 and Figure 4 .

[0061] Please refer to Figure 3 , a gate dielectric material layer 105 is formed on the surface of the substrate 100 , the sidewall surface and the bottom surface of the groove 104 ; and a gate material layer 106 is formed on the gate dielectric material layer 105 .

[0062] In this embodiment, the gate dielectric material layer 105 is made of silicon oxide and is formed by a chemical vapor deposition process. The gate dielectric material layer 105 is located on the surface of the hard mask layer 102 on the surface of the substrate 100 .

[0063] In this embodiment, the material of the gate material layer 106 includes pre-doped polysilicon; the formation process of the gate material layer 106 includes a chemical vapor deposition process and an in-situ doping process, and the reaction gas for forming the gate material layer 106 includes a gas containing first ions.

[0064] The material of the gate material layer 106 includes pre-doped polysilicon, and the first ions are doped during the formation of the gate material layer 106 , without the need for an additional ion doping process, and the thermal budget can be effectively controlled.

[0065] In this embodiment, the first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions. The gas containing the first ions includes phosphine.

[0066] By separately regulating the concentration of the first ions, the threshold voltage of the first gate structure is adjusted to achieve precise control of the device performance.

[0067] In other embodiments, the material of the gate material layer includes undoped polysilicon; after forming the gate material layer, the method further includes: performing ion implantation of first ions into the gate material layer.

[0068] Please refer to Figure 4 , the gate material layer 106 is etched back until the surface of the gate dielectric material layer 105 is exposed, and a first gate layer 108 is formed in the groove 104; after the first gate layer 108 is formed, the gate dielectric material layer 105 on the surface of the substrate 100 is removed, and a first gate dielectric layer 107 is formed on the sidewall surface and the bottom surface of the groove 104.

[0069] In this embodiment, after removing the gate dielectric material layer 105 , the process further includes: removing the hard mask layer 102 on the surface of the substrate 100 .

[0070] At this time, the first gate layer 108 is formed, and the top surface of the first gate layer 108 is higher than the surface of the substrate 100 .

[0071] In this embodiment, the height range of the top surface of the first gate layer 108 above the surface of the substrate 100 is greater than or equal to 0.05 microns and less than or equal to 0.2 microns. If the height of the first gate layer 108 is too low, the size of the first sidewall formed on the sidewall of the first gate layer 108 above the surface of the substrate 100 is too small, and a large process window cannot be provided for the subsequent formation of a first connection structure electrically connected to the first gate structure; if the height of the first gate layer 108 is too high, the morphology of the first gate layer 108 will be deteriorated, affecting the performance of the first gate structure.

[0072] Please refer to Figure 5 , a peripheral gate structure material layer is formed on the substrate 100 and the first gate structure, wherein the peripheral gate structure material layer includes a peripheral gate dielectric layer 109 located on the substrate 100 and the first gate structure and a peripheral gate material layer 110 located on the peripheral gate dielectric layer 109 .

[0073] In this embodiment, the material of the peripheral gate dielectric layer 109 includes silicon oxide, and the material of the peripheral gate material layer 110 includes undoped polysilicon.

[0074] Please refer to Figure 6 , ion implantation is performed on a portion of the peripheral gate material layer 110 on the peripheral region, so that the peripheral gate material layer 110 on the peripheral region is formed into a peripheral gate layer, wherein the peripheral gate layer has doped ions.

[0075] In this embodiment, the doped ions include second ions or third ions, and ion implantation is performed on a partial area of ​​the peripheral gate material layer 110 on the peripheral region, including: implanting the second ions into the peripheral gate material layer 110 on the first region I, so that the peripheral gate material layer 110 on the first region I is formed into a first peripheral gate layer 111, and the first peripheral gate layer 111 has the second ions; and implanting the third ions into the peripheral gate material layer 110 on the second region II, so that the peripheral gate material layer 110 on the second region II is formed into a second peripheral gate layer 112, and the second peripheral gate layer 112 has the third ions.

[0076] In this embodiment, the second ions and the third ions have different conductivity types and are implanted in different process steps.

[0077] In other embodiments, the second ion and the third ion have the same conductivity type, and the second ion and the third ion may be of the same type or different types; when the second ion and the third ion are the same, the second ion and the third ion may be implanted in one process step.

[0078] The method for performing ion implantation of second ions on the peripheral gate material layer 110 on the first region I includes: forming a first mask layer (not shown) on the peripheral gate material layer 110, wherein the first mask layer exposes the surface of the peripheral gate material layer 110 on the first region I; performing ion implantation of second ions on the exposed peripheral gate material layer 110 using the first mask layer as a mask, so that the peripheral gate material layer 110 on the first region I is formed into a first peripheral gate layer 111; after forming the first peripheral gate layer 111, removing the first mask layer.

[0079] The method for ion implantation of a third ion into the peripheral gate material layer 110 on the second region II includes: forming a second mask layer (not shown) on the peripheral gate material layer 110, the second mask layer exposing the surface of the peripheral gate material layer 110 on the second region II; using the second mask layer as a mask, ion implantation of a third ion into the exposed peripheral gate material layer 110, so that the peripheral gate material layer 110 on the second region II is formed into a second peripheral gate layer 112; after forming the second peripheral gate layer 112, removing the second mask layer.

[0080] The conductivity type of the second ions includes N-type or P-type, and the conductivity type of the third ions includes N-type or P-type; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.

[0081] In this embodiment, the conductivity type of the second ions includes N type, and the conductivity type of the third ions includes P type.

[0082] Next, the peripheral gate material layer 110 on the substrate 100 and the first gate structure is etched to form a first sidewall spacer on the sidewall of the first gate layer 108 higher than the surface of the substrate 100, and a peripheral gate structure is formed on the peripheral region, wherein the peripheral gate structure includes the peripheral gate layer. The formation process of the first sidewall spacer and the peripheral gate structure includes: Figure 7 and Figure 8 .

[0083] Please refer to Figure 7 A protection layer 113 is formed on the first peripheral gate layer 111 and the second peripheral gate layer 112 , wherein the protection layer 113 exposes the surface of the peripheral gate material 110 that has not been ion-implanted.

[0084] The material of the protection layer 113 includes an organic material, and the organic material includes amorphous carbon or photoresist.

[0085] Please refer to Figure 8 , the peripheral gate material layer 110 is etched back until the surface of the peripheral gate dielectric layer 109 is exposed, a first peripheral gate structure is formed on the first region I, a second peripheral gate structure is formed on the second region II, and a first sidewall 114 is formed on the sidewall of the first gate layer 108 higher than the surface of the substrate 100.

[0086] In this embodiment, the first peripheral gate structure includes a peripheral gate dielectric layer 109 located on the first region I and a first peripheral gate layer 111 located on the peripheral gate dielectric layer 109, and the first peripheral gate layer 111 has second ions therein; the second peripheral gate structure includes a peripheral gate dielectric layer 109 located on the second region II and a second peripheral gate layer 112 located on the peripheral gate dielectric layer 109, and the second peripheral gate layer 112 has third ions therein.

[0087] In this embodiment, the material of the first sidewall 114 includes undoped polysilicon. The intrinsic material of the first peripheral gate layer 111 and the second peripheral gate layer 112 is undoped polysilicon, that is, the material of the first sidewall 114 is the same as the intrinsic material of the first peripheral gate layer 111 and the second peripheral gate layer 112.

[0088] Please refer to Fig. 9 A second spacer 115 is formed on the sidewall of the peripheral gate structure and the sidewall of the first spacer 114 .

[0089] In this embodiment, the second spacer 115 is located on the sidewall of the first peripheral gate layer 111 , the sidewall of the second peripheral gate layer 112 , and the sidewall of the first spacer 114 .

[0090] The method for forming the second sidewall 115 includes: forming a sidewall material layer (not shown) on the surface of the peripheral gate dielectric layer 109, the sidewall surface and top surface of the first peripheral gate layer 111, the sidewall surface and top surface of the second peripheral gate layer 112, the sidewall surface of the first sidewall 114 and the top surface of the first gate layer 108; and etching back the sidewall material layer until the top surface of the first peripheral gate layer 111 and the top surface of the second peripheral gate layer 112 are exposed to form the second sidewall 115.

[0091] In this embodiment, the material of the second spacer 115 includes silicon nitride.

[0092] Please refer to Fig.10, a dielectric structure 118 is formed on the peripheral gate structure, the first gate structure and the substrate 100; a first connection structure 120 is formed on the first gate structure, and the first connection structure 120 is electrically connected to the first gate layer 108; a second connection structure is formed on the peripheral gate structure, and the second connection structure is electrically connected to the peripheral gate layer, and the first connection structure and the second connection structure are located in the dielectric structure 118.

[0093] In this embodiment, the second connection structure includes a first connection layer 119 located on the first peripheral gate structure and a second connection layer 121 located on the second peripheral gate structure, the first connection layer 119 is electrically connected to the first peripheral gate layer 111, and the second connection layer 121 is electrically connected to the second peripheral gate layer 112.

[0094] In this embodiment, the material of the first connection structure 120 includes metal or metal nitride; the material of the second connection structure includes metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0095] In this embodiment, the material of the dielectric structure 118 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0096] The formation process of the first connection structure 120 and the second connection structure includes: forming a dielectric structure 118 on a substrate, wherein the first gate layer 108, the first sidewall 114, the first peripheral gate structure and the second peripheral gate structure are located in the dielectric structure 118; forming a patterned mask layer on the dielectric structure 118; etching the dielectric structure 118 using the patterned mask layer as a mask to form a first opening (not shown), a second opening (not shown) and a third opening (not shown) in the dielectric structure 118, wherein the first opening exposes a portion of the surface of the first gate layer 108, the second opening exposes a portion of the surface of the first peripheral gate layer 111, and the third opening exposes a portion of the surface of the second peripheral gate layer 112; forming a connection material layer in the first opening, in the second opening, in the third opening and on the dielectric structure 118; planarizing the connection material layer, forming the first connection structure 120 in the first opening, forming the first connection layer 119 in the second opening, and forming the second connection layer 121 in the third opening.

[0097] Since the sidewall of the first gate layer 108 has a first sidewall 114, the first sidewall 114 increases the area of ​​the first gate layer 108. Therefore, when forming a first opening to expose the first gate layer 108, the position deviation of the first opening can be increased, thereby increasing the process window for forming the first connection structure 120, thereby avoiding the situation where the first connection structure 120 falls on the substrate when the position deviation is large, causing a short circuit in the first gate structure.

[0098] In addition, since the first spacer 114 is formed in the process of forming the peripheral gate layer, there is no need to add additional process flow, thus saving costs.

[0099] The method for forming the image sensor first forms a first gate structure in a groove of the pixel region A, and then forms a peripheral gate structure on the peripheral region. The process of forming the first gate structure in the substrate 100 and the process of forming the peripheral gate structure on the substrate 100 can be integrated into one process flow, thereby reducing the manufacturing process cost; in addition, the process of forming the first gate structure is separated from the process of forming the peripheral gate structure, which can achieve separate regulation of the first ion concentration in the first gate layer 108, facilitate adjustment of the threshold voltage of the first gate structure, and achieve precise control of device performance.

[0100] Accordingly, the embodiment of the present invention further provides an image sensor, please continue to refer to Fig.10 ,include:

[0101] A substrate 100, wherein the substrate 100 includes a pixel region A and a peripheral region;

[0102] A groove located in the pixel area A;

[0103] A first gate structure located in the groove, the first gate structure comprising a first gate layer 108, the first gate layer 108 having first ions therein, and a top surface of the first gate layer 108 being higher than a surface of the substrate 100;

[0104] A peripheral gate structure located on the peripheral region, the peripheral gate structure comprising a peripheral gate layer, the peripheral gate layer having doping ions therein;

[0105] The first spacer 114 is located on the sidewall of the first gate layer 108 and is higher than the surface of the substrate 100 . The material of the first spacer 114 is the same as the intrinsic material of the peripheral gate layer.

[0106] In this embodiment, the first gate structure further includes: a first gate dielectric layer 107 located on the sidewall surface and the bottom surface of the groove, and the first gate layer 108 is located on the surface of the first gate dielectric layer 107 .

[0107] In this embodiment, the material of the first gate layer 108 includes polysilicon, the first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

[0108] In this embodiment, it also includes: a second sidewall 115 located on the sidewall of the peripheral gate structure and the sidewall of the first sidewall 114; a dielectric structure 118 located on the peripheral gate structure, the first gate structure and the substrate 100; a first connection structure 120 located on the first gate structure, the first connection structure 120 is electrically connected to the first gate layer 108; a second connection structure located on the peripheral gate structure, the second connection structure is electrically connected to the peripheral gate layer, and the first connection structure and the second connection structure are located in the dielectric structure.

[0109] In this embodiment, the peripheral gate structure further includes: a peripheral gate dielectric layer located on the substrate 100 and the first gate structure, and the peripheral gate layer is located on the peripheral gate dielectric layer.

[0110] In this embodiment, the peripheral region includes a first region I and a second region II, the doped ions include second ions or third ions, and the peripheral gate structure includes: a first peripheral gate structure located on the first region I, the first peripheral gate structure including a peripheral gate dielectric layer 109 and a first peripheral gate layer 111 located on the peripheral gate dielectric layer 109, and the first peripheral gate layer 111 has second ions; a second peripheral gate structure located on the second region II, the second peripheral gate structure including a peripheral gate dielectric layer 109 and a second peripheral gate layer 112 located on the peripheral gate dielectric layer 109, and the second peripheral gate layer 112 has third ions, and the second ions and the third ions have different conductivity types.

[0111] In this embodiment, the second connection structure includes a first connection layer 119 located on the first peripheral gate structure and a second connection layer 121 located on the second peripheral gate structure, the first connection layer 119 is electrically connected to the first peripheral gate layer 111, and the second connection layer 121 is electrically connected to the second peripheral gate layer 112.

[0112] In this embodiment, the conductivity type of the second ions includes N-type or P-type, and the conductivity type of the third ions includes N-type or P-type; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.

[0113] In this embodiment, the height range of the top surface of the first gate layer 108 above the surface of the substrate 100 is less than or equal to 0.2 micrometers.

[0114] In the present embodiment, the material of the first gate layer 108 includes polysilicon; the materials of the first peripheral gate layer 111 and the second peripheral gate layer 112 include polysilicon.

[0115] Figures 11 to 13 It is a structural schematic diagram of a formation process of an image sensor in another embodiment of the present invention.

[0116] Please refer to Fig.11 , Fig.11 For Figure 1 Based on the schematic diagram, a first groove 203 and a second groove 204 are formed in the pixel area A.

[0117] The method for forming the first groove 203 and the second groove 204 can be found in Figure 2 , I will not go into details here.

[0118] In this embodiment, the spacing between the first groove 203 and the second groove 204 is in the range of 0.05 micrometers to 0.2 micrometers. After the first groove 203 and the second groove 204 are formed in the spacing range, the first gate structure and the second gate structure are formed in the second groove 204. Since the first gate structure and the second gate structure are opened and closed together, the channel control capabilities of the first gate structure and the second gate structure can be enhanced.

[0119] Please refer to Fig.12 A first gate structure is formed in the first groove 203, wherein the first gate structure includes: a first gate dielectric layer 205 located on the sidewall surface and the bottom surface of the first groove 203 and a first gate layer 206 located on the surface of the first gate dielectric layer 205, wherein the first gate layer 206 has first ions, and the top surface of the first gate layer 206 is higher than the surface of the substrate 100; and a second gate structure is formed in the second groove 204, wherein the second gate structure includes a second gate dielectric layer 207 located on the sidewall surface and the bottom surface of the second groove 204 and a second gate layer 208 located on the surface of the second gate dielectric layer 207, wherein the second gate layer 208 has first ions, and the top surface of the second gate layer 208 is higher than the surface of the substrate 100.

[0120] The formation process, materials and processes of the first gate structure and the second gate structure can be found in Figure 3 and Figure 4 And the text description will not be repeated here.

[0121] Please continue to refer to Fig.12, a first sidewall 212 is formed on the sidewall of the first gate layer 206 which is higher than the surface of the substrate 100, and a second sidewall 213 is formed on the sidewall of the second gate layer 208 which is higher than the surface of the substrate 100, and the adjacent first sidewalls 212 and second sidewalls 213 are merged together; a peripheral gate structure is formed on the peripheral area, and the peripheral gate structure includes a first peripheral gate structure located on the first area I and a second peripheral gate structure located on the second area II, the first peripheral gate structure includes a peripheral gate dielectric layer 209 and a first peripheral gate layer 210 located on the peripheral gate dielectric layer 209, the first peripheral gate layer 210 has second ions, the second peripheral gate structure includes a peripheral gate dielectric layer 209 and a second peripheral gate layer 211 located on the peripheral gate dielectric layer 209, and the second peripheral gate layer 211 has third ions; a third sidewall 215 is formed on the sidewalls of the peripheral gate structure, the sidewalls of the first sidewall 212 and the sidewalls of the second sidewall 213.

[0122] The formation process, materials and processes of the first sidewall spacer 212, the second sidewall spacer 213 and the peripheral gate structure can be found in Figures 5 to 8 The formation process, materials and process of the third sidewall 215 can be found in Fig. 9 And the text description will not be repeated here.

[0123] In this embodiment, since the adjacent first sidewalls 212 and second sidewalls 213 are merged together, the third sidewall 215 is located on one side of the first sidewall 212 and on one side of the second sidewall 213 .

[0124] Please refer to Fig.13 A dielectric structure 217 is formed on the peripheral gate structure, the first gate structure, the second gate structure and the substrate 100; a first connecting structure 219 is formed on the first gate structure and the second gate structure, the first connecting structure 219 is electrically connected to the first gate layer 206 and the second gate layer 208, and the first connecting structure 219 is also located on the merged first sidewall 212 and the second sidewall 213; a second connecting structure is formed on the peripheral gate structure, the second connecting structure is electrically connected to the peripheral gate layer, and the first connecting structure and the second connecting structure are located in the dielectric structure 217.

[0125] In this embodiment, the second connection structure includes a first connection layer 218 located on the first peripheral gate structure and a second connection layer 220 located on the second peripheral gate structure, the first connection layer 218 is electrically connected to the first peripheral gate layer 210, and the second connection layer 220 is electrically connected to the second peripheral gate layer 211.

[0126] The formation process of the dielectric structure 217, the first connection structure 219 and the second connection structure can be found in Fig.10 And the text description will not be repeated here.

[0127] The first connecting structure 219 needs to be connected to the first gate structure and the second gate structure at the same time to achieve simultaneous opening and closing of the first gate structure and the second gate structure. A first sidewall 212 is formed on the sidewall of the first gate layer 206 above the surface of the substrate 100, and a second sidewall 213 is formed on the sidewall of the second gate layer 208 above the surface of the substrate. The adjacent first sidewalls 212 and second sidewalls 213 are merged together, so that when forming the first connecting structure 219 electrically connected to the first gate structure and the second gate structure, the merged first sidewalls 212 and second sidewalls 213 increase the area of ​​the first gate structure and the second gate structure, thereby increasing the process window for forming the first connecting structure 219 and reducing the risk of the first connecting structure 219 being connected to the substrate.

[0128] Accordingly, the embodiment of the present invention further provides an image sensor, please continue to refer to Fig.13 ,include:

[0129] A substrate 100, wherein the substrate 100 includes a pixel region A and a peripheral region;

[0130] A first groove and a second groove located in the pixel area A;

[0131] A first gate structure located in the first groove, the first gate structure comprising a first gate layer 206, the first gate layer 206 having first ions therein, and a top surface of the first gate layer 206 being higher than a surface of the substrate 100;

[0132] A second gate structure located in the second groove, the second gate structure comprising a second gate layer 208, the second gate layer 208 having first ions therein, and a top surface of the second gate layer 208 being higher than a surface of the substrate 100;

[0133] A peripheral gate structure located on the peripheral region, the peripheral gate structure comprising a peripheral gate layer, the peripheral gate layer having doping ions therein;

[0134] A first spacer 212 located on a sidewall of the first gate layer 206 higher than the surface of the substrate 100, wherein the material of the first spacer 212 is the same as the intrinsic material of the peripheral gate layer;

[0135] The second sidewall spacer 213 located on the sidewall of the second gate layer 208 higher than the surface of the substrate 100 is formed by merging the adjacent first sidewall spacer 212 and the second sidewall spacer 213 together. The material of the second sidewall spacer 213 is the same as the intrinsic material of the peripheral gate layer.

[0136] In this embodiment, the first gate structure also includes: a first gate dielectric layer 205 located on the side wall surface and the bottom surface of the first groove, and the first gate layer 206 is located on the surface of the first gate dielectric layer 205; the second gate structure also includes: a second gate dielectric layer 207 located on the side wall surface and the bottom surface of the second groove, and the second gate layer 208 is located on the surface of the second gate dielectric layer 207.

[0137] In this embodiment, the materials of the first gate layer 206 and the second gate layer 208 include polysilicon; and the material of the peripheral gate layer includes polysilicon.

[0138] In this embodiment, the first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

[0139] In this embodiment, it also includes: a third sidewall 215 located on the sidewall of the peripheral gate structure, the sidewall of the first sidewall 212 and the sidewall of the second sidewall 213; a dielectric structure 217 located on the peripheral gate structure, the first gate structure, the second gate structure and the substrate 100; a first connecting structure 219 located on the first gate structure and the second gate structure, the first connecting structure 219 is electrically connected to the first gate layer 206 and the second gate layer 208, and the first connecting structure 219 is also located on the merged first sidewall 212 and the second sidewall 213; a second connecting structure located on the peripheral gate structure, the second connecting structure is electrically connected to the peripheral gate layer, and the first connecting structure 219 and the second connecting structure are located in the dielectric structure 217.

[0140] In this embodiment, the peripheral gate structure further includes: a peripheral gate dielectric layer located on the substrate 100 and the first gate structure, and the peripheral gate layer is located on the peripheral gate dielectric layer.

[0141] In this embodiment, the peripheral region includes a first region I and a second region II, the doped ions include second ions or third ions, and the peripheral gate structure includes: a first peripheral gate structure located on the first region I, the first peripheral gate structure including a peripheral gate dielectric layer 209 and a first peripheral gate layer 210 located on the peripheral gate dielectric layer 209, and the first peripheral gate layer 210 has second ions; a second peripheral gate structure located on the second region II, the second peripheral gate structure including a peripheral gate dielectric layer 209 and a second peripheral gate layer 211 located on the peripheral gate dielectric layer 209, and the second peripheral gate layer 211 has third ions, and the second ions and the third ions have different conductivity types.

[0142] In this embodiment, the conductivity type of the second ions includes N-type or P-type, and the conductivity type of the third ions includes N-type or P-type; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.

[0143] In this embodiment, the height range of the top surface of the first gate layer 206 above the surface of the substrate 100 is greater than or equal to 0.05 microns and less than or equal to 0.2 microns; the height range of the top surface of the second gate layer 208 above the surface of the substrate 100 is greater than or equal to 0.05 microns and less than or equal to 0.2 microns.

[0144] In this embodiment, there is a distance between the second gate structure and the first gate structure; the range of the distance is: 0.05 micrometers to 0.2 micrometers.

[0145] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming an image sensor, characterized in that: include: Providing a substrate, the substrate comprising a pixel region and a peripheral region; forming a groove in the pixel region; forming a first gate structure in the groove, wherein the first gate structure comprises a first gate layer, the first gate layer has first ions, and a top surface of the first gate layer is higher than a surface of the substrate; forming a peripheral gate structure material layer on the substrate and on the first gate structure, wherein the peripheral gate structure material layer comprises a peripheral gate material layer; Performing ion implantation on a portion of the peripheral gate material layer on the peripheral region, so that the peripheral gate material layer on the peripheral region is formed into a peripheral gate layer, wherein the peripheral gate layer has doped ions; After ion implantation is performed on a partial area of ​​the peripheral gate material layer on the peripheral region, the peripheral gate material layer on the substrate and the first gate structure is etched to form a first sidewall on the sidewall of the first gate layer above the surface of the substrate, and a peripheral gate structure is formed on the peripheral region, wherein the peripheral gate structure includes the peripheral gate layer.

2. The method for forming an image sensor according to claim 1, wherein: The first gate structure further includes: a first gate dielectric layer located on the sidewall surface and the bottom surface of the groove, and the first gate layer is located on the surface of the first gate dielectric layer.

3. The method for forming an image sensor according to claim 2, wherein: The method for forming the first gate structure includes: forming a gate dielectric material layer on the surface of the substrate, the sidewall surface of the groove and the bottom surface; forming a gate material layer on the gate dielectric material layer; etching back the gate material layer until the surface of the gate dielectric material layer is exposed, and forming a first gate layer in the groove; after forming the first gate layer, removing the gate dielectric material layer on the surface of the substrate, and forming the first gate dielectric layer on the sidewall surface and the bottom surface of the groove.

4. The method for forming an image sensor according to claim 3, wherein: The material of the gate material layer includes pre-doped polysilicon; the formation process of the gate material layer includes a chemical vapor deposition process and an in-situ doping process, and the reaction gas for forming the gate material layer includes a gas containing first ions.

5. The method for forming an image sensor according to claim 3, wherein: The material of the gate material layer includes undoped polysilicon; Before etching back the gate material layer, the method further comprises: Performing ion implantation of first ions into the gate material layer.

6. The method for forming an image sensor according to claim 1, wherein: The peripheral region includes a first region and a second region, the doped ions include second ions or third ions, and ion implantation is performed on a peripheral gate material layer in a partial area of ​​the peripheral region, including: implanting second ions into the peripheral gate material layer on the first region so that the peripheral gate material layer on the first region is formed into a first peripheral gate layer, wherein the first peripheral gate layer has second ions; implanting third ions into the peripheral gate material layer on the second region so that the peripheral gate material layer on the second region is formed into a second peripheral gate layer, wherein the second peripheral gate layer has third ions, and the second ions and the third ions have different conductivity types; removing the peripheral gate material layer on the substrate, forming a first peripheral gate structure on the first region, and forming a second peripheral gate structure on the second region.

7. The method for forming an image sensor according to claim 1, wherein: The peripheral gate structure material layer also includes: a peripheral gate dielectric layer located on the substrate and the first gate structure, and the peripheral gate material layer is located on the peripheral gate dielectric layer; the peripheral gate structure includes: a peripheral gate dielectric layer located on the peripheral region and a peripheral gate layer located on the peripheral gate dielectric layer.

8. The method for forming an image sensor according to claim 1, wherein: Also includes: Forming a second spacer on the sidewall of the peripheral gate structure and the sidewall of the first spacer; forming a dielectric structure on the peripheral gate structure, on the first gate structure and on the substrate; forming a first connection structure on the first gate structure, wherein the first connection structure is electrically connected to the first gate layer; A second connection structure is formed on the peripheral gate structure, wherein the second connection structure is electrically connected to the peripheral gate layer, and the first connection structure and the second connection structure are located in the dielectric structure.

9. An image sensor, characterized in that: include: A substrate, the substrate comprising a pixel region and a peripheral region; a groove located in the pixel region; a first gate structure located in the groove, the first gate structure comprising a first gate layer, the first gate layer having first ions therein, and a top surface of the first gate layer being higher than a surface of the substrate; a peripheral gate structure located on the peripheral region, the peripheral gate structure comprising a peripheral gate layer, the peripheral gate layer having doped ions therein; A first sidewall spacer is located on a sidewall of the first gate layer that is higher than the surface of the substrate, and the material of the first sidewall spacer is the same as the intrinsic material of the peripheral gate layer.

10. The image sensor according to claim 9, wherein: The first gate structure further includes: a first gate dielectric layer located on the sidewall surface and the bottom surface of the groove, and the first gate layer is located on the surface of the first gate dielectric layer.

11. The image sensor according to claim 9, wherein: The first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

12. The image sensor according to claim 9, wherein: Also includes: A second sidewall spacer located on the sidewall of the peripheral gate structure and the sidewall of the first sidewall spacer; a dielectric structure located on the peripheral gate structure, on the first gate structure, and on the substrate; a first connection structure located on the first gate structure, wherein the first connection structure is electrically connected to the first gate layer; A second connection structure is located on the peripheral gate structure, the second connection structure is electrically connected to the peripheral gate layer, and the first connection structure and the second connection structure are located in the dielectric structure.

13. The image sensor according to claim 9, wherein: The peripheral gate structure further comprises: a peripheral gate dielectric layer located on the substrate and the first gate structure, and the peripheral gate layer is located on the peripheral gate dielectric layer.

14. The image sensor according to claim 9, wherein: The peripheral region includes a first region and a second region, the doped ions include second ions or third ions, and the peripheral gate structure includes: a first peripheral gate structure located on the first region, the first peripheral gate structure includes a peripheral gate dielectric layer and a first peripheral gate layer located on the peripheral gate dielectric layer, and the first peripheral gate layer has second ions; a second peripheral gate structure located on the second region, the second peripheral gate structure includes a peripheral gate dielectric layer and a second peripheral gate layer located on the peripheral gate dielectric layer, and the second peripheral gate layer has third ions, and the second ions and the third ions have different conductivity types.

15. The image sensor according to claim 14, wherein: The conductivity type of the second ions includes N-type or P-type, and the conductivity type of the third ions includes N-type or P-type; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.

16. The image sensor according to claim 9, wherein: The height of the top surface of the first gate layer above the surface of the substrate is in the range of greater than or equal to 0.05 micrometers and less than or equal to 0.2 micrometers.

17. The image sensor according to claim 9, wherein: The material of the first gate layer includes polysilicon; the material of the peripheral gate layer includes polysilicon.

18. A method for forming an image sensor, characterized in that: include: Providing a substrate, the substrate comprising a pixel region and a peripheral region; forming a first groove and a second groove in the pixel region; forming a first gate structure in the first groove, wherein the first gate structure comprises a first gate layer, the first gate layer has first ions, and a top surface of the first gate layer is higher than a surface of the substrate; forming a second gate structure in the second groove, wherein the second gate structure comprises a second gate layer, the second gate layer has first ions, and a top surface of the second gate layer is higher than a surface of the substrate; forming a peripheral gate structure material layer on the substrate, on the first gate structure, and on the second gate structure, wherein the peripheral gate structure material layer comprises a peripheral gate material layer; Performing ion implantation on a portion of the peripheral gate material layer on the peripheral region, so that the peripheral gate material layer on the peripheral region is formed into a peripheral gate layer, wherein the peripheral gate layer has doped ions; After ion implantation is performed on a partial area of ​​the peripheral gate material layer on the peripheral region, the peripheral gate material layers on the substrate, the first gate structure and the second gate structure are etched to form a first sidewall on the sidewall of the first gate layer above the substrate surface, and a second sidewall on the sidewall of the second gate layer above the substrate surface. The adjacent first sidewalls and second sidewalls are merged together to form a peripheral gate structure on the peripheral region, wherein the peripheral gate structure includes a peripheral gate layer.

19. The method for forming an image sensor according to claim 18, wherein: The first gate structure also includes: a first gate dielectric layer located on the side wall surface and the bottom surface of the first groove, and the first gate layer is located on the surface of the first gate dielectric layer; the second gate structure also includes: a second gate dielectric layer located on the side wall surface and the bottom surface of the second groove, and the second gate layer is located on the surface of the second gate dielectric layer.

20. The method for forming an image sensor according to claim 19, wherein: The first gate structure and the second gate structure are formed synchronously, and the method for forming the first gate structure and the second gate structure includes: forming a gate dielectric material layer on the substrate surface, the first groove sidewall surface, the second groove sidewall surface and the bottom surface; forming a gate material layer on the gate dielectric material layer; etching back the gate material layer until the surface of the gate dielectric material layer is exposed, forming a first gate layer in the first groove, and forming a second gate layer in the second groove; after forming the first gate layer and the second gate layer, removing the gate dielectric material layer on the substrate surface, forming a first gate dielectric layer on the first groove sidewall surface and the bottom surface, and forming a second gate dielectric layer on the second groove sidewall surface and the bottom surface.

21. The method for forming an image sensor according to claim 20, wherein: The material of the gate material layer includes pre-doped polysilicon; the formation process of the gate material layer includes a chemical vapor deposition process and an in-situ doping process, and the reaction gas for forming the gate material layer includes a gas containing first ions.

22. The method for forming an image sensor according to claim 20, wherein: The material of the gate material layer includes undoped polysilicon; Before etching back the gate material layer, the method further comprises: Performing ion implantation of first ions into the gate material layer.

23. The method for forming an image sensor according to claim 18, wherein: The peripheral region includes a first region and a second region, the doped ions include second ions or third ions, and ion implantation is performed on a peripheral gate material layer in a partial area of ​​the peripheral region, including: implanting second ions into the peripheral gate material layer on the first region so that the peripheral gate material layer on the first region is formed into a first peripheral gate layer, wherein the first peripheral gate layer has second ions; implanting third ions into the peripheral gate material layer on the second region so that the peripheral gate material layer on the second region is formed into a second peripheral gate layer, wherein the second peripheral gate layer has third ions, and the second ions and the third ions have different conductivity types; removing the peripheral gate material layer on the substrate, forming a first peripheral gate structure on the first region, and forming a second peripheral gate structure on the second region.

24. The method for forming an image sensor according to claim 18, wherein: The peripheral gate structure material layer also includes: a peripheral gate dielectric layer located on the substrate and the first gate structure, and the peripheral gate material layer is located on the peripheral gate dielectric layer; the peripheral gate structure includes: a peripheral gate dielectric layer located on the peripheral region and a peripheral gate layer located on the peripheral gate dielectric layer.

25. The method for forming an image sensor according to claim 18, wherein: Also includes: Forming a third spacer on the sidewall of the peripheral gate structure, the first spacer sidewall and the second spacer sidewall; forming a dielectric structure on the peripheral gate structure, on the first gate structure, on the second gate structure and on the substrate; forming a first connection structure on the first gate structure and the second gate structure, wherein the first connection structure is electrically connected to the first gate layer and the second gate layer, and the first connection structure is also located on the merged first sidewall and the second sidewall; A second connection structure is formed on the peripheral gate structure, wherein the second connection structure is electrically connected to the peripheral gate layer, and the first connection structure and the second connection structure are located in the dielectric structure.

26. An image sensor, characterized in that: include: A substrate, the substrate comprising a pixel region and a peripheral region; A first groove and a second groove located in the pixel area; A first gate structure located in the first groove, the first gate structure comprising a first gate layer, the first gate layer having first ions therein, and a top surface of the first gate layer being higher than a surface of the substrate; a second gate structure located in the second groove, the second gate structure comprising a second gate layer, the second gate layer having first ions therein, and a top surface of the second gate layer being higher than a surface of the substrate; A peripheral gate structure located on the peripheral region, the peripheral gate structure comprising a peripheral gate layer, the peripheral gate layer having doping ions therein; A first sidewall spacer located above the sidewall of the first gate layer on the surface of the substrate, wherein the material of the first sidewall spacer is the same as the intrinsic material of the peripheral gate layer; The second sidewall spacer is located on the sidewall of the second gate layer higher than the substrate surface, and the adjacent first sidewall spacer and the second sidewall spacer are merged together. The material of the second sidewall spacer is the same as the intrinsic material of the peripheral gate layer.

27. The image sensor according to claim 26, wherein: The first gate structure also includes: a first gate dielectric layer located on the side wall surface and the bottom surface of the first groove, and the first gate layer is located on the surface of the first gate dielectric layer; the second gate structure also includes: a second gate dielectric layer located on the side wall surface and the bottom surface of the second groove, and the second gate layer is located on the surface of the second gate dielectric layer.

28. The image sensor according to claim 26, wherein: The materials of the first gate layer and the second gate layer include polysilicon; and the material of the peripheral gate layer includes polysilicon.

29. The image sensor according to claim 26, wherein: The first ions include N-type ions, and the N-type ions include phosphorus ions or arsenic ions.

30. The image sensor according to claim 26, wherein: Also includes: A third spacer located on the sidewall of the peripheral gate structure, the sidewall of the first spacer and the sidewall of the second spacer; a dielectric structure located on the peripheral gate structure, on the first gate structure, on the second gate structure and on the substrate; A first connection structure located on the first gate structure and the second gate structure, the first connection structure being electrically connected to the first gate layer and the second gate layer, and the first connection structure being also located on the merged first sidewall and the second sidewall; A second connection structure is located on the peripheral gate structure, the second connection structure is electrically connected to the peripheral gate layer, and the first connection structure and the second connection structure are located in the dielectric structure.

31. The image sensor according to claim 26, wherein: The peripheral gate structure further comprises: a peripheral gate dielectric layer located on the substrate and the first gate structure, and the peripheral gate layer is located on the peripheral gate dielectric layer.

32. The image sensor according to claim 26, wherein: The peripheral region includes a first region and a second region, the doped ions include second ions or third ions, and the peripheral gate structure includes: a first peripheral gate structure located on the first region, the first peripheral gate structure includes a peripheral gate dielectric layer and a first peripheral gate layer located on the peripheral gate dielectric layer, and the first peripheral gate layer has second ions; a second peripheral gate structure located on the second region, the second peripheral gate structure includes a peripheral gate dielectric layer and a second peripheral gate layer located on the peripheral gate dielectric layer, and the second peripheral gate layer has third ions, and the second ions and the third ions have different conductivity types.

33. The image sensor according to claim 32, wherein: The conductivity type of the second ions includes N-type or P-type, and the conductivity type of the third ions includes N-type or P-type; the N-type ions include phosphorus ions or arsenic ions, and the P-type ions include boron ions or indium ions.

34. The image sensor according to claim 26, wherein: The height range of the top surface of the first gate layer above the substrate surface is greater than or equal to 0.05 microns and less than or equal to 0.2 microns; the height range of the top surface of the second gate layer above the substrate surface is greater than or equal to 0.05 microns and less than or equal to 0.2 microns.

35. The image sensor of claim 26, wherein: There is a distance between the second gate structure and the first gate structure; the range of the distance is: 0.05 micrometers to 0.2 micrometers.

Images