Uncooled infrared detector reading circuit and uncooled infrared detector

Abstract

The invention provides an uncooled infrared detector reading circuit and an uncooled infrared detector. The reading circuit comprises an uncooled infrared focal plane array, a pixel gating module, a logic control module and a reading circuit module. The uncooled infrared focal plane array comprises a plurality of rows and columns of infrared sensitive pixels; the pixel gating module is connected with each infrared sensitive pixel; the logic control module and the pixel gating module are connected with a part of infrared sensitive pixels through a logic gate circuit, and the logic control module is configured to be capable of controlling the infrared sensitive pixels connected with the logic control module not to be gated and controlling the infrared sensitive pixels not connected with the logic control module to be gated; and the readout circuit module can be used for carrying out signal readout on the gated infrared sensitive pixels.

Description

Technical Field

[0001] The present application relates to the field of infrared imaging technology, and in particular to an uncooled infrared detector readout circuit and an uncooled infrared detector. Background Art

[0002] The thermosensitive material inside the uncooled infrared detector can absorb the radiation energy of the target object and convert it into thermal energy. The thermal energy changes the physical properties of the sensitive material. The target object can be detected by converting the change in physical properties into electrical signals.

[0003] With the development trend of infrared focal plane arrays to larger arrays, smaller pixels, and faster speeds, power consumption is also increasing while performance is improving. When reading out a large array of pixel arrays, if all pixels are selected and read out in each detection, a large power consumption is required. Summary of the invention

[0004] A first aspect of an embodiment of the present application provides an uncooled infrared detector readout circuit, the uncooled infrared detector readout circuit comprising:

[0005] An uncooled infrared focal plane array including multiple rows and columns of infrared sensitive pixels;

[0006] A pixel gating module is connected to each infrared sensitive pixel;

[0007] A logic control module, connected to the pixel gating module and the corresponding preset infrared sensitive pixel through a preset logic gate circuit, and configured to control the infrared sensitive pixel connected to the logic control module not to be gated, and to control the infrared sensitive pixel not connected to the logic control module to be gated;

[0008] The readout circuit module can read out the signal of the selected infrared sensitive pixel.

[0009] In some embodiments, the logic control module can provide corresponding logic control signals to each connected infrared sensitive pixel, and the pixel selection module can send a pixel selection signal to each infrared sensitive pixel. The logic control signal controls whether the corresponding infrared sensitive pixel is selected by controlling whether the pixel selection signal of the connected infrared sensitive pixel is invalid.

[0010] In some embodiments, the pixel gating module includes a row gating module and a column gating module, and the logic gate circuit includes a two-level logic gate circuit of a first-level logic gate circuit and a second-level logic gate circuit; the first-level logic gate circuit and the second-level logic gate circuit both have an input terminal and an output terminal; wherein,

[0011] The logic gate circuit includes two first-level logic gate circuits and one second-level logic gate circuit; the input end of one of the first-level logic gate circuits is connected to the row selection module and the logic control module, the input end of another first-level logic gate circuit is connected to the column selection module and the logic control module, and the output ends of the two first-level logic gate circuits are connected to the input end of the second-level logic gate circuit; or,

[0012] The logic gate circuit includes a first-level logic gate circuit and a second-level logic gate circuit connected to the corresponding infrared sensitive pixel; the input end of the first-level logic gate circuit is connected to the row selection module and the column selection module, and the logic control module; the output end of the first-level logic gate circuit and the other of the row selection module and the column selection module are connected to the input end of the second-level logic gate circuit.

[0013] In some embodiments, the logic gate circuit is an AND gate circuit, or the logic gate circuit is a NOR gate circuit.

[0014] In some embodiments, the digital control module is configured to control all infrared sensitive picture elements connected to the logic control module to not be selected when the logic control signal is a low level signal.

[0015] In some embodiments, the uncooled infrared detector readout circuit also includes a power supply circuit for providing power to the infrared sensitive pixel, and the infrared sensitive pixel connected to the logic control module is controlled not to be selected, including: controlling the infrared sensitive pixel connected to the logic control module to be disconnected from the power supply circuit.

[0016] In some embodiments, the infrared sensitive pixel connected to the logic control module is connected to the power circuit via a switch module, and the switch module is connected to the logic gate circuit; the controlling the infrared sensitive pixel connected to the logic control module to be disconnected from the power circuit includes:

[0017] Control the switch module to disconnect.

[0018] In some embodiments, the logic control module is configured to control all infrared sensitive pixels of the uncooled infrared focal plane array to be enabled.

[0019] In some embodiments, the logic control module is capable of providing a corresponding logic control signal to each connected infrared sensitive pixel, and the logic control module is configured to control the infrared sensitive pixel connected to the logic control module to be enabled when the logic control signal is a high-level signal, so as to control all the infrared sensitive pixels of the uncooled infrared focal plane array to be enabled.

[0020] In some embodiments, the uncooled infrared detector readout circuit further includes:

[0021] A prompt module is connected to the readout circuit module and the logic control module, and is used to generate a prompt signal when the electrical signal read out by the readout circuit module is not within a preset electrical signal range. The logic control module is configured to control all infrared sensitive pixels of the uncooled infrared focal plane array to be selected according to the prompt signal.

[0022] In some embodiments, the logic control module is configured to provide a corresponding logic control signal according to the prompt signal;

[0023] The waveforms output by the logic control signal and the prompt signal are the same, and the waveforms output by the logic control signal and the prompt signal are consistent in timing.

[0024] A second aspect of an embodiment of the present application provides an uncooled infrared detector, which includes the above-mentioned readout circuit.

[0025] The main technical effects achieved by the embodiments of the present application are:

[0026] The uncooled infrared detector readout circuit and the uncooled infrared detector provided in the embodiments of the present application are configured with a logic control module in the readout circuit, and the logic control module and the pixel selection module are connected to some infrared sensitive pixels through a preset logic gate circuit, so that the infrared sensitive pixels connected to the logic control module are not selected, thereby reducing the detection window of the uncooled infrared detector readout circuit, and the infrared sensitive pixels that are not selected do not perform detection work, which is beneficial to reducing the power consumption of the uncooled infrared detector readout circuit.

[0027] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0029] Figure 1 A schematic diagram of the structure of an uncooled infrared detector readout circuit provided in one embodiment of the present application;

[0030] Figure 2 A schematic diagram of a preset infrared sensitive pixel and its circuit connection provided in one embodiment of the present application;

[0031] Figure 3Another schematic diagram of a preset infrared sensitive pixel and its circuit connection provided in an embodiment of the present application;

[0032] Figure 4 An embodiment of the present application provides Figure 2 and Figure 3 The truth table of the corresponding circuit;

[0033] Figure 5 An infrared sensitive pixel gating timing sequence provided in one embodiment of the present application;

[0034] Figure 6 A schematic diagram of an uncooled infrared focal plane array in which preset infrared sensitive pixels are not selected according to an embodiment of the present application;

[0035] Figure 7 A schematic diagram of an uncooled infrared focal plane array in which all infrared sensitive pixels are selected according to an embodiment of the present application;

[0036] Figure 8 A schematic diagram of the structure of another uncooled infrared detector readout circuit provided in one embodiment of the present application;

[0037] Fig. 9 Another schematic diagram of a preset infrared sensitive pixel and its circuit connection provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] Here, the technical solutions in the embodiments (or "implementations") of the present application will be described clearly and completely in conjunction with the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0039] If there are terms involving directional indications or positional relationships in the embodiments of the present application (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationship, movement, etc. between the components in a certain specific posture; if the specific posture changes, the directional indication or positional relationship will also change accordingly. In addition, the terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of convenience of description and cannot be understood as indicating or implying relative importance.

[0040] The following is combined with Figures 1 to 9 , the uncooled infrared detector readout circuit and the uncooled infrared detector of the embodiment of the present application are described in detail. In the absence of conflict, the features of the following embodiments and implementations can complement or combine with each other.

[0041] The uncooled infrared detector readout circuit 100 provided in the embodiment of the present application includes an uncooled infrared focal plane array 10 , a pixel gating module 20 , a logic control module 70 and a readout circuit module 40 .

[0042] The uncooled infrared focal plane array 10 includes a plurality of rows and columns of infrared sensitive pixels 101. For ease of description, the uncooled infrared focal plane array 10 includes M rows and N columns for description below, wherein M and N are both positive integers.

[0043] The pixel gating module 20 is connected to each infrared sensitive pixel 101 and is used to perform gating on the infrared sensitive pixel 101 .

[0044] Some of the infrared sensitive pixels 101 in the plurality of rows and columns are connected to the logic control module 70 as preset infrared sensitive pixels 1011. The logic control module 70 and the pixel gating module 20 can be connected to the corresponding preset infrared sensitive pixels 1011 through a preset logic gate circuit 80.

[0045] The logic control module 70 is configured to control all preset infrared sensitive pixels 1011 connected to the logic control module 70 to be not enabled, and to control the infrared sensitive pixels 101 not connected to the logic control module 70 to be enabled.

[0046] The readout circuit module 40 can read out the signal of the selected infrared sensitive pixel 101 .

[0047] The above-mentioned uncooled infrared detector readout circuit 100, by setting a logic control module 70 in the readout circuit, and the logic control module 70 and the pixel selection module are connected to the corresponding preset infrared sensitive pixel 1011 through a preset logic gate circuit 80, so that the infrared sensitive pixel 1011 connected to the logic control module is not selected, and the infrared sensitive pixel 101 not connected to the logic control module 70 is selected, so as to narrow the detection window of the uncooled infrared detector readout circuit 100, and the infrared sensitive pixel that is not selected does not perform detection work, which is beneficial to reducing the power consumption of the uncooled infrared detector readout circuit 100.

[0048] The logic control module 70 can provide corresponding logic control signals to each connected infrared sensitive pixel 101, and the pixel selection module 20 can send a pixel selection signal to each infrared sensitive pixel. The logic control signal controls whether the corresponding infrared sensitive pixel 101 is selected by controlling whether the pixel selection signal of the connected infrared sensitive pixel 101 is invalid.

[0049] Combination Figures 2 to 7As shown, in some embodiments, the uncooled infrared detector readout circuit 100 may further include a digital control module 30. The logic control module 70 may be integrated into the digital control module 30, or may be disposed outside the digital control module 30.

[0050] The digital control module 30 can be responsible for coordinating and managing the operation of the uncooled infrared detector readout circuit 100, such as obtaining the readout signal through the readout circuit module 40, performing signal processing, providing an interface for communicating with external devices, supporting data transmission with internal modules or external devices, and being able to receive signals from the outside (such as signals transmitted by a computer, input by interactive keys set by the uncooled infrared detector readout circuit 100 detector, etc.), and controlling the operation of the pixel gating module 20, the logic control module 70, etc. When the digital control module 30 controls the operation of the gating module 20 and the logic control module 70, it can send corresponding control signals to the corresponding modules as needed, and the corresponding modules then control the gating operation of the corresponding pixels.

[0051] like Figure 1 As shown, the pixel gating module 20 includes a row gating module 21 and a column gating module 22 , and the row gating module 21 and the column gating module 22 are connected to each infrared sensitive pixel 101 , respectively.

[0052] Correspondingly, the digital control module 30 is also configured to provide corresponding row selection signals row and column selection signals col to the row selection module 21 and the column selection module 22, respectively, so as to control the preset infrared sensitive pixels 1011 connected to the logic control module 70 not to be selected, and to control the infrared sensitive pixels 101 not connected to the logic control module 70 to be selected.

[0053] The row selection module 21 can be connected to the infrared sensitive pixel 101 of the corresponding row through the corresponding row selection signal line ROW, and the column selection module 22 can be connected to the infrared sensitive pixel 101 of the corresponding column through the corresponding column selection signal line COL.

[0054] In some embodiments, the readout circuit module 40 can be connected to each infrared sensitive pixel 101 through a signal line 1013. A corresponding switch module 1014 is provided at the connection between the signal line 1013 and the corresponding infrared sensitive pixel 101. When a certain infrared sensitive pixel 101 is selected, the switch module 1014 connected to the infrared sensitive pixel 101 is closed, so that the readout circuit module 40 can read the signal through the connected signal line 1013. Correspondingly, when a certain infrared sensitive pixel 101 is not selected, the switch module 1014 connected to the infrared sensitive pixel 101 is disconnected, so that the readout circuit module 40 cannot read the corresponding signal.

[0055] It should be noted that each row of infrared sensitive pixels may correspond to a row selection signal line ROW, and the uncooled infrared detector readout circuit 100 has M row selection signal lines, namely ROW1, ROW2, ROW3, ​​... ROWm. The row selection module 21 is connected to the infrared sensitive pixels 101 corresponding to each row through the row selection signal lines.

[0056] Each column of infrared sensitive pixels may correspond to a column selection signal line COL. The uncooled infrared detector readout circuit 100 has N row selection signal lines, namely COL1, COL2, COL3, ... ROWn. The column selection module 22 is connected to the infrared sensitive pixels 101 corresponding to each column through the row selection signal lines.

[0057] The logic control module 70 of the uncooled infrared detector readout circuit 100 may include a logic control signal line En. The logic control signal line En is connected to a preset portion of infrared sensitive pixels 101 (i.e., preset infrared sensitive pixels 1011). The logic control signal line En is connected to a row selection signal line ROW of the preset infrared sensitive pixel 101, and a column selection signal line COL of the preset infrared sensitive pixel 1011 through a preset logic gate circuit 80.

[0058] In some embodiments, the logic gate circuit may include a two-stage logic gate circuit. Accordingly, the logic control module 70 and the row selection signal line ROW and the column selection signal line COL connected to the preset infrared sensitive pixel 1011 may be connected using a two-stage logic gate to achieve connection with the preset infrared sensitive pixel 1011.

[0059] In some embodiments, the logic control module 70 is connected to the preset infrared sensitive pixel 1011 through the row selection signal line and the column selection signal line through a preset two-level logic gate circuit, and the two-level logic gate circuit may include two first-level logic gate circuits and one second-level logic gate circuit. The first-level logic gate circuit and the second-level logic gate circuit both have an input end and an output end. Among them, the input end of a first-level logic gate circuit is connected to the logic control signal line and the row selection signal line to connect the logic control module and the row selection module; the input end of the other first-level logic gate circuit is connected to the logic control signal line and the column selection signal line to connect the logic control module and the column selection module. The output ends of the two first-level logic gate circuits are respectively connected to different input ends of the second-level logic gate circuit. The output end of the second-level logic gate circuit is connected to the infrared sensitive pixel as the output end of the entire logic gate circuit.

[0060] Combination Figure 1 and Figure 2As shown, the logic control signal line En includes two logic control signal lines 71 and 72. The logic control signal line 71 can be connected to each row selection signal line ROW connected to the preset infrared sensitive pixel 1011 through a first-level logic gate circuit 81, and the logic control signal line 72 can be connected to each column selection signal line COL connected to the preset infrared sensitive pixel 1011 through a first-level logic gate circuit 82, and then the corresponding two first-level logic gate circuits 81 and 82 are connected to the second-level logic gate circuit 83, and finally the output end is connected to the infrared sensitive pixel 101.

[0061] Continue to combine Figure 1 and Figure 2 As shown, the row selection signal lines ROW connecting the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows of infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are respectively connected to each logic control signal line 71 through a first-level logic gate circuit 81, and the column selection signal lines COL connecting the 3rd to (N / 2-1)th and (N / 2+2)th to (N-2)th columns of infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 72 through a first-level logic gate circuit 82. Among them, the infrared sensitive pixels 101 located in the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows and the 3rd to (N / 2-1)th and (N / 2+2)th to (N-2)th columns of the uncooled infrared focal plane array 10 are used as the preset infrared sensitive pixels 1011. The two first-level logic gate circuits 81 and 82 corresponding to each preset infrared-sensitive pixel 1011 are connected to the corresponding second-level logic gate circuit 83 , and the output end of the corresponding second-level logic gate circuit 83 is connected to the infrared-sensitive pixel 101 .

[0062] like Figure 2 As shown, in some embodiments, the logic gate circuit 80 is an AND gate circuit.

[0063] For the above implementation using two-stage logic gates, each stage of logic gate circuits 81 , 82 , 83 of the logic gate circuit 80 is an AND gate circuit.

[0064] In other embodiments, in combination Figure 1 and Figure 3As shown, the row selection signal lines ROW connecting the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows of infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are connected to each logic control signal line 71 through a first-level logic gate circuit 84, and the column selection signal lines COL connecting the 3rd to (N / 2-1)th and (N / 2+2)th to (N-2)th columns of infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are connected to the logic control signal line 72 through a first-level logic gate circuit 85. Among them, the infrared sensitive pixels 101 located in the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows and the 3rd to (N / 2-1)th and (N / 2+2)th to (N-2)th columns of the uncooled infrared focal plane array 10 are used as the preset infrared sensitive pixels 1011. The two first-level logic gate circuits 84 and 85 corresponding to each preset infrared sensitive pixel 1011 are connected to the corresponding second-level logic gate circuit 86, and the output end N1 of the corresponding second-level logic gate circuit 86 is connected to the preset infrared sensitive pixel 1011. Specifically, the output end N1 of the second-level logic gate circuit 86 can be connected to the corresponding switch module 1014 to control the connection with the corresponding signal line 1013.

[0065] like Figure 3 As shown, in some other embodiments, the logic gate circuit 80 is a NOR gate circuit.

[0066] For the above implementation using two-stage logic gates, each stage of logic gate circuits 84 , 85 , 86 of the logic gate circuit 80 is an AND gate circuit.

[0067] like Figure 8 As shown, in other embodiments, that is, in the uncooled infrared detector readout circuit 200, the logic control module 70 is connected to the preset infrared sensitive pixel 1011 through the row selection signal line connected through the preset two-level logic gate circuit, and the two-level logic gate circuit may include a first-level logic gate circuit and a second-level logic gate circuit. The first-level logic gate circuit and the second-level logic gate circuit both have an input end and an output end. Among them, the input end of the first-level logic gate circuit is connected to the logic control signal line and the row selection signal line to respectively connect the logic control module and the row selection module. The output end of the first-level logic gate circuit and the column selection signal line are respectively connected to different input ends of the second-level logic gate circuit. The output end of the second-level logic gate circuit is connected to the infrared sensitive pixel as the output end of the entire logic gate circuit.

[0068] Combination Figure 8 and Fig. 9As shown, the logic control signal line En may include a logic control signal line 71, and the logic control signal line 71 may be connected to each row selection signal line ROW connected to a preset infrared sensitive pixel 1011 through a first-level logic gate circuit 81, and then the corresponding first-level logic gate circuit 81 and the corresponding column selection signal line COL are connected to the second-level logic gate circuit 83, and finally the output end is connected to the infrared sensitive pixel 101.

[0069] Continue to combine Figure 8 and Fig. 9 As shown, the row selection signal lines ROW connecting the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows of infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 71 through a first-level logic gate circuit 81. Among them, the infrared sensitive pixels 101 located in the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows of the uncooled infrared focal plane array 10 are used as preset infrared sensitive pixels 1011. The first-level logic gate circuit 81 and the corresponding column selection signal line COL corresponding to each preset infrared sensitive pixel 1011 are connected to the corresponding second-level logic gate circuit 83, and the output end of the corresponding second-level logic gate circuit 83 is connected to the preset infrared sensitive pixel 1011.

[0070] like Fig. 9 As shown, in some embodiments, the logic gate circuit 80 is an AND gate circuit.

[0071] For the above implementation using two-stage logic gates, each stage of the logic gate circuit 80 , 81 and 82 , is an AND gate circuit.

[0072] Of course, in some other embodiments, the logic control module 70 is connected to the row selection signal line connected to the preset infrared sensitive pixel 1011 through a preset two-level logic gate circuit, and the logic gate circuit can also be a NOR gate circuit.

[0073] It should be noted that the logic control module 70 is connected to the preset infrared sensitive pixel 1011 through the column selection signal line through the preset logic gate circuit, and the two-level logic gate circuit may include a first-level logic gate circuit and a second-level logic gate circuit. The first-level logic gate circuit and the second-level logic gate circuit both have an input end and an output end. Among them, the input end of the first-level logic gate circuit is connected to the logic control signal line and the column selection signal line. The output end of the first-level logic gate circuit and the row selection signal line are respectively connected to different input ends of the second-level logic gate circuit. The output end of the second-level logic gate circuit is connected to the infrared sensitive pixel as the output end of the entire logic gate circuit. In this example, the two-level logic gate circuit can be an AND gate circuit or a NOR gate circuit.

[0074] Of course, in some other embodiments, the logic control signal line can also be connected to the corresponding row selection signal line, column selection signal line and infrared sensitive pixel through other forms of logic gate circuits. For example, the logic control signal line is connected to the row selection signal line and the column selection signal line through a logic gate circuit with three input terminals and one output terminal.

[0075] In some embodiments, the digital control module 30 is configured to control the infrared sensitive picture elements 101 connected to the logic control module 70 to not be selected when the logic control signal en is a low level signal.

[0076] like Figure 4 As shown, in some embodiments, the low level signal is 0 and the high level signal is 1. Figure 4 It can be seen that when the logic control signal en is a low level signal 0, no matter the row selection signal row and the column selection signal col are high or low, the output result is 0, that is, the infrared sensitive pixel 101 connected to the logic control module 70 will not be selected.

[0077] In some embodiments, the logic control module 70 includes an enable module, and the logic control signal en is an enable signal.

[0078] In some embodiments, the uncooled infrared detector readout circuit 100 also includes a power supply circuit 60, each of the infrared sensitive pixel 101 is connected to the power supply circuit 60, and the control of not enabling the infrared sensitive pixel 101 connected to the logic control module 70 includes: controlling the infrared sensitive pixel 101 connected to the logic control module 70 to be disconnected from the power supply circuit 60.

[0079] It should be noted that a switch module 601 may be provided at the connection between the power circuit 60 and each infrared sensitive pixel 101 .

[0080] The logic control module 70 , the row selection module 21 , and the column selection module 22 are connected to the switch module 601 of the corresponding preset infrared sensitive pixel 1011 through a preset logic gate circuit 80 at each preset infrared sensitive pixel 1011 .

[0081] Correspondingly, the control to disconnect the preset infrared sensitive pixel 1011 connected to the logic control module 70 from the power supply circuit 60 includes controlling the switch module 601 to be disconnected.

[0082] Combination Figures 1 to 3 In some embodiments, the output terminal N1 of the second-stage logic gate circuit 86 may be connected to the switch module 601 of the power supply circuit 60 to control the switch module 601 to be disconnected.

[0083] Accordingly, the digital control module 30 can control the preset infrared sensitive pixel 1011 connected to the logic control module 70 to be disconnected from the power supply circuit 60 by controlling the opening and closing of the switch module 601 .

[0084] In some embodiments, the digital control module 30 is further configured to control all infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 to be strobed, and the power circuits connected to all infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are turned on. That is, the digital control module 30 is configured to control the preset infrared sensitive pixels 1011 connected to the logic control module 70 and the infrared sensitive pixels 1012 not connected to the logic control module 70 to be strobed, and the power circuits 60 connected to the preset infrared sensitive pixels 1011 and the infrared sensitive pixels 1012 are turned on.

[0085] In some embodiments, the digital control module 30 is configured to control the preset infrared sensitive pixel 1011 connected to the logic control module 70 to be enabled when the logic control signal en is a high level signal.

[0086] like Figure 4 As shown, in some embodiments, the low level signal is 0 and the high level signal is 1. Figure 4 It can be seen that when the logic control signal en is a high level signal 1, the preset infrared sensitive pixels 1011, that is, the infrared sensitive pixels 101 connected to the logic control module 70, are all selected. That is, the row selection module and the column selection module can select all the infrared sensitive pixels 101, and when the row selection signal row and the column selection signal col are high, the output results are all 1, and each infrared sensitive pixel 101 of the uncooled infrared focal plane array 10 can be selected in sequence.

[0087] In some embodiments, the uncooled infrared detector readout circuit 100 further includes a prompt module 50 .

[0088] The prompt module 50 is connected to the readout circuit module 40 and to the logic control module 70, and is used to generate a prompt signal Alarm when the electrical signal read out by the readout circuit module 40 is not within a preset electrical signal range. The logic control module 70 can control all infrared sensitive pixels 101 of the uncooled infrared focal plane array to be selected according to the prompt signal Alarm.

[0089] The preset electrical signal range can be set according to specific needs, for example, when the infrared sensitive pixel connected to the logic control module 70 is enabled and other infrared sensitive pixels are not enabled, whether the image generated by the electrical signal read by the readout circuit module 40 contains any abnormal situation that requires adding enabled infrared sensitive pixels to further confirm the target.

[0090] In some embodiments, the prompt module 50 can be connected to the logic control module 70 by connecting to the digital control module 30. The prompt module 50 can feed back the prompt signal Alarm to the digital control module 30. The digital control module 30 generates a logic control signal according to the corresponding prompt signal Alarm. Then, the digital control module 30 can provide the corresponding logic control signal to the logic control module 70 to control all the infrared sensitive pixels of the uncooled infrared focal plane array 10 to be selected.

[0091] Combination Figure 5 As shown, in some embodiments, the waveform output by the logic control signal is the same as that by the alarm signal Alarm, and the waveform output by the logic control signal is consistent with that by the alarm signal in timing, so that all infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are intelligently controlled to be enabled to meet the requirement that all infrared sensitive pixels 101 perform detection work.

[0092] It should be noted that, in some other embodiments, the digital control module 30 can also control the preset infrared sensitive pixel 1011 connected to the logic control module 70 to be selected by other methods. For example, the outside world inputs a signal to the digital control module 30 through a button or other methods, so that the digital control module 30 inputs a corresponding en signal (such as a high level signal) to the logic control module 70.

[0093] Based on the above description, combined with Figures 4 to 7As shown, for the above-mentioned uncooled infrared focal plane array 10 including M rows and N columns of infrared sensitive pixels 101, the row selection signal lines ROW of the 3rd to (M / 2-1)th and (M / 2+2)th to (M-2)th rows of infrared sensitive pixels 101 are respectively connected to each logic control signal line 71 through a first-level logic gate circuit 81, and the column selection signal lines COL of the 3rd to (N / 2-1)th and (N / 2+2)th to (N-2)th columns of infrared sensitive pixels 101 of the uncooled infrared focal plane array 10 are respectively connected to the logic control signal line 72 through a first-level logic gate circuit 82. The two first-level logic gate circuits 81 and 82 corresponding to each preset infrared sensitive pixel 1011 are connected to the corresponding second-level logic gate circuit 83, and the output end of the corresponding second-level logic gate circuit 83 is connected to the infrared sensitive pixel 101 for exemplary description. The uncooled infrared focal plane array 10 is exemplified as 10 rows and 8 columns, wherein the timing diagram only illustrates the digital timing of the first 3 rows and the first 3 columns. The START signal is a control signal for the global operation of the entire uncooled infrared detector readout circuit 100. When the START signal is low, it indicates that the uncooled infrared detector readout circuit 100 starts to work. The default Alarm signal is low, that is, no image abnormality occurs. When en is low, the low power consumption mode is turned on. In this low power consumption mode, the preset infrared sensitive pixels 1011 are not selected, and the other infrared sensitive pixels 1012 are selected, such as Figure 6 As shown. Figure 6 As shown, the infrared sensitive pixels corresponding to the dark gray area are infrared sensitive pixels 1012 that are selected, and the infrared sensitive pixels corresponding to the light gray area are preset infrared sensitive pixels 1011 that are not selected. Combined with the timing diagram of the first 3 rows and 3 columns, only the infrared sensitive pixels 101 in the first 3 rows and 3 columns are selected. At this time, the corresponding infrared sensitive pixels 1012 in the first row, first column and second column, and the first row, first column and second column are selected. When the prompt module 50 detects that the electrical signal read out by the readout circuit module 40 is not within the preset electrical signal range (such as a voltage signal or a current signal), that is, when the image generated by the readout signal of the uncooled infrared detector readout circuit 100 has an abnormal situation that requires the addition of selected infrared sensitive pixels for further confirmation, the Alarm signal generated by the prompt module 50 is high, and en is converted to a high level accordingly. All infrared sensitive pixels 101 included in the uncooled infrared focal plane array 10 can be selected, as shown in FIG. Figure 7 As shown, the pixel array is output row by row.

[0094] The embodiment of the present application further provides an uncooled infrared detector, which includes the uncooled infrared detector readout circuit 100 described in any of the above embodiments. The uncooled infrared detector of the present application can realize that the preset infrared sensitive pixel 1011 is not selected, and the infrared sensitive pixel 101 not connected to the logic control module 70 is selected through a simple logic circuit, so as to reduce the detection window of the uncooled infrared detector readout circuit 100, which is conducive to reducing the power consumption and detection efficiency of the uncooled infrared detector readout circuit 100.

[0095] It should be noted that the technical solutions or technical features described in the above embodiments can be combined or supplemented with each other without causing conflicts. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the drawings; all modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. An uncooled infrared detector readout circuit, characterized in that: The uncooled infrared detector readout circuit comprises: An uncooled infrared focal plane array including multiple rows and columns of infrared sensitive pixels; A pixel gating module is connected to each infrared sensitive pixel; A logic control module, connected to the pixel gating module and part of the infrared sensitive pixels through a logic gate circuit, and configured to control all infrared sensitive pixels connected to the logic control module not to be gated, and to control infrared sensitive pixels not connected to the logic control module to be gated; The readout circuit module can read out the signal of the selected infrared sensitive pixel.

2. The uncooled infrared detector readout circuit according to claim 1, characterized in that: The logic control module can provide corresponding logic control signals to each connected infrared sensitive pixel, and the pixel selection module can send a pixel selection signal to each infrared sensitive pixel. The logic control signal controls whether the corresponding infrared sensitive pixel is selected by controlling whether the pixel selection signal of the connected infrared sensitive pixel is invalid.

3. The uncooled infrared detector readout circuit according to claim 1, characterized in that: The pixel gating module includes a row gating module and a column gating module, and the logic gate circuit includes a two-level logic gate circuit of a first-level logic gate circuit and a second-level logic gate circuit; the first-level logic gate circuit and the second-level logic gate circuit both have an input terminal and an output terminal; wherein, The logic gate circuit includes two first-level logic gate circuits and one second-level logic gate circuit; the input end of one of the first-level logic gate circuits is connected to the row selection module and the logic control module, the input end of another first-level logic gate circuit is connected to the column selection module and the logic control module, and the output ends of the two first-level logic gate circuits are connected to the input end of the second-level logic gate circuit; or, The logic gate circuit includes a first-level logic gate circuit and a second-level logic gate circuit; the input end of the first-level logic gate circuit is connected to one of the row selection module and the column selection module, and the logic control module; the output end of the first-level logic gate circuit and the other of the row selection module and the column selection module are connected to the input end of the second-level logic gate circuit.

4. The uncooled infrared detector readout circuit according to any one of claims 1 to 3, characterized in that: The logic gate circuit is an AND gate circuit, or the logic gate circuit is a NOR gate circuit.

5. The uncooled infrared detector readout circuit according to claim 2, characterized in that: The logic control module is configured to control all infrared sensitive picture elements connected to the logic control module to not be selected when the logic control signal is a low level signal.

6. The uncooled infrared detector readout circuit according to claim 1, characterized in that: The uncooled infrared detector readout circuit also includes a power supply circuit for providing power to the infrared sensitive pixel. The infrared sensitive pixel connected to the logic control module is controlled not to be selected, including: controlling the infrared sensitive pixel connected to the logic control module to be disconnected from the power supply circuit.

7. The uncooled infrared detector readout circuit according to claim 6, characterized in that: The infrared sensitive pixel connected to the logic control module is connected to the power circuit via a switch module, and the switch module is connected to the logic gate circuit; the control method of disconnecting the infrared sensitive pixel connected to the logic control module from the power circuit includes: Control the switch module to disconnect.

8. The uncooled infrared detector readout circuit according to claim 1, characterized in that: The logic control module is configured to control all infrared sensitive pixels of the uncooled infrared focal plane array to be enabled.

9. The uncooled infrared detector readout circuit according to claim 8, characterized in that: The logic control module can provide corresponding logic control signals to each connected infrared sensitive pixel. The logic control module is configured to control the infrared sensitive pixel connected to the logic control module to be enabled when the logic control signal is a high-level signal, so as to control all the infrared sensitive pixels of the uncooled infrared focal plane array to be enabled.

10. The uncooled infrared detector readout circuit according to claim 8, characterized in that: The uncooled infrared detector readout circuit also includes: A prompt module is connected to the readout circuit module and the logic control module, and is used to generate a prompt signal when the electrical signal read out by the readout circuit module is not within a preset electrical signal range. The logic control module is configured to control all infrared sensitive pixels of the uncooled infrared focal plane array to be selected according to the prompt signal.

11. The uncooled infrared detector readout circuit according to claim 10, characterized in that: The logic control module is configured to provide a corresponding logic control signal according to the prompt signal; The waveforms output by the logic control signal and the prompt signal are the same, and the waveforms output by the logic control signal and the prompt signal are consistent in timing.

12. An uncooled infrared detector, characterized in that: The uncooled infrared detector comprises an uncooled infrared detector readout circuit as claimed in any one of claims 1 to 11.

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