Multi-threshold voltage logic design method and system for passive internet-of-things tag chip

Abstract

The invention relates to the technical field of passive internet-of-things tag chips, and discloses a multi-threshold voltage logic design method and system for a passive internet-of-things tag chip, and the method comprises the steps: dividing the passive internet-of-things tag chip into a plurality of functional domains, carrying out the threshold voltage demand analysis of each functional domain, and obtaining a functional domain threshold voltage parameter table; configuring a multi-threshold transistor configuration structure for each functional domain, and designing a multi-threshold logic gate circuit group for each functional domain by using the multi-threshold transistor configuration structure; constructing a threshold voltage dynamic adjustment system, and designing a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network; the inter-domain signal transmission network and the multi-threshold logic gate circuit group are integrated, and physical isolation layout and optimization are carried out to obtain a passive Internet of Things tag chip design scheme, so that the energy utilization efficiency is improved, and the problem of unstable performance of a traditional passive Internet of Things tag chip single-threshold design in an energy fluctuation environment is solved.

Description

Technical Field

[0001] The present application relates to the technical field of passive IoT tag chips, and in particular to a multi-threshold voltage logic design method and system for a passive IoT tag chip. Background Art

[0002] Traditional passive tag chips use a single threshold voltage design, which shows obvious limitations in actual application scenarios with complex and changeable working environments. When the tag is far away from the reader or is subject to electromagnetic interference, the energy captured by the chip fluctuates violently. The single threshold voltage design cannot take into account both energy capture efficiency and circuit stability at the same time, resulting in the chip being unable to work stably in a weak field environment, limited reading distance, and having problems such as high bit error rate and poor data integrity.

[0003] The single threshold voltage design of traditional passive tag chips faces irreconcilable technical contradictions: if a lower threshold voltage is used to improve sensitivity, although it can work in a weak electromagnetic field, it will significantly increase leakage current, resulting in increased power consumption and shortened data retention time; if a higher threshold voltage is used to reduce power consumption, the minimum operating voltage of the chip is limited, making it completely unable to work in the case of insufficient energy. In addition, the single threshold voltage design is extremely sensitive to temperature changes. In extremely cold or high temperature environments, the threshold voltage drift causes the tag performance to deteriorate sharply, and it cannot meet the requirements of stable operation over the full temperature range. Summary of the invention

[0004] The present application provides a multi-threshold voltage logic design method and system for a passive IoT tag chip, thereby improving energy utilization efficiency and solving the problem of unstable performance of a traditional passive IoT tag chip with a single threshold design in an energy fluctuation environment.

[0005] The first aspect of the present application provides a multi-threshold voltage logic design method for a passive IoT tag chip, the multi-threshold voltage logic design method for a passive IoT tag chip comprising: The passive IoT tag chip is divided into multiple functional domains, and the threshold voltage requirement analysis is performed on each functional domain to obtain a functional domain threshold voltage parameter table; According to the functional domain threshold voltage parameter table, configuring a multi-threshold transistor configuration structure for each functional domain, and using the multi-threshold transistor configuration structure to design a multi-threshold logic gate circuit group for each functional domain; Based on the multi-threshold logic gate circuit group, a threshold voltage dynamic adjustment system is constructed, and the threshold voltage dynamic adjustment system is used to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network; The inter-domain signal transmission network is integrated with the multi-threshold logic gate circuit group, and physically isolated layout and optimization are performed to obtain a passive IoT tag chip design solution.

[0006] The second aspect of the present application provides a multi-threshold voltage logic design system for a passive IoT tag chip, the multi-threshold voltage logic design system for a passive IoT tag chip comprising: An analysis module is used to divide the passive IoT tag chip into multiple functional domains, and perform threshold voltage requirement analysis on each functional domain to obtain a functional domain threshold voltage parameter table; A configuration module, configured to configure a multi-threshold transistor configuration structure for each functional domain according to the functional domain threshold voltage parameter table, and to design a multi-threshold logic gate circuit group for each functional domain using the multi-threshold transistor configuration structure; A construction module is used to construct a threshold voltage dynamic adjustment system based on the multi-threshold logic gate circuit group, and adopt the threshold voltage dynamic adjustment system to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network; The optimization module is used to integrate the inter-domain signal transmission network with the multi-threshold logic gate circuit group, and perform physical isolation layout and optimization to obtain a passive IoT tag chip design solution.

[0007] Compared with the prior art, the present application has the following beneficial effects: the multi-threshold voltage logic design method of the present invention divides the chip into four functional domains and configures different threshold voltage transistors for each domain, so that the passive tag chip can work stably within an ultra-wide voltage range, breaking through the minimum operating voltage limit of the traditional single-threshold design; by configuring ultra-low threshold transistors for the RF front-end domain to maximize the energy capture efficiency, combined with the threshold voltage dynamic adjustment system, the optimization of the reading distance and static power consumption is achieved; based on the design of the threshold voltage generator and the temperature compensation circuit, the passive tag maintains stable working characteristics within the full temperature range; by designing three types of cross-threshold domain signal transmission buffers, the signal integrity problem between different threshold domains is significantly improved; different threshold voltage domains are physically isolated to improve the anti-interference ability; the integrated RF energy detector and dynamic threshold switching mechanism can automatically switch the optimal threshold working mode according to the input energy in a very short time; combined with the functional domain dynamic shutdown technology based on activity detection and the progressive wake-up sequence, the energy utilization efficiency is greatly improved, and the problem of unstable performance of the traditional single threshold design in an energy fluctuation environment is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0009] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0010] Figure 1 It is a flow chart of a multi-threshold voltage logic design method for a passive IoT tag chip provided by an embodiment of the present invention; Figure 2 It is a schematic block diagram of the structure of a multi-threshold voltage logic design system for a passive IoT tag chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0012] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0013] It should also be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0014] It should be further understood that the term "and / or" used in the specification and appended claims of this application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations. Figure 1 , an embodiment of the multi-threshold voltage logic design method of the passive IoT tag chip in the embodiment of the present application includes: Step 100: Divide the passive IoT tag chip into multiple functional domains, and perform threshold voltage requirement analysis on each functional domain to obtain a functional domain threshold voltage parameter table; It is understandable that the execution subject of the present application can be a multi-threshold voltage logic design system of a passive IoT tag chip, or a terminal or a server, which is not limited here. The present application embodiment is described by taking a server as the execution subject as an example.

[0015] Specifically, the passive IoT tag chip is divided into multiple functional domains, including the RF front-end domain, the clock control domain, the protocol processing domain, and the storage domain. Each functional domain has different working requirements and voltage requirements. By dividing the chip into multiple functional domains, the power consumption and performance of each part can be controlled more accurately. The energy capture efficiency of the RF front-end domain is measured. The main task of the RF front-end domain is to capture and process external RF signals, and its energy capture efficiency directly affects the working performance of the chip. The energy capture efficiency of the RF front-end domain is measured in different voltage ranges, usually in the voltage range of 0.1V to 1.5V. These test data help draw the energy capture efficiency curve of the RF front-end domain to ensure that the energy collection efficiency of this domain is optimized at a specific voltage. By analyzing the efficiency curve, the optimal operating voltage of the RF front-end domain is determined to maximize the energy capture effect and improve the overall performance of the system. The clock control domain is tested for stable oscillation to test the minimum voltage required for stable oscillation under the temperature range of -20℃ to 85℃. Through the test, the minimum voltage threshold data of the clock control domain is obtained. The protocol processing domain is tested for complete data frame processing. This process involves the relationship between the minimum operating voltage and power consumption required for the protocol processing unit to process data frames in a specific frequency band (such as 915MHz). Through these tests, the relationship between the minimum operating voltage and power consumption of the protocol processing domain is obtained to help determine the operating voltage of the protocol processing unit under different power consumption conditions. By adjusting the operating voltage, the processing performance and power consumption are balanced to optimize the efficiency of the protocol processing process and ensure the accuracy and reliability of data transmission. The static leakage current and data retention time of the storage domain are measured at different voltage thresholds to obtain the leakage performance curve of the storage domain, and the optimal voltage threshold is determined based on this curve. By optimizing the voltage threshold, the leakage current is effectively reduced and the data is ensured to remain valid for a long time. According to the energy capture efficiency curve of the RF front-end domain, the minimum voltage threshold data of the clock control domain, the relationship between the minimum operating voltage and power consumption of the protocol processing domain, and the leakage performance curve of the storage domain, the optimal threshold voltage of each functional domain is determined, and the functional domain threshold voltage correspondence table is obtained. Based on the functional domain threshold voltage correspondence table, key parameters such as the timing requirements, power consumption budget, and noise tolerance of signal transmission between each functional domain are recorded. Inter-domain interface specifications are formulated to ensure that signals can be stably transmitted between different voltage domains, and a functional domain threshold voltage parameter table is obtained.

[0016] Step 200: configuring a multi-threshold transistor configuration structure for each functional domain according to the functional domain threshold voltage parameter table, and using the multi-threshold transistor configuration structure to design a multi-threshold logic gate circuit group for each functional domain;Specifically, transistor types are allocated to multiple functional domains according to the functional domain threshold voltage parameter table. Different types of transistors are selected for matching according to the voltage requirements, power consumption requirements and performance requirements of each functional domain. The main task of the RF front-end domain is to efficiently capture RF signals, so transistors with ultra-low thresholds (such as ultra-low threshold transistors ULVt) are selected to maximize energy capture efficiency. The clock control domain needs to maintain a stable oscillation frequency, so low threshold transistors (LVt) are selected to ensure good stability and low power consumption. The protocol processing domain involves more complex logical calculations and requires higher anti-interference capabilities and processing performance, so standard threshold transistors (SVt) are selected. The storage domain needs to ensure data storage stability under low power consumption, so high threshold transistors (HVt) are selected to reduce leakage current and extend data retention time. Through transistor type allocation, a transistor type allocation scheme is obtained. Based on the transistor type allocation scheme, a multi-threshold transistor process parameter table is matched. In this process, according to the selected transistor type, the specific process parameters applicable to each functional domain are determined with reference to the process parameters of the transistor, including threshold voltage, subthreshold swing, current drive capability, etc. The ultra-low threshold transistor selected in the RF front-end domain should have a low threshold voltage and a small subthreshold swing, which helps to improve the RF response. The low threshold transistor selected in the clock control domain has a high current driving capability and a small power consumption to ensure the stable operation of the oscillator in a wide temperature range. The standard threshold transistor selected in the protocol processing domain should have good anti-interference ability and relatively low power consumption while ensuring performance. The high threshold transistor in the storage domain needs to have a high leakage current control capability and a long data retention time to ensure the reliability and stability of data storage. By selecting and matching each transistor type, a multi-threshold transistor process parameter table is generated. The structural scheme of each type of transistor is generated according to the multi-threshold transistor process parameter table, which determines how the transistor is laid out in the actual circuit to maximize its performance. The ultra-low threshold transistor in the RF front-end domain requires a shorter channel length to improve its response speed and efficiency. The channel length is shortened to 0.8 times the minimum design rule during design. The low threshold transistor in the clock control domain needs to optimize the channel width-to-length ratio to balance oscillation stability and power consumption, which is set to 2:1. The standard threshold transistor in the protocol processing domain adopts an 8T transistor structure to improve anti-interference ability. The high-threshold transistors in the storage domain use deep N-well isolation technology to reduce static leakage current and increase data retention time. Through these designs, a suitable transistor structure scheme is tailored for each functional domain to ensure that the circuits of each functional domain can achieve the best working state at different voltage thresholds. According to the transistor structure scheme, the physical layout of multi-threshold transistors is designed. Through reasonable layout, different types of transistors can be effectively integrated on the same chip to avoid mutual interference. The ultra-low threshold transistors in the RF front-end domain are physically isolated from the high threshold transistors in the storage domain to avoid mutual interference.The design requires that the physical isolation distance between these two types of transistors is not less than 15μm to ensure signal stability. For the low threshold transistors in the clock control domain, a ring gate structure is used to reduce edge effects and improve clock stability. The standard threshold transistors in the protocol processing domain use an island-shaped substrate bias structure to form a threshold voltage fine-tuning area to further optimize the protocol processing performance. After completing these layout designs, the transistor physical layout diagram is obtained. The transistor physical layout diagram is used to carry out multi-threshold transistor array integration design, and different threshold transistors are efficiently integrated according to the predetermined layout scheme to ensure that they are interconnected and work together on the chip. By adopting differentiated process flows in different areas of the common wafer, physical isolation and interconnection of various types of transistors are achieved. After the transistor array design is completed, the threshold voltage drift test is performed on the integrated transistor array layout structure. Through the test, the threshold voltage drift curves of various types of transistors under different temperatures and working conditions are recorded, and their key parameters such as current driving capability, subthreshold swing and response time are evaluated. According to the multi-threshold transistor configuration structure obtained from the test results, the corresponding multi-threshold voltage logic gate circuit is designed for each functional domain. According to the multi-threshold transistor configuration structure, the multi-threshold logic gate circuit designed for each functional domain will work based on different threshold voltages to ensure the best balance between the performance and power consumption of each functional domain. For example, the ultra-low threshold transistors in the RF front-end domain are used to design low-power data demodulators, the low threshold transistors in the clock control domain are used to design stable clock oscillators, the standard threshold transistors in the protocol processing domain are used to design efficient processing units, and the high threshold transistors in the storage domain are used to design low-leakage storage units. Through the above design, a multi-threshold voltage logic gate circuit group is obtained.

[0017] According to the parameters of the ultra-low threshold transistor (first threshold transistor) required by the RF front-end domain, a special logic gate circuit is designed. The main task of the RF front-end domain is to efficiently capture and demodulate external RF signals, so power consumption and response speed are particularly important during design. By adopting the low threshold characteristics of the first threshold transistor, an ultra-low power data demodulator circuit is designed, and by reducing the number of stacked transistors, the circuit can still work stably at low voltage. The logic gate circuit of the RF front-end domain needs to have efficient data processing capabilities and ensure that it can operate stably at low voltage, thereby maximizing energy capture efficiency. In the design of the clock control domain, a logic gate circuit suitable for the clock control domain is designed according to the parameters of the second threshold transistor. The clock control domain controls the synchronous operation of various parts inside the chip, so its design needs to focus on timing stability and anti-interference ability. According to the parameters of the second threshold transistor, a ring oscillator with a stable frequency is designed using the characteristics of the low threshold transistor, and it is ensured that the clock control circuit maintains high stability and low power consumption over the full temperature range. The use of low threshold transistors can effectively reduce power consumption while ensuring the accuracy and reliability of the clock signal. In the design of the protocol processing domain, based on the parameters of the third threshold transistor, the third threshold logic gate circuit is designed to perform complex data processing tasks. The protocol processing domain needs to process data from the RF front-end domain and convert it into a format that can be used by other parts of the chip. Using the medium threshold voltage characteristics of the third threshold transistor, an efficient 8-bit RISC instruction processor is designed to ensure that the execution time of each instruction is completed in as few clock cycles as possible. At the same time, the state machine controller in the design should support multiple state transitions, and its transition delay should be kept within the minimum range. In order to ensure the integrity and rapidity of data processing, a CRC check unit is integrated in the protocol processing circuit to ensure the correctness of data transmission. Through these designs, the logic gate circuit of the protocol processing domain effectively supports various data processing and protocol conversion tasks, thereby improving the processing efficiency of the entire system. For the design of the storage domain, the fourth threshold logic gate circuit is designed according to the parameters of the fourth threshold transistor. The task of the storage domain is to save and maintain data, so its design focuses on low power consumption and high data retention capability. Using the high threshold voltage characteristics of the fourth threshold transistor, a low-leakage 8T-SRAM storage unit is designed. The storage unit guarantees low power consumption and maintains data stability for a long time. The storage domain also needs to support fast read and write operations, so the design also includes a register array with independent read and write ports to enable fast data access without affecting performance. In order to ensure that the data is retained for at least 100 milliseconds when there is no external power supply, a non-volatile configuration register is designed to keep the data in the event of a power outage. Circuit simulation is performed on the first, second, third, and fourth threshold logic gate circuits to verify that each circuit works properly within the expected voltage range and to ensure that they meet parameters such as timing requirements, power consumption limits, and noise tolerance.During the simulation process, we focus on the key performance indicators of each logic gate, such as propagation delay, power consumption, and noise sensitivity, and record these data to form a multi-threshold logic gate characteristic database. Based on the multi-threshold logic gate characteristic database, we design the interconnection of the logic gate circuits of each functional domain to form a multi-threshold logic gate circuit group. According to the design requirements of each functional domain, we reasonably interconnect the logic gate circuits to ensure efficient transmission of signals between the functional domains.

[0018] Step 300: construct a threshold voltage dynamic adjustment system based on a multi-threshold logic gate circuit group, and use the threshold voltage dynamic adjustment system to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network; It should be noted that the threshold voltage monitoring circuit is designed by using the first threshold logic gate circuit in the multi-threshold logic gate circuit group to monitor the voltage changes of each functional domain of the chip in real time. In the low-voltage and low-power RF front-end domain, the threshold voltage monitoring circuit realizes nanosecond voltage sampling and microsecond response speed through modules such as high-precision energy detectors, fast-response voltage fluctuation monitors, and stable temperature sensors, ensuring rapid feedback of the current voltage state when the energy input fluctuates. At the same time, based on the second threshold logic gate circuit in the multi-threshold logic gate circuit group, a multifunctional threshold voltage generator circuit is designed, which dynamically provides adjustable voltage output according to the voltage requirements of different functional domains. By designing an independently adjustable bandgap reference source, multiple specific threshold voltages, such as 0.35V, 0.55V, 0.75V, and 0.95V, are stably output to meet the optimal operating voltage requirements of different functional domains. In order to cope with environmental changes and fluctuations in the internal load of the chip, the threshold voltage generator circuit integrates an adjustable fine-tuning circuit and a temperature compensation module, so that the output voltage can be accurately adjusted within the range of ±0.15V, and the voltage accuracy is kept within ±2%, thereby ensuring that the system can still provide a stable operating voltage when the chip temperature changes or the external RF energy input fluctuates. According to the output data of the threshold voltage monitoring circuit, a dynamic threshold switching decision circuit is designed. The circuit quickly determines whether the voltage threshold needs to be switched and selects the appropriate voltage gear according to the monitored voltage, energy input and the working status of the current functional domain. By introducing a threshold selection algorithm based on energy prediction, the decision circuit completes the threshold switching decision within 10 microseconds after detecting the change in external RF energy. In order to improve the reliability of the chip under extremely low energy conditions, a switching strategy controller based on functional priority is designed for the decision circuit. When the energy supply is insufficient, the stable operation of the storage domain is prioritized to avoid data loss. At the same time, a burst mode recognition module is integrated in the dynamic threshold switching decision circuit to identify the data burst transmission mode of the protocol processing domain, so that it can switch to a higher voltage mode in advance when large amounts of data are transmitted, ensuring the performance and speed of protocol processing. Based on the threshold voltage generator circuit and the dynamic threshold switching decision circuit, a threshold switching execution circuit is designed to achieve smooth voltage switching. By designing four independent threshold voltage controllers, each controller corresponds to a functional domain, and stably switches to the target threshold voltage within 5 microseconds. At the same time, in order to avoid transient interference generated during the voltage switching process, a smooth transition module is introduced in the switching execution circuit, which controls the voltage change rate within 0.01V / microsecond to reduce the noise and current shock introduced during the switching process. The power isolation control module is integrated in the switching execution circuit. When the threshold voltage is switched, the power supply of each functional domain is independently controlled to avoid signal interference and power supply noise propagation between different voltage domains, thereby ensuring that the entire system can still operate stably during the dynamic adjustment process.The threshold voltage monitoring circuit, threshold voltage generator circuit, dynamic threshold switching decision circuit and threshold switching execution circuit are interconnected and integrated to construct a threshold voltage dynamic control system circuit. During the integration process, through reasonable layout design, the signal transmission path between modules is ensured to be the shortest, the timing control is optimized, and the efficiency and stability of dynamic voltage adjustment are achieved. In order to verify the function of the threshold voltage dynamic control system, circuit function verification tests are carried out, including dynamic adjustment performance tests under different temperatures, different RF energy inputs and different functional domain load conditions. In these tests, the system can show an efficient performance with an overall response time of no more than 20 microseconds, verifying the reliability and practicality of the design, and obtaining a threshold voltage dynamic adjustment system. Using the threshold voltage dynamic adjustment system, a cross-threshold domain signal transmission buffer is designed to form an inter-domain signal transmission network. By designing a level conversion module in the buffer, the input signal is accurately converted between 0.35V, 0.55V, 0.75V and 0.95V, and the conversion time is ensured to be no more than 1.5 nanoseconds. At the same time, dynamic bias control and Schmitt trigger design are introduced in the buffer to improve noise resistance and reduce power consumption to less than 50 nanowatts when the signal is static, and no more than 1 microwatt when it is dynamic. When designing a multi-stage transmission buffer, the combination of progressive threshold conversion and transmission line matching circuits is used to achieve the effect of reducing signal transmission delay and reflection coefficient. Through the reasonable layout of these buffers, an inter-domain signal transmission network is constructed at the boundaries of different functional domains, so that signals can be reliably transmitted between different voltage domains, effectively ensuring the stability and efficiency of the chip in a multi-threshold voltage environment.

[0019] By using the threshold voltage dynamic adjustment system, the signal transmission characteristics between different threshold voltage domains are analyzed to obtain the inter-domain signal characteristic data. Through the monitoring function of the dynamic adjustment system, the signal transmission conditions between different voltage domains are collected, including the degradation rate of the rising and falling edges of the signal, the attenuation of the signal amplitude, the maximum allowable transmission delay, and the minimum hold time requirements. By analyzing the signal noise coupling coefficient, the interference degree between different voltage domains is determined. According to the inter-domain signal characteristic data, the level conversion circuit, the input stage with Schmitt trigger and the dynamic bias control module are designed to construct the second threshold to fourth threshold domain transmission buffer to obtain the low-high domain transmission buffer. The low-high domain transmission buffer accurately converts the lower threshold voltage (such as 0.35V, 0.55V, 0.75V) to the higher threshold voltage (such as 0.55V, 0.75V, 0.95V) and ensures the signal integrity during the conversion process. The level conversion circuit adopts dynamic bias control technology to make the buffer power consumption less than 50nW in static state, and the power consumption in dynamic operation is controlled within 1μW. In order to enhance the anti-noise capability, the input stage of the buffer integrates a Schmitt trigger design, which improves the anti-noise capability by at least 150mV, so that a high signal-to-noise ratio can be maintained in a complex signal environment. And by optimizing the circuit topology, the signal level conversion time does not exceed 1.5ns, ensuring the response speed and accuracy during high-speed data transmission. While designing the low-high domain transmission buffer, the high-low domain transmission buffer is designed according to the inter-domain signal characteristic data. The buffer converts the signal with a higher threshold voltage (such as 0.95V, 0.75V, 0.55V) to a lower threshold voltage (such as 0.75V, 0.55V, 0.35V). In order to achieve this function, a pull-down level conversion circuit is introduced in the high-low domain transmission buffer to achieve safe conversion from high voltage to low voltage by precisely controlling the current path. The buffer also integrates a current limiting protection circuit to prevent the strong current signal in the high threshold domain from damaging the circuit in the low threshold domain. Through the output driver module with threshold compensation, the buffer automatically adjusts the driving strength according to the characteristics of the input signal, so that the output of the buffer can adapt to voltage fluctuations of up to ±15%, thereby effectively improving the robustness and stability of cross-domain signal transmission. In order to optimize the transmission effect of signals across multiple threshold domains, a multi-level domain transmission buffer is designed based on the low-high domain and high-low domain transmission buffers. The multi-level domain transmission buffer uses a progressive threshold conversion circuit to make the signal smoothly transition between different threshold voltage domains, avoiding drastic fluctuations and losses in the signal during the conversion process. At the same time, the buffer uses an on-chip transmission line matching circuit to accurately match the impedance of the transmission line, so that the reflection coefficient of the signal is reduced to below 0.2, thereby effectively reducing signal reflection and energy loss during transmission.At the same time, the buffer integrates a variable gain output stage to dynamically adjust the gain of the output signal according to the actual load conditions, so that the signal can still maintain a high driving strength under different load conditions. The design of the multi-level buffer reduces the signal transmission delay and improves the efficiency of cross-domain signal transmission. Based on the multi-level domain transmission buffer, a differential signal transmission circuit, a low-swing signal transmission technology and a clock data recovery circuit are designed, and a high-speed inter-domain bus is designed to achieve high-speed data transmission between the functional domains in the chip. In the bus design, a differential signal transmission circuit is used to improve the ability to resist common-mode noise, and the signal swing is controlled within 70% of the threshold voltage through low-swing signal transmission technology to reduce power consumption in signal transmission. The high-speed inter-domain bus also integrates a clock data recovery circuit to achieve accurate transmission of inter-domain data without a synchronous clock, so that the bus can still provide reliable communication capabilities in various complex scenarios. The low-high domain transmission buffer, the high-low domain transmission buffer, the multi-level domain transmission buffer and the high-speed inter-domain bus are arranged at the boundaries of each functional domain, and the inter-domain communication network is interconnected to obtain an inter-domain signal transmission network. During the layout process, circuit wiring is performed according to the physical location of each functional domain and the optimal length of the signal transmission path to ensure that the signal delay and loss during transmission are minimized. At the same time, by setting up dedicated buffers and signal conditioning modules at the boundary areas of different threshold domains, the signal can maintain stable transmission quality when crossing different voltage domains. Through this layout and interconnection design, the inter-domain signal transmission network formed can ensure the reliability of signal transmission under all working conditions, effectively improving the performance and work efficiency of the entire passive IoT tag chip.

[0020] Step 400: Integrate the inter-domain signal transmission network with the multi-threshold logic gate circuit group, and perform physical isolation layout and optimization to obtain a passive IoT tag chip design solution.

[0021] Specifically, the inter-domain signal transmission network and the multi-threshold logic gate circuit group are physically isolated and designed to ensure that the signal interference between domains with different threshold voltages is minimized. In the physical isolation layout, deep trench isolation technology is used to effectively block leakage current and parasitic capacitance effects by constructing isolation trenches with a depth of more than 15μm between domains with different threshold voltages, thereby avoiding electrical interference during inter-domain signal transmission. A Guard Ring protection structure is designed around each functional domain to form a barrier for surrounding protection, further reducing signal coupling and improving the chip's anti-interference ability in complex electromagnetic environments. Based on the multi-threshold domain physical isolation structure, a multi-threshold domain power distribution network is designed. The design of the power distribution network takes into account the independence of each threshold voltage domain, so an independent power rail is provided for each voltage domain. By adopting a distributed on-chip decoupling capacitor network, the power supply voltage fluctuation within each functional domain is minimized. In the design, at least a total of no less than 200pF of decoupling capacitors are arranged inside each functional domain. When the power supply voltage undergoes transient changes, these capacitors quickly provide or absorb charge to maintain the stability of the power supply voltage. In addition, in order to reduce the propagation of power noise between different domains, a power noise isolation structure is designed to make the coupling attenuation of power noise between domains reach at least 20dB. In order to improve the stability of the power supply, a low-impedance power distribution grid is designed. By optimizing the width and number of layers of metal wiring, the IR voltage drop of the power distribution network does not exceed 5% of the threshold voltage, thereby ensuring the reliable supply of power voltage to the chip under various working conditions. According to the multi-threshold domain power distribution network, a multi-threshold domain timing optimization structure containing four threshold voltage domains is established. In the design process, by establishing a unified timing model, the timing parameters of each threshold voltage domain are accurately modeled, and the dynamic frequency adjustment mechanism based on the critical path is used to enable the chip to automatically adjust the clock frequency within different operating voltages (from 0.3V to 1.2V) to maintain the correctness of the function. In order to solve the timing uncertainty problem of cross-domain signals, an asynchronous handshake mechanism is introduced. Through the dual latch structure, the mismatch of the clock domain is eliminated when the signal is transmitted between different voltage domains, thereby improving the reliability of cross-domain data transmission. Clock tree balancing technology is used to adjust the clock distribution network inside the chip. By precisely controlling the clock delay, the clock skew in four different threshold voltage domains is kept within 10ns, improving the accuracy of clock synchronization and effectively reducing the risk of timing violations. The multi-threshold domain timing optimization structure is optimized for power consumption to obtain a multi-threshold domain power consumption optimization system. In the process of power consumption optimization, the power consumption of the functional domain in the inactive state is reduced by introducing the dynamic shutdown technology of the functional domain based on activity detection. Fine-grained clock gating technology is introduced in the protocol processing domain to automatically shut down the clocks of some logic modules when there is no data processing task, thereby reducing dynamic power consumption.In addition, a progressive wake-up sequence is designed to control the transition time of the chip from deep sleep state to full-function working state within 100μs, effectively improving the response speed of the chip in low power mode. In order to reduce the power consumption of the protocol processor, a data-aware computing technology is designed to automatically adjust the working mode of the processor by dynamically analyzing the characteristics of the input data, so that the frequency and voltage of the processor are reduced when processing simple data, thereby reducing the overall power consumption. After completing the power consumption optimization, the entire multi-threshold voltage domain system is simulated and verified under full working conditions to obtain the multi-threshold system verification results. In the simulation verification, the voltage range from 0.3V to 1.2V and the temperature range from -20℃ to 85℃ are covered, and the robustness of the design under different process deviations is verified by Monte Carlo simulation analysis. And RF interference injection test is carried out to verify the anti-interference ability of the chip under input power of -3dBm to 10dBm. In the actual scenario test, the data consistency of the chip in the mobile scenario is verified by reading distance and data integrity evaluation. Based on the verification results of the multi-threshold system, the multi-threshold domain physical isolation structure, the multi-threshold domain power distribution network, the multi-threshold domain timing optimization structure and the multi-threshold domain power consumption optimization system are integrated to finally obtain the passive IoT tag chip design. During the integration process, the physical layout of each module is optimized to locate the inter-domain signal transmission buffer in the best position and shorten the transmission path as much as possible to reduce signal delay. At the same time, by designing independent power rails and isolation structures, it is ensured that the power supply noise between the functional domains will not affect each other. Compared with the traditional design, the completed passive IoT tag chip design has improved the reading distance, reduced the static power consumption, and maintained stable operation over the full temperature range. Under the same working conditions, the design can provide an additional data processing time window, significantly improving the chip's adaptability to application scenarios.

[0022] In the embodiment of the present application, the multi-threshold voltage logic design method of the present invention divides the chip into four functional domains and configures different threshold voltage transistors for each domain, so that the passive tag chip can work stably within an ultra-wide voltage range, breaking through the minimum operating voltage limit of the traditional single threshold design; by configuring ultra-low threshold transistors for the RF front-end domain to maximize the energy capture efficiency, combined with the threshold voltage dynamic adjustment system, the optimization of the reading distance and static power consumption is achieved; based on the design of the threshold voltage generator and the temperature compensation circuit, the passive tag maintains stable working characteristics within the full temperature range; by designing three types of cross-threshold domain signal transmission buffers, the signal integrity problem between different threshold domains is significantly improved; different threshold voltage domains are physically isolated to improve the anti-interference ability; the integrated RF energy detector and dynamic threshold switching mechanism can automatically switch the optimal threshold working mode according to the input energy in a very short time; combined with the functional domain dynamic shutdown technology based on activity detection and the progressive wake-up sequence, the energy utilization efficiency is greatly improved, and the problem of unstable performance of the traditional single threshold design in an energy fluctuation environment is solved.

[0023] In a specific embodiment, the process of executing step 100 may specifically include the following steps: The passive IoT tag chip is divided into multiple functional domains, including a radio frequency front-end domain, a clock control domain, a protocol processing domain, and a storage domain; Measure the energy capture efficiency of the RF front-end domain to obtain the energy capture efficiency curve of the RF front-end domain, and perform a stable oscillation test on the clock control domain to obtain the minimum voltage threshold data of the clock control domain; Perform a complete data frame processing test on the protocol processing domain to obtain a relationship diagram between the minimum operating voltage and power consumption of the protocol processing domain, and measure the static leakage current and data retention time of the storage domain at different voltage thresholds to obtain a leakage performance curve of the storage domain; According to the energy capture efficiency curve of the RF front-end domain, the minimum voltage threshold data of the clock control domain, the relationship diagram between the minimum operating voltage and power consumption of the protocol processing domain, and the leakage performance curve of the storage domain, the optimal threshold voltage of each functional domain is determined, and a corresponding table of functional domain threshold voltages is obtained; Based on the functional domain threshold voltage correspondence table, the signal transmission timing requirements, power consumption budget and noise tolerance between each functional domain are recorded, and the inter-domain interface specifications are formulated to obtain the functional domain threshold voltage parameter table.

[0024] Specifically, the design of the chip is planned, and the chip is divided into four main functional domains: RF front-end domain, clock control domain, protocol processing domain, and storage domain. Each functional domain has its own unique working requirements and performance requirements, so the threshold voltage of each domain needs to be analyzed and determined separately. The main task of the RF front-end domain is to capture RF energy from the external environment, so one of the key parameters of its design is the energy capture efficiency. During the design process, the energy capture efficiency of the RF front-end domain is measured, and the energy capture efficiency curve of the RF front-end domain is plotted. The energy capture efficiency indicates the percentage of effective energy that the RF front-end domain can capture from the external environment under different operating voltages. Assume that the energy capture efficiency of the RF front-end domain is ,in Indicates voltage, It is expressed as: in, is the power at a certain moment, and is the power provided by the power supply. The efficiency data under different voltages are obtained through experimental measurement, and the efficiency curve is drawn to analyze the voltage range in which the energy capture efficiency of the RF front-end domain is the highest, and then determine the optimal operating voltage of the RF front-end domain. In the design of the clock control domain, a stable oscillation test is performed to determine the minimum voltage threshold of the clock control domain. The function of the clock control domain is to provide a stable clock signal to ensure the synchronous operation of all parts in the chip. The stability of the clock circuit is affected by the operating voltage, so the stability of the clock oscillator under different voltage conditions is tested. During the test, the minimum voltage threshold of the clock control domain is obtained by measuring the operating frequency and frequency stability of the oscillator under different voltage conditions. Assume that the minimum voltage threshold of the clock control domain is , this value is measured experimentally, that is, when the voltage is lower than this, the oscillator cannot maintain a stable operating frequency. The value of is a key parameter in the design of clock control circuits. In the design of the protocol processing domain, data frame processing tests are performed to obtain the relationship between the minimum operating voltage and power consumption. The protocol processing domain is responsible for the communication protocol parsing and data processing tasks of the chip, and a reasonable voltage setting is crucial to its performance and power consumption. Assume that the minimum operating voltage of the protocol processing domain is At this voltage, the protocol processing domain can complete the processing of a data frame without errors. At the same time, the power consumption of the protocol processing domain is related to the operating voltage. The relationship between the voltage and the voltage is expressed by the following formula: in, is the capacitance, is the operating voltage, is the clock frequency. Through experiments, the relationship between the minimum operating voltage and power consumption is obtained, which helps to select the optimal operating voltage to reduce power consumption while ensuring data processing capabilities. The static leakage current and data retention time of the storage domain are measured at different voltage thresholds. Assume that the static current of the storage domain is , and its relationship with voltage is expressed by the following formula: in, is a constant, is the thermal voltage. By measuring the current at different voltages and drawing the current performance curve, the current change of the storage domain at different voltage thresholds can be obtained. The voltage of the storage domain also needs to ensure that the data is maintained for a certain period of time without power supply, that is, the data retention time. The data retention time is related to the voltage. The longest time that the data can be maintained at different voltages is determined by experiments, so as to select a balanced voltage value to ensure low power consumption while ensuring data stability. By analyzing the RF front-end domain, clock control domain, protocol processing domain and storage domain, the optimal threshold voltage of each functional domain is determined based on their energy capture efficiency curve, minimum voltage threshold data, minimum operating voltage and power consumption relationship diagram and current performance curve. After summarizing these data, a functional domain threshold voltage correspondence table is obtained to record the voltage requirements of each functional domain in the optimal working state. According to the functional domain threshold voltage correspondence table, the signal transmission timing requirements, power consumption budget and noise margin between each functional domain are recorded. The signal transmission timing requirements refer to the maximum transmission delay and minimum retention time requirements that the signal must meet when data is transmitted between different voltage domains. The power consumption budget is the upper limit setting of the power consumption of each functional domain to ensure that the entire system operates within the power consumption control range. The noise margin refers to the maximum noise level that each functional domain can tolerate, ensuring that signal transmission between different voltage domains is not interfered by noise. Based on these parameters, inter-domain interface specifications are formulated to ensure that signal transmission between different voltage domains can be stable and reliable, and the overall performance of the system will not be affected by voltage differences, timing mismatches or excessive power consumption.

[0025] In a specific embodiment, the process of executing step 200 may specifically include the following steps: According to the functional domain threshold voltage parameter table, transistor types are assigned to multiple functional domains to obtain a transistor type assignment scheme, and a multi-threshold transistor process parameter table is matched based on the transistor type assignment scheme; the RF front-end domain selects a first threshold transistor, the clock control domain selects a second threshold transistor, the protocol processing domain selects a third threshold transistor, and the storage domain selects a fourth threshold transistor; Generate various types of transistor structure schemes according to the multi-threshold transistor process parameter table, and design the multi-threshold transistor physical layout based on the various types of transistor structure schemes to obtain a transistor physical layout diagram; Using the transistor physical layout diagram to carry out multi-threshold transistor array integrated design, and obtain the integrated transistor array layout structure; Performing threshold voltage drift tests on various types of transistors in the integrated transistor array layout structure, recording threshold voltage drift curves, current driving capabilities, subthreshold swings, and response time data of various types of transistors, and obtaining a multi-threshold transistor configuration structure; By utilizing the multi-threshold transistor configuration structure, a corresponding multi-threshold voltage logic gate circuit is designed for each functional domain to obtain a multi-threshold logic gate circuit group.

[0026] Specifically, by analyzing the functional domain threshold voltage parameter table, the optimal operating voltage of each functional domain is obtained. For example, the RF front-end domain requires fast response at low voltage, and the first threshold transistor (ultra-low threshold transistor, referred to as ULVt) is selected. The clock control domain needs to provide a stable oscillation frequency. Under different temperature and environmental conditions, the low threshold transistor (referred to as LVt) provides better stability and power consumption balance. The protocol processing domain involves processing calculations with higher complexity, and the third threshold transistor (standard threshold transistor, referred to as SVt) is selected to balance performance and power consumption. The storage domain requires low static power consumption and guarantees data retention time. The selection of the fourth threshold transistor (high threshold transistor, referred to as HVt) helps to reduce leakage current and improve data stability. Match these types with the multi-threshold transistor process parameter table. The multi-threshold transistor process parameter table provides electrical performance parameters of different types of transistors under different working conditions, including threshold voltage, current drive capability, subthreshold swing, etc. The first threshold transistor selected by the RF front-end domain has a lower threshold voltage and a smaller subthreshold swing to ensure fast response and low power consumption. The second threshold transistor selected by the clock control domain has a higher current drive capability and better temperature stability. The third threshold transistor of the protocol processing domain has good anti-interference ability and moderate power consumption to balance processing performance and energy consumption. The fourth threshold transistor selected by the storage domain requires a higher threshold voltage to effectively control leakage current and work stably in low power mode. Based on the multi-threshold transistor process parameter table, the structural scheme of each type of transistor is generated. The structural design of the transistor must meet its working requirements. The ultra-low threshold transistor (ULVt) selected by the RF front-end domain is designed with a shorter channel length to improve the response speed and achieve better RF response. The low threshold transistor (LVt) of the clock control domain requires the optimization of the channel width-to-length ratio to balance power consumption and frequency stability. The standard threshold transistor (SVt) used in the protocol processing domain adopts an 8T transistor structure to enhance anti-interference ability and ensure the accuracy and stability of data processing. The high threshold transistor (HVt) of the storage domain adopts deep N-well isolation technology to effectively reduce static current and improve data retention. The physical layout design of the multi-threshold transistor is carried out based on the structural scheme of each type of transistor. Different types of transistors are reasonably arranged on the chip to ensure their isolation in physical space to reduce mutual interference. The ultra-low threshold transistors in the RF front-end domain and the high threshold transistors in the storage domain need to maintain a large physical isolation of no less than 15μm to avoid signal interference. The low threshold transistors in the clock control domain use a ring gate structure to reduce edge effects and improve the stability of the clock signal. The standard threshold transistors in the protocol processing domain use an island-shaped substrate bias structure to fine-tune the threshold voltage and optimize circuit performance. Through reasonable layout design, the signals in each functional domain can be effectively guaranteed to work stably at different voltages. After completing the physical layout of the transistors, the integrated design of the multi-threshold transistor array is carried out.Transistors with different voltage thresholds are efficiently integrated according to the design plan to ensure that they are interconnected and work together on the chip. By adopting differentiated process flows in different areas of the common wafer, transistors with different thresholds are physically isolated to avoid mutual interference and ensure correct signal transmission between different voltage domains. After the integrated design is completed, a multi-threshold transistor array layout structure is obtained. The threshold voltage drift test of the integrated transistor array layout structure helps evaluate the performance of the transistor under different environmental conditions such as temperature and process changes, ensuring that it maintains a stable working state in practical applications. Assume use. , , ,and Respectively represent the threshold voltages of transistors in the RF front-end domain, clock control domain, protocol processing domain, and storage domain. The threshold voltage drift curves of these transistors under different working conditions are obtained through testing. The current driving capability, subthreshold swing, and response time of the transistor are tested. Through these test data, the electrical performance of the transistor under different working conditions is obtained, and the configuration of the transistor is adjusted according to the test results to optimize the overall performance. Based on the multi-threshold transistor configuration structure, the corresponding multi-threshold voltage logic gate circuit is designed for each functional domain. The logic gate circuit of the RF front-end domain is designed as an ultra-low power transmission gate structure and can perform data demodulation at the lowest voltage. The logic gate circuit of the clock control domain is designed as a robust ring oscillator and a low-jitter clock distribution circuit to ensure the stability of the clock signal. The logic gate circuit of the protocol processing domain uses an efficient instruction processor and a state machine controller to ensure that the data processing task can be completed quickly at a lower working voltage. The logic gate circuit of the storage domain is designed as a low-leakage storage unit and a non-volatile register array to ensure that the data can be stably maintained at a lower voltage. Through these designs, a multi-threshold logic gate circuit group is finally obtained.

[0027] In a specific embodiment, the execution step utilizes a multi-threshold transistor configuration structure to design a corresponding multi-threshold voltage logic gate circuit for each functional domain, and the process of obtaining a multi-threshold logic gate circuit group may specifically include the following steps: Designing a first threshold logic gate circuit for the RF front-end domain according to the first threshold transistor parameters in the multi-threshold transistor configuration structure; designing a second threshold logic gate circuit for the clock control domain based on the second threshold transistor parameters in the multi-threshold transistor configuration structure; Designing a third threshold logic gate circuit for the protocol processing domain by using the third threshold transistor parameter in the multi-threshold transistor configuration structure; designing a fourth threshold logic gate circuit for the storage domain according to the fourth threshold transistor parameters in the multi-threshold transistor configuration structure; Performing circuit simulation verification on the first threshold logic gate circuit, the second threshold logic gate circuit, the third threshold logic gate circuit and the fourth threshold logic gate circuit to obtain a multi-threshold logic gate characteristic database; Based on the multi-threshold logic gate characteristic database, the logic gate circuits of each functional domain are interconnected and designed to obtain a multi-threshold logic gate circuit group.

[0028] Specifically, the logic gate circuit of the RF front-end domain is designed according to the parameters of the first threshold transistor selected by the RF front-end domain. The RF front-end domain needs to efficiently process RF signals at low voltages, and an ultra-low threshold transistor (referred to as transistor 1) is selected to meet this requirement. The logic gate circuit design of the RF front-end domain needs to target the lowest voltage consumption while ensuring the demodulation and transmission accuracy of the RF signal. Assume that the threshold voltage of the first threshold transistor is , the transistor has a smaller subthreshold swing and a higher response speed. In order to improve the processing capability of RF signals, the logic gate circuit adopts a transmission gate structure, which can reduce the number of transistor layers, thereby effectively reducing power consumption. In addition, the RF front-end circuit designs a low-power data demodulator, which works normally when the input signal is at the lowest voltage. Power consumption of RF front-end circuit It is usually proportional to the square of the voltage and is expressed by the following formula: in, is the capacitance, is the threshold voltage of the first threshold transistor, is the operating frequency. By optimizing the circuit structure, it is ensured that the circuit can maintain stable performance at low voltage. Based on the parameters of the second threshold transistor, the logic gate circuit of the clock control domain is designed. The task of the clock control domain is to provide a stable clock signal for the entire system, so its design needs to ensure a balance between the stability of the clock frequency and low power consumption. Selecting a low threshold transistor (transistor 2) helps to reduce power consumption while ensuring the stability of the oscillator. In the clock control domain, a ring oscillator structure is used, which can provide a stable oscillation frequency at a lower voltage. Assume that the threshold voltage of the second threshold transistor is , its current driving capability and power consumption are expressed by the following formula: in, is the capacitance, is the threshold voltage of the second threshold transistor, is the clock frequency. By properly designing the clock distribution circuit, the clock control domain can operate at a lower voltage while maintaining good frequency stability. In the design of the protocol processing domain, the logic gate circuit of the protocol processing domain is designed based on the parameters of the third threshold transistor. The task of the protocol processing domain is to process and parse the received data, so it requires efficient computing power and data processing performance. The standard threshold transistor (transistor 3) is suitable for this high performance requirement and can control power consumption while providing high processing speed. Assume that the threshold voltage of the third threshold transistor is , its current driving capability and power consumption are expressed by the following formula: in, is the capacitance, is the threshold voltage of the third threshold transistor, The protocol processing circuit includes an 8-bit instruction processor and a state machine controller, which can process complex protocol data while operating efficiently. By optimizing the design of the circuit, the power consumption and performance of the protocol processing domain are balanced, especially the data can be processed stably at a lower voltage. In the design of the storage domain, the logic gate circuit of the storage domain is designed based on the parameters of the fourth threshold transistor. The storage domain requires lower power consumption and long-term data retention capability, so a high threshold transistor (transistor 4) is selected to effectively reduce the current and ensure stable storage of data. Assume that the threshold voltage of the fourth threshold transistor is , its current is expressed by the following formula: in, is a constant, is the thermal voltage. The storage domain circuit adopts an 8T storage unit design. By optimizing the threshold voltage of the circuit, the static power consumption is kept at a low level, while ensuring that the data can be retained for a long time when the power is off. In addition, the storage domain is designed with a register array with independent read and write ports to ensure efficient data access. Circuit simulation verification is performed on the first threshold logic gate circuit, the second threshold logic gate circuit, the third threshold logic gate circuit, and the fourth threshold logic gate circuit. Through simulation, the performance indicators such as timing, power consumption, and noise tolerance of the first, second, third, and fourth threshold logic gate circuits are verified. During the simulation process, key data such as the propagation delay, power consumption, and noise tolerance of each logic gate are recorded to form a multi-threshold logic gate characteristic database. Assume that the delay obtained by simulation is , the power consumption is , the noise tolerance is , these data are used to further optimize each circuit. Through these simulation results, potential timing problems, excessive power consumption or noise sensitivity problems are identified and solved, thereby ensuring the stability and efficiency of logic gate circuits in practical applications. Based on the multi-threshold logic gate characteristic database, the logic gate circuits of each functional domain are interconnected to form a complete multi-threshold logic gate circuit group. In the interconnection design, the connection and signal transmission path of the logic gate are reasonably arranged according to the timing requirements, power consumption limitations and noise tolerance of each circuit. Through reasonable layout and timing optimization, it is ensured that the signals between different functional domains can be transmitted stably, and the delay and power consumption are minimized. Through the interconnection design, a multi-threshold logic gate circuit group is obtained.

[0029] In a specific embodiment, the process of executing step 300 may specifically include the following steps: Designing a threshold voltage monitoring circuit using a first threshold logic gate circuit in a multi-threshold logic gate circuit group, and designing a threshold voltage generator circuit based on a second threshold logic gate circuit in the multi-threshold logic gate circuit group; According to the output data of the threshold voltage monitoring circuit, a dynamic threshold switching decision circuit is designed, and based on the threshold voltage generator circuit and the dynamic threshold switching decision circuit, a threshold switching execution circuit is designed; Interconnecting and integrating the threshold voltage monitoring circuit, the threshold voltage generator circuit, the dynamic threshold switching decision circuit and the threshold switching execution circuit to construct a threshold voltage dynamic control system circuit; The threshold voltage dynamic control system circuit is functionally verified to obtain the threshold voltage dynamic adjustment system; A threshold voltage dynamic adjustment system is adopted to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network.

[0030] Specifically, an efficient threshold voltage monitoring circuit is designed using the first threshold logic gate circuit in the multi-threshold logic gate circuit. The main function of the threshold voltage monitoring circuit is to detect the voltage changes of different functional domains in the chip in real time, especially in the low-voltage and low-power RF front-end domain. The circuit realizes dynamic monitoring of each voltage domain through a high-precision voltage sampling module, a fast-response comparator, and a stable bias circuit. When designing a threshold voltage monitoring circuit, the first threshold logic gate circuit is used to construct a voltage comparator, which compares the current voltage and a preset threshold voltage , output a voltage status signal , indicating whether the current voltage is within the safe range: in, is the voltage monitored in real time, is the set threshold of the first threshold logic gate circuit. When , it indicates that the voltage is normal; when When the system needs to adjust the voltage to ensure stability. Based on the second threshold logic gate circuit in the multi-threshold logic gate circuit, a threshold voltage generator circuit is designed. The function of the threshold voltage generator is to provide dynamically adjustable threshold voltages for different functional domains. By designing a bandgap reference source with multiple voltage outputs and combining it with the precision voltage divider circuit in the second threshold logic gate circuit, multiple stable threshold voltages are generated. , and These voltages are switched by the selector to meet the needs of different functional domains in different working states. For example, an adjustable voltage source is designed by using a resistor divider and an operational amplifier. It is expressed as: in, is the reference voltage, and is a voltage divider resistor, which can be adjusted by and ratio, dynamically adjust the output voltage To meet different threshold requirements. According to the output data of the threshold voltage monitoring circuit, a dynamic threshold switching decision circuit is designed. The decision circuit quickly decides whether the threshold voltage needs to be switched based on the real-time voltage data and the state of the functional domain. The decision circuit analyzes the voltage state signal output by the monitoring circuit through the logic judgment module and the priority encoder. , and decides the voltage switching strategy according to the priority of different functional domains. When the voltage is too low, the dynamic threshold switching decision circuit outputs a switching signal , triggering the threshold switching execution circuit. The threshold switching execution circuit realizes smooth voltage switching by combining with the threshold voltage generator circuit and the dynamic threshold switching decision circuit. The execution circuit dynamically switches the voltage source through the multi-way switch selector to ensure that the system always maintains the optimal voltage state in different working modes. The smooth transition during the voltage switching process is achieved through the charge spring and capacitor filter to avoid circuit instability caused by voltage mutation. Assume that the voltage before switching is , the target voltage after switching is , the voltage change during switching It is expressed by the exponential decay formula: in, is the time constant, which controls the switching speed by matching the capacitor and resistor to ensure the voltage transition time Within the range allowed by the system. The threshold voltage monitoring circuit, threshold voltage generator circuit, dynamic threshold switching decision circuit and threshold switching execution circuit are interconnected and integrated to construct a threshold voltage dynamic control system circuit. In the interconnection design, by arranging independent power rails and signal lines, accurate control signal transmission between modules is realized to ensure the rapid response and stable operation of the dynamic adjustment system. In order to verify the function of the system, simulation tests are carried out, including voltage regulation response speed, stability test, safety test under extreme working conditions, etc. In the simulation, the characteristic data of the threshold voltage dynamic adjustment system is obtained by measuring the transition time, maximum voltage deviation and time for the circuit to return to a stable state during the voltage dynamic switching process. Based on the threshold voltage dynamic adjustment system, a cross-threshold domain signal transmission buffer is designed to form an inter-domain signal transmission network. Since different functional domains work at different voltage thresholds, level conversion, signal enhancement and timing correction are required when signals are transmitted between different voltage domains. By designing a buffer circuit with dynamic bias control, the voltage level of the signal is effectively adjusted so that the signal remains stable during cross-domain transmission. For example, in the signal transmission from the low voltage domain to the high voltage domain, the buffer gradually increases the signal level through a multi-stage amplifier to avoid signal distortion. During the transmission process from the high voltage domain to the low voltage domain, the pull-down level conversion circuit is used to achieve precise control of the signal level, ensuring the integrity of the cross-domain signal and the accuracy of the timing.

[0031] In a specific embodiment, the execution step adopts a threshold voltage dynamic adjustment system, designs a cross-threshold domain signal transmission buffer, and forms an inter-domain signal transmission network, which may specifically include the following steps: By using the threshold voltage dynamic adjustment system, the signal transmission characteristics between different threshold voltage domains are analyzed to obtain the inter-domain signal characteristic data; According to the inter-domain signal characteristic data, a level conversion circuit, an input stage with a Schmitt trigger and a dynamic bias control are designed to construct a second threshold to fourth threshold domain transmission buffer to obtain a low-high domain transmission buffer; Based on the inter-domain signal characteristic data, a pull-down level conversion circuit, a current limiting protection circuit and an output driver with threshold compensation are designed to construct a fourth threshold to second threshold domain transmission buffer to obtain a high-low domain transmission buffer; According to the structure of low-high domain transmission buffer and high-low domain transmission buffer, a progressive threshold conversion circuit, an on-chip transmission line matching circuit and a variable gain output stage are designed to construct a multi-level domain transmission buffer; Based on multi-level domain transmission buffers, differential signal transmission circuits, low swing signal transmission technology and clock data recovery circuits are designed to build high-speed inter-domain buses; The low-high domain transmission buffer, the high-low domain transmission buffer, the multi-level domain transmission buffer and the high-speed inter-domain bus are arranged at the boundaries of each functional domain, and the inter-domain communication network is interconnected to obtain the inter-domain signal transmission network.

[0032] Specifically, the threshold voltage dynamic adjustment system is used to analyze the characteristics of signal transmission between different threshold voltage domains to obtain inter-domain signal characteristic data, including signal rise and fall time, transmission delay, signal amplitude attenuation, noise margin, and stability of cross-domain voltage conversion. When performing characteristic analysis, the monitoring circuit in the dynamic adjustment system collects waveform data and timing information of the signal when it is transmitted between different voltage domains in real time, such as voltage and The signal level conversion process between It is expressed by the formula: in, is the load capacitance, and are the second and fourth threshold voltages respectively, is the driving current. By collecting these signal characteristic data, the dynamic characteristics of signal transmission between different voltage domains can be understood. Based on the inter-domain signal characteristic data, a low-to-high domain transmission buffer from the second threshold to the fourth threshold domain is designed to achieve stable conversion of lower voltage signals to higher voltage signals. When designing the low-to-high domain transmission buffer, a level conversion circuit, an input stage with a Schmitt trigger, and a dynamic bias control module are used to ensure a smooth transition of the signal between different voltage domains. The level conversion circuit uses a multi-stage amplifier to gradually increase the signal voltage, while the Schmitt trigger provides a hysteresis characteristic to effectively filter noise signals and prevent signal jitter during the voltage conversion process. Assume that the input voltage is , the output voltage is , the output voltage of the Schmitt trigger is expressed as: in, and They are the high and low voltage threshold values ​​of the Schmitt trigger respectively. The dynamic bias control module ensures that the circuit can provide a stable output voltage under different load conditions by automatically adjusting the gate voltage of the transistor. At the same time, based on the inter-domain signal characteristic data, a high-low domain transmission buffer from the fourth threshold to the second threshold domain is designed to achieve safe conversion of high voltage signals to low voltage signals. In this design, a pull-down level conversion circuit, a current limiting protection circuit, and an output driver module with threshold compensation are used to ensure the safety and stability of the signal during the high voltage to low voltage conversion process. The pull-down level conversion circuit controls the pull-down current and load capacitance The relationship between can realize precise control of signal level, and its voltage conversion rate is expressed as: in, is a pull-down resistor, is the load capacitance in the circuit, is the input voltage. During the conversion process, the current limiting protection circuit introduces a current limiting resistor into the circuit. , the transient current Control within a safe range: Effectively protect the circuit components in the low threshold domain from being damaged by high voltage shocks. Construct a multi-domain transmission buffer based on the low-high domain and high-low domain transmission buffers to achieve smooth conversion of signals between multiple threshold voltage domains. The multi-domain transmission buffer uses a progressive threshold conversion circuit, an on-chip transmission line matching circuit, and a variable gain output stage to gradually increase or decrease the signal from the lowest voltage to the highest voltage. When designing a progressive threshold conversion circuit, a multi-stage capacitor divider and amplifier cascade structure are used to ensure that the signal remains stable at each stage of conversion and prevent voltage overshoot or undershoot. The transmission line matching circuit accurately matches the impedance of the transmission line. and the output impedance of the drive circuit Ensure the reflection coefficient of the signal during transmission Minimum: The variable gain output stage automatically adjusts the gain of the output signal according to the signal transmission distance and load changes through the feedback circuit. , ensuring that the signal maintains high signal quality during long-distance transmission. Based on the multi-level domain transmission buffer, a high-speed domain bus is designed to ensure high-speed data transmission between the functional domains in the chip. The high-speed domain bus achieves low signal latency and high anti-interference capability through differential signal transmission circuits, low swing signal transmission technology, and clock data recovery circuits. Differential signal transmission technology eliminates common mode noise by transmitting positive and negative signals on the bus at the same time, and differential voltage It is expressed as: in, and are the voltages of the positive and negative signal lines respectively. Low-swing signal transmission technology reduces power consumption during signal transmission by controlling the signal swing within a smaller range. The clock data recovery circuit uses a phase-locked loop circuit to track the clock information in the data stream in real time, so that the receiving end can accurately identify the data bit. The low-high domain transmission buffer, high-low domain transmission buffer, multi-level domain transmission buffer and high-speed inter-domain bus are rationally arranged at the boundaries of each functional domain to form an inter-domain signal transmission network. During the layout process, the circuit wiring design is used to ensure that the signal transmission path between modules is the shortest and the timing control is optimal.

[0033] In a specific embodiment, the process of executing step 400 may specifically include the following steps: Perform physical isolation layout design on the inter-domain signal transmission network and the multi-threshold logic gate circuit group to obtain a multi-threshold domain physical isolation structure; Based on the multi-threshold domain physical isolation structure, a multi-threshold domain power distribution network is designed, and based on the multi-threshold domain power distribution network, a multi-threshold domain timing optimization structure containing four threshold voltage domains is established; The power consumption of the multi-threshold domain timing optimization structure is optimized to obtain a multi-threshold domain power consumption optimization system; Based on the multi-threshold domain power consumption optimization system, perform multi-threshold voltage domain full working condition simulation verification to obtain multi-threshold system verification results; According to the verification results of the multi-threshold system, the multi-threshold domain physical isolation structure, multi-threshold domain power distribution network, multi-threshold domain timing optimization structure and multi-threshold domain power consumption optimization system are integrated to obtain the design scheme of passive IoT tag chip.

[0034] Specifically, the inter-domain signal transmission network and multi-threshold logic gate circuit group are physically isolated and designed to obtain a multi-threshold domain physical isolation structure to minimize signal interference between domains with different threshold voltages. In the layout design, effective electrical isolation is established between different functional domains by using deep trench isolation technology and metal shielding layers. For example, a deep isolation of 1000nm is designed between the RF front-end domain and the storage domain. The depth of the isolation groove and width The following relationship needs to be satisfied: in, is the isolation coefficient, verified by experiments. After physical isolation is achieved, a multi-threshold domain power distribution network is designed to ensure stable power supply between different voltage domains. In the design, independent power rails are used to provide a stable voltage source for each threshold voltage domain. to , by placing decoupling capacitors in the power rails to , eliminate power supply noise and maintain the stability of the power supply voltage. The impedance of the power distribution network Controlled in a lower range to ensure that the power supply voltage fluctuates less when the load changes Keeping within the allowable range, the relationship between power supply fluctuation and impedance is expressed as: in, is the load current, The impedance of the power distribution network. By designing a multi-layer power distribution network structure, the impedance of the power rail is effectively reduced and the stability of the power supply is improved. Based on the multi-threshold domain power distribution network, a multi-threshold domain timing optimization structure containing four threshold voltage domains is established. In the timing optimization design, the main task is to ensure that the signal transmission delay between different voltage domains is minimized and timing violations are avoided. During the signal transmission process, there is a phase difference between the clock signals in different voltage domains. , which will cause timing deviation The timing skew is calculated using the following formula: in, is the clock frequency. By designing clock buffers and delay compensation circuits, the clock phase difference can be effectively eliminated and the synchronization of clock signals in various voltage domains can be maintained. In addition, the introduction of cross-domain synchronizers in the timing optimization structure can automatically adjust the timing of the signal when the signal is transmitted from one voltage domain to another, so that the signals between different domains can be transmitted seamlessly. The power consumption of the multi-threshold domain timing optimization structure is optimized to obtain a multi-threshold domain power consumption optimization system. The power consumption of non-essential logic gate circuits is reduced through dynamic voltage adjustment and clock gating technology. In dynamic voltage adjustment, different operating voltages are used in different functional domains, such as lowering the voltage of the storage domain to , while the voltage of the protocol processing domain is maintained at , significantly reducing the overall power consumption of the chip. It is mainly composed of dynamic power consumption and static power consumption, and its expression is expressed as: in, is the dynamic power consumption, is the static power consumption, is the total capacitance, is the operating voltage, is the clock frequency, is the quiescent current. and value, effectively reducing dynamic power consumption and reducing static current by using high threshold transistors , it can significantly reduce static power consumption. In order to verify the effectiveness of the multi-threshold domain power consumption optimization system, multi-threshold voltage domain simulation verification is performed under all working conditions to obtain multi-threshold system verification results. During the simulation process, all working conditions from low temperature to high temperature (for example, -20°C to 85°C) and from low voltage to high voltage (for example, 0.3V to 1.2V) are covered to evaluate the stability and power consumption performance of the chip in different environments. In the simulation verification, attention is paid to the power supply fluctuations, signal delays and data stability of the chip under extreme conditions, such as by measuring the voltage change rate. and timing delay , and verify whether the chip can maintain stable operation under all conditions. According to the verification results of the multi-threshold system, the multi-threshold domain physical isolation structure, the multi-threshold domain power distribution network, the multi-threshold domain timing optimization structure and the multi-threshold domain power consumption optimization system are integrated to obtain the passive IoT tag chip design scheme. In the integration process, the signal transmission path between domains is made shortest by rationally arranging different functional domains to reduce signal delay. At the same time, by introducing a dynamic adjustment module in the physical isolation structure, the strength of physical isolation is adjusted according to the actual working conditions to adapt to different electromagnetic environments. In the power distribution network, by introducing an intelligent power management module, the power distribution of each voltage domain is automatically adjusted according to the real-time load of the chip to improve the energy efficiency of the chip. In the timing optimization structure, by adjusting the distribution of the clock tree and the delay of the buffer, the clock signal is synchronized in all voltage domains, thereby avoiding data errors caused by clock phase errors. The final passive IoT tag chip design scheme achieves efficient power management, stable signal transmission and excellent timing performance through a multi-threshold voltage logic design method.

[0035] The above describes the multi-threshold voltage logic design method of the passive IoT tag chip in the embodiment of the present application. The following describes the multi-threshold voltage logic design system 10 of the passive IoT tag chip in the embodiment of the present application. Figure 2 In one embodiment of the present application, a multi-threshold voltage logic design system 10 for a passive IoT tag chip includes: The analysis module 11 is used to divide the passive IoT tag chip into multiple functional domains, and perform threshold voltage requirement analysis on each functional domain to obtain a functional domain threshold voltage parameter table; A configuration module 12, configured to configure a multi-threshold transistor configuration structure for each functional domain according to the functional domain threshold voltage parameter table, and to design a multi-threshold logic gate circuit group for each functional domain using the multi-threshold transistor configuration structure; A construction module 13 is used to construct a threshold voltage dynamic adjustment system based on a multi-threshold logic gate circuit group, and adopt the threshold voltage dynamic adjustment system to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network; The optimization module 14 is used to integrate the inter-domain signal transmission network with the multi-threshold logic gate circuit group, and perform physical isolation layout and optimization to obtain a passive IoT tag chip design solution.

[0036] Through the collaborative cooperation of the above-mentioned components, the multi-threshold voltage logic design method of the present invention divides the chip into four functional domains and configures different threshold voltage transistors for each domain, so that the passive tag chip can work stably within an ultra-wide voltage range, breaking through the minimum operating voltage limit of the traditional single-threshold design; by configuring ultra-low threshold transistors for the RF front-end domain to maximize the energy capture efficiency, combined with the threshold voltage dynamic adjustment system, the optimization of the reading distance and static power consumption is achieved; based on the design of the threshold voltage generator and the temperature compensation circuit, the passive tag maintains stable working characteristics within the full temperature range; by designing three types of cross-threshold domain signal transmission buffers, the signal integrity problem between different threshold domains is significantly improved; different threshold voltage domains are physically isolated to improve the anti-interference ability; the integrated RF energy detector and dynamic threshold switching mechanism can automatically switch the optimal threshold working mode according to the input energy in a very short time; combined with the functional domain dynamic shutdown technology based on activity detection and the progressive wake-up sequence, the energy utilization efficiency is greatly improved, and the problem of unstable performance of the traditional single threshold design in an energy fluctuation environment is solved.

[0037] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0038] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable an electronic device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0039] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A multi-threshold voltage logic design method for a passive IoT tag chip, characterized in that: The method comprises: The passive IoT tag chip is divided into multiple functional domains, and the threshold voltage requirement analysis is performed on each functional domain to obtain a functional domain threshold voltage parameter table; According to the functional domain threshold voltage parameter table, configuring a multi-threshold transistor configuration structure for each functional domain, and using the multi-threshold transistor configuration structure to design a multi-threshold logic gate circuit group for each functional domain; Based on the multi-threshold logic gate circuit group, a threshold voltage dynamic adjustment system is constructed, and the threshold voltage dynamic adjustment system is used to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network; The inter-domain signal transmission network is integrated with the multi-threshold logic gate circuit group, and physically isolated layout and optimization are performed to obtain a passive IoT tag chip design solution.

2. The multi-threshold voltage logic design method of the passive IoT tag chip according to claim 1 is characterized in that: The passive IoT tag chip is divided into multiple functional domains, and the threshold voltage requirement analysis is performed on each functional domain to obtain a functional domain threshold voltage parameter table, including: Divide the passive IoT tag chip into multiple functional domains, including a radio frequency front-end domain, a clock control domain, a protocol processing domain, and a storage domain; Performing energy capture efficiency measurement on the RF front-end domain to obtain an energy capture efficiency curve of the RF front-end domain, and performing a stable oscillation test on the clock control domain to obtain minimum voltage threshold data of the clock control domain; Performing a complete data frame processing test on the protocol processing domain to obtain a relationship diagram between the minimum operating voltage and power consumption of the protocol processing domain, and measuring the static leakage current and data retention time of the storage domain at different voltage thresholds to obtain a storage domain leakage performance curve; According to the energy capture efficiency curve of the RF front-end domain, the minimum voltage threshold data of the clock control domain, the relationship diagram between the minimum operating voltage and power consumption of the protocol processing domain, and the leakage performance curve of the storage domain, the optimal threshold voltage of each functional domain is determined to obtain a functional domain threshold voltage correspondence table; Based on the functional domain threshold voltage correspondence table, the signal transmission timing requirements, power consumption budget and noise tolerance between the functional domains are recorded, and the inter-domain interface specifications are formulated to obtain the functional domain threshold voltage parameter table.

3. The multi-threshold voltage logic design method of the passive IoT tag chip according to claim 2 is characterized in that: The method of configuring a multi-threshold transistor configuration structure for each functional domain according to the functional domain threshold voltage parameter table, and using the multi-threshold transistor configuration structure to design a multi-threshold logic gate circuit group for each functional domain includes: According to the functional domain threshold voltage parameter table, transistor types are assigned to the multiple functional domains to obtain a transistor type assignment scheme, and a multi-threshold transistor process parameter table is matched based on the transistor type assignment scheme; the RF front-end domain selects a first threshold transistor, the clock control domain selects a second threshold transistor, the protocol processing domain selects a third threshold transistor, and the storage domain selects a fourth threshold transistor; Generating various types of transistor structure schemes according to the multi-threshold transistor process parameter table, and designing a multi-threshold transistor physical layout based on the various types of transistor structure schemes to obtain a transistor physical layout diagram; Using the transistor physical layout diagram to perform multi-threshold transistor array integrated design to obtain an integrated transistor array layout structure; Performing a threshold voltage drift test on each type of transistor in the integrated transistor array layout structure, recording the threshold voltage drift curve, current driving capability, subthreshold swing and response time data of each type of transistor, and obtaining a multi-threshold transistor configuration structure; By utilizing the multi-threshold transistor configuration structure, a corresponding multi-threshold voltage logic gate circuit is designed for each functional domain to obtain a multi-threshold logic gate circuit group.

4. The multi-threshold voltage logic design method of the passive IoT tag chip according to claim 3 is characterized in that: The multi-threshold transistor configuration structure is used to design a corresponding multi-threshold voltage logic gate circuit for each functional domain to obtain a multi-threshold logic gate circuit group, including: Designing a first threshold logic gate circuit for the RF front-end domain according to the first threshold transistor parameter in the multi-threshold transistor configuration structure; designing a second threshold logic gate circuit for the clock control domain based on the second threshold transistor parameters in the multi-threshold transistor configuration structure; Designing a third threshold logic gate circuit for the protocol processing domain using the third threshold transistor parameter in the multi-threshold transistor configuration structure; designing a fourth threshold logic gate circuit for the storage domain according to a fourth threshold transistor parameter in the multi-threshold transistor configuration structure; Performing circuit simulation verification on the first threshold logic gate circuit, the second threshold logic gate circuit, the third threshold logic gate circuit, and the fourth threshold logic gate circuit to obtain a multi-threshold logic gate characteristic database; Based on the multi-threshold logic gate characteristic database, the logic gate circuits of each functional domain are interconnected and designed to obtain a multi-threshold logic gate circuit group.

5. The multi-threshold voltage logic design method for a passive IoT tag chip according to claim 4, characterized in that: The method comprises: constructing a threshold voltage dynamic adjustment system based on the multi-threshold logic gate circuit group, and using the threshold voltage dynamic adjustment system to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network, including: Designing a threshold voltage monitoring circuit using a first threshold logic gate circuit in the multi-threshold logic gate circuit group, and designing a threshold voltage generator circuit based on a second threshold logic gate circuit in the multi-threshold logic gate circuit group; According to the output data of the threshold voltage monitoring circuit, a dynamic threshold switching decision circuit is designed, and based on the threshold voltage generator circuit and the dynamic threshold switching decision circuit, a threshold switching execution circuit is designed; The threshold voltage monitoring circuit, the threshold voltage generator circuit, the dynamic threshold switching decision circuit and the threshold switching execution circuit are interconnected and integrated to construct a threshold voltage dynamic control system circuit; Performing functional verification on the threshold voltage dynamic control system circuit to obtain a threshold voltage dynamic adjustment system; The threshold voltage dynamic adjustment system is adopted to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network.

6. The multi-threshold voltage logic design method for a passive IoT tag chip according to claim 5, characterized in that: The threshold voltage dynamic adjustment system is used to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network, including: Using the threshold voltage dynamic adjustment system, characteristic analysis is performed on signal transmission between different threshold voltage domains to obtain inter-domain signal characteristic data; According to the inter-domain signal characteristic data, a level conversion circuit, an input stage with a Schmitt trigger and a dynamic bias control are designed to construct a second threshold to fourth threshold domain transmission buffer to obtain a low-high domain transmission buffer; Based on the inter-domain signal characteristic data, a pull-down level conversion circuit, a current limiting protection circuit and an output driver with threshold compensation are designed to construct a fourth threshold to second threshold domain transmission buffer to obtain a high-low domain transmission buffer; According to the structures of the low-high domain transmission buffer and the high-low domain transmission buffer, a progressive threshold conversion circuit, an on-chip transmission line matching circuit and a variable gain output stage are designed to construct a multi-stage domain transmission buffer; Based on the multi-level domain transmission buffer, a differential signal transmission circuit, a low swing signal transmission technology and a clock data recovery circuit are designed to construct a high-speed inter-domain bus; The low-high domain transmission buffer, the high-low domain transmission buffer, the multi-level domain transmission buffer and the high-speed inter-domain bus are arranged at the boundaries of each functional domain, and the inter-domain communication network is interconnected to obtain an inter-domain signal transmission network.

7. The multi-threshold voltage logic design method for a passive IoT tag chip according to claim 1, characterized in that: The inter-domain signal transmission network is integrated with the multi-threshold logic gate circuit group, and physically isolated and laid out and optimized to obtain a passive IoT tag chip design solution, including: Performing physical isolation layout design on the inter-domain signal transmission network and the multi-threshold logic gate circuit group to obtain a multi-threshold domain physical isolation structure; Based on the multi-threshold domain physical isolation structure, a multi-threshold domain power distribution network is designed, and according to the multi-threshold domain power distribution network, a multi-threshold domain timing optimization structure including four threshold voltage domains is established; Performing power consumption optimization on the multi-threshold domain timing optimization structure to obtain a multi-threshold domain power consumption optimization system; Based on the multi-threshold domain power consumption optimization system, perform multi-threshold voltage domain full working condition simulation verification to obtain a multi-threshold system verification result; According to the verification results of the multi-threshold system, the multi-threshold domain physical isolation structure, the multi-threshold domain power distribution network, the multi-threshold domain timing optimization structure and the multi-threshold domain power consumption optimization system are integrated to obtain a passive IoT tag chip design solution.

8. A multi-threshold voltage logic design system for a passive IoT tag chip, characterized in that: A method for designing a multi-threshold voltage logic of a passive IoT tag chip according to any one of claims 1 to 7, wherein the multi-threshold voltage logic design system of the passive IoT tag chip comprises: An analysis module is used to divide the passive IoT tag chip into multiple functional domains, and perform threshold voltage requirement analysis on each functional domain to obtain a functional domain threshold voltage parameter table; A configuration module, configured to configure a multi-threshold transistor configuration structure for each functional domain according to the functional domain threshold voltage parameter table, and to design a multi-threshold logic gate circuit group for each functional domain using the multi-threshold transistor configuration structure; A construction module is used to construct a threshold voltage dynamic adjustment system based on the multi-threshold logic gate circuit group, and adopt the threshold voltage dynamic adjustment system to design a cross-threshold domain signal transmission buffer to form an inter-domain signal transmission network; The optimization module is used to integrate the inter-domain signal transmission network with the multi-threshold logic gate circuit group, and perform physical isolation layout and optimization to obtain a passive IoT tag chip design solution.

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