Photoelectric co-packaging device and preparation method thereof

Abstract

The invention discloses a photoelectric co-packaging device and a preparation method thereof, the photoelectric co-packaging device comprises a reverse mold packaging module, the reverse mold packaging module comprises a reverse mold packaging material, and at least one optical chip and at least one electric chip packaged in the reverse mold packaging material, the front surface of the at least one optical chip and the front surface of the at least one electric chip are both located on the first surface of the reverse mold packaging material; wherein a first wire is further formed on the first surface of the reverse mold packaging material, and the first wire is used for connecting the optical chip and the electric chip. According to the technical scheme provided by the invention, the problem of interface connection between chips in a photoelectric co-packaging technology is solved, so that the integrity and reliability of signal transmission are ensured.

Description

Technical Field

[0001] The present application belongs to the field of optoelectronic co-packaging technology, and in particular, relates to an optoelectronic co-packaging device and a preparation method thereof. Background Art

[0002] With the rapid development of cloud computing, big data, artificial intelligence and other applications, the demand for high-speed, high-bandwidth, and low-power optical communications is increasing, requiring smaller package sizes and higher integration density. In order to improve the performance of electrical chips and reduce power consumption, packaging technology needs to support high-speed electrical signal transmission and have an effective heat dissipation mechanism. Traditional pluggable optical modules face limitations in bandwidth, latency, energy efficiency, and speed. The new optoelectronic co-packaging (Co-Packaged Optics, CPO) technology has emerged. This technology not only shortens the conversion path between optical and electrical signals, but also significantly improves the data transmission rate and energy efficiency. By stacking multiple chips or devices, it can achieve higher integration and performance.

[0003] In CPO technology, how to solve the interface connection problem between chips to ensure the integrity and reliability of signal transmission is the main problem that needs to be solved. Summary of the invention

[0004] The present application provides an optoelectronic co-packaging device and a preparation method thereof, aiming to solve the interface connection problem between chips in optoelectronic co-packaging technology to ensure the integrity and reliability of signal transmission.

[0005] In a first aspect, an embodiment of the present application provides an optoelectronic co-packaged device, the optoelectronic co-packaged device comprising a reverse mold packaging module, the reverse mold packaging module comprising a reverse mold packaging material, and at least one optical chip and at least one electrical chip packaged in the reverse mold packaging material, the front surface of the at least one optical chip and the front surface of the at least one electrical chip are both located on the first surface of the reverse mold packaging material;

[0006] A first wiring is also formed on the first surface of the above-mentioned reverse-mold packaging material, and the above-mentioned first wiring is used to connect the above-mentioned optical chip and the above-mentioned electrical chip.

[0007] In some embodiments, the number of the optical chips is at least two, and a second wiring is further formed on the first surface of the reverse-mold packaging material, and the second wiring is used to connect different optical chips.

[0008] In some embodiments, the first routing line is a planar printed metal routing line, and / or the second routing line is a printed waveguide line.

[0009] In some embodiments, a thin film circuit is disposed on the back side of at least one of the optical chips, and the thin film circuit is formed on a heat dissipation substrate.

[0010] In some embodiments, the optoelectronic co-packaged device further comprises:

[0011] The refrigeration module is encapsulated in the above-mentioned reverse-molding encapsulation material and is in direct contact with the above-mentioned heat dissipation substrate.

[0012] In some embodiments, the inverted mold packaging material also forms a through hole that passes through the first surface and the second surface, and a third trace electrically connected to the at least one optical chip and / or the at least one electrical chip is arranged in the through hole, and the second surface is arranged opposite to the first surface.

[0013] In some embodiments, the optoelectronic packaging device further includes:

[0014] The circuit board is arranged on the second surface of the above-mentioned reverse-mold packaging material and is electrically connected to the above-mentioned third trace.

[0015] In some embodiments, a groove is formed in the above-mentioned reverse-mold packaging material and located on the light-emitting side of at least one of the above-mentioned optical chips, and the above-mentioned groove is used to accommodate the optical fiber.

[0016] In a second aspect, the present application also provides a method for preparing an optoelectronic co-packaged device, comprising:

[0017] Forming a reverse mold packaging module, the reverse mold packaging module comprising a reverse mold packaging material, and at least one optical chip and at least one electrical chip encapsulated in the reverse mold packaging material, wherein the front surface of the at least one optical chip and the front surface of the at least one electrical chip are both located on the first surface of the reverse mold packaging material;

[0018] A first wiring is formed on the first surface of the above-mentioned flip-mold packaging material, and the above-mentioned first wiring is used to connect the above-mentioned optical chip and the above-mentioned electrical chip.

[0019] In some embodiments, the number of the optical chips is at least two, and a second wiring is formed on the first surface of the reverse-mold packaging material, and the second wiring is used to connect different optical chips.

[0020] In some embodiments, a through hole penetrating the first surface and the second surface is formed in the reverse mold packaging material, a third trace electrically connected to the at least one optical chip and / or the at least one electrical chip is arranged in the through hole, and the second surface is arranged opposite to the first surface.

[0021] In some embodiments, a groove is formed in the above-mentioned reverse-mold packaging material and located on the light-emitting side of at least one of the above-mentioned optical chips, and the above-mentioned groove is used to arrange an optical fiber.

[0022] The technical solution provided by the embodiment of the present application, wherein the optoelectronic co-packaging device includes a reverse mold packaging module, the reverse mold packaging module includes a reverse mold packaging material, and at least one optical chip and at least one electrical chip packaged in the reverse mold packaging material, the front of at least one optical chip and the front of at least one electrical chip are both located on the first surface of the reverse mold packaging material; wherein a first trace is also formed on the first surface of the reverse mold packaging material, and the first trace is used to connect the optical chip and the electrical chip. The reverse mold process is used for packaging, so that the optical chip and the electrical chip are packaged and integrated to the same height, and the first trace is set to connect the optical chip and the electrical chip, so as to solve the interface connection problem between chips in the optoelectronic co-packaging technology, so as to ensure the integrity and reliability of signal transmission.

[0023] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0025] Figure 1 A schematic diagram of the front structure of an optoelectronic co-packaged device provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a top view of an optoelectronic co-packaged device provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the right side structure of an optoelectronic co-packaged device provided in an embodiment of the present application;

[0028] Figure 4 A schematic flow chart of a method for preparing an optoelectronic co-packaged device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0031] In the description of the present application, “plurality” means two or more.

[0032] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0033] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0034] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0035] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0036] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0037] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0038] In CPO technology, the interface connection mainly involves the connection between PICs and between PIC and EIC. The connection between PICs requires extremely high surface flatness and high consistency to ensure the integrity and reliability of signal transmission. With the increase in integration density, precise alignment between PICs has become a major technical difficulty. The usual solution is to use advanced polishing and grinding technology, combined with high-precision alignment equipment such as optical or electron microscopes. The connection between PIC and EIC mainly relies on wire bonding technology, but the number of interconnections in this method is limited and it is difficult to meet the requirements of high-density integration. Although the EIC flip-chip and PIC interconnection solution (specific description: EIC and PIC are interconnected through micro bumps (μbumps) or copperpillars, and the PIC is then connected to the PCB board through wire bonding) has improved the integration, there is an obvious thermal crosstalk problem, that is, the heat generated by the EIC will be transferred to the PIC, affecting the performance of the optical device. Although the interposer and through silicon via (TSV) interconnection solution (specific description: placing the EIC and PIC on the same interposer, and then interconnecting the interposer with the substrate through TSV) helps to improve the compactness of integration, the high-speed signal needs to pass through two bump connections, which may affect the bandwidth performance of the signal.

[0039] CPO technology tightly integrates optical components and electronic components on the same substrate, which significantly improves the power density of the packaging area. As the power density increases, the heat generated also increases, posing a huge challenge to thermal management. Since the heat cannot be dissipated in time, the temperature inside the CPO package will increase significantly. High temperature may cause the performance of optical components to degrade, such as laser wavelength drift, reduced sensitivity of photodetectors, etc. At the same time, it may also affect the reliability of electronic components, such as increasing leakage current and reducing breakdown voltage. In addition, the thermal stress generated by the temperature gradient inside the CPO package may cause material deformation, solder joint breakage and other problems, which in turn affects the reliability and stability of the package.

[0040] In view of the above problems existing in the related art, the present application provides an optoelectronic co-packaged device. Figure 1 This is a schematic diagram of the front view of an optoelectronic co-packaged device provided in an embodiment of the present application. Figure 2 A schematic diagram of a top view of an optoelectronic co-packaged device provided in an embodiment of the present application, Figure 3 This is a right-side structural schematic diagram of an optoelectronic co-packaged device provided in an embodiment of the present application.

[0041] Specifically, as mentioned above Figure 1 , Figure 2 and Figure 3 As shown, the optoelectronic co-packaged device 10 provided in the embodiment of the present application may include:

[0042] A reverse mold packaging module 100 includes a reverse mold packaging material 101, and at least one optical chip 102 and at least one electrical chip 108 encapsulated in the reverse mold packaging material 101, wherein the front side of the optical chip 102 and the front side of the electrical chip 108 are both located on the first surface 106 of the reverse mold packaging material 101, wherein the front side of the chip refers to the side where the circuits and components on the chip are located, and it is the key part for the chip to realize its function; a first trace 107 is also formed on the first surface 106 of the reverse mold packaging material 101, and the first trace 107 is used to connect the optical chip 102 and the electrical chip 108.

[0043] Among them, the reverse mold packaging module 100 may include an optical receiving module or an optical transmitting module. For example, in the optical transmitting module, it can usually include at least two optical chips 102 and one electrical chip 108, wherein the two optical chips 102 can be a laser 1021 and a modulator 1022 respectively, and the electrical chip 108 can be a driver chip of the modulator; the structure of the optical receiving module may be simpler because it mainly focuses on converting optical signals back into electrical signals, and usually includes at least one optical chip 102 and one electrical chip 108.

[0044] In the embodiment of the present application, the reverse molding packaging material 101 is an epoxy resin material. The epoxy resin has good insulation, corrosion resistance and mechanical strength and a low thermal expansion coefficient, which is conducive to reducing the stress caused by temperature changes, thereby protecting the internal chip from damage. The optical chip 102 and the electrical chip 108 are packaged and integrated to the same height through the reverse molding process.

[0045] Thanks to the reverse molding process, a first trace 107 for connecting the optical chip 102 and the electrical chip 108 can be provided on the first surface 106 of the reverse molding packaging material 101. The first trace 107 can be a radio frequency trace, so as to transmit the radio frequency signal between the two. The method of the present invention simplifies the wiring structure and ensures the integrity and reliability of signal transmission.

[0046] The technical solution provided by the embodiment of the present application, wherein the optoelectronic co-packaging device includes a reverse mold packaging module, the reverse mold packaging module includes a reverse mold packaging material, and at least one optical chip and at least one electrical chip packaged in the reverse mold packaging material, the front of at least one optical chip and the front of at least one electrical chip are both located on the first surface of the reverse mold packaging material; wherein a first trace is also formed on the first surface of the reverse mold packaging material, and the first trace is used to connect the optical chip and the electrical chip. By using the reverse mold process for packaging, the optical chip and the electrical chip are packaged and integrated to the same height, and the first trace for connecting the optical chip and the electrical chip can be set on a plane, solving the interface connection problem between chips in the optoelectronic co-packaging technology to ensure the integrity and reliability of signal transmission.

[0047] In some embodiments, the number of optical chips 102 is at least two, and a second trace 103 is also formed on the first surface 106 of the reverse mold packaging material 101, and the second trace 103 is used to connect different optical chips 102. In the embodiment of the present application, the optical chip 102 is a light emitting chip, so the number of optical chips 102 is at least two, namely a laser 1021 and a modulator 1022, wherein the connection between optical signals requires extremely high surface flatness and high consistency. The present technical solution is based on the reverse mold process, and a second trace 103 is provided on the first surface 106 of the reverse mold packaging material 101, and the second trace 103 is used to connect different optical chips 102 to ensure the integrity and reliability of signal transmission.

[0048] In some embodiments, the first routing line 107 is a planar printed metal routing line, and / or the second routing line 103 is a printed waveguide line. Among them, the use of planar printed metal routing lines to form the RF routing lines connecting the optical chip 102 and the electrical chip 108 can accurately control the width, thickness and shape of the routing lines, thereby meeting the high-precision requirements of the RF routing lines between the optical chip 102 and the electrical chip 108. In addition, based on the inverted mold process, the second routing line 103 connecting the laser 1021 and the modulator 1022 is formed by photonic wire bonding (PWB) technology to ensure high-precision alignment between the optical chips 102, thereby significantly reducing coupling losses. PWB technology uses high-precision manufacturing technologies such as two-photon lithography to directly print three-dimensional free-form waveguides between photonic chips or between photonic chips and optical fibers. These waveguides complete the adiabatic transformation of the mode field through the gradual change of the waveguide cross section, thereby realizing efficient transmission of optical signals. However, a major challenge faced by PWB technology in the implementation process is the precise alignment between optical chips. With the assistance of the reverse molding process, not only the alignment accuracy between optical chips is greatly improved, but also the practicality and reliability of PWB technology are further improved.

[0049] In some embodiments, a thin film circuit 112 is disposed on the back of at least one of the optical chips 102, and the thin film circuit 112 is formed on a heat dissipation substrate. The heat dissipation substrate is made of diamond or aluminum nitride material, and its thickness can be reduced to 0.2 mm, and the surface is gold-plated for making the thin film circuit 112. The thermal conductivity of the diamond and aluminum nitride substrates can reach 2000-2600 W / m·K and 170-320 W / m·K respectively.

[0050] In some embodiments, the optoelectronic co-packaged device 10 also includes a refrigeration module 111 encapsulated in the reverse mold packaging material 101 and in direct contact with the heat dissipation substrate. The refrigeration module 111 can be a semiconductor refrigerator (Thermo Electric Cooler, TEC), which is a device that uses the Peltier Effect of semiconductor materials to achieve cooling or heating functions. By precisely controlling the current, TEC can achieve very precise temperature control, usually achieving an accuracy of ±0.1°C or even higher. TEC has a compact structure, small size, and light weight, and is easy to integrate into the reverse mold. The embodiment of the present application adopts a modular laser design and realizes separate temperature control, combined with advanced technologies such as liquid cooling and heat pipe cooling, which directly and effectively reduces the chip temperature. The dynamic thermal management strategy flexibly adjusts the heat dissipation measures according to the workload and environmental conditions, and comprehensively improves the heat dissipation performance. Compared with the prior art, the heat dissipation performance of this solution is better, and it can more effectively reduce the chip temperature and improve the stability and life of the system.

[0051] In some embodiments, a through hole 104 penetrating the first surface 106 and the second surface 114 is further formed in the reverse mold packaging material 101, and a third trace 105 electrically connected to at least one optical chip 102 and / or at least one electrical chip 108 is arranged in the through hole 104, and the second surface 114 is arranged opposite to the first surface 106. Among them, the through hole 104 can be an epoxy resin through hole, and a third trace 105 electrically connected to at least one optical chip 102 and / or at least one electrical chip 108 is arranged in the through hole 104, and the third trace 105 is a DC trace. This design greatly optimizes the signal transmission path.

[0052] In some embodiments, the optoelectronic packaging device 10 also includes a circuit board 109 disposed on the second surface 114 of the reverse mold packaging material 101, and is electrically connected to the third trace 105 through a micro-bump 110. Among them, the micro-bump is a technology for realizing high-density and high-reliability electrical interconnection between the chip and the substrate. It is widely used in various advanced chip packaging technologies, such as 2.5D packaging, 3D packaging, etc. In 2.5D packaging, micro-bumps are often used to connect chips to interposers; while in 3D packaging, it may be used to realize stacking interconnection between chips. Among them, the circuit board 109 is a printed circuit board (PCB), and the design of the circuit layout on the PCB needs to match the number of interfaces of the above-mentioned optical chip 102 and the electrical chip 108. In addition, some metal layers on the PCB can play a role in heat dissipation, helping components in the circuit to disperse heat and prevent overheating damage.

[0053] In some embodiments, a groove 113 for accommodating an optical fiber is formed in the reverse mold packaging material 101 and located on the light-emitting side of at least one optical chip 103. The groove 113 may be a U-shaped groove or a V-shaped groove. After the reverse mold process is completed, the reverse mold packaging material 101 may be etched to form the groove 113, and the groove 113 is designed to achieve direct coupling of the optical fiber.

[0054] The present application also provides a method for preparing an optoelectronic co-packaged device, by which the above-mentioned Figure 1-3 The optoelectronic co-package device 10 in the illustrated embodiment. Figure 4 A schematic diagram of a process for preparing a photoelectric co-packaged device provided in an embodiment of the present application, wherein the specific structure can be referred to Figure 1-3 As shown, Figure 4 As shown, the preparation method comprises the following steps:

[0055] Step 201: As shown in the above figures, a reverse mold packaging module 100 is formed, wherein the reverse mold packaging module 100 includes a reverse mold packaging material 101, and at least one optical chip 102 and at least one electrical chip 108 packaged in the reverse mold packaging material 101, wherein the front surface of the at least one optical chip 102 and the front surface of the at least one electrical chip 108 are both located on the first surface 106 of the reverse mold packaging material 101;

[0056] Exemplarily, first, the optical chip 102 and the electrical chip 108 are placed in an upside-down manner on an auxiliary substrate inside the mold, and then the mold is filled with liquefied epoxy resin material 101. The epoxy resin material 101 is widely used in electronic packaging due to its good insulation, corrosion resistance and mechanical strength. The mold filled with epoxy resin is heated to its glass transition temperature, i.e. 160 degrees Celsius. During this process, the epoxy resin undergoes a transition from liquid to solid to form a solid packaging layer. After curing is completed, the mold is turned over so that the optical chip 102 and the electrical chip 108 are exposed on the same horizontal plane. The number of optical chips 102 and electrical chips 108 varies with demand, such as Figure 2 , it can be seen that there are three groups of photon integrated emission chips in the embodiment of the present application.

[0057] The optical chip 102 is formed using III-V group quaternary compound semiconductor materials, such as InGaAsP / AlGaAsP, etc. The optical chip 102 includes a high-power laser 1021 with a height of about 200μm, a length of about 1.5mm, and a push-pull modulator 1022 made of thin-film lithium niobate, whose bandwidth can reach 67GHz, and the overall height of the chip is about 0.6mm. The spacing between the laser 1021 and the modulator 1022 is about 0.25mm. The electrical chip 108 is the driver chip of the modulator 1022, and the thickness of the chip is relatively thin, which meets the requirements of the reverse molding process.

[0058] Step 202 : forming a first wiring 107 on the first surface 106 of the reverse molding packaging material 101 , wherein the first wiring 107 is used to connect the optical chip 102 and the electrical chip 108 .

[0059] Exemplarily, a first trace 107 for connecting the optical chip 102 and the electrical chip 108 is formed by micro-printing technology on the first surface 106 of the reverse mold packaging material 101, and the first trace 107 is a radio frequency trace. Printed metal trace technology is an advanced micro-nano manufacturing technology that uses precision printing equipment to deposit conductive materials directly on a substrate in the form of tiny ink droplets or lines to form high-precision, high-performance electrode traces.

[0060] Step 203 : forming a second wiring 103 on the first surface 106 of the reverse molding packaging material 101 , wherein the second wiring 103 is used to connect different optical chips 102 , wherein the number of the optical chips 102 is at least two.

[0061] The optical chip shown in the embodiment of the present application is a light emitting chip, so there are two optical chips 102, including a laser and a modulator. A second wire 103 connecting the laser 1021 and the modulator 1022 in the optical chip 102 is formed on the first surface 106 of the reverse mold packaging material 101 by photonic wire bonding (PWB) technology. PWB technology uses high-precision manufacturing technologies such as two-photon lithography to directly print a three-dimensional free-form waveguide between the laser and the modulator as the second wire 103 connecting different optical chips 102, such as Figure 2 As shown. These waveguides complete the adiabatic transformation of the mode field through the gradual change of the waveguide cross section, thereby achieving efficient transmission of optical signals. With the assistance of the reverse molding process, the alignment accuracy between the optical chips 102 is greatly improved.

[0062] Step 204: A through hole 104 penetrating the first surface 106 and the second surface 114 is formed in the reverse mold packaging material 101, wherein the second surface 114 is arranged opposite to the first surface 106, and a third trace 105 electrically connected to at least one optical chip 102 and / or at least one electrical chip 108 is arranged in the through hole 104.

[0063] For example, Figure 1 As shown, the third trace 105 is electrically connected vertically downward to the laser 1021, the modulator 1022 and the electrical chip 108 in the optical chip 102 through the epoxy resin through hole 104, and runs through the first surface 106 and the second surface 114. This design greatly optimizes the signal transmission path. The third trace 105 is a DC trace, which can be formed by micro-printing technology, wherein the DC trace is designed as a vertical through-hole trace, which effectively reduces the overall package size. When combined with the RF planar trace, the coupling and crosstalk between two different types of signals can be significantly reduced.

[0064] Step 205 : forming a groove 113 for arranging an optical fiber in the reverse-molding packaging material 101 and located on the light-emitting side of at least one optical chip 102 .

[0065] Exemplarily, in the reverse molding packaging material 101, after the reverse molding process is completed, a groove 113 is formed on the light emitting side of the optical chip 102 by wet etching or dry etching. The groove 113 may be a U-shaped groove or a V-shaped groove. This groove 113 is designed to achieve direct coupling of optical fibers.

[0066] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An optoelectronic co-package device, characterized in that: The invention comprises a reverse mold packaging module, wherein the reverse mold packaging module comprises a reverse mold packaging material, and at least one optical chip and at least one electrical chip encapsulated in the reverse mold packaging material, wherein the front surface of the at least one optical chip and the front surface of the at least one electrical chip are both located on the first surface of the reverse mold packaging material; A first wiring is also formed on the first surface of the reverse-mold packaging material, and the first wiring is used to connect the optical chip and the electrical chip.

2. The optoelectronic co-package device according to claim 1, characterized in that: The number of the optical chips is at least two, and a second wiring is further formed on the first surface of the reverse mold packaging material, and the second wiring is used to connect different optical chips.

3. The optoelectronic co-package device according to claim 2, characterized in that: The first routing line is a planar printed metal routing line, and / or the second routing line is a printed waveguide line.

4. The optoelectronic co-package device according to claim 2, characterized in that: A thin film circuit is disposed on the back side of at least one of the optical chips, and the thin film circuit is formed on a heat dissipation substrate.

5. The optoelectronic co-package device according to claim 4, characterized in that: Also includes: The refrigeration module is encapsulated in the reverse-molding encapsulation material and is in direct contact with the heat dissipation substrate.

6. The optoelectronic co-packaged device according to any one of claims 1 to 5, characterized in that: The reverse mold packaging material also has a through hole penetrating the first surface and the second surface, in which a third trace electrically connected to the at least one optical chip and / or the at least one electrical chip is arranged, and the second surface is arranged opposite to the first surface.

7. The optoelectronic co-packaged device according to claim 6, characterized in that: The optoelectronic packaging device further includes: A circuit board is arranged on the second surface of the reverse-mold packaging material and is electrically connected to the third trace.

8. The optoelectronic co-packaged device according to claim 1, characterized in that: A groove is formed in the reverse-molding packaging material and located on the light-emitting side of at least one of the optical chips, and the groove is used to accommodate an optical fiber.

9. A method for preparing an optoelectronic co-packaged device, characterized in that: include: Forming a reverse mold packaging module, the reverse mold packaging module comprising a reverse mold packaging material, and at least one optical chip and at least one electrical chip encapsulated in the reverse mold packaging material, wherein the front surface of the at least one optical chip and the front surface of the at least one electrical chip are both located on the first surface of the reverse mold packaging material; A first wiring is formed on a first surface of the flip-mold packaging material, where the first wiring is used to connect the optical chip and the electrical chip.

10. The preparation method according to claim 9, characterized in that: The number of the optical chips is at least two, and further includes: A second wiring is formed on the first surface of the reverse molding packaging material, and the second wiring is used to connect different optical chips.

11. The preparation method according to claim 9, characterized in that: Also includes: A through hole penetrating the first surface and the second surface is formed in the reverse mold packaging material, a third trace electrically connected to the at least one optical chip and / or the at least one electrical chip is arranged in the through hole, and the second surface is arranged opposite to the first surface.

12. The preparation method according to claim 9, characterized in that: Also includes: A groove is formed in the reverse-molding packaging material and located on the light-emitting side of at least one of the optical chips, and the groove is used to arrange an optical fiber.

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