Deconvolution method and device based on multi-memristor array, electronic equipment and medium

Abstract

The invention relates to the technical field of information, in particular to a deconvolution method and device based on a multi-memristor array, electronic equipment and a medium, and the method comprises the steps: obtaining to-be-calculated target data, and recognizing each sub-data of each group of data in the target data; dispersing each sub-data of each group of data to different operation positions of the multi-memristor array; and completing convolution operation at different operation positions of the multi-memristor array, and accumulating convolution operation results at different operation positions to obtain a final convolution result of each group of data in the target data. Therefore, the problem that the final calculation precision is affected due to the fact that the convolution acceleration operation of multiple groups of data on multiple memristor arrays is completed respectively and errors exist in each group of calculated convolution results in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of information technology, and in particular to a deconvolution method, device, electronic device and medium based on a multi-memristor array. Background Art

[0002] The deconvolution algorithm is a widely used algorithm that plays an important role in image processing, computational optics and other fields. However, the deconvolution algorithm involves a large number of complex operations and requires extremely high computing power. Memristor arrays can accelerate the deconvolution algorithm with their excellent matrix-vector multiplication acceleration capabilities. Considering that the task scenarios processed by the deconvolution algorithm usually have a huge amount of data, in actual applications, multiple memristor arrays with the same hardware design and the same parameter matrix stored on the array are usually used to accelerate the deconvolution algorithm in parallel.

[0003] The data flow implemented by the deconvolution algorithm based on multi-memristor array commonly used in related technologies is as follows: Figure 1 As shown, multiple groups of data complete convolution acceleration operations on multiple memristor arrays respectively, and then based on the requirements of the typical deconvolution algorithm, each group of data is usually accumulated after completing the convolution. In order to simplify data scheduling, multiple groups of data complete convolution acceleration operations on multiple memristor arrays respectively. For example, the first group of data completes the convolution operation only based on the first memristor array, the second group of data completes the convolution operation only based on the second memristor array, and the third group of data completes the convolution operation only based on the third memristor array. However, since the write bias on each memristor array (i.e., the deviation between the parameter matrix mapped to the memristor array and the actual parameter matrix) is fixed, for a group of data, each "convolution result" calculated in this way will be subject to similar "interference", that is, there is a strong correlation between the random variables representing the "interference" on each "convolution result", so the final result obtained after accumulation will be subject to more serious "interference", thereby affecting the final calculation accuracy. Summary of the invention

[0004] The present application provides a deconvolution method, device, electronic device and medium based on a multi-memristor array to solve the problem in the related art that multiple groups of data are subjected to convolution acceleration operations on multiple memristor arrays respectively, and each group of convolution results calculated has errors, thereby affecting the final calculation accuracy.

[0005] The first aspect of the present application provides a deconvolution method based on a multi-memristor array, comprising the following steps: obtaining target data to be calculated, identifying each sub-data of each group of data in the target data; dispersing each sub-data of each group of data to different operating positions of the multi-memristor array; completing a convolution operation at different operating positions of the multi-memristor array, and accumulating the convolution operation results of different operating positions to obtain the final convolution result of each group of data in the target data.

[0006] Optionally, different operation positions of the multi-memristor array include at least one of different memristor arrays and different sub-arrays in the memristor array.

[0007] Optionally, if different operation positions of the multi-memristor array are different memristor arrays, the convolution operation results of the different operation positions are accumulated to obtain the final convolution result of each group of data in the target data, including: obtaining the output data of the memristor arrays participating in the operation in the multi-memristor array; accumulating the output data of the memristor arrays participating in the operation to obtain the final convolution result.

[0008] Optionally, if different operation positions of the multi-memristor array are different sub-arrays in the memristor array, the convolution operation results of the different operation positions are accumulated to obtain the final convolution result of each group of data in the target data, including: obtaining the output data of the sub-arrays participating in the operation in the memristor array; accumulating the output data of the sub-arrays participating in the operation to obtain the final convolution result.

[0009] Optionally, different sub-arrays in the memristor array include a first data stream sub-array and a second data stream sub-array, wherein the first data stream sub-array and the second data stream sub-array perform discrete Fourier transform in different data stream modes.

[0010] Optionally, the data stream mode includes a first data stream and a second data stream, wherein the first data stream completes real part operations based on the first side subarray and completes imaginary part operations based on the second side subarray, and the second data stream completes imaginary part operations based on the first side subarray and completes real part operations based on the second side subarray.

[0011] Optionally, the multiple memristor arrays are multiple memristor arrays with the same structure, multiple memristor arrays with different structures, or multiple memristor arrays of different types.

[0012] The second aspect of the present application provides a deconvolution device based on a multi-memristor array, including: an acquisition module, used to acquire target data to be calculated and identify each sub-data of each group of data in the target data; a dispersion module, used to disperse each sub-data of each group of data to different operation positions of the multi-memristor array; a processing model, used to complete the convolution operation at different operation positions of the multi-memristor array, and accumulate the convolution operation results of different operation positions to obtain the final convolution result of each group of data in the target data.

[0013] Optionally, different operation positions of the multi-memristor array include at least one of different memristor arrays and different sub-arrays in the memristor array.

[0014] Optionally, if different operation positions of the multi-memristor array are different memristor arrays, the processing module is further used to obtain output data of the memristor arrays participating in the operation in the multi-memristor array; accumulate the output data of the memristor arrays participating in the operation to obtain the final convolution result.

[0015] Optionally, if different operation positions of the multi-memristor array are different sub-arrays in the memristor array, the processing module is further used to obtain output data of the sub-arrays participating in the operation in the memristor array; and accumulate the output data of the sub-arrays participating in the operation to obtain the final convolution result.

[0016] Optionally, different sub-arrays in the memristor array include a first data stream sub-array and a second data stream sub-array, wherein the first data stream sub-array and the second data stream sub-array perform discrete Fourier transform in different data stream modes.

[0017] Optionally, the data stream mode includes a first data stream and a second data stream, wherein the first data stream completes real part operations based on the first side subarray and completes imaginary part operations based on the second side subarray, and the second data stream completes imaginary part operations based on the first side subarray and completes real part operations based on the second side subarray.

[0018] Optionally, the multiple memristor arrays are multiple memristor arrays with the same structure, multiple memristor arrays with different structures, or multiple memristor arrays of different types.

[0019] The third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement a deconvolution method based on a multi-memristor array as in the above embodiment.

[0020] A fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, the program being executed by a processor to implement a deconvolution method based on a multi-memristor array as in the above-mentioned embodiment.

[0021] Therefore, this application includes the following beneficial effects:

[0022] The embodiment of the present application can disperse each sub-data in a set of data to different memristor arrays to complete the convolution operation, which can effectively reduce the impact of the non-ideal characteristics of the memristor on the calculation result, improve the calculation accuracy, and make the final calculation result after accumulation more accurate. Thus, the problem that multiple groups of data in the related art complete the convolution acceleration operation on multiple memristor arrays separately, and each group of convolution results calculated has errors, thereby affecting the final calculation accuracy, etc.

[0023] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0025] Figure 1 An example diagram of data flow scheduling between multiple arrays in the related art;

[0026] Figure 2 A flowchart of a deconvolution method based on a multi-memristor array provided according to an embodiment of the present application;

[0027] Figure 3 This is an example diagram of result accumulation provided according to an embodiment of the present application;

[0028] Figure 4 This is an example diagram of deconvolution data flow scheduling based on a multi-memristor array according to an embodiment of the present application;

[0029] Figure 5 A structural diagram of a memristor discrete Fourier transform calculation module provided according to an embodiment of the present application;

[0030] Figure 6 Two data flow schemes of discrete Fourier transform of a memristor according to an embodiment of the present application are shown;

[0031] Figure 7 An example diagram of discrete Fourier transform data flow scheduling provided according to an embodiment of the present application;

[0032] Figure 8 A comparison diagram of simulation effects provided according to an embodiment of the present application;

[0033] Fig. 9 A block diagram of a deconvolution device based on a multi-memristor array according to an embodiment of the present application;

[0034] Fig.10 Schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0036] The following describes the deconvolution method, device, electronic device and medium based on a multi-memristor array of an embodiment of the present application with reference to the accompanying drawings. In response to the problems mentioned in the above background technology, the present application provides a deconvolution method based on a multi-memristor array, in which each sub-data in a set of data is dispersed to different memristor arrays to complete the convolution operation, which can effectively reduce the impact of the non-ideal characteristics of the memristor on the calculation result, improve the calculation accuracy, and make the final calculation result after accumulation more accurate. Thus, the problem that multiple groups of data in the related art complete the convolution acceleration operation on multiple memristor arrays respectively, and each group of convolution results calculated has errors, thereby affecting the final calculation accuracy, etc.

[0037] Specifically, Figure 1 A schematic flow chart of a deconvolution method based on a multi-memristor array provided in an embodiment of the present application.

[0038] like Figure 1 As shown, the deconvolution method based on the multi-memristor array includes the following steps:

[0039] In step S101, target data to be calculated is obtained, and each sub-data of each group of data in the target data is identified.

[0040] In step S102, each sub-data of each group of data is dispersed to different operation positions of the multi-memristor array.

[0041] The multi-memristor array may be a plurality of memristor arrays with the same structure, a plurality of memristor arrays with different structures, or a plurality of memristor arrays of different types.

[0042] Specifically, if Figure 3 As shown, in the embodiment of the present application, the sub-data of each group of data can be arranged separately on different memristor arrays to complete the convolution operation. Since the write deviations on the memristor array are randomly distributed, there is almost no correlation between the write deviations of each array. Therefore, the correlation between the "interference" of the "convolution result" of each group of data can be greatly reduced, so that the last term 2Cov(X,Y) of formula (1) is approximately equal to zero, so that the variance value Var(X+Y) of the superimposed random variable is reduced.

[0043] Var(X+Y)=Var(X)+Var(Y)+2Cov(X,Y) (1)

[0044] In step S103, convolution operations are performed at different operation positions of the multi-memristor array, and the convolution operation results of different operation positions are accumulated to obtain the final convolution result of each group of data in the target data.

[0045] It can be understood that the embodiment of the present application can disperse each sub-data in a set of data to different memristor arrays (and / or different memristor sub-arrays) to complete the convolution operation, thereby reducing the correlation between the "interference" of each "convolution result", so that the "interference" variance of the "final result" is approximately equal to the sum of the "interference" variances of each "convolution result", such as Figure 3 As shown, the influence of the non-ideal characteristics of the memristor on the calculation results is effectively reduced, and the calculation accuracy is improved.

[0046] Among them, different operation positions of the multi-memristor array may include different memristor arrays and at least one of different sub-arrays in the memristor array. Therefore, the embodiment of the present application can use different memristor arrays or different sub-arrays in the memristor array alone to complete the convolution operation, or can use different memristor arrays and different sub-arrays in the memristor array in combination to complete the convolution operation. Those skilled in the art can make specific choices based on actual needs without specific limitations. In the following embodiments, using it alone is taken as an example. When used in combination, the steps in the following embodiments are combined. In order to avoid redundancy, the combination is not described in detail. The following will specifically explain the use of different memristor arrays or different sub-arrays in the memristor array alone to complete the convolution operation:

[0047] In one embodiment of the present application, if different operation positions of a multi-memristor array are different memristor arrays, the convolution operation results of different operation positions are accumulated to obtain the final convolution result of each group of data in the target data, including: obtaining the output data of the memristor arrays participating in the operation in the multi-memristor array; accumulating the output data of the memristor arrays participating in the operation to obtain the final convolution result.

[0048] It is understandable that if Figure 4 As shown, the embodiment of the present application can perform convolution operations on multiple memristor arrays in parallel, and each memristor array processes the sub-data assigned to it. Since there is almost no correlation between the "interference" generated on each memristor array, when these convolution results are accumulated, the "interference" variance of the "final result" is close to the sum of the "interference" variances of each "convolution result", rather than significantly increasing. Therefore, by accumulating the convolution results from different memristor arrays to form the final convolution result of the group of data, the error under the calculation of multiple memristor arrays is reduced, and a high calculation accuracy is maintained.

[0049] In one embodiment of the present application, if different operation positions of the multi-memristor array are different sub-arrays in the memristor array, the convolution operation results of the different operation positions are accumulated to obtain the final convolution result of each group of data in the target data, including obtaining the output data of the sub-arrays participating in the operation in the memristor array; accumulating the output data of the sub-arrays participating in the operation to obtain the final convolution result.

[0050] The different subarrays in the memristor array include a first data stream subarray and a second data stream subarray, wherein the first data stream subarray and the second data stream subarray have different data stream modes for completing discrete Fourier transform. The data stream mode includes a first data stream and a second data stream, wherein the first data stream completes the real part operation based on the first side subarray and completes the imaginary part operation based on the second side subarray, and the second data stream completes the imaginary part operation based on the first side subarray and completes the real part operation based on the second side subarray.

[0051] It is understandable that in a single convolution acceleration core based on a memristor array, such as Figure 5 As shown, the embodiments of the present application can utilize different sub-arrays in the memristor array (for example, the upper left corner and the lower right corner map the real part of the parameter matrix, and the upper right corner and the lower left corner map the imaginary part of the parameter matrix) to perform convolution operations, obtain respective convolution results, and then accumulate these results to obtain the final convolution result.

[0052] In actual execution, the computing core is as follows Figure 5 The memristor discrete Fourier transform calculation module shown in FIG. The basic calculation principle is as follows: the real part Re(x) and the imaginary part Im(x) of the input signal x are simultaneously input to the row line of the memristor array, and the real part Re(y) and the imaginary part Im(y) of the result y after the time-frequency transformation are output on the column line, where the calculation formula of the real part is Re(y)=Re(x)Re(W)-Im(x)Im(W), and the calculation formula of the imaginary part is Im(y)=Re(x)Im(W)+Im(x)Re(W). It should be noted that for the sake of simplicity, the positive and negative elements in the parameter matrix are not considered here; in fact, in order to map the parameter matrix containing both positive and negative numbers, a memristor array of twice the size is needed to represent the parameter matrix in differential form; the processing of the positive and negative elements of the parameter matrix can refer to the existing technology, and will not be described here. In the schematic diagram, a memristor array is used to represent a parameter matrix (elements can be positive or negative) by default.

[0053] In the current common practice, the real part Re(x) and the imaginary part Im(x) of the input signal are expressed as Figure 5 The method shown is input to the memristor array; then the real part Re(y) and imaginary part Im(y) of the frequency domain signal are output on the left and right sides of the array output respectively. Figure 5There are two "identical memristor sub-arrays" in the computing module shown, that is, the upper left corner and the lower right corner are mapped to the real part of the parameter matrix, and the upper right corner and the lower left corner columns are mapped to the imaginary part of the parameter matrix.

[0054] Therefore, the embodiments of the present application can be Figure 5 The same “distribution of sub-data to different sub-arrays for operation” is performed inside the calculation module shown, thereby further reducing the correlation between the “interference” on each “convolution result”. According to mathematical derivation, the following formula can be obtained:

[0055] -Im(y)=Re(x)·(-Im(W))+(-Im(x))·Re(W) (2)

[0056] Re(y)=Re(x)·Re(W)+(-Im(x))·Im(W) (3)

[0057] Furthermore, if Figure 6 As shown, the embodiment of the present application can adopt a new data flow solution in Figure 6 The discrete Fourier transform is performed on the memristor array shown (only a small number of inverters need to be added to invert the calculation result of formula (2)). In the actual implementation process, the embodiment of the present application can refer to the traditional data flow scheme as the first data flow, that is, Figure 6 The new data stream scheme is called the second data stream, that is, Figure 6 It should be noted that in "DFT data stream A", the real part Re(y) is calculated based on the two sub-arrays on the left, and the imaginary part Im(y) is calculated based on the two sub-arrays on the right; while in "DFT data stream B", the real part Re(y) is calculated based on the two sub-arrays on the right, and the imaginary part Im(y) is calculated based on the two sub-arrays on the left.

[0058] Therefore, the correlation between the "interference" of the calculation results obtained by "DFT data stream A" and "DFT data stream B" is extremely low. The overall calculation data stream scheduling scheme (new discrete Fourier transform data stream scheduling scheme) based on the above two schemes "A, B" is as follows Figure 7 As shown. For sub-data A and B of a certain set of data, the convolution operation can be completed using "DFT data stream A" and "DFT data stream B" respectively to obtain "convolution results" A and B, which are then accumulated. In this way, the correlation between the "interference" on the "convolution results" A and B is very small.

[0059] In addition, the embodiments of the present application also provide practical application effects of the above two novel data flow schemes (multi-array data flow scheduling scheme and novel discrete Fourier transform data flow scheduling scheme). Figure 8The comparison of the calculation results before and after using the two new schemes is shown. Under the traditional data flow scheme, adding a write deviation of ±0.5μS (equivalent to about 2.5%) to the memristor array results in a peak signal-to-noise ratio (PSNR) of 44dB; adding a write deviation of ±1μS (equivalent to about 5%) to the memristor array results in a peak signal-to-noise ratio (PSNR) of 35dB; adding a write deviation of ±3μS (equivalent to about 15%) to the memristor array results in a peak signal-to-noise ratio (PSNR) of 21dB. Under the new data flow scheme, adding a write deviation of ±0.5μS (equivalent to about 2.5%) to the memristor array results in a peak signal-to-noise ratio (PSNR) of 51dB; adding a write deviation of ±1μS (equivalent to about 5%) to the memristor array results in a peak signal-to-noise ratio (PSNR) of 45dB; adding a write deviation of ±3μS (equivalent to about 15%) to the memristor array results in a peak signal-to-noise ratio (PSNR) of 36dB. It can be seen that no matter what the write deviation level is, the calculation results of the new data flow scheme are significantly better than those of the traditional data flow scheme.

[0060] It should be noted that the memristor array of the embodiment of the present application can also be of the following structure: using different types of memristors (such as resistive memory, phase change memory, magnetic random access memory, etc.); using different structures of storage and computing integrated architecture or units (such as 1T1R, 2T2R, 2T1R, etc.). Other algorithms with similar data streams (i.e., data are calculated separately and then accumulated) can also use the method proposed in the embodiment of the present application to reduce the error in multi-memristor array calculation.

[0061] According to the deconvolution method for multiple memristor arrays proposed in the embodiment of the present application, each sub-data in a set of data is dispersed to different memristor arrays to complete the convolution operation, which can effectively reduce the impact of the non-ideal characteristics of the memristor on the calculation results, improve the calculation accuracy, and make the final calculation result after accumulation more accurate. Thus, the problem that multiple groups of data in the related art complete the convolution acceleration operation on multiple memristor arrays separately, and each group of convolution results calculated has errors, thereby affecting the final calculation accuracy, etc.

[0062] Next, a deconvolution device based on a multi-memristor array proposed according to an embodiment of the present application is described with reference to the accompanying drawings.

[0063] Fig. 9 It is a block diagram of a deconvolution device based on a multi-memristor array according to an embodiment of the present application.

[0064] like Fig. 9 As shown, the deconvolution device 10 based on a multi-memristor array includes: an acquisition module 100 , a dispersion module 200 and a processing module 300 .

[0065] Among them, the acquisition module 100 is used to acquire the target data to be calculated and identify the sub-data of each group of data in the target data; the dispersion module 200 is used to disperse the sub-data of each group of data to different operation positions of the multi-memristor array; the processing model 300 is used to complete the convolution operation at different operation positions of the multi-memristor array, and accumulate the convolution operation results of different operation positions to obtain the final convolution result of each group of data in the target data.

[0066] In one embodiment of the present application, different operation positions of the multi-memristor array include at least one of different memristor arrays and different sub-arrays in the memristor array.

[0067] In one embodiment of the present application, if different operation positions of the multi-memristor array are different memristor arrays, the processing module 300 is further used to obtain output data of the memristor arrays participating in the operation in the multi-memristor array; and accumulate the output data of the memristor arrays participating in the operation to obtain the final convolution result.

[0068] In one embodiment of the present application, if different operation positions of the multi-memristor array are different sub-arrays in the memristor array, the processing module 300 is further used to obtain output data of the sub-arrays participating in the operation in the memristor array; and accumulate the output data of the sub-arrays participating in the operation to obtain the final convolution result.

[0069] In one embodiment of the present application, different subarrays in the memristor array include a first data stream subarray and a second data stream subarray, wherein the first data stream subarray and the second data stream subarray perform discrete Fourier transform in different data stream modes.

[0070] In one embodiment of the present application, the data stream mode includes a first data stream and a second data stream, wherein the first data stream completes real part operations based on the first side subarray and completes imaginary part operations based on the second side subarray, and the second data stream completes imaginary part operations based on the first side subarray and completes real part operations based on the second side subarray.

[0071] In one embodiment of the present application, the multi-memristor array is a plurality of memristor arrays with the same structure, a plurality of memristor arrays with different structures, or a plurality of memristor arrays of different types.

[0072] It should be noted that the aforementioned explanation of the embodiment of the deconvolution method based on a multi-memristor array is also applicable to the deconvolution device based on a multi-memristor array of this embodiment, and will not be repeated here.

[0073] According to the deconvolution device based on a multi-memristor array proposed in the embodiment of the present application, each sub-data in a set of data is dispersed to different memristor arrays to complete the convolution operation, which can effectively reduce the impact of the non-ideal characteristics of the memristor on the calculation result, improve the calculation accuracy, and make the final calculation result after accumulation more accurate. Thus, the problem that multiple groups of data in the related art complete the convolution acceleration operation on multiple memristor arrays separately, and each group of convolution results calculated has errors, thereby affecting the final calculation accuracy, etc.

[0074] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0075] A memory 1001 , a processor 1002 , and a computer program stored in the memory 1001 and executable on the processor 1002 .

[0076] When the processor 1002 executes the program, the deconvolution method based on the multi-memristor array provided in the above embodiment is implemented.

[0077] Furthermore, the electronic device further comprises:

[0078] The communication interface 1003 is used for communication between the memory 1001 and the processor 1002 .

[0079] The memory 1001 is used to store computer programs that can be executed on the processor 1002 .

[0080] The memory 1001 may include a high-speed RAM (Random Access Memory) memory, and may also include a non-volatile memory, such as at least one disk memory.

[0081] If the memory 1001, the processor 1002 and the communication interface 1003 are implemented independently, the communication interface 1003, the memory 1001 and the processor 1002 can be connected to each other through a bus and communicate with each other. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.10 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0082] Optionally, in a specific implementation, if the memory 1001, the processor 1002 and the communication interface 1003 are integrated on a chip, the memory 1001, the processor 1002 and the communication interface 1003 can communicate with each other through an internal interface.

[0083] The processor 1002 may be a CPU (Central Processing Unit), or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application.

[0084] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned deconvolution method based on a multi-memristor array.

[0085] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0086] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0087] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0088] It should be understood that the various parts of the present application can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, the steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array, a field programmable gate array, etc.

[0089] A person of ordinary skill in the art may understand that all or part of the steps carried by the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the above-mentioned program may be stored in a computer-readable storage medium, which, when executed, includes one of the steps of the method embodiment or a combination thereof.

[0090] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A deconvolution method based on a multi-memristor array, characterized in that: The following steps are involved: Acquire target data to be calculated, and identify each sub-data of each group of data in the target data; Distributing each sub-data of each group of data to different computing positions of the multi-memristor array; Convolution operations are performed at different operation positions of the multi-memristor array, and the convolution operation results of the different operation positions are accumulated to obtain the final convolution result of each group of data in the target data.

2. The deconvolution method based on a multi-memristor array according to claim 1, characterized in that: The different operation positions of the multi-memristor array include at least one of different memristor arrays and different sub-arrays in the memristor array.

3. The deconvolution method based on a multi-memristor array according to claim 2, characterized in that: If different operation positions of the multi-memristor array are different memristor arrays, accumulating the convolution operation results of the different operation positions to obtain the final convolution result of each group of data in the target data includes: Obtaining output data of a memristor array participating in a calculation in the multi-memristor array; The output data of the memristor array involved in the operation are accumulated to obtain the final convolution result.

4. The deconvolution method based on a multi-memristor array according to claim 2, characterized in that: If different operation positions of the multi-memristor array are different sub-arrays in the memristor array, accumulating the convolution operation results of the different operation positions to obtain the final convolution result of each group of data in the target data includes: Obtaining output data of a subarray participating in a calculation in the memristor array; The output data of the sub-arrays involved in the operation are accumulated to obtain the final convolution result.

5. The deconvolution method based on a multi-memristor array according to claim 2 or 4, characterized in that: The different sub-arrays in the memristor array include a first data stream sub-array and a second data stream sub-array, wherein the first data stream sub-array and the second data stream sub-array perform discrete Fourier transform in different data stream modes.

6. The deconvolution method based on a multi-memristor array according to claim 2 or 4, characterized in that: The data stream mode includes a first data stream and a second data stream, wherein the first data stream completes real part calculation based on the first side subarray and completes imaginary part calculation based on the second side subarray, and the second data stream completes imaginary part calculation based on the first side subarray and completes real part calculation based on the second side subarray.

7. The deconvolution method based on a multi-memristor array according to claim 1, characterized in that: The multiple memristor arrays are multiple memristor arrays with the same structure, multiple memristor arrays with different structures, or multiple memristor arrays of different types.

8. A deconvolution device based on a multi-memristor array, characterized in that: include: An acquisition module, used for acquiring target data to be calculated and identifying each sub-data of each group of data in the target data; A dispersing module, used for dispersing each sub-data of each group of data to different operation positions of the multi-memristor array; A processing model is used to complete convolution operations at different operation positions of the multi-memristor array, and accumulate the convolution operation results of the different operation positions to obtain the final convolution result of each group of data in the target data.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the deconvolution method based on a multi-memristor array as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed, the deconvolution method based on a multi-memristor array as described in any one of claims 1 to 7 is implemented.

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