Apparatus and method for internal horizontal synchronization signal generation

Abstract

A display driver includes a timing controller and a driving circuit. The timing controller receives an external horizontal synchronization signal and generates an internal horizontal synchronization signal based on the external horizontal synchronization signal. The driving circuit drives the display panel in synchronization with the internal horizontal synchronization signal. Generating the internal horizontal synchronization signal includes: generating a first pulse of the internal horizontal synchronization signal in response to detection of the first pulse of the external horizontal synchronization signal after expiration of a masking period that starts when a first previous pulse is detected in the external horizontal synchronization signal; and generating a second pulse of the internal horizontal synchronization signal in response to detection of the second pulse of the external horizontal synchronization signal in a non-masking period that starts when a second previous pulse is detected in the external horizontal synchronization signal.

Description

Technical Field

[0001] The present disclosure relates generally to display devices, and more particularly to the generation of internal horizontal synchronization signals in display devices. Background Art

[0002] A display driver configured to drive a display panel (e.g., a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, and a micro light emitting diode (μLED) display panel) may be configured to receive a horizontal synchronization signal and a vertical synchronization signal from an external controller to operate synchronously with the horizontal synchronization signal and the vertical synchronization signal. The horizontal synchronization signal may define the start and end of each horizontal synchronization period (or row period), and the vertical synchronization signal may define the start and end of each vertical synchronization period (or frame period). The horizontal synchronization signal received from the outside may be referred to as an external horizontal synchronization signal hereinafter, and the vertical synchronization signal received from the outside may be referred to as an external vertical synchronization signal hereinafter.

[0003] The display driver may generate an internal horizontal synchronization signal and an internal vertical synchronization signal according to an external horizontal synchronization signal and an external vertical synchronization signal, respectively, for internal use. More specifically, the display driver may be configured to generate pulses of the internal horizontal synchronization signal in response to detection of pulses in the external horizontal synchronization signal, and to generate pulses of the internal vertical synchronization signal in response to detection of pulses in the external vertical synchronization signal. The internal horizontal synchronization signal and the internal vertical synchronization signal thus generated may be used to implement timing control in the display driver. Summary of the invention

[0004] This summary is provided to introduce a selection of concepts that are further described below in a simplified form. This summary is not intended to necessarily identify key features or essential features of the present disclosure. The present disclosure may include the following various aspects and embodiments.

[0005] In an exemplary embodiment, the present disclosure provides a display driver. The display driver includes a timing controller and a driving circuit. The timing controller is configured to receive an external horizontal synchronization signal and generate an internal horizontal synchronization signal based on the external horizontal synchronization signal. The driving circuit is configured to drive the display panel synchronously with the internal horizontal synchronization signal. Generating the internal horizontal synchronization signal includes: generating a first pulse of the internal horizontal synchronization signal in response to the detection of a first pulse of the external horizontal synchronization signal after a masking period has expired. When the timing controller detects a first previous pulse of the external horizontal synchronization signal before the detection of the first pulse of the external horizontal synchronization signal, the masking period begins. Generating the internal horizontal synchronization signal also includes generating a second pulse of the internal horizontal synchronization signal in response to the detection of a second pulse of the external horizontal synchronization signal in a non-masking period, and the non-masking period starts when the timing controller detects the second previous pulse of the external horizontal synchronization signal before the detection of the second pulse of the external horizontal synchronization signal.

[0006] In another exemplary embodiment, the present disclosure provides a system. The system includes an external source and a display driver. The external source is configured to provide an external horizontal synchronization signal. The display driver is configured to: generate an internal horizontal synchronization signal based on the external horizontal synchronization signal; and drive the display panel synchronously with the internal horizontal synchronization signal. Generating the internal horizontal synchronization signal includes: generating a first pulse of the internal horizontal synchronization signal in response to the detection of a first pulse of the external horizontal synchronization signal after the masking period has expired. When the timing controller detects a first previous pulse of the external horizontal synchronization signal before the detection of the first pulse of the external horizontal synchronization signal, the masking period begins. Generating the internal horizontal synchronization signal also includes generating a second pulse of the internal horizontal synchronization signal in response to the detection of a second pulse of the external horizontal synchronization signal in a non-masking period, and the non-masking period starts when the timing controller detects the second previous pulse of the external horizontal synchronization signal before the detection of the second pulse of the external horizontal synchronization signal.

[0007] In another exemplary embodiment, the present disclosure provides a method. The method includes receiving an external horizontal synchronization signal. The method also includes: generating a first pulse of an internal horizontal synchronization signal in response to detection of a first pulse of the external horizontal synchronization signal after a masking period has expired. The masking period starts when a first previous pulse of the external horizontal synchronization signal is detected before detection of the first pulse of the external horizontal synchronization signal. The method also includes generating a second pulse of the internal horizontal synchronization signal in response to detection of a second pulse of the external horizontal synchronization signal in a non-masking period, the non-masking period starting when the second previous pulse of the external horizontal synchronization signal is detected before detection of the second pulse of the external horizontal synchronization signal. The method also includes driving a display panel synchronously with the internal horizontal synchronization signal.

[0008] Additional features and aspects are described in additional detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an exemplary configuration of a display device according to one or more examples of the present disclosure.

[0010] Figure 2 An exemplary scheme for generating an internal horizontal synchronization signal and an internal vertical synchronization signal according to one or more examples of the present disclosure is shown.

[0011] Figure 3A and 3B An exemplary signal masking implemented on an external horizontal synchronization signal according to one or more examples of the present disclosure is shown.

[0012] Figure 4 Showing the use of one or more examples according to the present disclosure Figure 3A and 3B 1 and 2 are exemplary waveforms of an internal horizontal synchronization signal and an internal vertical synchronization signal generated by a signal mask as shown in FIG.

[0013] Figure 5 Exemplary operations of a timing controller according to one or more examples of the present disclosure are shown.

[0014] Figure 6 Exemplary operations of a timing controller suitable for modified signal masking according to one or more examples of the present disclosure are shown.

[0015] Fig. 7A Exemplary operations of a timing controller during vertical synchronization periods each including a duration-adjusted horizontal synchronization period according to one or more examples of the present disclosure are shown.

[0016] Figure 7B Another exemplary operation of a timing controller during vertical synchronization periods each including a horizontal synchronization period whose duration is adjusted according to one or more examples of the present disclosure is shown.

[0017] Figure 8 is a flow chart of an exemplary process for driving a display panel according to one or more examples of the present disclosure.

[0018] To facilitate understanding, the same reference numerals have been used, where possible, to designate elements that are common to the drawings. It is contemplated that elements disclosed in one embodiment may be utilized in other embodiments without specific recitation. Suffixes may be appended to reference numerals to distinguish elements from one another. Unless specifically noted, the drawings referred to herein should not be understood to be drawn to scale. Moreover, for clarity of presentation and explanation, the drawings are generally simplified and details or components are omitted. The drawings and discussion are used to explain the principles discussed below. DETAILED DESCRIPTION

[0019] The following specific embodiments are merely exemplary in nature and are not intended to limit the disclosed technology or the application and use of the disclosed technology. In addition, there is no intention to be bound by any express or implied theory proposed in the above technical field, background technology, summary of the invention or the following specific embodiments.

[0020] In the following detailed description of the embodiments, many specific details are set forth to provide a more thorough understanding of the disclosed technology. However, it will be apparent to one of ordinary skill in the art that the disclosed technology can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0021] As used herein, the term "coupled" means directly connected to or connected through one or more intermediate components or circuits. In addition, throughout this application, ordinals (e.g., first, second, third, etc.) may be used as adjectives of elements (i.e., any nouns in this application). Unless explicitly disclosed, such as by using the terms "before," "after," "single," and other such terms, the use of ordinals is not intended to imply or create any particular ordering of elements, nor is it intended to limit any element to only a single element. Rather, the use of ordinals is intended to distinguish between elements. For example, a first element is different from a second element, and a first element may include more than one element and is after (or before) the second element in the ordering of the elements.

[0022] A display driver configured to drive a display panel (e.g., an LCD panel, an OLED display panel, and a μLED display panel) may be configured to receive an external horizontal synchronization (Hsync) signal and an external vertical synchronization (Vsync) signal from an external controller to operate in synchronization with the external Hsync signal and the external Vsync signal. The external Hsync signal may define the start and end of each horizontal synchronization period (or row period), and the external Vsync signal may define the start and end of each vertical synchronization period (or frame period). The horizontal synchronization period may be defined as the period between the times when two adjacent pulses appear in the external Hsync signal, and the vertical synchronization period may be defined as the period between the times when two adjacent pulses appear in the external Vsync signal.

[0023] The display driver may generate an internal Hsync signal and an internal Vsync signal according to an external Hsync signal and an external Vsync signal, respectively, for internal use. More specifically, the display driver may be configured to generate pulses of the internal Hsync signal in response to detection of pulses in the external Hsync signal and to generate pulses of the internal Vsync signal in response to detection of pulses in the external Vsync signal. The internal Hsync signal and the internal Vsync signal thus generated may be delivered to various circuits in the display driver (e.g., image processing circuits, panel interface circuits, and source drive circuits) to achieve timing control.

[0024] In an actual operating environment, noise (such as electrostatic discharge (ESD) noise) may affect the external Hsync signal and / or the external Vsync signal. The external Hsync signal and / or the external Vsync signal may contain noise-induced pulses, which may cause unexpected pulses to be generated in the internal Hsync signal and / or the internal Vsync signal. The unexpected pulses may cause timing confusion during operation and may cause malfunction of the display device (e.g., image corruption).

[0025] One method for mitigating the effects of noise may be to implement signal masking on the external Hsync signal and / or the external Vsync signal. In one implementation, signal masking may be implemented by preventing the display device from detecting and / or processing pulses in the external Hsync signal and / or the external Vsync signal during the masking period. For example, during signal masking, upon detecting pulses in the external Hsync signal and / or the external Vsync signal, the display device may discard or filter out noise-induced pulses, thereby allowing pulses of the internal Hsync signal and / or the internal Vsync signal to be generated at appropriate timing.

[0026] Some implementations can achieve synchronization between the external Hsync signal and the external Vsync signal by adjusting the duration of a specific one of the horizontal synchronization periods of each vertical synchronization period. A specific one of the horizontal synchronization periods may be referred to as a horizontal synchronization period whose duration is adjusted hereinafter. In ideal operation, it is desirable to generate an external Hsync signal and an external Vsync signal so that the period of the external Vsync signal is exactly an integer multiple of the period of the external Hsync signal (for example, the frequency of the external Hsync signal is exactly an integer multiple of the frequency of the external Vsync signal). However, in actual implementations, the external Hsync signal and the external Vsync signal may be generated by different oscillators with insufficient timing accuracy for pulse generation. In such implementations, the period of the external Vsync signal may be significantly different from the integer multiple of the period of the external Hsync signal. In order to achieve synchronization between the external Hsync signal and the external Vsync signal, the duration of the horizontal synchronization period whose duration is adjusted for each vertical synchronization period may be adjusted so that the end of the last horizontal synchronization period of each vertical synchronization period coincides with the beginning of the next vertical synchronization period. The duration of the horizontal synchronization period whose duration is adjusted may be different from the duration of other horizontal synchronization periods.

[0027] The present disclosure recognizes that the use of a horizontal synchronization period with an adjusted duration may be incompatible with signal masking applied to an external Hsync signal because the signal masking may undesirably discard pulses defining the horizontal synchronization period with an adjusted duration. The present disclosure provides various techniques for properly generating an internal Hsync signal in a display device configured to implement signal masking on an external Hsync signal and / or an external Vsync signal.

[0028] Figure 1 1 is a block diagram showing an exemplary configuration of a display device 1000 according to one or more examples of the present disclosure. In the illustrated embodiment, the display device 1000 includes a display driver 100 and a display panel 200. Examples of the display panel 200 include, but are not limited to, an LCD panel, an OLED display panel, a μLED display panel, and other display panels utilizing suitable display technologies.

[0029] The display driver 100 is configured to receive image data from the image source 300 and drive or update the display panel 200 based on the image data. In the illustrated embodiment, the display driver 100 includes an interface (I / F) 110, an image buffer 120, an image processing circuit 130, and a driving circuit 140. The interface 110 is configured to receive image data from the image source 300 and forward the received image data to the image buffer 120. The image buffer 120 is configured to temporarily store the image data. The image processing circuit 130 is configured to receive image data from the image buffer 120 and process the received image data to generate processed image data. The image processing circuit 130 is further configured to provide the processed image data to the driving circuit 140. The driving circuit 140 is configured to drive or update the display panel 200 based on the processed image data. In one implementation, the driving circuit 140 is configured as a source driver that generates a data voltage based on the processed image data and drives or updates the pixels of the display panel 200 using the generated data voltage.

[0030] The display driver 100 is further configured to receive an external horizontal synchronization (Hsync) signal and an external vertical synchronization (Vsync) signal from an external source 400 and operate in synchronization with the external Hsync signal and the external Vsync signal. The external Hsync signal may define the beginning and end of each horizontal synchronization period (or row period), and the external Vsync signal may define the beginning and end of each vertical synchronization period (or frame period). In some implementations, the external source 400 may be a bridge integrated circuit (IC) or other type of IC configured to interface with the display driver 100. In other implementations, the external source 400 may be a master display driver configured to provide an external Hsync signal and an external Vsync signal to the display driver 100. In such implementations, the display driver 100 may operate as a slave display driver and coordinate with the master display driver to update the display panel 200. Although Figure 1 The external source 400 is illustrated as a separate device from the image source 300 , but the image source 300 and the external source 400 may be formed as a single device.

[0031] In the illustrated embodiment, the display driver 100 further includes an interface 150 and a timing controller 160. The interface 150 is configured to receive an external Hsync signal and an external Vsync signal from an external source 400 and forward the external Hsync signal and the external Vsync signal to the timing controller 160. The timing controller 160 is configured to generate an internal Hsync signal and an internal Vsync signal according to the external Hsync signal and the external Vsync signal, respectively. The internal Hsync signal and the internal Vsync signal are used for timing control in the display driver 100. More specifically, the timing controller 160 is further configured to provide the internal Hsync signal and the internal Vsync signal to the driving circuit 140, thereby controlling the operation timing of the driving circuit 140. The driving circuit 140 is configured to drive the display panel 200 synchronously with the internal Hsync signal and the internal Vsync signal. The timing controller 160 may be further configured to provide the internal Hsync signal and / or the internal Vsync signal to other circuits in the display driver 100, which may include the image processing circuit 130. The image processing circuit 130 may be configured to process image data using an internal Hsync signal and / or an internal Vsync signal.

[0032] In the illustrated embodiment, the timing controller 160 includes a register 165. In some implementations, the register 165 can be configured to store information for controlling the generation of an internal Hsync signal and an internal Vsync signal.

[0033] Figure 2 An exemplary scheme for generating an internal Hsync signal and an internal Vsync signal according to one or more examples of the present disclosure is shown. Figure 2 1 shows an example operation of the timing controller 160 to generate an internal Hsync signal and an internal Vsync signal during vertical synchronization periods 500 and 502, each of which includes a blanking period 410 (also referred to as a backporch period), a display update period 420, and a blanking period 430 (also referred to as a frontporch period). The blanking period may also be referred to as a non-display update period.

[0034] The timing controller 160 is configured to detect pulses of the external Hsync signal and generate pulses of the internal Hsync signal in response to the detection of the external Hsync signal. In some implementations, the timing controller 160 may be configured to generate pulses of the internal Hsync signal after a predetermined delay from the detection of the pulses of the external Hsync signal when the pulses of the external Hsync signal are detected. In other implementations, the timing controller 160 may be configured to generate a number of pulses of the internal Hsync signal that is different from the number of pulses of the external Hsync signal. For example, the timing controller 160 may be configured to generate three pulses of the internal Hsync signal for two pulses of the external Hsync signal.

[0035] The timing controller 160 is further configured to detect a pulse of the external Vsync signal and generate a pulse of the internal Vsync signal in response to the detection of the external Vsync signal. In one implementation, the timing controller 160 may be configured to, upon detecting a pulse of the external Vsync signal, generate a pulse of the internal Vsync signal after a predetermined delay from the detection of the pulse of the external Vsync signal.

[0036] In one or more embodiments, the timing controller 160 is configured to implement signal masking on the external Hsync signal and / or the internal Vsync signal to mitigate the effects of noise (such as electrostatic discharge (ESD) noise) applied to the external Hsync signal and / or the external Vsync signal. The noise may generate unexpected pulses in the external Hsync signal and / or the external Vsync signal, which may cause the generation of unexpected pulses of the internal Hsync signal and / or the internal Vsync signal. The generation of unexpected pulses may cause the display driver 100 to malfunction. The signal masking applied to the external Hsync signal and / or the internal Vsync signal can effectively prevent the generation of unexpected pulses of the internal Hsync signal by the noise.

[0037] Figure 3A 1 shows an exemplary signal masking implemented on an external Hsync signal according to one or more examples of the present disclosure. As previously described, signal masking of the external Hsync signal is implemented by prohibiting the timing controller 160 from detecting any pulses in the external Hsync signal during a masking period, which begins each time the timing controller 160 detects a pulse of the external Hsync signal. Figure 3A6, 622, and 624 are shown, which start when the timing controller 160 detects pulses 610, 612, and 614, respectively, in the external Hsync period. The time duration of the masking period is set so that no pulses are expected to appear in the external Hsync signal during the masking period. In some implementations, the time duration of the masking period (e.g., masking period 620, 622, and 624) can be set to be slightly shorter than the period of the external Hsync period.

[0038] The timing controller 160 discards or rejects any pulses that appear in the external Hsync signal during the masking periods 620, 622, and 624. Figure 3B When a noise-induced pulse 630 appears in the external Hsync signal during the masking period 620 shown in FIG. 1 , the timing controller 160 discards the noise-induced pulse 630 and does not generate a corresponding pulse of the internal Hsync signal.

[0039] After the masking period 620 has expired, the timing controller 160 is allowed to detect pulses of the external Hsync signal. Figure 3A and 3B In the example shown in , after the masking period 620 has expired, the timing controller 160 detects the pulse 612 and generates a pulse of the internal Hsync signal. At the same time, the next masking period 622 starts in response to the detection of the pulse 612. The timing controller 160 is allowed to detect the pulse of the external Hsync signal after the masking period 622 has expired. The timing controller 160 detects the pulse 614 after the masking period 622 has expired, and the next masking period 624 starts in response to the detection of the pulse 614. A similar process is performed each time a pulse is detected in the external Hsync signal.

[0040] The timing controller 160 may also be configured to implement signal masking on the external Vsync signal to prevent unexpected pulses from being generated in the internal Vsync signal due to noise applied to the external Vsync signal. In one implementation, the timing controller 160 may be configured to discard all pulses in the external Vsync signal during a masking period that begins when a previous pulse is detected in the external Vsync signal. The masking period for the external Vsync signal may continue until the count of pulses in the external Hsync signal reaches a predetermined number after the previous pulse is detected. Alternatively, similar to Hysnc, the masking period of the external Vsync may be set to a period slightly shorter than the external Vsync period.

[0041] Figure 4 1 and 12 during vertical synchronization periods 510 and 512 according to one or more examples of the present disclosure. Figure 3A and3B 1 and 2 show exemplary waveforms of the internal Hsync signal and the internal Vsync signal generated by the signal mask. Although noise is applied to the external Hsync signal in the vertical synchronization period 510, the timing controller 160 discards the noise-induced pulse 632, thereby preventing the generation of unexpected pulses in the internal Hsync signal. This can effectively suppress the malfunction of the display driver 100.

[0042] In some implementations, as described above, the external source 400 can be configured to adjust the duration of the horizontal synchronization period whose duration is adjusted for each vertical synchronization period to achieve synchronization of the external Hsync signal with the external Vsync signal. The adjustment of the duration of the horizontal synchronization period whose duration is adjusted can be achieved by adjusting the timing of the generation of the pulse that defines the end of the horizontal synchronization period whose duration is adjusted. The duration of the horizontal synchronization period whose duration is adjusted can be different from the duration of other horizontal synchronization periods. The duration of the horizontal synchronization period whose duration is adjusted for each vertical synchronization period can be adjusted so that the end of the last horizontal synchronization period of each vertical synchronization period coincides with the beginning of the next vertical synchronization period.

[0043] Figure 5 An exemplary operation of the timing controller 160 during vertical sync periods 520 and 522, each including a horizontal sync period 412 with an adjusted duration, according to one or more examples of the present disclosure, is shown. In the illustrated implementation, the horizontal sync period 412 with an adjusted duration is provided in the blanking period 410 of each of the vertical sync periods 520 and 522, because changes in the duration of the horizontal sync period during the display update period 420 may cause artifacts in the image displayed on the display panel 200. In the illustrated embodiment, the horizontal sync period 412 with an adjusted duration is provided at the end of the blanking period 410 of each of the vertical sync periods 520 and 522. In other implementations, the horizontal sync period 412 with an adjusted duration may be provided at any temporal position in the blanking period 410 or 430, except at the end of the blanking period 410. In one implementation, the external source 400 may be configured to count pulses in the external Hsync signal during each vertical synchronization period and initiate a horizontal synchronization period 412 of adjusted duration when the count of pulses in the external Hsync signal after the start of the current vertical synchronization period reaches a predetermined value.

[0044] This disclosure recognizes that Figure 3A , 3B The signal masking described in and 4 may be incompatible with the use of a horizontal synchronization period whose duration is adjusted. In some cases, such as Figure 5, the horizontal synchronization period with adjusted duration may have a short duration (as indicated by "short 1H") such that pulse 642 of the external Hsync period defining the end of the horizontal synchronization period with adjusted duration 412 falls within the masking period that begins when the previous pulse 640 is detected. Note that the previous pulses 640 respectively define the beginning of the horizontal synchronization period with adjusted duration 412. In such a case, the timing controller 160 may fail to detect pulse 642, resulting in the inability to successfully generate a corresponding pulse of the internal Hsync signal. The absence of the corresponding pulse in the internal Hsync signal is caused by Figure 5 ” Absent indication in . The absence of a pulse of the internal Hsync signal corresponding to the pulse 642 of the external Hsync signal may cause image artifacts due to timing control failure. For example, the drive circuit 140 configured to operate synchronously with the internal Hsync signal may not be able to update the horizontal lines of the display panel 200 at the correct timing. In addition, in embodiments in which the masking period of the external Vsync signal is defined based on the count of pulses of the external Hsync signal during each external vertical synchronization period, the timing controller 160 may not be able to detect the pulse 650 in the external Vsync signal, resulting in the corresponding pulse of the internal Vsync signal not being generated, such as Figure 5 The lack of a corresponding pulse of the internal Vsync signal may cause severe image corruption.

[0045] In one or more embodiments, to avoid failing to detect a pulse that defines the end of a horizontal synchronization period whose duration is adjusted, the timing controller 160 is configured to implement a modified signal masking on the external Hsync signal. The modified signal masking defines an unmasked period during which the timing controller 160 is allowed to detect pulses in the external Hsync signal. The timing controller 160 does not discard any pulses in the external Hsync signal during the unmasked period. In some embodiments, each unmasked period begins when the timing controller 160 detects a pulse of the external Hsync signal that defines the beginning of a horizontal synchronization period whose duration is adjusted.

[0046] Figure 6 FIG. 1 shows an exemplary operation of the timing controller 160 suitable for modified signal masking according to one or more examples of the present disclosure. Figure 6In the example shown in , a masking period 720 begins when the timing controller 160 detects a pulse 710 in the external Hsync signal. After the masking period 720 has expired, the timing controller 160 detects a pulse 712 in the external Hsync signal. The timing controller 160 identifies the pulse 712 as a pulse that defines the beginning of a horizontal synchronization period 722 whose duration is adjusted as an unmasked period. In one implementation, the timing controller 160 may make this identification based on a count of pulses in the external Hsync signal after the start of the current vertical synchronization period. In the illustrated embodiment, the entire horizontal synchronization period 722 whose duration is adjusted is defined as an unmasked period during which the timing controller 160 is allowed to detect pulses in the external Hsync signal. Therefore, the timing controller 160 successfully detects a pulse 714 in the external Hsync signal that defines the end of the horizontal synchronization period 722 whose duration is adjusted, and generates a corresponding pulse of the internal Hsync signal in response to the detection of the pulse 714. The detection of pulse 714 also causes a masking period 724 to begin, and after masking period 724 has expired, timing controller 160 detects pulse 716 in the external Hsync signal. A similar process is then performed each time a pulse is detected in the external Hsync signal.

[0047] Fig. 7A An exemplary operation of the timing controller 160 during vertical synchronization periods 530 and 532, each including a horizontal synchronization period 414 with an adjusted duration, is shown according to one or more examples of the present disclosure. In one embodiment, the horizontal synchronization period 414 with an adjusted duration is provided at the end of the blanking period 410 of each vertical synchronization period. The horizontal synchronization period 414 with an adjusted duration may be provided at any time position in the blanking period 410 or 430, except at the end of the blanking period 410.

[0048] In the illustrated embodiment, the timing controller 160 detects a pulse 730 in the external Hsync signal during the vertical synchronization period 530, and generates a pulse 740 of the internal Hsync signal in response to the detection of the pulse 730 in the external Hsync signal. The timing controller 160 further identifies the pulse 730 as a pulse that defines the beginning of the horizontal synchronization period 414 with adjusted duration based on the count of pulses in the external Hsync signal during the vertical synchronization period 530. Since the horizontal synchronization period 414 with adjusted duration is defined as a non-masked period, the timing controller 160 is still allowed to detect a pulse of the external Hsync signal during the horizontal synchronization period 414 with adjusted duration. The timing controller 160 successfully detects a pulse 732 in the external Hsync signal that defines the end of the horizontal synchronization period 414 with adjusted duration, and generates a corresponding pulse 742 of the internal Hsync signal in response to the detection of the pulse 732 in the external Hsync signal. In addition, since the timing controller 160 correctly counts the pulses of the external Hsync signal, the timing controller 160 successfully detects the pulse 750 in the external Vsync signal after the masking period of the external Vsync signal has expired based on the count of the pulses of the external Hsync signal during the vertical synchronization period 530. The timing controller 160 generates a pulse of the internal Vsync signal in response to the detection of the pulse 750 in the external Vsync signal. During the vertical synchronization period 532, a similar operation is performed. Fig. 7A The operation of the timing controller 160 shown in FIG. 1 effectively avoids the occurrence of image artifacts potentially caused by the inability to detect a pulse defining the end of a horizontal synchronization period whose duration is adjusted.

[0049] Figure 7B Another exemplary operation of the timing controller 160 during vertical sync periods 540 and 542, each including a horizontal sync period 414 with adjusted duration, is shown according to one or more examples of the present disclosure. In addition to generating the timing of the pulse 760 of the internal Hsync signal in response to the detection of the pulse 732 in the external Hsync signal defining the end of the horizontal sync period 414 with adjusted duration, Figure 7B The operation shown in Fig. 7A The operations shown in Figure 7B In the embodiment shown in , the timing controller 160 is configured to measure the time interval between two adjacent pulses of the external Hsync signal, except for the pulses defining the beginning and the end of the horizontal synchronization period 414 whose duration is adjusted. The timing controller 160 is further configured to determine the specified time interval P between two adjacent pulses of the internal Hsync signal based on the measured time interval between two adjacent pulses of the external Hsync signal.HI , and the specified time interval P HI Stored in register 165 (in Figure 1 In some implementations, the specified time interval P HI The specified time interval P may be equal to the measured time interval between two adjacent pulses of the external Hsync signal. In embodiments where the number of pulses of the internal Hsync signal is different from the number of pulses of the external Hsync signal, the specified time interval P HI The measured time interval P may be different from the measured time interval between two adjacent pulses of the external Hsync signal. The timing controller 160 is further configured to detect a pulse 730 in the external Hsync signal after the timing controller 160 detects a time interval P equal to the specified time interval P. HI After a period of time of duration P, a pulse 760 of the internal Hsync signal is generated. Note that the pulse 730 of the external Hsync signal defines the beginning of the horizontal synchronization period 414 whose duration is adjusted. In embodiments where the number of pulses of the external Hsync signal is different from the number of pulses of the internal Hsync signal, it may be preferable to use a pulse based on the specified time interval P. HI The generation timing of pulse 760.

[0050] Figure 8 is a flow chart of an exemplary process for driving a display panel according to one or more examples of the present disclosure. Process 800 may be performed by Figure 1 However, it will be appreciated that including Figure 1 A display device with additional and / or fewer components as shown in FIG. 8 may be used to perform process 800 , any of the following steps may be performed in any suitable order, and process 800 may be performed in any suitable environment.

[0051] Process 800 includes, at step 802 , receiving an external horizontal synchronization signal.

[0052] Process 800 also includes, at step 804, responding to a masking period (e.g., Figure 6 The first pulse of the external horizontal synchronization signal (eg, Figure 6 The pulses 712 and 716 shown in FIG. Fig. 7A ) to generate a first pulse of an internal horizontal sync signal (eg, Fig. 7A and 7B The masking period is preceded by the first preceding pulse of the external horizontal sync signal (eg, Figure 6The pulses 710 and 714 shown in FIG. 1 start when they are detected prior to detection of the first pulse of the external horizontal synchronization signal.

[0053] Process 800 also includes, at step 806, responding to a non-masking period (e.g., Figure 6 The second pulse of the external horizontal synchronization signal (eg, Figure 6 The pulse 714 shown in FIG. Fig. 7A and 7B ) to generate a second pulse of the internal horizontal sync signal (eg, Fig. 7A The pulses 742 and Figure 7B The unmasked period is preceded by a second preceding pulse of the external horizontal sync signal (e.g., Figure 6 The pulse 712 shown in FIG. Fig. 7A and 7B The pulse 730 shown in FIG. 1 starts when the pulse 730 is detected before the detection of the second pulse of the external horizontal synchronization signal.

[0054] Process 800 also includes, at step 808, driving the display panel in synchronization with an internal horizontal synchronization signal (eg, Figure 1 ).

[0055] Unless otherwise indicated herein or clearly contradicted by context, the use of the terms "a", "an", "the", "at least one", and similar referents in the context of describing the present invention (especially in the context of the following claims) is to be interpreted as covering both the singular and the plural. Unless otherwise indicated herein or clearly contradicted by context, the use of the term "at least one" followed by a listing of one or more items (e.g., "at least one of A and B") is to be interpreted as meaning one item (A or B) selected from the listed items or any combination of two or more of the listed items (A and B). Unless otherwise indicated, the terms "comprising, including", "having", and "containing" are to be interpreted as open-ended terms (i.e., meaning "including but not limited to"). Unless otherwise indicated herein, the recitation of ranges of values ​​herein is intended merely to serve as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were individually recited herein. Unless otherwise indicated herein or otherwise clearly contradicted with the context, all methods described herein can be performed in any suitable order. Unless otherwise claimed, the use of any and all examples or exemplary language (e.g., "such as") provided herein is only intended to better illustrate the present invention and does not limit the scope of the present invention. The language in this specification should not be interpreted as indicating any unclaimed elements that are necessary for practicing the present invention.

[0056] Exemplary embodiments are described herein. When reading the foregoing description, variations of those exemplary embodiments may become apparent to those of ordinary skill in the art. The inventor expects that the skilled person will adopt such variations when appropriate, and the inventor intends to practice the present invention in other ways except as specifically described herein. Therefore, the present invention includes all modifications and equivalents of the subject matter recorded in the claims attached to the present invention as permitted by applicable law. In addition, unless otherwise indicated herein or otherwise clearly contradictory to the context, the present invention includes any combination of the above-described elements in all possible variations thereof.

Claims

1. A display driver, comprising: A timing controller configured to: Receive external horizontal synchronization signal; as well as generating an internal horizontal synchronization signal based on the external horizontal synchronization signal; as well as A driver circuit configured to drive a display panel in synchronization with the internal horizontal synchronization signal, wherein generating the internal horizontal synchronization signal comprises: generating a first pulse of the internal horizontal synchronization signal in response to detection of a first pulse of the external horizontal synchronization signal after a masking period has expired, wherein the masking period begins when the timing controller detects a first previous pulse of the external horizontal synchronization signal prior to the detection of the first pulse of the external horizontal synchronization signal; and A second pulse of the internal horizontal synchronization signal is generated in response to detection of a second pulse of the external horizontal synchronization signal in a non-masked period, and the non-masked period starts when the timing controller detects a second previous pulse of the external horizontal synchronization signal before the detection of the second pulse of the external horizontal synchronization signal.

2. The display driver according to claim 1, wherein: The timing controller is further configured to discard one or more pulses present in the external horizontal synchronization signal during the masking period.

3. The display driver according to claim 1, wherein: The timing controller is further configured to not discard pulses occurring in the external horizontal synchronization signal during the non-masking period.

4. The display driver according to claim 1, wherein: The non-masked period corresponds to a horizontal synchronization period with adjusted duration, and the horizontal synchronization period with adjusted duration has a duration adjusted so that the end of the last horizontal synchronization period of the first vertical synchronization period including the horizontal synchronization period with adjusted duration coincides with the beginning of the second vertical synchronization period following the first vertical synchronization period.

5. The display driver according to claim 4, wherein: The duration of the horizontal synchronization period whose duration is adjusted is different from the duration of different horizontal synchronization periods of the first vertical synchronization period.

6. The display driver according to claim 4, wherein: The horizontal synchronization period with the adjusted duration is set in the blanking period of the first vertical synchronization period.

7. The display driver according to claim 4, wherein: The timing controller is further configured to determine a time interval between adjacent pulses of the internal horizontal synchronization signal based on the external horizontal synchronization signal, and Wherein, generating the second pulse of the internal horizontal synchronization signal comprises: generating the second pulse after a certain time period has passed after the timing controller detects the second previous pulse, the time period having a duration equal to the determined time interval.

8. The display driver according to claim 1, wherein: The non-masking period starts in response to counting of pulses of the external horizontal synchronization signal reaching a predetermined number.

9. A system comprising: an external source configured to provide an external horizontal synchronization signal; The display driver is configured to: generating an internal horizontal synchronization signal based on the external horizontal synchronization signal; as well as driving the display panel in synchronization with the internal horizontal synchronization signal, Wherein, generating the internal horizontal synchronization signal comprises: generating a first pulse of the internal horizontal synchronization signal in response to detection of a first pulse of the external horizontal synchronization signal after a masking period has expired, wherein the masking period begins when the display driver detects a first previous pulse of the external horizontal synchronization signal prior to the detection of the first pulse of the external horizontal synchronization signal; and A second pulse of the internal horizontal synchronization signal is generated in response to detection of a second pulse of the external horizontal synchronization signal in a non-masked period, and the non-masked period starts when the display driver detects a second previous pulse of the external horizontal synchronization signal before the detection of the second pulse of the external horizontal synchronization signal.

10. The system of claim 9, wherein: The display driver is further configured to discard one or more pulses present in the external horizontal synchronization signal during the masking period.

11. The system of claim 9, wherein: The display driver is further configured to not discard pulses appearing in the external horizontal synchronization signal during the non-masking period.

12. The system of claim 9, wherein: The non-masking period is a horizontal synchronization period whose duration is adjusted, and Wherein, the external source is further configured to adjust the duration of the horizontal synchronization period with adjusted duration so that the end of the last horizontal synchronization period of the first vertical synchronization period including the horizontal synchronization period with adjusted duration coincides with the beginning of the second vertical synchronization period following the first vertical synchronization period.

13. The system of claim 12, wherein: The duration of the horizontal synchronization period whose duration is adjusted is different from the duration of different horizontal synchronization periods of the first vertical synchronization period.

14. The system of claim 12, wherein: The horizontal synchronization period with the adjusted duration is set in the blanking period of the first vertical synchronization period.

15. The system of claim 12, wherein: The display driver is further configured to determine a time interval between adjacent pulses of the internal horizontal synchronization signal based on the external horizontal synchronization signal, and Wherein, generating the second pulse of the internal horizontal synchronization signal includes: generating the second pulse after a time period has passed after the display driver detects the second previous pulse, the time period having a duration equal to the determined time interval.

16. The system of claim 9, wherein: The unmasking period is initiated in response to counting a predetermined number of pulses present in the external horizontal synchronization signal.

17. A method comprising: Receive external horizontal synchronization signal; as well as generating a first pulse of an internal horizontal synchronization signal in response to detection of a first pulse of the external horizontal synchronization signal after a masking period has expired, wherein the masking period begins when a first previous pulse of the external horizontal synchronization signal is detected prior to the detection of the first pulse of the external horizontal synchronization signal; generating a second pulse of the internal horizontal synchronization signal in response to detection of a second pulse of the external horizontal synchronization signal in an unmasked period, the unmasked period beginning when a second previous pulse of the external horizontal synchronization signal is detected prior to the detection of the second pulse of the external horizontal synchronization signal; and The display panel is driven in synchronization with the internal horizontal synchronization signal.

18. The method of claim 17, further comprising discarding one or more pulses occurring in the external horizontal synchronization signal during the masking period.

19. The method of claim 17, wherein: The non-masking period is a horizontal synchronization period whose duration is adjusted, and The method further includes adjusting the duration of the horizontal synchronization period whose duration is adjusted so that the end of the last horizontal synchronization period of the first vertical synchronization period including the horizontal synchronization period whose duration is adjusted coincides with the beginning of the second vertical synchronization period following the first vertical synchronization period.

20. The method of claim 19, wherein: The horizontal synchronization period with the adjusted duration is set in the blanking period of the first vertical synchronization period.

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