Electronic component

Abstract

The invention relates to an electronic component. An electronic component (1) is provided with: a substrate (2); a plurality of multilayer capacitors (10) mounted on the first main surface (2a) of the substrate (2); and a sealing part (11) which is formed of a resin and seals the plurality of laminated capacitors (10), in which a first external electrode (13) and a second external electrode (14) of each laminated capacitor (10) are mounted on the substrate (2) by means of a solder (H), at least parts of adjacent laminated capacitors (10) overlap when viewed from the facing direction of a pair of side surfaces (12e, 12f) of the element body (12) and in the direction along the first main surface (2a) of the substrate (2), and the first external electrode (13) and the second external electrode (14) of each laminated capacitor (10) overlap when viewed from the facing direction of the pair of side surfaces (12e, 12f) of the element body (12). In adjacent laminated capacitors (10), the lamination directions of the plurality of internal electrodes (15A, 15B) are the same, and the distance between adjacent laminated capacitors (10) is less than or equal to 1 / 2 of the height of the laminated capacitors (10) mounted on the substrate (2).

Description

Technical Field

[0001] The present invention relates to an electronic component. Background Art

[0002] As an electronic component, there is known an electronic component including a substrate and a plurality of multilayer capacitors mounted on the substrate (see, for example, Japanese Patent Application Laid-Open No. 2023-101721). The plurality of multilayer capacitors are used, for example, for smoothing purposes and are arranged in parallel on the substrate. Summary of the invention

[0003] When a voltage is applied to a multilayer capacitor, electrostrictive deformation may occur. In a multilayer capacitor, stress may be generated in the element body due to the electrostrictive deformation, and the element body may be damaged. In a multilayer capacitor, if the applied voltage increases, the electrostrictive deformation also increases. Therefore, in electronic components, the voltage applied to the multilayer capacitor is limited, and a high voltage cannot be applied.

[0004] An object of one embodiment of the present invention is to provide an electronic component having improved withstand voltage.

[0005] (1) An electronic component according to one embodiment of the present invention comprises: a substrate; a plurality of multilayer capacitors mounted on a mounting surface of the substrate; and a sealing portion formed of a resin and sealing the plurality of multilayer capacitors, each of the plurality of multilayer capacitors comprising: a body formed by stacking a plurality of dielectric layers and having a pair of end faces and four side faces connecting the pair of end faces; an external electrode arranged in the body; and a plurality of internal electrodes arranged in the body and arranged relative to each other in a stacking direction of the plurality of dielectric layers, the external electrodes of the multilayer capacitor being mounted on the substrate by solder, at least a portion of adjacent multilayer capacitors overlapping when viewed from the relative directions of a pair of side faces of the body and along the mounting surface of the substrate, the stacking directions of the plurality of internal electrodes in adjacent multilayer capacitors being the same, and the distance between adjacent multilayer capacitors being less than 1 / 2 of the height of the multilayer capacitors mounted on the substrate.

[0006] An electronic component according to one embodiment of the present invention includes a sealing portion that seals a plurality of stacked capacitors. Thus, in the electronic component, the electrostrictive deformation of the stacked capacitor can be suppressed by the sealing portion. In addition, in the electronic component, the stacked capacitor is mounted (joined) to the substrate by solder. Therefore, in the electronic component, the stacked capacitor is firmly joined to the substrate, so the electrostrictive deformation of the stacked capacitor can be suppressed.

[0007] In an electronic component, if electrostrictive deformation occurs in a stacked capacitor, the side surface of the element body is deformed. Specifically, due to the electrostrictive deformation, the element body expands in the stacking direction, whereby the side surfaces relative to each other in the stacking direction are deformed (bent) into a convex shape. In addition, the side surfaces relative to each other in a direction orthogonal to the stacking direction are deformed into a concave shape toward the inside of the element body. In view of such a phenomenon, in an electronic component, when viewed from the relative direction of a pair of side surfaces of the element body and along the mounting surface of the substrate, at least a portion of adjacent stacked capacitors overlap, and in adjacent stacked capacitors, the stacking direction is the same. In addition, in the electronic component, the distance between adjacent stacked capacitors is less than 1 / 2 of the height of the stacked capacitor mounted on the substrate. Moreover, in the electronic component, a plurality of stacked capacitors are sealed by a sealing portion. The sealing portion is filled between adjacent stacked capacitors.

[0008] Thus, when a voltage is applied to the stacked capacitor, in each of the adjacent stacked capacitors, a force pressing the sealing portion due to expansion is applied, or a force pulling the sealing portion toward the stacked capacitor side is applied. In the electronic component, the stacking direction of the adjacent stacked capacitors is the same, so the direction of the above-mentioned force in the adjacent stacked capacitors is in the opposite direction. Therefore, in the adjacent stacked capacitors, mutual deformation can be suppressed. Therefore, in the electronic component, the electrostrictive deformation of the stacked capacitor can be suppressed, so a high voltage can be applied. As a result, in the electronic component, an increase in withstand voltage can be achieved.

[0009] (2) In the electronic component of (1) above, the plurality of stacked capacitors have the same structure, shape, and size, and are arranged so as to overlap when viewed from the relative directions of a pair of side surfaces of the element body and along the mounting surface of the substrate. In this structure, opposing forces effectively act on adjacent stacked capacitors. Therefore, in the electronic component, mutual deformation can be more reliably suppressed in adjacent stacked capacitors.

[0010] (3) In the electronic component of (1) or (2) above, the stacked capacitor may be arranged in such a way that the stacking direction of the plurality of internal electrodes is orthogonal to the mounting surface. In this structure, when a voltage is applied to the stacked capacitor, a force that attracts the sealing portion toward the stacked capacitor side is exerted in each of the adjacent stacked capacitors. In the electronic component, the stacking direction of the adjacent stacked capacitors is the same, so the directions of the above-mentioned forces acting in the adjacent stacked capacitors are opposite. Therefore, in the adjacent stacked capacitors, mutual deformation can be suppressed.

[0011] (4) In the electronic component of any one of (1) to (3) above, the number of stacked dielectric layers of the multilayer capacitor may be 100 or more, and the length of the element body in the stacking direction may be 1.0 mm or more. In this structure, electrostrictive deformation is likely to occur in the multilayer capacitor. Therefore, in the case of such a multilayer capacitor, the above structure is particularly effective in improving the withstand voltage.

[0012] (5) In the electronic component of any one of (1) to (4) above, the distance between the mounting surface of the substrate and the element body of the multilayer capacitor facing the mounting surface may be 0.2 mm or less, and a sealing portion may be arranged between the mounting surface and the element body. In this structure, since the entire multilayer capacitor is covered by the sealing portion, the occurrence of electrostrictive deformation in the multilayer capacitor can be further suppressed.

[0013] (6) In the electronic component of any one of (1) to (6) above, the sealing portion may be formed of a silicone resin or an epoxy resin. In this structure, it is possible to satisfactorily suppress the occurrence of electrostrictive deformation in the multilayer capacitor.

[0014] (7) In the electronic component of any one of (1) to (6) above, the height of the sealing portion from the mounting surface may be at least twice the height of the multilayer capacitor mounted on the mounting surface. In this structure, the sealing portion can effectively suppress electrostrictive deformation of the plurality of multilayer capacitors.

[0015] According to one embodiment of the present invention, it is possible to improve the withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a perspective view showing an electronic component.

[0017] Figure 2 It is a top view of the electronic components.

[0018] Figure 3 is a side view of an electronic component.

[0019] Figure 4 This is a three-dimensional diagram of a multilayer capacitor.

[0020] Figure 5 This is an exploded perspective view of a multilayer capacitor.

[0021] Figure 6 yes Figure 1 Cross-sectional view along line VI-VI in FIG.

[0022] Figure 7 This is a diagram of a multilayer capacitor viewed from the lateral direction.

[0023] Figure 8 It is a cross-sectional view of an electronic component according to another embodiment.

[0024] Fig. 9 It is a top view of an electronic component according to another embodiment.

[0025] Fig.10 It is a top view of an electronic component according to another embodiment.

[0026] Fig.11 It is a top view of an electronic component according to another embodiment.

[0027] Fig.12 It is a top view of an electronic component according to another embodiment.

[0028] Fig.13 It is a top view of an electronic component according to another embodiment. DETAILED DESCRIPTION

[0029] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same or corresponding elements are denoted by the same reference numerals, and repeated descriptions are omitted.

[0030] Reference Figure 1 to Figure 3 , the electronic component 1 is described. Figure 1 This is a perspective view of an electronic component according to one embodiment. Figure 2 It is a top view of the electronic components. Figure 3 is a side view of an electronic component.

[0031] like Figure 1 to Figure 3 As shown in FIG. 1 , the electronic component 1 includes a substrate 2, a plurality of multilayer capacitors 10, and a sealing portion 11. The electronic component 1 may also include terminal electrodes. Figure 1 In the embodiment, a first direction D1, a second direction D2 and a third direction D3 are set respectively. Figure 2 In FIG. 1 , the sealing portion 11 is omitted. Figure 3 In FIG. 1 , the sealing portion 11 is indicated by a two-dot chain line.

[0032] The substrate 2 is, for example, a PCB (Printed Circuit Board). The substrate 2 has a first main surface 2a, a second main surface 2b opposite to the first main surface 2a, and a side surface 2c connecting the first main surface 2a and the second main surface 2b. When viewed from the relative direction (third direction D3) between the first main surface 2a and the second main surface 2b, the substrate 2 is, for example, rectangular. The first main surface 2a is a mounting surface on which a plurality of stacked capacitors 10 are mounted. The second main surface 2b constitutes the lower surface (bottom surface) of the electronic component 1. The side surface 2c constitutes the side surface of the electronic component 1.

[0033] like Figure 2As shown, a first pad electrode 3, a second pad electrode 4, a third pad electrode 5, a fourth pad electrode 6, a fifth pad electrode 7 and a sixth pad electrode 8 are provided on the substrate 2. The first pad electrode 3, the second pad electrode 4, the third pad electrode 5, the fourth pad electrode 6, the fifth pad electrode 7 and the sixth pad electrode 8 are, for example, rectangular in shape.

[0034] The first pad electrode 3, the second pad electrode 4, the third pad electrode 5, the fourth pad electrode 6, the fifth pad electrode 7 and the sixth pad electrode 8 are arranged on the first main surface 2a of the substrate 2. The first pad electrode 3 and the second pad electrode 4 are arranged at a predetermined interval in the second direction D2. The third pad electrode 5 and the fourth pad electrode 6 are arranged at a predetermined interval in the second direction D2. The fifth pad electrode 7 and the sixth pad electrode 8 are arranged at a predetermined interval in the second direction D2.

[0035] The first pad electrode 3 , the third pad electrode 5 , and the fifth pad electrode 7 are arranged at predetermined intervals in the first direction D1 . The second pad electrode 4 , the fourth pad electrode 6 , and the sixth pad electrode 8 are arranged at predetermined intervals in the first direction D1 .

[0036] Figure 4 It is a perspective view of the multilayer capacitor 10 . Figure 5 FIG. 1 is an exploded perspective view of the multilayer capacitor 10. Figure 4 and Figure 5 As shown, the multilayer capacitor 10 includes an element body 12, a first external electrode 13, a second external electrode 14, and a plurality of internal electrodes 15A and 15B. In the following description, the three multilayer capacitors 10 are sometimes described separately as a multilayer capacitor 10A, a multilayer capacitor 10B, and a multilayer capacitor 10C. In the present embodiment, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C have the same structure, shape, and size.

[0037] The element body 12 is in the shape of a rectangular parallelepiped. The rectangular parallelepiped shape includes the shape of a rectangular parallelepiped with chamfered corners and ridges, and the shape of a rectangular parallelepiped with rounded corners and ridges. The element body 12 has a pair of end faces 12a, 12b, a pair of main faces (side faces) 12c, 12d, and a pair of side faces 12e, 12f as outer surfaces. The end faces 12a, 12b are opposite to each other. The main faces 12c, 12d are opposite to each other. The side faces 12e, 12f are opposite to each other. The main face 12d is a mounting face, for example, a face opposite to the substrate 2 (first main face 2a) when the multilayer capacitor 10 is mounted on the substrate 2.

[0038] like Figure 5As shown, the element body 12 is formed by stacking a plurality of dielectric layers 16. In the present embodiment, the element body 12 is, for example, stacked with more than 100 dielectric layers 16. The stacking direction of the dielectric layers 16 is the relative direction of a pair of main surfaces 12c and 12d of the element body 12. Each dielectric layer 16 is, for example, composed of a sintered body of a ceramic green sheet containing a dielectric material. The dielectric material, for example, contains dielectric ceramics such as BaTiO3, Ba(Ti,Zr)O3 or (Ba,Ca)TiO3. In the actual element body 12, each dielectric layer 16 is integrated to the extent that the boundaries between the dielectric layers 16 cannot be visually recognized.

[0039] The first external electrode 13 is arranged on one end face 12a side of the element body 12. The second external electrode 14 is arranged on the other end face 12b side of the element body 12. The first external electrode 13 is arranged on the end face 12a, a part of the main faces 12c and 12d, and a part of the side faces 12e and 12f of the element body 12. The second external electrode 14 is arranged on the end face 12b, a part of the main faces 12c and 12d, and a part of the side faces 12e and 12f of the element body 12.

[0040] The first external electrode 13 and the second external electrode 14 are made of a conductive material (for example, Ni or Cu). A plating layer may be formed on the surface of the first external electrode 13 and the second external electrode 14. The plating layer may have a layer structure consisting of a Cu plating layer, a Ni plating layer and a Sn plating layer, or a layer structure consisting of a Ni plating layer and a Sn plating layer.

[0041] The internal electrodes 15A and 15B are arranged in the element body 12. A plurality of the internal electrodes 15A and 15B are arranged. The plurality of internal electrodes 15A are connected to the first external electrode 13. The plurality of internal electrodes 15B are connected to the second external electrode 14. The internal electrodes 15A and 15B are made of a conductive material (such as Ni or Cu). Figure 7 Although seven internal electrodes 15A and 15B are shown as an example, the number of internal electrodes 15A and 15B is not limited to this.

[0042] like Figure 2 As shown, the multilayer capacitor 10A is configured on the first pad electrode 3 and the second pad electrode 4. Specifically, the first external electrode 13 of the multilayer capacitor 10A is configured on the first pad electrode 3, and the second external electrode 14 of the multilayer capacitor 10A is configured on the second pad electrode 4. The first external electrode 13 and the first pad electrode 3 are joined by solder H. The second external electrode 14 and the second pad electrode 4 are joined by solder H.

[0043] The multilayer capacitor 10B is arranged on the third pad electrode 5 and the fourth pad electrode 6. Specifically, the first external electrode 13 of the multilayer capacitor 10B is arranged on the third pad electrode 5, and the second external electrode 14 of the multilayer capacitor 10B is arranged on the fourth pad electrode 6. The first external electrode 13 and the third pad electrode 5 are joined by the solder H. The second external electrode 14 and the fourth pad electrode 6 are joined by the solder H.

[0044] The multilayer capacitor 10C is configured at the fifth pad electrode 7 and the sixth pad electrode 8. Specifically, the first external electrode 13 of the multilayer capacitor 10C is configured at the fifth pad electrode 7, and the second external electrode 14 of the multilayer capacitor 10C is configured at the sixth pad electrode 8. The first external electrode 13 and the fifth pad electrode 7 are joined by solder H. The second external electrode 14 and the sixth pad electrode 8 are joined by solder H.

[0045] In addition, the first pad electrode 3, the third pad electrode 5, and the fifth pad electrode 7 may also be one component (member). That is, the first external electrode 13 of the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may be configured on one pad electrode. The second pad electrode 4, the fourth pad electrode 6, and the sixth pad electrode 8 may also be one component. That is, the second external electrode 14 of the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may also be configured on one pad electrode.

[0046] In addition, the first pad electrode 3, the second pad electrode 4, the third pad electrode 5, the fourth pad electrode 6, the fifth pad electrode 7 and the sixth pad electrode 8 may also be buried in the substrate 2. For example, the first pad electrode 3, the second pad electrode 4, the third pad electrode 5, the fourth pad electrode 6, the fifth pad electrode 7 and the sixth pad electrode 8 may also be flush with the first main surface 2a of the substrate 2.

[0047] In the present embodiment, the stacked capacitor 10A, the stacked capacitor 10B, and the stacked capacitor 10C are arranged at the same position in the second direction D2. That is, the positions of the stacked capacitor 10A, the stacked capacitor 10B, and the stacked capacitor 10C in the second direction D2 are consistent. When observed from the first direction D1 (the relative direction of a pair of side surfaces 12f, 12e and the direction along the first main surface 2a of the substrate 2), the stacked capacitor 10A, the stacked capacitor 10B, and the stacked capacitor 10C overlap each other. That is, when observed from the first direction D1 or the third direction D3, the stacked capacitor 10A, the stacked capacitor 10B, and the stacked capacitor 10C do not protrude in the second direction D2.

[0048] like Figure 6As shown, the stacking directions of the internal electrodes 15A and 15B of the multilayer capacitors 10A, 10B, and 10C are consistent. The multilayer capacitors 10A, 10B, and 10C are arranged so that the stacking directions of the internal electrodes 15A and 15B are along the third direction D3. The multilayer capacitors 10A, 10B, and 10C are arranged so that the stacking directions of the internal electrodes 15A and 15B are orthogonal to the first main surface 2a of the substrate 2.

[0049] like Figure 2 and Figure 3 As shown, the distance P1 between the adjacent multilayer capacitors 10A and 10B is less than 1 / 2 (50%) of the height T1 of the multilayer capacitor 10 (P1 ≤ H1 / 2). In the present embodiment, the distance P1 is the distance between the element bodies 12 of the multilayer capacitor 10A and the element bodies 12 of the multilayer capacitor 10B.

[0050] The distance P2 between the adjacent multilayer capacitors 10B and 10C is equal to or less than 1 / 2 of the height T1 of the multilayer capacitor 10 (P2 ≤ H1 / 2). In the present embodiment, the distance P2 is the distance between the element bodies 12 of the multilayer capacitors 10B and 10C.

[0051] like Figure 3 As shown, in this embodiment, the height T1 of the multilayer capacitor 10 is the length of the element body 12 in the third direction D3 (the distance between the pair of main surfaces 12c and 12d). The height T1 of the multilayer capacitor 10 is the height of the multilayer capacitor 10 when mounted on the substrate 2. The height T1 of the multilayer capacitor 10 is, for example, 1.0 mm or more. In addition, the height T1 of the multilayer capacitor 10 may also be the length of the portion that has the largest dimension in the third direction D3. For example, the height T1 of the multilayer capacitor 10 may also be the length of the first external electrode 13 and the second external electrode 14 in the third direction D3.

[0052] like Figure 7 As shown, in this embodiment, a space S is formed between the first main surface 2a of the substrate 2 and the element body 12 of the multilayer capacitor 10. The distance P3 between the first main surface 2a of the substrate 2 and the element body 12 of the multilayer capacitor 10 is, for example, 0.2 mm or less, preferably 0.1 mm or less.

[0053] like Figure 1 As shown, the sealing portion 11 seals (covers) the plurality of stacked capacitors 10. The sealing portion 11 is, for example, roughly in the shape of a rectangular parallelepiped. The sealing portion 11 is formed of a resin. The resin can be a resin commonly used for potting and molding. The resin is, for example, a silicone resin, an epoxy resin, etc. The sealing portion 11 may be permeable or non-permeable (may also be opaque).

[0054] The sealing portion 11 is provided to protect the multilayer capacitor 10. The sealing portion 11 has a function of suppressing electrostrictive deformation of the multilayer capacitor 10. In addition, the sealing portion 11 has a function of suppressing external force applied to the multilayer capacitor 10, a function of electrically insulating the multilayer capacitor 10 from the outside, and a function of protecting the multilayer capacitor 10 from dust, dirt, etc.

[0055] The sealing portion 11 has a main surface 11 a and four side surfaces 11 b as outer surfaces. The main surface 11 a constitutes the upper surface of the electronic component 1 . The four side surfaces 11 b constitute the side surfaces of the electronic component 1 .

[0056] like Figure 3 As shown, the height T2 of the sealing portion 11 (the distance between the first main surface 2a of the substrate 2 and the main surface 11a of the sealing portion 11) is at least twice the height T1 of the multilayer capacitor 10. Figure 4 As shown, the sealing portion 11 is arranged (filled) in a space S between the first main surface 2 a of the substrate 2 and the element body 12 of the multilayer capacitor 10 .

[0057] As described above, the electronic component 1 of the present embodiment includes the sealing portion 11 that seals the plurality of multilayer capacitors 10. Thus, in the electronic component 1, the electrostrictive deformation of the multilayer capacitor 10 can be suppressed by the sealing portion 11. In addition, in the electronic component 1, the multilayer capacitor 10 is mounted (joined) to the substrate 2 by the solder H. Therefore, in the electronic component 1, the multilayer capacitor 10 is firmly joined to the substrate 2, so that the electrostrictive deformation of the multilayer capacitor 10 can be suppressed.

[0058] In the electronic component 1, if electrostrictive deformation occurs in the stacked capacitor 10, the main surfaces 12c, 12d and the side surfaces 12e, 12f of the element body 12 are deformed. Specifically, due to the electrostrictive deformation, the element body 12 expands in the stacking direction of the internal electrodes 15A, 15B, and thereby the main surfaces 12c, 12d opposite to each other in the stacking direction are deformed (bent) into a convex shape. In addition, the side surfaces 12e, 12f opposite to each other in the direction orthogonal to the stacking direction are deformed into a concave shape toward the inside of the element body 12. In view of such a phenomenon, in the electronic component 1, when viewed from the first direction D1, the adjacent stacked capacitors 10 overlap, and in the adjacent stacked capacitors 10, the stacking directions of the plurality of internal electrodes 15A, 15B are the same. In addition, in the electronic component 1, the distances P1, P2 between the adjacent stacked capacitors 10 are less than 1 / 2 of the height T1 of the stacked capacitor 10 mounted on the substrate 2. Furthermore, in electronic component 1, a plurality of multilayer capacitors 10 are sealed by sealing portion 11. Sealing portion 11 is filled between adjacent multilayer capacitors 10.

[0059] In the electronic component 1 of the present embodiment, the multilayer capacitor 10 is arranged in such a manner that the stacking direction of the plurality of internal electrodes 15A, 15B is orthogonal to the first main surface 2a (mounting surface) of the substrate 2. In this structure, when a voltage is applied to the multilayer capacitor 10, a force that attracts the sealing portion 11 toward the multilayer capacitor 10 side acts in each of the adjacent multilayer capacitors 10. In the electronic component 1, the stacking direction of the adjacent multilayer capacitors 10 is the same, so the directions of the above-mentioned forces acting in the adjacent multilayer capacitors 10 are opposite directions. Therefore, in the adjacent multilayer capacitors 10, mutual deformation can be suppressed. Therefore, in the electronic component 1, the electrostrictive deformation of the multilayer capacitor 10 can be suppressed, so a high voltage can be applied. As a result, in the electronic component 1, an improvement in withstand voltage can be achieved.

[0060] In the electronic component 1 of the present embodiment, the number of stacked dielectric layers 16 of the multilayer capacitor 10 is 100 or more. In the multilayer capacitor 10, the length of the element body 12 in the stacking direction (the relative direction of the pair of main surfaces 12c and 12d) is 1.0 mm or more. In this structure, electrostrictive deformation is likely to occur in the multilayer capacitor 10. Therefore, in the case of such a multilayer capacitor 10, the above structure is particularly effective for improving the withstand voltage.

[0061] In the electronic component 1 of the present embodiment, the distance between the first principal surface 2a of the substrate 2 and the principal surface 12d of the element body 12 of the multilayer capacitor 10 is 0.2 mm or less. In the electronic component 1, the sealing portion 11 is arranged between the first principal surface 2a of the substrate 2 and the principal surface 12d of the element body 12. In this structure, the multilayer capacitor 10 is entirely covered by the sealing portion 11, so that the occurrence of electrostrictive deformation in the multilayer capacitor 10 can be further suppressed.

[0062] In the electronic component 1 of the present embodiment, the sealing portion 11 is formed of a silicone resin or an epoxy resin. In this structure, the occurrence of electrostrictive deformation in the multilayer capacitor 10 can be suppressed favorably.

[0063] In the electronic component 1 of the present embodiment, the height T2 of the sealing portion 11 from the first main surface 2a of the substrate 2 is at least twice the height T1 of the multilayer capacitor 10 mounted on the first main surface 2a of the substrate 2. In this structure, the sealing portion 11 can effectively suppress the electrostrictive deformation of the plurality of multilayer capacitors 10.

[0064] As mentioned above, although embodiment of this invention was described, this invention is not necessarily limited to the said embodiment, Various changes can be made without departing from the range which concerns on this invention.

[0065] In the above embodiment, the substrate 2 is described as an example in which the substrate 2 has a rectangular shape. However, the shape of the substrate 2 is not limited to this.

[0066] In the above embodiment, the sealing portion 11 is described as an example in which the sealing portion 11 has a substantially rectangular parallelepiped shape. However, the shape of the sealing portion 11 is not limited thereto.

[0067] In the above embodiment, the first external electrode 13 and the second external electrode 14 are Figure 4 The embodiment of the structure shown is described as an example. However, the structure of the first external electrode 13 and the second external electrode 14 is not limited to this, and may be, for example, in an L shape.

[0068] In the above embodiment, the embodiment in which the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C have the same structure, shape, and size is described as an example. However, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may have different structures. In this case, the distances P1 and P2 are set based on the multilayer capacitor 10 with the largest height T1.

[0069] In the above embodiment, the embodiment in which the stacked capacitor 10A, the stacked capacitor 10B, and the stacked capacitor 10C are arranged in a manner such that the stacking direction of the internal electrodes 15A and 15B is along the third direction D3 is described as an example. That is, the embodiment in which the stacked capacitor 10A, the stacked capacitor 10B, and the stacked capacitor 10C are arranged in a manner such that the stacking direction of the internal electrodes 15A and 15B is orthogonal to the first main surface 2a of the substrate 2 is described as an example. However, if Figure 8 As shown, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may be arranged so that the stacking direction of the internal electrodes 15A and 15B is along the first direction D1.

[0070] In this structure, when a voltage is applied to the multilayer capacitor 10, a force that presses the sealing portion 11 acts on each of the adjacent multilayer capacitors 10 due to expansion. In the electronic component 1, the stacking directions of the adjacent multilayer capacitors 10 are the same, so the directions of the above-mentioned forces acting on the adjacent multilayer capacitors 10 are opposite. Therefore, in the adjacent multilayer capacitors 10, mutual deformation can be suppressed. Therefore, in the electronic component 1, the electrostrictive deformation of the multilayer capacitor 10 can be suppressed, so a high voltage can be applied. As a result, in the electronic component 1, the withstand voltage can be improved.

[0071] In the above embodiment, the embodiment in which the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C are arranged at the same position in the second direction D2 is described as an example. That is, the embodiment in which the positions of the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C in the second direction D2 are consistent is described as an example. However, the arrangement of the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C is not limited to this.

[0072] like Fig. 9 As shown, in the electronic component 1A, the multilayer capacitors 10A, 10B, and 10C may be arranged in a staggered manner. Fig.10 As shown, in the electronic component 1B, the multilayer capacitor 10A, the multilayer capacitor 10B, and the multilayer capacitor 10C may be arranged so as to be shifted in a stepwise manner in the second direction D2.

[0073] like Fig.11 As shown, in the electronic component 1C, the stacked capacitor 10A, the stacked capacitor 10B, and the stacked capacitor 10C may be arranged in a manner that the intervals between adjacent stacked capacitors 10A, 10B, and 10C are not fixed (in a manner that the intervals are different). In this structure, the distance P1 is the shortest distance between the stacked capacitor 10A and the stacked capacitor 10B. The distance P2 is the shortest distance between the stacked capacitor 10B and the stacked capacitor 10C.

[0074] In the above embodiment, an embodiment in which three multilayer capacitors 10 are installed is described as an example. However, the number of multilayer capacitors 10 in the electronic component is not limited thereto. In the electronic component, the number of multilayer capacitors 10 installed may be two or more. Fig.12 As shown, the electronic component 1D is mounted with six multilayer capacitors 10. In the electronic component 1D, three multilayer capacitors 10 arranged side by side in the first direction D1 are arranged in two rows in the second direction D2.

[0075] Based on the above implementation, Fig.13 As shown, in the electronic component 1E, for example, two multilayer capacitors 10 may be arranged overlapping in the third direction D3. The first external electrodes 13 and the second external electrodes 14 of the two overlapping multilayer capacitors 10 are electrically connected by a bonding member (conductive adhesive, solder) or the like.

[0076] Example

[0077] Hereinafter, the present invention will be described in more detail based on Examples and Comparative Examples, but the present invention is not limited to the following Examples.

[0078] <Production of electronic components>

[0079] (Example 1) As a body of a multilayer capacitor, a body having a length L (distance between a pair of end faces) of 3.2 mm, a width W (distance between a pair of side faces) of 2.5 mm, and a height T (distance between a pair of main faces) of 2.5 mm was used. The thickness of the dielectric layer forming the body of the multilayer capacitor was 4.9 μm. In the internal electrode, the distance to the end face (L-Gap) was 196 μm, and the distance to the side face (W-Gap) was 180 μm. The first external electrode and the second external electrode were formed by forming a sintered layer of Cu, and Ni / Sn was plated on the sintered layer.

[0080] The above-mentioned multilayer capacitor is mounted on a glass epoxy substrate using Sn-Ag-Cu solder. In the electronic component of Example 1, three multilayer capacitors are mounted. The three multilayer capacitors are electrically connected in parallel. The multilayer capacitor is arranged in such a way that the stacking direction of the plurality of internal electrodes is orthogonal to the mounting surface of the substrate. Figure 2 As shown, three stacked capacitors are arranged in a manner that the length L of the element body is consistent. The distance between adjacent stacked capacitors is 45% of the height of the element body. The distance between the element body of the stacked capacitor and the substrate is 0.1 mm. The stacked capacitor is sealed with a silicone resin to form a sealing portion. The height of the sealing portion is 2.1 times the height of the element body. The electronic component of Example 1 is obtained in the above manner.

[0081] (Example 2) An electronic component of Example 2 was obtained by manufacturing an electronic component in the same manner as in Example 1 except that the height of the sealing portion was set to 1.5 times the height of the element body.

[0082] (Example 3) An electronic component of Example 3 was obtained by manufacturing an electronic component in the same manner as in Example 1 except that the height of the sealing portion was set to 1.5 times the height of the element body and the sealing portion was formed of epoxy resin.

[0083] (Example 4) Figure 8 As shown, the electronic component of Example 4 was obtained by manufacturing the electronic component in the same manner as Example 1 except that the stacked capacitor was configured so that the stacking direction of the plurality of internal electrodes was horizontal to the mounting surface of the substrate and the height of the sealing portion was set to 1.5 times the height of the element body.

[0084] (Example 5) An electronic component of Example 4 was obtained by manufacturing an electronic component in the same manner as in Example 1 except that the number of multilayer capacitors was changed to two.

[0085] (Example 6) An electronic component of Example 6 was obtained by manufacturing an electronic component in the same manner as in Example 1 except that the number of multilayer capacitors was changed to two and the height of the sealing portion was changed to 1.5 times the height T of the element body.

[0086] (Example 7) The stacked capacitor and the substrate are joined via a connecting component (metal terminal), the distance between the element body of the stacked capacitor and the substrate is set to 0.8 mm, and the height of the sealing part is set to 1.5 times the height of the element body. Except for this, the electronic component is manufactured in the same manner as in Example 1 to obtain the electronic component of Example 7.

[0087] (Comparative Example 1) An electronic component of Comparative Example 1 was obtained by manufacturing an electronic component in the same manner as in Example 1 except that the sealing portion was not provided.

[0088] (Comparative Example 2) An electronic component of Comparative Example 2 was obtained by manufacturing an electronic component in the same manner as in Example 1 except that the distance between adjacent multilayer capacitors was 70% of the height of the element body and the height of the sealing portion was 1.5 times the height T of the element body.

[0089] (Comparative Example 3) Two of the three stacked capacitors are arranged in such a manner that the stacking direction of the multiple internal electrodes is orthogonal to the mounting surface of the substrate, and the stacking direction of an internal electrode arranged between the two stacked capacitors is arranged in such a manner that the stacking direction of the multiple internal electrodes is horizontal to the mounting surface of the substrate, and the height of the sealing portion is set to 1.5 times the height T of the element body. Except for this, the electronic component is manufactured in the same manner as in Example 1 to obtain the electronic component of Comparative Example 3.

[0090] (Comparative Example 4) An electronic component of Comparative Example 4 was obtained by manufacturing an electronic component in the same manner as in Example 1 except that one multilayer capacitor was mounted and the height of the sealing portion was set to 1.5 times the height T of the element body.

[0091] <Measurement method>

[0092] The voltage at which the electronic component breaks was measured with a voltage of 10 V / sec and a current threshold of 10 mA. Ten voltages were measured for each of the electronic components of Examples 1 to 7 and Comparative Examples 1 to 4, and the median of the voltages was taken as the breakdown voltage. The measurement results are shown in Table 1.

[0093] [Table 1]

[0094]

[0095] In electronic components, the breakdown voltage required as a withstand voltage is 300 V or more, preferably 320 V, and more preferably 340 V or more. As shown in Table 1, in the electronic components of Examples 1 to 7, the breakdown voltage is 300 V or more. In the electronic components of Comparative Examples 1 to 4, the breakdown voltage is less than 300 V. As described above, it is confirmed that the electronic components of Examples 1 to 7 achieve an improvement in withstand voltage.

Claims

1. An electronic component, wherein: have: substrate; A plurality of stacked capacitors mounted on a mounting surface of the substrate; and a sealing portion formed of resin and sealing the plurality of the multilayer capacitors, Each of the plurality of stacked capacitors has: An element body formed by laminating a plurality of dielectric layers and having a pair of end faces and four side faces connecting the pair of end faces; An external electrode, which is disposed on the element body; and a plurality of internal electrodes disposed in the element body and arranged opposite to each other in a stacking direction of the plurality of dielectric layers; The external electrodes of the multilayer capacitor are mounted on the substrate by soldering, When viewed from the direction in which the pair of side surfaces of the element body face each other and along the mounting surface of the substrate, at least a portion of adjacent multilayer capacitors overlap. In the adjacent multilayer capacitors, the stacking direction of the plurality of internal electrodes is the same, The distance between adjacent multilayer capacitors is equal to or less than 1 / 2 of the height of the multilayer capacitor mounted on the substrate.

2. The electronic component according to claim 1, wherein The plurality of stacked capacitors have the same structure, shape and size. The plurality of multilayer capacitors are arranged so as to overlap each other when viewed from the opposing direction of the pair of side surfaces of the element body and along the mounting surface of the substrate.

3. The electronic component according to claim 1 or 2, wherein: The multilayer capacitor is arranged such that the stacking direction of the plurality of internal electrodes is perpendicular to the mounting surface.

4. The electronic component according to claim 1 or 2, wherein: The number of stacked dielectric layers of the multilayer capacitor is 100 or more. The length of the element body in the stacking direction is 1.0 mm or more.

5. The electronic component according to claim 1 or 2, wherein: The distance between the mounting surface of the substrate and the element body of the multilayer capacitor facing the mounting surface is 0.2 mm or less. The sealing portion is arranged between the mounting surface and the element body.

6. The electronic component according to claim 1 or 2, wherein: The resin is silicone resin or epoxy resin.

7. The electronic component according to claim 1 or 2, wherein: A height of the sealing portion from the mounting surface is at least twice a height of the multilayer capacitor mounted on the mounting surface.

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