Multilayer electronic component and manufacturing method thereof

Abstract

The invention provides a multilayer electronic component and a method of manufacturing the same. The multilayer electronic component may include: a body including a plurality of dielectric layers, a first internal electrode, a second internal electrode, and an edge pattern; and an external electrode disposed on the main body. The first internal electrodes and the second internal electrodes may be alternately disposed in a first direction, and the dielectric layer is interposed between the first internal electrodes and the second internal electrodes, and the edge pattern may be disposed at a different position from the first internal electrodes and the second internal electrodes in the first direction, and may be disposed so as not to overlap the first internal electrode or the second internal electrode in the first direction.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0128213 filed on September 25, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0166963 filed on November 27, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to a multilayer electronic component and a method for manufacturing the same. Background Art

[0003] Multilayer ceramic capacitors (MLCC, a type of multilayer electronic component) are chip capacitors that are mounted on and used to charge or discharge circuits of various types of electronic products such as image display devices (including liquid crystal displays (LCDs) and plasma display panels (PDPs)), computers, smartphones, and mobile phones, and various types of electrical products such as on-board chargers (OBC) DC-DC converters for electric vehicles.

[0004] Multilayer ceramic capacitors are used as components in various electronic devices due to their small size, high capacitance, and ease of mounting, and with the miniaturization and high output power of various electronic devices such as computers and mobile devices, the demand for miniaturization and high capacitance of multilayer ceramic capacitors is also increasing.

[0005] According to the trend of miniaturization and high capacitance of multilayer ceramic capacitors, the importance of increasing the capacitance per unit volume of multilayer ceramic capacitors is increasing. As a method of achieving miniaturization and high capacitance of multilayer ceramic capacitors, attempts have been made to increase the number of stacked layers by thinning the thickness of internal electrodes.

[0006] In addition, as the application of automotive electrical components increases, high reliability in various environments is required. In order to ensure high reliability, dispersing the concentration of the electric field by improving the connectivity and thickness uniformity of the inner electrode may play a decisive role. In addition, in order to ensure high reliability in various environments, excellent high temperature load life is required.

[0007] However, when the number of stacked layers is increased by forming thinner internal electrodes, the internal electrodes may be bent or bunched up due to height difference portions in the capacitance forming portion and the edge portion of the multilayer ceramic capacitor, which may cause a problem of deteriorated connectivity of the internal electrodes. In addition, when the number of stacked layers is increased by forming thinner internal electrodes, the spacing distance between the internal electrodes may be reduced, which may cause a decrease in the breakdown voltage (BDV) of the multilayer ceramic capacitor.

[0008] In addition, the phenomenon of electric field concentration in the ends of the inner electrodes may become worse as the inner electrodes or the dielectric layer become thinner, and may become worse when a high voltage is applied. The phenomenon of electric field concentration at the ends of the inner electrodes may be another reason for the breakdown voltage (BDV) of the multilayer ceramic capacitor to decrease. Summary of the invention

[0009] An aspect of the present disclosure is to provide a multilayer electronic component which reduces a phenomenon in which an electric field is concentrated in an end portion of an internal electrode.

[0010] An aspect of the present disclosure is to provide a multilayer electronic component that reduces a step portion between a capacitance forming portion and an edge portion.

[0011] An aspect of the present disclosure is to provide a multilayer electronic component having improved electrostatic capacitance.

[0012] An aspect of the present disclosure is to provide a multilayer electronic component having excellent high temperature load life.

[0013] However, aspects of the present disclosure are not limited to the above and may be more easily understood in the course of describing specific embodiments of the present disclosure.

[0014] According to one aspect of the present disclosure, a multilayer electronic component may include: a body including a plurality of dielectric layers, a first inner electrode, a second inner electrode, and an edge pattern; and an outer electrode disposed on the body. The first inner electrode and the second inner electrode are alternately disposed in a first direction, and the dielectric layer is interposed between the first inner electrode and the second inner electrode, and the edge pattern is disposed at a position different from the first inner electrode and the second inner electrode in the first direction, and is disposed not to overlap with the first inner electrode or the second inner electrode in the first direction.

[0015] According to one aspect of the present disclosure, a method for manufacturing a multilayer electronic component may include: a stacking operation of obtaining a stacked body in the following manner: alternately stacking a first sheet having a first pattern on a first ceramic sheet and a second sheet having a second pattern on a second ceramic sheet in a first direction, and arranging a third sheet having a third pattern on a third ceramic sheet between the first sheet and the second sheet, and the third sheet is stacked so that the third pattern does not overlap with the first pattern or the second pattern in the first direction; a sintering operation of obtaining a main body by sintering the stacked body; and an operation of forming an external electrode on the main body.

[0016] According to one aspect of the present disclosure, a multilayer electronic component may include: a body including a capacitor forming portion, the capacitor forming portion including a plurality of dielectric layers, a first inner electrode and a second inner electrode, the body further including an edge pattern, the edge pattern including a portion disposed in a region outside the capacitor forming portion; and an outer electrode disposed on the body. The first inner electrode and the second inner electrode are alternately disposed in a first direction, and the dielectric layer is interposed between the first inner electrode and the second inner electrode, and in the first direction, the edge pattern is disposed at a position different from the first inner electrode and the second inner electrode.

[0017] One of various effects of the present disclosure is to provide a multilayer electronic component that reduces a phenomenon in which an electric field is concentrated in an end portion of an internal electrode by adjusting a position and a shape of an edge pattern.

[0018] One of various effects of the present disclosure is to provide a multilayer electronic component in which a step portion between a capacitance forming portion and an edge portion is mitigated by adjusting the position and shape of an edge pattern.

[0019] One of various effects of the present disclosure is to provide a multilayer electronic component having improved electrostatic capacitance.

[0020] One of the various effects of the present disclosure is to provide a multilayer electronic component having an excellent high-temperature load life.

[0021] Various beneficial advantages and effects of the present disclosure are not limited to the foregoing and can be more easily understood in the course of describing specific exemplary embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 schematically illustrates a perspective view of a multi-layer electronic assembly according to an example embodiment of the present disclosure; Figure 2A , Figure 2B , Figure 2C and Figure 2D is a plan view schematically illustrating an inner electrode and an edge pattern of a multilayer electronic component according to example embodiments; Figure 3 It is along Figure 1 A schematic cross-sectional view taken along line II' of ; Figure 4 It is along Figure 1 A schematic cross-sectional view taken along line II-II'; Figure 5 It is along Figure 1 A schematic cross-sectional view taken along line III-III'; Figure 6 It is along Figure 1 A schematic cross-sectional view taken along line IV-IV'; Figure 7 is a plan view schematically illustrating a state in which an internal electrode is disposed on a ceramic sheet according to an example embodiment; Figure 8 is a plan view schematically illustrating a state in which an edge pattern is provided on a ceramic sheet according to an example embodiment; Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D is a plan view schematically illustrating an inner electrode and an edge pattern according to an example embodiment; Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D is a plan view schematically illustrating an inner electrode and an edge pattern according to an example embodiment; Fig.11A , Fig. 11B , Fig. 11C and Fig.11D is a plan view schematically illustrating an inner electrode and an edge pattern according to an example embodiment; Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is a plan view schematically illustrating an inner electrode and an edge pattern according to an example embodiment; Fig.13A , Fig. 13B , Fig. 13C and Fig.13D is a plan view schematically illustrating an inner electrode and an edge pattern according to an example embodiment; Fig.14A , Fig. 14B , Fig. 14C and Fig.14D is a plan view schematically illustrating an inner electrode and an edge pattern according to an example embodiment; Fig.15A , Fig. 15B , Fig. 15C and Fig.15D is a plan view schematically illustrating an inner electrode and an edge pattern according to an example embodiment; Fig.16A , Fig. 16B , Fig. 16C and Fig.16D is a plan view schematically illustrating an inner electrode and an edge pattern according to an example embodiment; Fig.17A , Fig. 17B , Fig. 17Cand Fig.17D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments; and Fig.18A , Fig.18B , Fig.18C and Fig.18D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to specific example embodiments and the accompanying drawings. However, embodiments of the present disclosure may be illustrated in many different forms and should not be construed as being limited to the specific embodiments set forth herein. The example embodiments disclosed herein are provided to better explain the present disclosure to those skilled in the art. In the accompanying drawings, for clarity, the shapes and sizes of the elements may be exaggerated, and the same reference numerals will always be used to represent the same or similar elements.

[0024] In addition, in order to clearly illustrate the present disclosure in the drawings, contents irrelevant to the description are omitted, and since the size (e.g., thickness) of each component shown in the drawings is arbitrarily shown for the convenience of description, the present disclosure is not limited thereto. In addition, components having the same functions within the same conceptual scope are described using the same reference numerals. Throughout the specification, unless otherwise specified, when a part "includes" or "contains" a component, this indicates that other components are not excluded and other components may be further included.

[0025] In the drawings, a first direction may be defined as a thickness direction, a second direction may be defined as a length direction, and a third direction may be defined as a width direction.

[0026] Multilayer electronic components Figure 1 A perspective view of a multilayer electronic assembly according to an example embodiment of the present disclosure is schematically shown.

[0027] Figure 2A , Figure 2B , Figure 2C and Figure 2D is a plan view schematically illustrating inner electrodes and edge patterns of a multilayer electronic component according to example embodiments.

[0028] Figure 3 It is along Figure 1 Schematic cross-sectional view taken along line II'.

[0029] Figure 4 It is along Figure 1 Schematic cross-sectional view taken along line II-II'.

[0030] Figure 5 It is along Figure 1 Schematic cross-sectional view taken along line III-III'.

[0031] Figure 6 It is along Figure 1 Schematic cross-sectional view taken along line IV-IV'.

[0032] In the following, reference will be made to Figures 1 to 6 The multilayer electronic component 100 according to an exemplary embodiment of the present disclosure is described in detail. In addition, a multilayer ceramic capacitor (MLCC) will be described as an example of a multilayer electronic component, but the present disclosure is not limited thereto, and the multilayer electronic component 100 can also be applied to various other multilayer electronic components using ceramic materials, such as an inductor, a piezoelectric element, a varistor, or a thermistor.

[0033] A multilayer electronic component 100 according to an example embodiment of the present disclosure may include: a body 110 including a plurality of dielectric layers 111, a first internal electrode 121, a second internal electrode 122, and edge patterns 123 and 124, wherein the first internal electrodes 121 and the second internal electrodes 122 may be alternately disposed in a first direction with the dielectric layer 111 interposed therebetween, and the edge pattern 123 or 124 is disposed at a different position from the first internal electrode 121 and the second internal electrode 122 in the first direction and is disposed not to overlap the first internal electrode 121 or the second internal electrode 122 in the first direction; and external electrodes 131 and 132 disposed on the body 110. In the present disclosure, the internal electrodes may be referred to as internal electrode layers.

[0034] According to an example embodiment of the present disclosure, a multilayer electronic component 100 may include a plurality of dielectric layers 111, a first internal electrode 121, a second internal electrode 122, and edge patterns 123 and 124, and the first internal electrode 121 and the second internal electrode 122 may be alternately arranged in a first direction, and the dielectric layer 111 is interposed between the first internal electrode 121 and the second internal electrode 122, and the edge pattern 123 or 124 may be arranged at a position different from the first internal electrode 121 and the second internal electrode 122 in the first direction, and is arranged not to overlap with the first internal electrode 121 or the second internal electrode 122 in the first direction, so that the phenomenon of electric field concentration in the end of the internal electrode 121 or 122 can be reduced, and the step portion between the capacitance forming portion and the edge portion can be alleviated, thereby improving the electrostatic capacitance and high temperature load life of the multilayer electronic component.

[0035] Hereinafter, each element of the multilayer electronic component 100 will be described in detail.

[0036] The body 110 may include a plurality of dielectric layers 111 , a first internal electrode 121 , a second internal electrode 122 , and edge patterns 123 and 124 .

[0037] There is no particular limitation on the specific shape of the body 110, but Figure 1 As shown, the body 110 may have a hexahedral shape or a shape similar to the hexahedral shape. Due to shrinkage of ceramic powder particles included in the body 110 during a sintering process, the body 110 may not have a hexahedral shape having perfect straight lines but may generally have a hexahedral shape.

[0038] The body 110 may have: a first surface 1 and a second surface 2, which are opposite to each other in a first direction; a third surface 3 and a fourth surface 4, which are connected to the first surface 1 and the second surface 2 and are opposite to each other in the second direction; and a fifth surface 5 and a sixth surface 6, which are connected to the first surface 1 and the second surface 2, connected to the third surface 3 and the fourth surface 4, and are opposite to each other in a third direction.

[0039] Since edge regions of the dielectric layer 111 where the internal electrodes 121 and 122 are not provided overlap each other in the first direction, a step portion due to the thickness of the internal electrodes 121 and 122 may occur, so that when viewed from the first surface or the second surface, a corner connecting the first surface with the third surface to the sixth surface and / or a corner connecting the second surface with the third surface to the sixth surface may have a shape that shrinks toward the center of the body 110 in the first direction. Alternatively, due to shrinkage behavior during the sintering process of the body, when viewed from the first surface 1 or the second surface 2, a corner connecting the first surface 1 with the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6 and / or a corner connecting the second surface 2 with the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6 may have a shape that shrinks toward the center of the body 110 in the first direction. Optionally, in order to prevent peeling defects, the corners of each surface of the connecting body 110 can be rounded by performing a separate process, so that the corners connecting the first surface 1 and the third surface 3 to the sixth surface 6 and / or the corners connecting the second surface 2 and the third surface 3 to the sixth surface 6 can have a rounded shape.

[0040] In addition, in order to suppress the height difference portion caused by the internal electrodes 121 and 122, after the ceramic green sheets are stacked to obtain a stacked body, the stacked body is cut so that the internal electrodes 121 and 122 are exposed to both side surfaces of the capacitor forming portion blank in the third direction (width direction), and then edge portions 114 and 115 are formed by stacking a single dielectric layer or two or more dielectric layers on both side surfaces of the capacitor forming portion blank in the third direction (width direction), so that the portion connecting the first surface 1 to the fifth surface 5 and the portion connecting the first surface 1 to the sixth surface 6 and the portion connecting the second surface 2 to the fifth surface 5 and the portion connecting the second surface 2 to the sixth surface 6 may not have a contracted shape.

[0041] In a state where a plurality of dielectric layers 111 forming the main body 110 are sintered, adjacent dielectric layers 111 can be integrated with each other, making it difficult to identify the boundary between adjacent dielectric layers 111 without using a scanning electron microscope (SEM). The number of dielectric layers 111 is not particularly limited and can be determined in consideration of the size of the multilayer electronic component. For example, the main body 110 can be formed by stacking 400 or more dielectric layers 111.

[0042] The dielectric layer 111 can be formed by: producing a ceramic slurry including ceramic powder particles, an organic solvent, and a binder, coating the ceramic slurry on a carrier film and drying it to prepare a green ceramic sheet, and then firing the green ceramic sheet. The ceramic powder particles are not particularly limited as long as sufficient electrostatic capacitance can be obtained. For example, barium titanate (BaTiO3)-based powder particles can be used as the ceramic powder particles. For a more specific example, the ceramic powder particles can be at least one of BaTiO3, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1), and Ba(Ti 1-y Zr y )O3 (0 < y < 1).

[0043] According to the present disclosure, even when the thickness of the dielectric layer 111 is thin, shortening of the high-temperature load life can be prevented, and when the thickness of the dielectric layer 111 is thick, the high-temperature load life can be further improved, so that the average thickness of the dielectric layer 111 is not particularly limited and can be arbitrarily set according to desired characteristics or purposes. For a specific example, the average thickness of the dielectric layer 111 can be greater than or equal to 300 nm and less than or equal to 10 µm. In addition, the average thickness of at least one of the plurality of dielectric layers 111 can be greater than or equal to 300 nm and less than or equal to 10 µm.

[0044] Here, the average thickness of the dielectric layer 111 may refer to the average size of the dielectric layer 111 disposed between the internal electrodes 121 and 122 in the first direction. The average thickness of the dielectric layer 111 may be measured by scanning the cross-section of the first direction and the second direction of the body 110 with a scanning electron microscope (SEM) at a magnification of 10,000 times and obtaining an image. More specifically, the average value of the thickness of the dielectric layer 111 may be measured by measuring the thickness at a plurality of points (e.g., 30 points spaced apart from each other at equal intervals in the second direction) of one dielectric layer 111 and averaging the measured thickness. 30 points with equal intervals may be specified in the capacitor forming portion Ac described below. In addition, when the average value measurement is extended to 10 dielectric layers 111, the average size of the dielectric layer 111 may be more generalized.

[0045] The internal electrodes 121 and 122 may be alternately disposed with the dielectric layers 111 in the first direction.

[0046] The internal electrodes 121 and 122 may include a first internal electrode 121 and a second internal electrode 122. The first internal electrodes 121 and the second internal electrodes 122 may be alternately disposed to face each other with the dielectric layer 111 interposed therebetween, and the first internal electrodes 121 and the second internal electrodes 122 may extend to the third surface 3 and the fourth surface 4 of the body 110, respectively. Specifically, one end of the first internal electrode 121 may be connected (i.e., extended) to the third surface 3, and one end of the second internal electrode 122 may be connected (i.e., extended) to the fourth surface 4. That is, in example embodiments, the internal electrode 121 or 122 may contact the third surface 3 or the fourth surface 4.

[0047] like FIG. 2A to FIG. 2D As shown in , the first inner electrode 121 may be spaced apart from the fourth surface 4 and may be exposed to the third surface 3, and the second inner electrode 122 may be spaced apart from the third surface 3 and may be exposed to the fourth surface 4. The first outer electrode 131 may be disposed on the third surface 3 of the body 110 and may be connected to the first inner electrode 121, and the second outer electrode 132 may be disposed on the fourth surface 4 of the body 110 and may be connected to the second inner electrode 122.

[0048] That is, the first internal electrode 121 is not connected to the second external electrode 132 but is connected to the first external electrode 131, and the second internal electrode 122 is not connected to the first external electrode 131 but is connected to the second external electrode 132. Therefore, the first internal electrode 121 may be formed to be spaced apart from the fourth surface 4 by a certain distance, and the second internal electrode 122 may be formed to be spaced apart from the third surface 3 by a certain distance. In this case, the first internal electrode 121 and the second internal electrode 122 may be electrically separated from each other by the dielectric layer 111 disposed therebetween.

[0049] The material forming the internal electrodes 121 and 122 is not particularly limited, and any material having excellent conductivity may be used. For example, the internal electrodes 121 and 122 may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0050] In addition, the internal electrodes 121 and 122 may be formed by printing a conductive paste for internal electrodes on a ceramic green sheet, the conductive paste for internal electrodes including one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. The printing method of the conductive paste for internal electrodes may be a screen printing method or a gravure printing method, but the present disclosure is not limited thereto.

[0051] The average thickness of the internal electrodes 121 and 122 is not particularly limited and can be arbitrarily set according to desired characteristics or purposes. For a specific example, the average thickness of the internal electrodes 121 and 122 may be greater than or equal to 300nm and less than or equal to 10µm. In addition, the average thickness of at least one of the plurality of internal electrodes 121 and 122 may be greater than or equal to 300nm and less than or equal to 10µm.

[0052] In order to obtain the average thickness of the internal electrodes 121 and 122, for a total of five internal electrode layers extracted from an image obtained by scanning the length direction and thickness direction (LT) cross sections cut at the center of the width direction of the body 110 with a scanning electron microscope (SEM), the five internal electrode layers including the internal electrode layer at the point where the length center line of the body intersects with the thickness center line of the body, and two internal electrode layers at the top and two internal electrode layers at the bottom based on the internal electrode layer, the average value can be measured by setting five points based on the point where the length center line of the body 110 intersects with the thickness direction center line (including the point and two points to the left and two points to the right at equal intervals with respect to the point as a reference point) and measuring the thickness at each point.

[0053] Reference Figures 3 to 6 , the body 110 may include cover parts 112 and 113 formed above and below the capacitance forming part Ac in the first direction.

[0054] In addition, the capacitance forming portion Ac is a portion contributing to forming capacitance of a capacitor and may be formed by repeatedly stacking a plurality of first internal electrodes 121 and a plurality of second internal electrodes 122 with the dielectric layer 111 interposed therebetween.

[0055] Reference Figures 3 to 6, the covering portions 112 and 113 may include: an upper covering portion 112 disposed above the capacitance forming portion Ac in the first direction; and a lower covering portion 113 disposed below the capacitance forming portion Ac in the first direction.

[0056] The upper covering portion 112 and the lower covering portion 113 may be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the capacitor forming portion Ac in the thickness direction, respectively, and may be substantially used to prevent damage to the internal electrodes due to physical stress and / or chemical stress.

[0057] The upper cover 112 and the lower cover 113 do not include an internal electrode, and may include the same material as that of the dielectric layer 111 .

[0058] That is, the upper cover 112 and the lower cover 113 may include a ceramic material, for example, a barium titanate (BaTiO 3 )-based ceramic material.

[0059] In addition, the thickness of the covering parts 112 and 113 does not need to be particularly limited. For example, the thickness of the covering parts 112 and 113 may be 10 μm to 300 μm. However, in order to more easily achieve miniaturization and high capacitance of multilayer electronic components, the thickness of the covering parts 112 and 113 may be less than or equal to 15 μm.

[0060] The average thickness of the covering portions 112 and 113 may refer to a first direction dimension, and may be a value obtained by averaging the first direction dimensions of the covering portions above or below the capacitance forming portion Ac measured at five points spaced apart from each other at equal intervals.

[0061] Reference Figures 4 to 6 , the edge portions 114 and 115 may be disposed on side surfaces of the capacitance forming portion Ac that are opposite to each other in the third direction.

[0062] The edge portions 114 and 115 may include: a first edge portion 114 disposed on one side surface of the capacitance forming portion Ac in the third direction (ie, the width direction); and a second edge portion 115 disposed on the other side surface of the capacitance forming portion Ac in the third direction (ie, the width direction). That is, the edge portions 114 and 115 may be disposed on two side surfaces of the capacitance forming portion Ac that are opposite to each other in the third direction (ie, the width direction).

[0063] like Figure 5 As shown, the edge portions 114 and 115 may refer to regions between both ends of the first and second internal electrodes 121 and 122 and the outer surface of the body 110 in a cross section obtained by cutting the body 110 in a width direction-thickness direction.

[0064] The edge portions 114 and 115 may substantially serve to prevent damage to the inner electrodes due to physical stress and / or chemical stress.

[0065] The edge portions 114 and 115 may be formed by not coating the conductive paste on regions of the ceramic green sheets where the edge portions are to be formed when forming the internal electrodes by coating the conductive paste on the ceramic green sheets and sintering the conductive paste.

[0066] In addition, in order to suppress the step portion caused by the internal electrodes 121 and 122, the edge portions 114 and 115 can be formed in the following manner: after stacking the ceramic green sheets to obtain a stacked body, the stacked body is cut so that the internal electrodes 121 and 122 are exposed to both side surfaces of the capacitor forming portion blank in the third direction (width direction), and then a single dielectric layer or two or more dielectric layers are stacked on both side surfaces of the capacitor forming portion blank in the third direction (width direction).

[0067] In addition, the width of the edge portions 114 and 115 does not need to be particularly limited. For example, the width of the edge portions 114 and 115 may be 5 μm to 300 μm. However, in order to more easily achieve miniaturization and high capacitance of multilayer electronic components, the average width of the edge portions 114 and 115 may be less than or equal to 15 μm.

[0068] The average width of the edge portions 114 and 115 may refer to an average size of an area in the third direction where the inner electrode is spaced apart from the fifth surface and an average size of an area in the third direction where the inner electrode is spaced apart from the sixth surface, and may be an average value obtained by averaging the third direction dimensions measured at five points on the side surface of the capacitor forming portion Ac that are spaced apart from each other at equal intervals.

[0069] Therefore, in example embodiments, an average size of regions where the internal electrodes 121 and 122 are spaced apart from the fifth surface 5 and the sixth surface 6 in the third direction may each be less than or equal to 15 μm.

[0070] The external electrodes 131 and 132 may be disposed on the third surface 3 and the fourth surface 4 of the body 110 .

[0071] The external electrodes 131 and 132 may include a first external electrode 131 disposed on the third surface 3 of the body 110 and connected to the first internal electrode 121 , and a second external electrode 132 disposed on the fourth surface 4 of the body 110 and connected to the second internal electrode 122 .

[0072] In this example embodiment, a structure in which the multilayer electronic component 100 has two external electrodes 131 and 132 is described, but the number and / or shape of the external electrodes 131 and 132 may be changed according to the shapes of the internal electrodes 121 and 122 and / or other purposes.

[0073] In addition, the external electrodes 131 and 132 may be formed using any material as long as they have conductivity like metal, and a specific material may be determined in consideration of electrical characteristics, structural stability, etc., and further, the external electrodes 131 and 132 may have a multi-layered structure.

[0074] For example, the external electrodes 131 and 132 may include an electrode layer disposed on the body 110 and a plating layer formed on the electrode layer.

[0075] For a more specific example of the electrode layer, the electrode layer may be a sintered electrode layer including a conductive metal and glass, or may be a resin-based electrode layer including a conductive metal and resin.

[0076] In addition, the electrode layer may be in the form of a sintered electrode layer and a resin-based electrode layer sequentially formed on the main body. In addition, the electrode layer may be formed by transferring a sheet including a conductive metal onto the main body, or may be formed by transferring a sheet including a conductive metal onto the sintered electrode layer. In addition, the electrode layer may be formed as a plating layer, or may be a layer formed using a deposition method such as a sputtering method or an atomic layer deposition (ALD) method.

[0077] As the conductive metal included in the electrode layer, any metal material having excellent conductivity may be used without particular limitation. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and alloys thereof.

[0078] The plating layer is used to improve mounting characteristics. The type of the plating layer is not particularly limited, and may be a plating layer including one or more of Ni, Sn, Pd, and alloys thereof, or may be formed of a plurality of layers.

[0079] For a more specific example of the plating layer, the plating layer may be a Ni plating layer or a Sn plating layer, and may be in the form of sequentially forming a Ni plating layer and a Sn plating layer on the electrode layer, or may be in the form of sequentially forming a Sn plating layer, a Ni plating layer, and a Sn plating layer. In addition, the plating layer may include a plurality of Ni plating layers and / or a plurality of Sn plating layers. In addition, the plating layer may be in the form of sequentially forming a Ni plating layer and a Pd plating layer on the electrode layer.

[0080] The size of the multilayer electronic component 100 does not need to be particularly limited. According to the present disclosure, the multilayer electronic component 100 can be advantageously miniaturized and high-capacitance, and thus can be applied to small-sized IT products, and the multilayer electronic component 100 can ensure high reliability under various environments, and thus can be applied to automotive electrical products requiring high reliability.

[0081] According to an example embodiment of the present disclosure, the body 110 may include edge patterns 123 and 124 .

[0082] The edge patterns 123 and 124 may be disposed on the dielectric layer 111 where the internal electrodes 121 and 122 are not disposed, and may serve to alleviate a step portion between a capacitance forming portion and an edge portion.

[0083] Specifically, refer to FIG. 2A to FIG. 2D as well as Figures 3 to 6 , the edge patterns 123 and 124 may be disposed at positions different from the first and second internal electrodes 121 and 122 in the first direction, and may be disposed not to overlap the first and second internal electrodes 121 and 122 in the first direction. The edge patterns 123 and 124 being disposed at positions different from the first and second internal electrodes 121 and 122 in the first direction means that the first direction positions of the edge patterns are different from the first direction positions of the first and second internal electrodes 121 and 122. The first direction positions of the edge patterns 123 and 124 may be located between the first direction position of the first internal electrode 121 and the first direction position of the second internal electrode 122. When viewed in the first direction, the first edge pattern 123 extends along an edge of the first internal electrode 121, and the second edge pattern 124 extends along an edge of the second internal electrode 122.

[0084] Therefore, since the first edge pattern 123 is set in the area where the first internal electrode 121 is not formed, and the second edge pattern 124 is set in the area where the second internal electrode 122 is not formed, the step portion caused by the difference in the stacking degree of the internal electrodes can be effectively alleviated, thereby reducing the phenomenon of electrostatic capacitance reduction caused by deformation of the internal electrodes 121 and 122 and the dielectric layer 111.

[0085] In addition, since the edge patterns 123 and 124 are arranged at different positions from the first and second internal electrodes 121 and 122 in the first direction, the phenomenon of electric field concentration in the ends of the first and second internal electrodes 121 and 122 can be reduced, thereby reducing the phenomenon of insulation breakdown under high voltage.

[0086] Therefore, in a multilayer electronic component according to an example embodiment of the present disclosure, the edge patterns 123 and 124 may be disposed at positions different from the first internal electrode 121 and the second internal electrode 122 in the first direction, and may be disposed not to overlap with the first internal electrode 121 or the second internal electrode 122 in the first direction, thereby improving electrostatic capacitance and high temperature load life.

[0087] In addition, the edge patterns 123 and 124 may preferably include a metal component that is difficult to diffuse into the dielectric layer 111 to improve the effect of compensating the stepped portion, and may preferably include a conductive metal to suppress the phenomenon that the electric field is concentrated in the ends of the internal electrodes 121 and 122. Specifically, the edge patterns 123 and 124 may include the same material as the internal electrodes 121 and 122, for example, the edge patterns 123 and 124 may include the same conductive metal as the conductive metal of the internal electrodes 121 and 122.

[0088] However, the conductive metal included in the edge patterns 123 and 124 is not necessarily the same as the conductive metal included in the internal electrodes 121 and 122, and when the conductive metal included in the edge patterns 123 and 124 is the same as the conductive metal included in the internal electrodes 121 and 122, the effect of alleviating the step portion according to the present disclosure can be further improved.

[0089] Reference FIG. 2A to FIG. 2D , the edge patterns 123 and 124 according to example embodiments may include: a first edge pattern 123 disposed not to overlap the first internal electrode 121 in the first direction; and a second edge pattern 124 disposed not to overlap the second internal electrode 122 in the first direction. Therefore, when viewed in the first direction, the first edge pattern 123 and the second edge pattern 124 may be formed on an edge of the first internal electrode 121 and an edge of the second internal electrode 122, respectively, thereby further improving the step reduction effect (i.e., the effect of alleviating the step portion).

[0090] In example embodiments, at least a portion of the first edge pattern 123 may be disposed to overlap a portion of a region in which the first internal electrode 121 is spaced apart from the fourth surface 4 in the first direction, and at least a portion of the second edge pattern 124 may be disposed to overlap a portion of a region in which the second internal electrode 122 is spaced apart from the third surface 3 in the first direction. Therefore, a phenomenon in which an electric field is concentrated in ends of the first internal electrode 121 and ends of the second internal electrode 122 may be more effectively reduced.

[0091] Reference FIG. 2A to FIG. 2D , the first edge pattern 123 and the second edge pattern 124 may be spaced apart from the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6. Therefore, the first edge pattern 123 and the second edge pattern 124 may be provided so as not to be connected to the external electrodes 131 and 132, and a phenomenon in which an electric field is concentrated in the end portions of the first internal electrode 121 and the end portions of the second internal electrode 122 may be more effectively reduced while alleviating the step portion.

[0092] When the first edge pattern 123 and the second edge pattern 124 are connected to the first external electrode 131 and the second external electrode 132, respectively, the spacing distance between the first edge pattern 123 and the second external electrode 132 and the spacing distance between the second edge pattern 124 and the first external electrode 131 may be short, so there may be concerns about short circuits. In addition, the first edge pattern 123 and the second edge pattern 124 may affect the capacitance and withstand voltage characteristics of the multilayer electronic component 100. Specifically, compared with the first internal electrode 121 and the second internal electrode 122, the first edge pattern 123 and the second edge pattern 124 are easier to bend and have lower connectivity, making it difficult to achieve effective capacitance and withstand voltage. In addition, it may be difficult to reduce the phenomenon that the electric field is concentrated in the ends of the first internal electrode 121 and the ends of the second internal electrode 122.

[0093] The edge patterns 123 and 124 may be disposed not to overlap the internal electrodes 121 and 122 included in the capacitance forming portion Ac, but may be disposed sufficiently adjacent to the first and second internal electrodes 121 and 122 to prevent bending of the internal electrodes and degradation of connectivity of the internal electrodes in the edge portions. That is, the edge patterns 123 and 124 may include portions disposed in an area outside the capacitance forming portion Ac.

[0094] Specifically, when viewed in the first direction, the spacing distance between the first internal electrode 121 and the first edge pattern 123 may be less than or equal to 30 μm, and the spacing distance between the second internal electrode 122 and the second edge pattern 124 may be less than or equal to 30 μm. Therefore, bending of the internal electrode due to the step portion and degradation of connectivity of the internal electrode may be effectively suppressed.

[0095] In addition, the lower limit values ​​of the spacing distance between the first internal electrode 121 and the first edge pattern 123 and the lower limit values ​​of the spacing distance between the second internal electrode 122 and the second edge pattern 124 do not need to be particularly limited, but can be determined considering the printing resolution of the internal electrodes 121 and 122 and the edge patterns 123 and 124.

[0096] Specifically, when viewed in the first direction, the spacing distance between the first inner electrode 121 and the first edge pattern 123 may be greater than or equal to 0.5µm and less than or equal to 30µm, and the spacing distance between the second inner electrode 122 and the second edge pattern 124 may be greater than or equal to 0.5µm and less than or equal to 30µm.

[0097] The spacing distance between the first internal electrode 121 and the first edge pattern 123 and the spacing distance between the second internal electrode 122 and the second edge pattern 124 may represent the spacing distance in the second direction between the internal electrodes 121 and 122 and the edge patterns 123 and 124 in the first and second direction cross sections of the multilayer electronic component. In this case, the spacing distance in the second direction between the internal electrodes 121 and 122 and the edge patterns 123 and 124 in the first and second direction cross sections may be generalized by measuring the distances in the second direction between five internal electrode layers disposed upwardly and five internal electrode layers disposed downwardly relative to the first direction center and the edge patterns corresponding thereto in the first and second direction cross sections polished to the third direction center of the multilayer electronic component, and averaging the measured values.

[0098] In addition, the spacing distance between the first internal electrode 121 and the first edge pattern 123 and the spacing distance between the second internal electrode 122 and the second edge pattern 124 may represent the spacing distance in the third direction between the internal electrodes 121 and 122 and the edge patterns 123 and 124 in the first and third direction cross sections of the multilayer electronic component. In this case, the spacing distance in the third direction between the internal electrodes 121 and 122 and the edge patterns 123 and 124 in the first and third direction cross sections may be generalized by measuring the distances in the third direction between five internal electrode layers disposed upwardly and five internal electrode layers disposed downwardly relative to the center of the first direction and the edge patterns corresponding thereto in the first and third direction cross sections polished to the center of the second direction of the multilayer electronic component, and averaging the measured values.

[0099] In addition, preferably, the first edge pattern 123 and the second edge pattern 124 may be sufficiently spaced apart from the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6 of the body 110 to prevent connection with the external electrodes 131 and 132 and to prevent degradation of moisture resistance reliability. Specifically, in example embodiments, the first edge pattern 123 and the second edge pattern 124 may be spaced apart from the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6 by a distance of 15 μm or more. More preferably, the first edge pattern 123 and the second edge pattern 124 may be spaced apart from the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6 by a distance of 15 μm or more and 150 μm or less.

[0100] The first directional positions of the first edge pattern 123 and the second edge pattern 124 may be determined relative to the first directional positions of the first and second internal electrodes 121 and 122. Specifically, in example embodiments, the first directional position of the first edge pattern 123 may be located between the first directional position of the first internal electrode 121 and the first directional position of the second internal electrode 122, and the first directional position of the second edge pattern 124 may be located between the first directional position of the second internal electrode 122 and the first directional position of the first internal electrode 121.

[0101] In example embodiments, when viewed from the first direction, the first edge pattern 123 may have a shape surrounding the first internal electrode 121, and the second edge pattern 124 may have a shape surrounding the second internal electrode 122. FIG. 2A to FIG. 2D As shown, when observed from the first direction, the shape may represent the following shape: the first edge pattern 123 is arranged to surround the surface of the first internal electrode 121 facing the fourth surface 4, the surface of the first internal electrode 121 facing the fifth surface 5, and the surface of the first internal electrode 121 facing the sixth surface 6, and the second edge pattern 124 is arranged to surround the surface of the second internal electrode 122 facing the third surface 3, the surface of the second internal electrode 122 facing the fifth surface 5, and the surface of the second internal electrode 122 facing the sixth surface 6.

[0102] The width (i.e., the dimension in the third direction) and the length (i.e., the dimension in the second direction) of the edge patterns 123 and 124 may be adjusted relative to the length of the length edge and the width of the width edge, which will be described later. Specifically, when the edge patterns 123 and 124 occupy too large a proportion of the width edge and the length edge, the edge patterns 123 and 124 may be exposed to the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6 of the body 110, and thus the proportion occupied by the remaining width edge and the length edge is insufficient, and the effect of alleviating the step portion may be reduced. Therefore, according to the example embodiment, when the width and the length of the edge pattern are appropriately adjusted in the relationship between the width of the width edge and the length of the length edge, the edge patterns 123 and 124 may be prevented from being exposed to the outside of the body 110, and a sufficient effect of alleviating the step portion may be obtained.

[0103] Specifically, refer to FIG. 2A to FIG. 2D, the area where the first inner electrode 121 is spaced apart from the fifth surface 5 may be defined as a 1-1 width edge, the area where the first inner electrode 121 is spaced apart from the fourth surface 4 may be defined as a first length edge, the third directional dimension of the 1-1 width edge may be defined as WM1, the third directional dimension of a portion of the edge pattern overlapping the 1-1 width edge in the first direction may be defined as WMP1, the second directional dimension of the first length edge may be defined as LM1, and the second directional dimension of a portion of the edge pattern overlapping the 1-1 width edge in the first direction may be defined as LMP1. In the present disclosure, the overlapping relationship of the edge pattern with a specific edge or area in the first direction may be briefly described as the edge pattern overlapping the specific edge or area.

[0104] In this case, when WMP1 / WM1 and LMP1 / LM1 are less than 0.33, the effect of alleviating the step portion may be insufficient because sufficient first edge patterns 123 are not formed. When WMP1 / WM1 and LMP1 / LM1 exceed 0.54, the first edge pattern 123 and the first internal electrode 121 may be formed to overlap each other when viewed from the first direction.

[0105] Therefore, in example embodiments, WMP1 / WM1 and LMP1 / LM1 may satisfy greater than or equal to 0.33 and less than or equal to 0.54, so that the edge patterns 123 and 124 may be prevented from being exposed to the outside of the body 110 and the effect of alleviating the step portion may be obtained.

[0106] On the other hand, when WMP1 / WM1 is greater than or equal to 0.37 and less than or equal to 0.54, and LMP1 / LM1 is greater than or equal to 0.33 and less than or equal to 0.51, the effect of preventing the edge patterns 123 and 124 from being exposed to the outside of the body 110 and the effect of alleviating the step portion may become more significant.

[0107] In addition, refer to FIG. 2A to FIG. 2D, the area where the first inner electrode 121 and the fourth surface 4 are spaced apart from each other is called the first length edge, the area where the second inner electrode 122 and the third surface 3 are spaced apart from each other is called the second length edge, the area where the first inner electrode 121 and the fifth surface 5 are spaced apart from each other is called the 1-1 width edge, the area where the first inner electrode 121 and the sixth surface 6 are spaced apart from each other is called the 1-2 width edge, the area where the second inner electrode 122 and the fifth surface 5 are spaced apart from each other is called the 2-1 width edge, and the area where the second inner electrode 122 and the sixth surface 6 are spaced apart from each other is called the 2-2 width edge, the second direction dimension of the first length edge is denoted as LM1, the second direction dimension of the second length edge is denoted as LM2, the third direction dimension of the 1-1 width edge is denoted as WM1, the third direction dimension of the 1-2 width edge is denoted as WM1', the third direction dimension of the 2-1 width edge is denoted as WM2, and the third direction dimension of the 2-2 width edge is denoted as WM2'. The first width edge includes a 1-1st width edge and a 1-2nd width edge, and the second width edge includes a 2-1st width edge and a 2-2nd width edge.

[0108] In addition, the second directional dimension of the portion of the first edge pattern 123 overlapping the first length edge is represented as LMP1, the second directional dimension of the portion of the second edge pattern 124 overlapping the second length edge is represented as LMP2, the third directional dimension of the portion of the first edge pattern 123 overlapping the 1-1 width edge is represented as WMP1, the third directional dimension of the portion of the first edge pattern 123 overlapping the 1-2 width edge is represented as WMP1', the third directional dimension of the portion of the second edge pattern 124 overlapping the 2-1 width edge is represented as WMP2, and the third directional dimension of the portion of the second edge pattern 124 overlapping the 2-2 width edge is represented as WMP2'.

[0109] In example embodiments, WMP1' / WM1 may satisfy 0.33 or more and 0.54 or less, and preferably 0.37 or more and 0.54 or less. Thus, the effects of preventing the edge patterns 123 and 124 from being exposed to the outside of the body 110 and mitigating the step portion may be improved.

[0110] In example embodiments, WMP2 / WM2 may satisfy 0.33 or more and 0.54 or less, and preferably 0.37 or more and 0.54 or less. Thus, the effects of preventing the edge patterns 123 and 124 from being exposed to the outside of the body 110 and mitigating the step portion may be improved.

[0111] In example embodiments, WMP2' / WM2' may satisfy 0.33 or more and 0.54 or less, and preferably 0.37 or more and 0.54 or less. Thus, the effects of preventing the edge patterns 123 and 124 from being exposed to the outside of the body 110 and mitigating the step portion may be improved.

[0112] In example embodiments, LMP2 / LM2 may satisfy 0.33 or more and 0.54 or less, and preferably 0.33 or more and 0.51 or less. Therefore, the effects of preventing the edge patterns 123 and 124 from being exposed to the outside of the body 110 and mitigating the step portion may be improved.

[0113] In addition, in this specification, for the convenience of explanation, FIG. 2A to FIG. 2D LM1 , LM2 , WM1 , WM1 ′, WM2 , WM2 ′, LMP1 , LPM2 , WMP1 , WMP1 ′, WMP2 , and WMP2 ′ are shown in (a plan view of the inner electrodes and the edge pattern viewed from the first direction).

[0114] LM1, LM2, LMP1 and LPM2 may be average values ​​of corresponding values ​​measured for five internal electrode layers arranged upward and five internal electrode layers arranged downward relative to the center of the first direction and edge patterns corresponding thereto, in first and second direction cross sections polished to the center of the third direction of the multilayer electronic component 100.

[0115] WM1, WM1', WM2, WM2', WMP1, WMP1', WMP2 and WMP2` can be: in the first direction and third direction cross-sections polished to the second direction center of the multilayer electronic component 100, the average values ​​of the corresponding values ​​measured for the five internal electrode layers arranged upward and the five internal electrode layers arranged downward relative to the center of the first direction and the edge patterns corresponding thereto.

[0116] Hereinafter, internal electrodes and edge patterns of the multilayer electronic component 100 according to various embodiments will be described in detail.

[0117] Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0118] Reference Fig. 9A , Fig. 9B , Fig. 9C and Fig.9DAccording to example embodiments, the first inner electrode 121 may include a first inner pattern 121a and a first dummy pattern 121b, the first inner pattern 121a extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6, the first dummy pattern 121b being spaced apart from the first inner pattern 121a and extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second inner electrode 122 may include a second inner pattern 122a and a second dummy pattern 122b, the second inner pattern 122a extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second dummy pattern 122b being spaced apart from the second inner pattern 122a and extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6.

[0119] In this case, the first edge pattern 123 may be disposed to overlap with a region where the first internal electrode 121 is spaced apart from the fifth and sixth surfaces 5 and 6 and a space where the first internal pattern 121a and the first dummy pattern 121b are spaced apart from each other, and the second edge pattern 124 may be disposed to overlap with a region where the second internal electrode 122 is spaced apart from the fifth and sixth surfaces 5 and 6 and a space where the second internal pattern 122a and the second dummy pattern 122b are spaced apart from each other. Therefore, even if the internal electrodes 121 and 122 have a structure including the dummy patterns 121b and 122b, the step portion may be mitigated by forming the edge pattern as a whole in a region where the internal pattern or the dummy pattern is not formed.

[0120] Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0121] Reference Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D According to example embodiments, the first inner electrode 121 may include a 1-1th inner pattern 121c and a 1-2th inner pattern 121d, the 1-1th inner pattern 121c extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6, the 1-2th inner pattern 121d being spaced apart from the 1-1th inner pattern 121c and extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second inner electrode 122 may include a floating pattern 122e spaced apart from the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6.

[0122] In this case, the first edge pattern 123 may be disposed to overlap with a region where the first inner electrode 121 is spaced apart from the fifth surface 5 and the sixth surface 6 and a space where the 1-1st inner pattern 121c and the 1-2nd inner pattern 121d are spaced apart from each other, and the second edge pattern 124 may be disposed to overlap with a space where the second inner electrode 122 is spaced apart from the third surface 3 to the sixth surface 6. Therefore, even if the inner electrode 122 has a structure including the floating pattern 122e, the step portion may be mitigated by forming the edge pattern as a whole in a region where the inner pattern or the floating pattern is not formed.

[0123] Fig.11A , Fig. 11B , Fig. 11C and Fig.11D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0124] Reference Fig.11A , Fig. 11B , Fig. 11C and Fig.11D , when the area where the first inner electrode 121 is spaced apart from the fifth surface 5 is referred to as a 1-1 width edge, the area where the first inner electrode 121 is spaced apart from the sixth surface 6 is referred to as a 1-2 width edge, and the area where the first inner electrode 121 is spaced apart from the fourth surface 4 is referred to as a first length edge, the first edge pattern 123' may be disposed to overlap with one of the 1-1 width edge and the 1-2 width edge and the first length edge in the first direction.

[0125] Similarly, when the area where the second inner electrode 122 is spaced apart from the fifth surface 5 is referred to as the 2-1 width edge, the area where the second inner electrode 122 is spaced apart from the sixth surface 6 is referred to as the 2-2 width edge, and the area where the second inner electrode 122 is spaced apart from the third surface 3 is referred to as the second length edge, the second edge pattern 124' may be set to overlap with one of the 2-1 width edge and the 2-2 width edge and the second length edge in the first direction.

[0126] In this case, when the first edge pattern 123' is arranged to overlap the 1-2 width edge in the first direction, the second edge pattern 124' may be arranged to overlap the 2-1 width edge in the first direction, and when the first edge pattern 123' is arranged to overlap the 1-1 width edge in the first direction, the second edge pattern 124' may be arranged to overlap the 2-2 width edge in the first direction. Therefore, the first edge pattern 123' and the second edge pattern 124' may be prevented from overlapping each other in the width edge in the first direction, thereby alleviating the step portion caused by the overlap of the edge patterns 123' and 124' in the first direction.

[0127] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0128] Fig.13A , Fig. 13B , Fig. 13C and Fig.13D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0129] Even when the internal electrodes 121 and 122 have the dummy patterns 121 b and 122 b or the floating pattern 122 e, a structure in which the first edge pattern 123 ′ is disposed to overlap one of the 1-1 width edge and the 1-2 width edge and the first length edge in the first direction, and a structure in which the second edge pattern 124 ′ is disposed to overlap one of the 2-1 width edge and the 2-2 width edge and the second length edge in the first direction may be applied.

[0130] Reference Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D According to example embodiments, the first inner electrode 121 may include a first inner pattern 121a and a first dummy pattern 121b, the first inner pattern 121a extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6, the first dummy pattern 121b being spaced apart from the first inner pattern 121a and extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second inner electrode 122 may include a second inner pattern 122a and a second dummy pattern 122b, the second inner pattern 122a extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second dummy pattern 122b being spaced apart from the second inner pattern 122a and extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6.

[0131] In this case, according to the example embodiment, the first edge pattern 123' may be disposed to overlap with one of the 1-1 width edge and the 1-2 width edge and a region where the first inner pattern 121a and the first dummy pattern 121b are spaced apart from each other in the first direction, and the second edge pattern 124' may be disposed to overlap with one of the 2-1 width edge and the 2-2 width edge and a region where the second inner pattern 122a and the second dummy pattern 122b are spaced apart from each other.

[0132] Reference Fig.13A , Fig. 13B , Fig. 13C and Fig.13D According to example embodiments, the first inner electrode 121 may include a 1-1th inner pattern 121c and a 1-2th inner pattern 121d, the 1-1th inner pattern 121c extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6, the 1-2th inner pattern 121d being spaced apart from the first inner pattern 121c and extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second inner electrode 122 may include a floating pattern 122e spaced apart from the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6.

[0133] In this case, the first edge pattern 123' according to example embodiments may be disposed to overlap one of the 1-1th and 1-2th width edges and a region where the 1-1th and 1-2th inner patterns 121c and 121d are spaced apart from each other in the first direction.

[0134] In addition, Fig. 13B , the first edge pattern 123' disposed on one dielectric layer 111 is represented as having a structure overlapping the 1-1 width edge in the first direction, and the first edge pattern 123' disposed on another dielectric layer may have a structure overlapping the 1-2 width edge in the first direction. In addition, in example embodiments, since the second inner electrode 122 includes the floating pattern 122e, the second edge pattern 124 may be disposed to overlap at least one of a region in which the second inner electrode 122 is spaced apart from the third surface 3, a region in which the second inner electrode 122 is spaced apart from the fourth surface 4, a region in which the second inner electrode 122 is spaced apart from the fifth surface 5, and a region in which the second inner electrode 122 is spaced apart from the sixth surface 6 in the first direction.

[0135] Fig.14A , Fig. 14B , Fig. 14C and Fig.14D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0136] Reference Fig.14A , Fig. 14B , Fig. 14C and Fig.14D In example embodiments, the internal electrodes 121 and 122 may include: main portions 121-1 and 122-1, which are regions where the first and second internal electrodes 121 and 122 overlap each other in a first direction to form a capacitor; and lead portions 121-2 and 122-2, which have a size in a third direction larger than that of the main portions in the third direction and extend from the main portions 121-1 and 122-1 to the third surface 3 or the fourth surface 4.

[0137] Therefore, the step portion occurring due to the edge patterns 123 and 124 not being formed in the region of the dielectric layer 111 close to the third surface 3 or the fourth surface 4 can be alleviated by arranging the lead portions 121-2 and 122-2 to have a size in the third direction larger than the size in the third direction of the main portions 121-1 and 122-1.

[0138] Fig.15A , Fig. 15B , Fig. 15C and Fig.15D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0139] Reference Fig.15A , Fig. 15B , Fig. 15C and Fig.15D According to example embodiments, the first inner electrode 121 may include a first inner pattern 121a and a first dummy pattern 121b, the first inner pattern 121a extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6, the first dummy pattern 121b being spaced apart from the first inner pattern 121a and extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second inner electrode 122 may include a second inner pattern 122a and a second dummy pattern 122b, the second inner pattern 122a extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second dummy pattern 122b being spaced apart from the second inner pattern 122a and extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6.

[0140] The first internal pattern 121a may include a main portion 121a-1 and a lead portion 121a-2, the main portion 121a-1 being a region where the first internal pattern and the second internal pattern overlap each other in the first direction, the lead portion 121a-2 having a size in the third direction greater than that of the main portion 121a-1 in the third direction and extending from the main portion 121a-1 to the third surface 3, and the first dummy pattern 121b may include a main portion 121b-1 and a lead portion 121b-2, the size in the third direction greater than that of the main portion 121b-1 in the third direction and extending from the main portion 121b-1 to the fourth surface 4.

[0141] Similarly, the second internal pattern 121b may include a main portion 122a-1 and a lead portion 122a-2, the main portion 122a-1 being a region where the first internal pattern and the second internal pattern overlap each other in the first direction, the lead portion 122a-2 having a size in the third direction greater than that of the main portion 122a-1 in the third direction and extending from the main portion 122a-1 to the fourth surface 4, and the second dummy pattern 122b may include the main portion 122b-1 and a lead portion 122b-2 connected to the main portion 122b-1, the lead portion 122b-2 having a size in the third direction greater than that of the main portion 122b-1 in the third direction and extending from the main portion 122b-1 to the third surface 3.

[0142] In this case, in an example embodiment, the first edge pattern 123 may be disposed to overlap with the 1-1 width edge and the 1-2 width edge in the first direction and a region where the first inner pattern 121a and the first dummy pattern 121b are spaced apart from each other, and the second edge pattern 124 may be disposed to overlap with the 2-1 width edge and the 2-2 width edge in the first direction and a region where the second inner pattern 122a and the second dummy pattern 122b are spaced apart from each other.

[0143] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0144] According to example embodiments, the first inner electrode 121 may include a 1-1th inner pattern 121c and a 1-2th inner pattern 121d, the 1-1th inner pattern 121c extending to the third surface 3 and spaced apart from the fourth surface 4, the fifth surface 5, and the sixth surface 6, the 1-2th inner pattern 121d being spaced apart from the 1-1th inner pattern 121c and extending to the fourth surface 4 and spaced apart from the third surface 3, the fifth surface 5, and the sixth surface 6, and the second inner electrode 122 may include a floating pattern 122e spaced apart from the third surface 3, the fourth surface 4, the fifth surface 5, and the sixth surface 6.

[0145] The 1-1st internal pattern 121c may include a main portion 121c-1 and a lead portion 121c-2, the lead portion 121c-2 having a size in the third direction larger than that of the main portion 121c-1 and extending from the main portion 121c-1 to the third surface 3, and the 1-2nd internal pattern 121d may include a main portion 121d-1 and a lead portion 121d-2, the lead portion 121d-2 having a size in the third direction larger than that of the main portion 121d-1 and extending from the main portion 121d-1 to the fourth surface 4.

[0146] In this case, the first edge pattern 123 according to example embodiments may be disposed to overlap the 1-1th and 1-2th width edges and a region where the 1-1th and 1-2th inner patterns 121c and 121d are spaced apart from each other in the first direction.

[0147] In this case, the second edge pattern 124 may be set to overlap in the first direction with at least one of a region where the second internal electrode 122 is spaced apart from the third surface 3, a region where the second internal electrode 122 is spaced apart from the fourth surface 4, a region where the second internal electrode 122 is spaced apart from the fifth surface 5, and a region where the second internal electrode 122 is spaced apart from the sixth surface 6.

[0148] Fig.17A , Fig. 17B , Fig. 17C and Fig.17D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0149] Reference Fig.17A , Fig. 17B , Fig. 17C and Fig.17D , the edge patterns 123'' and 124'' according to the example embodiment may include a plurality of spaced apart patterns. Therefore, the edge patterns 123'' and 124'' may be formed in at least one region of the length edge and the width edge, which may alleviate the step portion and simultaneously improve the adhesion between the dielectric layers 111, so that the electrostatic capacitance and high temperature load life of the multilayer electronic component 100 may be improved, while the strength of the multilayer electronic component 100 itself may be improved.

[0150] Fig.18A , Fig.18B , Fig.18C and Fig.18D is a plan view schematically illustrating an inner electrode and an edge pattern according to example embodiments.

[0151] Reference Fig.18A , Fig.18B , Fig.18C and Fig.18D , the edge patterns 123''' and 124''' according to example embodiments may not be set to overlap with the length edge, but may be set to overlap with only the width edge. That is, when the area where the first inner electrode 121 is spaced apart from the fifth surface and the sixth surface is referred to as the first width edge, the area where the first inner electrode 121 is spaced apart from the fourth surface is referred to as the first length edge, the area where the second inner electrode 122 is spaced apart from the fifth surface and the sixth surface is referred to as the second width edge, and the area where the second inner electrode 122 is spaced apart from the third surface is referred to as the second length edge, the first edge pattern 123''' and the second edge pattern 124''' may be set to overlap with the first width edge and the second width edge, and may be set not to overlap with the first length edge and the second length edge. In this case, the edge patterns 123''' and 124''' may have a straight line shape when viewed from the stacking direction. In addition, as Fig.18A , Fig.18B , Fig.18C and Fig.18D As shown, the edge patterns 123''' and 124''' may be disposed to overlap the width edges of both sides, but the present disclosure is not limited thereto, and the edge patterns 123''' and 124''' may be disposed to overlap the width edge of only either side.

[0152] Method for producing a multilayer electronic component Figure 7 is a plan view schematically illustrating a state in which an internal electrode is disposed on a ceramic sheet according to example embodiments.

[0153] Figure 8 is a plan view schematically illustrating a state in which an edge pattern is provided on a ceramic sheet according to an exemplary embodiment.

[0154] In the following, reference will be made to Figure 7 and Figure 8 A method for manufacturing a multi-layer electronic component according to an example embodiment of the present disclosure is described.

[0155] The method for manufacturing a multilayer electronic component according to an example embodiment of the present disclosure may include: a stacking operation of obtaining a stacked body in the following manner, alternately stacking a first sheet having a first pattern 221 disposed on a first ceramic sheet 211 and a second sheet having a second pattern 222 disposed on a second ceramic sheet 212 in a first direction, and disposing a third sheet having third patterns 223 and 224 disposed on third ceramic sheets 213 and 214 between the first sheet and the second sheet, and stacking the third sheet so that the third pattern does not overlap with the first pattern or the second pattern in the first direction; a sintering operation of obtaining a body 110 by sintering the stacked body; and an operation of forming external electrodes on the body. In the present disclosure, a ceramic sheet refers to a ceramic green sheet.

[0156] The ceramic sheets 211 , 212 , 213 , and 214 may be divided into a first ceramic sheet 211 , a second ceramic sheet 212 , a 3-1st ceramic sheet 213 , and a 3-2nd ceramic sheet 214 .

[0157] The ceramic sheets 211 , 212 , 213 , and 214 may be formed using a ceramic paste including ceramic powder particles, an organic solvent, a dispersant, and a binder. The ceramic powder particles may include a raw material for forming the dielectric layer 111 of the multilayer electronic component 100 .

[0158] Reference Figure 7 , the first pattern 221 may be disposed on the first ceramic sheet 211 , and the second pattern 222 may be disposed on the second ceramic sheet 212 .

[0159] An example of a method for forming the first pattern 221 and the second pattern 222 may include screen printing or gravure printing a conductive paste including a conductive metal on the first ceramic sheet 211 and the second ceramic sheet 212, but the present disclosure is not limited thereto, and the conductive metal may be deposited on the first ceramic sheet 211 and the second ceramic sheet 212 using a thin film deposition method such as a sputtering method or a vacuum deposition method.

[0160] The first pattern 221 and the second pattern 222 may include a conductive metal. The conductive metal is not particularly limited, and any metal material having excellent conductivity may be used. For example, the conductive metal may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0161] The first pattern 221 and the second pattern 222 may be a plurality of patterns disposed to be spaced apart from each other by a certain interval in a direction perpendicular to the stacking direction.

[0162] The first pattern 221 may be sintered to form the first internal electrode 121 , and the second pattern 222 may be sintered to form the second internal electrode 122 .

[0163] In the stacking step according to an example embodiment of the present disclosure, a third sheet having third patterns 223 and 224 disposed on the third ceramic sheets 213 and 214 may be disposed between the first sheet and the second sheet.

[0164] In this case, the first and second sheets may be stacked to be offset by the distance between adjacent cutting lines CL in the second direction, and the third sheet may be stacked such that the third patterns 223 and 224 do not overlap the first pattern 221 or the second pattern 222 .

[0165] Reference Figure 8, when viewed from the stacking direction, the third patterns 223 and 224 may surround the first pattern 221 and the second pattern 222. However, the third patterns 223 and 224 may have a shape that does not overlap with the first pattern 221 and the second pattern 222 when viewed from the stacking direction. However, when viewed from the first direction, each of the patterns forming the third patterns 223 and 224 may not completely surround the first pattern 221 and the second pattern 222. Specifically, each unit pattern in the third patterns 223 and 224 may be arranged to be divided into two patterns based on a cutting line CL described below, and may be a shape that is symmetrical to each other based on the cutting line CL.

[0166] In addition, the third patterns 223 and 224 may preferably include a component that is difficult to diffuse into the ceramic sheets 211, 212, 213, and 214 to improve the effect of compensating the stepped portion, and may preferably include a conductive metal to suppress the phenomenon that the electric field is concentrated in the ends of the internal electrodes 121 and 122. Specifically, the edge patterns 223 and 224 and the internal electrodes 121 and 122 may include the same material, for example, the third patterns 223 and 224 may include the same conductive metal as the first and second patterns 221 and 222.

[0167] However, the conductive metal included in the third patterns 223 and 224 is not necessarily the same as the conductive metal included in the first pattern 221 and the second pattern 222, but when the conductive metal included in the third patterns 223 and 224 is the same as the conductive metal included in the first pattern 221 and the second pattern 222, the effect of reducing the step portion according to the present disclosure can be further improved.

[0168] Reference Figure 8 The third patterns 223 and 224 may be disposed and stacked on a ceramic sheet (third ceramic sheet) different from the ceramic sheets (first ceramic sheet and second ceramic sheet) on which the first patterns 221 and the second patterns 222 for forming the internal electrodes 121 and 122 are disposed and then sintered, and thus the sintered third patterns 223 and 224 may be disposed at positions different from the first and second internal electrodes 121 and 122 in the first direction, thereby forming edge patterns 123 and 124 so that the edge patterns 123 and 124 do not overlap with the first internal electrode 121 or the second internal electrode 122 in the first direction.

[0169] After the stacking operation, the first to third sheets may be formed into a stacked body, and then, a cutting operation of cutting along a cutting line CL may be performed. Figure 7 The cutting line CL and Figure 8The cutting line CL may be the same cutting line. The cutting line CL may be a straight line passing through the center of each pattern forming the first pattern 221 and the second pattern 222 and a straight line passing through the center of a space in which the respective patterns are spaced apart from each other, but may be deviated according to a process.

[0170] After the cutting operation, a sintering operation for obtaining a body by sintering the stacked body may be performed.

[0171] The temperature in the sintering operation is not particularly limited, but sintering may be performed, for example, at 1000° C. to 1300° C. Furthermore, sintering may be performed under a reducing atmosphere.

[0172] After the sintering operation, an operation of forming the external electrodes 131 and 132 on the body 110 may be performed.

[0173] The external electrodes 131 and 132 may be formed by transferring a sheet including a conductive metal, or by a method of sequentially forming a sintered electrode layer and a resin-based electrode layer including a conductive metal and a resin on a stacked body.

[0174] The third sheet may include a 3-1 sheet having a 3-1 pattern 223 disposed on a 3-1 ceramic sheet 213 and a 3-2 sheet having a 3-2 pattern 224 disposed on a 3-2 ceramic sheet 214, and the stacking operation may include an operation of alternately stacking the 3-1 sheet and the 3-2 sheet in the first direction. Therefore, as a result of sequentially stacking the first sheet, the 3-1 sheet, the second sheet, and the 3-2 sheet, the 3-1 pattern 223 forming the first edge pattern 123 after sintering may be disposed not to overlap the first pattern 221 in the first direction, and the 3-2 pattern 224 forming the second edge pattern 124 after sintering may be disposed not to overlap the second pattern 222 in the first direction. That is, in example embodiments, the 3-1 pattern may be disposed not to overlap the first pattern in the first direction, and the 3-2 pattern may be disposed not to overlap the second pattern in the first direction.

[0175] In example embodiments, when viewed in the first direction, a spacing distance between the first pattern 221 and the 3-1st pattern 223 may be 30µm or less, and a spacing distance between the second pattern 222 and the 3-2nd pattern 224 may be 30µm or less. Therefore, after sintering, when viewed in the first direction, a spacing distance between the first inner electrode 121 and the first edge pattern 123 may be 30µm or less, and a spacing distance between the second inner electrode 122 and the second edge pattern 124 may be 30µm or less.

[0176] In example embodiments, when viewed in the first direction, a spacing distance between the first pattern 221 and the 3-1 pattern 223 may be greater than or equal to 0.5µm and less than or equal to 30µm, and a spacing distance between the second pattern 222 and the 3-2 pattern 224 may be greater than or equal to 0.5µm and less than or equal to 30µm. Therefore, after sintering, when viewed in the first direction, a spacing distance between the first inner electrode 121 and the first edge pattern 123 may be greater than or equal to 0.5µm and less than or equal to 30µm, and a spacing distance between the second inner electrode 122 and the second edge pattern 124 may be greater than or equal to 0.5µm and less than or equal to 30µm.

[0177] Although the exemplary embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited to the above embodiments and the accompanying drawings, but is defined by the appended claims. Therefore, those of ordinary skill in the art may make various substitutions, modifications or variations without departing from the scope of the present disclosure defined by the appended claims, and these substitutions, modifications or variations should be interpreted as being included within the scope of the present disclosure.

[0178] In addition, the expression "embodiment" used in the present disclosure does not mean the same embodiment, but is provided to emphasize and explain different features. The embodiment presented above does not exclude the combination of features with another embodiment. For example, although the content described in a specific embodiment is not described in another embodiment, unless there is a description contrary to or contradictory to the content in another embodiment, the content can be understood as a description related to another embodiment.

[0179] In the present disclosure, the terms are used only to describe specific embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, a singular form may also include a plural form.

Claims

1. A multilayer electronic component comprising: a body including a plurality of dielectric layers, a first inner electrode, a second inner electrode, and an edge pattern; as well as an outer electrode, disposed on the body, wherein the first internal electrodes and the second internal electrodes are alternately arranged in a first direction, and the dielectric layer is interposed between the first internal electrodes and the second internal electrodes, and The edge pattern is disposed at a different position from the first and second internal electrodes in the first direction, and is disposed not to overlap the first or second internal electrodes in the first direction.

2. The multilayer electronic component according to claim 1, wherein The edge pattern includes: a first edge pattern disposed not to overlap the first internal electrode in the first direction; and a second edge pattern disposed not to overlap the second internal electrode in the first direction, and The first edge patterns and the second edge patterns are alternately arranged in the first direction.

3. The multilayer electronic component according to claim 2, wherein: The body has a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposite to each other in the third direction.

4. The multilayer electronic component according to claim 3, wherein: The first inner electrode extends to the third surface and is spaced apart from the fourth surface, the fifth surface, and the sixth surface, The second inner electrode extends to the fourth surface and is spaced apart from the third surface, the fifth surface, and the sixth surface, and The first edge pattern and the second edge pattern are spaced apart from the third to sixth surfaces.

5. The multilayer electronic component according to claim 4, wherein: When viewed in the first direction, a spacing distance between the first internal electrode and the first edge pattern is less than or equal to 30 μm, and a spacing distance between the second internal electrode and the second edge pattern is less than or equal to 30 μm.

6. The multilayer electronic component according to claim 4, wherein: When viewed in the first direction, a spacing distance between the first inner electrode and the first edge pattern is greater than or equal to 0.5 µm and less than or equal to 30 µm, and a spacing distance between the second inner electrode and the second edge pattern is greater than or equal to 0.5 µm and less than or equal to 30 µm.

7. The multilayer electronic component according to claim 4, wherein: The first edge pattern and the second edge pattern are spaced apart from the third surface to the sixth surface by a distance greater than or equal to 15 μm.

8. The multilayer electronic component according to claim 1, wherein The first direction position of the edge pattern is located between the first direction position of the first internal electrode and the first direction position of the second internal electrode.

9. The multilayer electronic component according to claim 4, wherein: The area where the first inner electrode is spaced apart from the fifth surface is referred to as a 1-1 width edge, the area where the first inner electrode is spaced apart from the fourth surface is referred to as a first length edge, a third direction dimension of the 1-1 width edge is referred to as WM1, a third direction dimension of a portion of the first edge pattern overlapping the 1-1 width edge in the first direction is referred to as WMP1, a second direction dimension of the first length edge is referred to as LM1, and a second direction dimension of a portion of the first edge pattern overlapping the first length edge in the first direction is referred to as LMP1, and WMP1 / WM1 and LMP1 / LM1 satisfy the conditions of being greater than or equal to 0.33 and less than or equal to 0.

54.

10. The multilayer electronic component according to claim 9, wherein WMP1 / WM1 satisfies greater than or equal to 0.37 and less than or equal to 0.54, and LMP1 / LM1 satisfies greater than or equal to 0.33 and less than or equal to 0.

51.

11. The multilayer electronic component according to claim 4, wherein: When viewed from the first direction, the first edge pattern has a shape surrounding the first internal electrode, and the second edge pattern has a shape surrounding the second internal electrode.

12. The multilayer electronic component according to claim 4, wherein: The area where the first inner electrode is spaced apart from the fifth surface is referred to as a 1-1 width edge, the area where the first inner electrode is spaced apart from the sixth surface is referred to as a 1-2 width edge, and the area where the first inner electrode is spaced apart from the fourth surface is referred to as a first length edge, and The first edge pattern is disposed to overlap the first length edge and one of the 1-1th width edge and the 1-2th width edge in the first direction.

13. The multilayer electronic component according to claim 4, wherein: A region where the first inner electrode is spaced apart from the fifth surface and the sixth surface is referred to as a first width edge, a region where the first inner electrode is spaced apart from the fourth surface is referred to as a first length edge, a region where the second inner electrode is spaced apart from the fifth surface and the sixth surface is referred to as a second width edge, and a region where the second inner electrode is spaced apart from the third surface is referred to as a second length edge, and The first edge pattern and the second edge pattern are disposed to overlap the first width edge and the second width edge, respectively, in the first direction, and are disposed not to overlap the first length edge and the second length edge, respectively, in the first direction.

14. The multilayer electronic component according to claim 1, wherein The edge pattern includes a plurality of spaced-apart patterns.

15. The multilayer electronic component according to claim 3, wherein The first inner electrode includes: a first inner pattern extending to the third surface and spaced apart from the fourth surface, the fifth surface, and the sixth surface; and a first dummy pattern spaced apart from the first inner pattern and extending to the fourth surface and spaced apart from the third surface, the fifth surface, and the sixth surface, and The second inner electrode includes: a second inner pattern extending to the fourth surface and spaced apart from the third, fifth and sixth surfaces; and a second dummy pattern spaced apart from the second inner pattern and extending to the third surface and spaced apart from the fourth, fifth and sixth surfaces.

16. The multilayer electronic component according to claim 15, wherein The first edge pattern is disposed to overlap a region in which the first internal electrode is spaced apart from the fifth surface and the sixth surface and a space in which the first internal pattern and the first dummy pattern are spaced apart from each other in the first direction, and The second edge pattern is disposed to overlap a region in which the second internal electrode is spaced apart from the fifth and sixth surfaces and a space in which the second internal pattern and the second dummy pattern are spaced apart from each other in the first direction.

17. The multilayer electronic component according to claim 3, wherein: The first inner electrode includes: a 1-1 inner pattern extending to the third surface and spaced apart from the fourth surface, the fifth surface, and the sixth surface; and a 1-2 inner pattern spaced apart from the 1-1 inner pattern, extending to the fourth surface, and spaced apart from the third surface, the fifth surface, and the sixth surface, and The second internal electrode includes a floating pattern spaced apart from the third to sixth surfaces.

18. The multilayer electronic component according to claim 17, wherein: The first edge pattern is disposed to overlap a region in which the first inner electrode is spaced apart from the fifth surface and the sixth surface and a space in which the 1-1st inner pattern and the 1-2nd inner pattern are spaced apart from each other in the first direction, and The second edge pattern is disposed to overlap at least one of a region where the second internal electrode is spaced apart from the third surface, a region where the second internal electrode is spaced apart from the fourth surface, a region where the second internal electrode is spaced apart from the fifth surface, and a region where the second internal electrode is spaced apart from the sixth surface in the first direction.

19. A method for manufacturing a multilayer electronic component, the method comprising: A stacking operation of obtaining a stacked body is performed in the following manner: a first sheet having a first pattern provided on a first ceramic sheet and a second sheet having a second pattern provided on a second ceramic sheet are alternately stacked in a first direction, and a third sheet having a third pattern provided on a third ceramic sheet is disposed between the first sheet and the second sheet, and the third sheet is stacked so that the third pattern does not overlap with the first pattern or the second pattern in the first direction; A sintering operation of obtaining a main body by sintering the stack; as well as An operation of forming external electrodes on the body.

20. The method for producing a multilayer electronic component according to claim 19, wherein: The third sheet includes: a 3-1 sheet, on which a 3-1 pattern is arranged; and a 3-2 sheet, on which a 3-2 pattern is arranged, and In the stacking operation, the 3-1st ceramic sheets and the 3-2nd ceramic sheets are alternately stacked in the first direction.

21. The method for manufacturing a multilayer electronic component according to claim 20, wherein: The 3-1st pattern is disposed so as not to overlap the first pattern in the first direction, and the 3-2nd pattern is disposed so as not to overlap the second pattern in the first direction.

22. The method for producing a multilayer electronic component according to claim 21, wherein: When viewed in the first direction, the spacing distance between the first pattern and the 3-1 pattern is less than or equal to 30 μm, and the spacing distance between the second pattern and the 3-2 pattern is less than or equal to 30 μm.

23. The method for manufacturing a multilayer electronic component according to claim 21, wherein: When viewed in the first direction, the spacing distance between the first pattern and the 3-1 pattern is greater than or equal to 0.5µm and less than or equal to 30µm, and the spacing distance between the second pattern and the 3-2 pattern is greater than or equal to 0.5µm and less than or equal to 30µm.

24. A multilayer electronic component comprising: a body including a capacitance forming portion including a plurality of dielectric layers, a first inner electrode and a second inner electrode, the body further including an edge pattern including a portion disposed in a region outside the capacitance forming portion; as well as an outer electrode, disposed on the body, wherein the first internal electrodes and the second internal electrodes are alternately arranged in a first direction, and the dielectric layer is interposed between the first internal electrodes and the second internal electrodes, and The edge pattern is disposed at a position different from the first internal electrode and the second internal electrode in the first direction.

25. The multilayer electronic assembly of claim 24, wherein: The edge pattern includes a first edge pattern and a second edge pattern, and The first internal electrodes, the first edge patterns, the second internal electrodes, and the second edge patterns are alternately disposed in the first direction.

26. The multilayer electronic component of claim 25, wherein: The body has a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposite to each other in the third direction, The first inner electrode extends to the third surface and is spaced apart from the fourth surface, the fifth surface, and the sixth surface, The second inner electrode extends to the fourth surface and is spaced apart from the third surface, the fifth surface, and the sixth surface, and The first edge pattern and the second edge pattern are spaced apart from the third to sixth surfaces.

27. The multilayer electronic component of claim 26, wherein: When viewed in the first direction, a spacing distance between the first internal electrode and the first edge pattern is less than or equal to 30 μm, and a spacing distance between the second internal electrode and the second edge pattern is less than or equal to 30 μm.

28. The multilayer electronic assembly of claim 26, wherein: The first edge pattern and the second edge pattern are spaced apart from the third surface to the sixth surface by a distance greater than or equal to 15 μm.

29. The multilayer electronic assembly of claim 25, wherein: When viewed in the first direction, the first edge pattern extends along an edge of the first internal electrode, and the second edge pattern extends along an edge of the second internal electrode.

30. The multilayer electronic assembly of claim 24, wherein: The edge pattern includes a plurality of spaced-apart patterns.

31. The multilayer electronic assembly of claim 24, wherein: The edge pattern includes the same material as the first and second internal electrodes.

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