Chip packaging method and packaging structure

Abstract

The embodiment of the invention provides a chip packaging method and a chip packaging structure, and the method comprises the steps: providing a wafer and a carrier plate, enabling the functional surface of the wafer to be provided with a hybrid bonding structure, enabling the orthographic projection of the hybrid bonding structure on the wafer to fall in the wafer, and enabling the functional surface of the wafer to be provided with a plurality of vertical conductive structures which penetrate through a part of the thickness of the wafer; forming an adhesive layer on the functional surface of the wafer and the hybrid bonding structure; a sacrificial layer is formed on the carrier plate, and a photoresist box dam is formed at the edge of the sacrificial layer in a surrounding mode; the carrier plate and the wafer function face are in temporary bonding connection through the bonding glue layer, so that the photoresist box dam is supported in the edge area of the wafer; thinning the non-functional surface of the wafer to expose the vertical conductive structure; forming a signal output layer electrically connected with the vertical conductive structure on the non-functional surface of the thinned wafer; and removing the carrier plate, the adhesive layer and the photoresist box dam, and cutting the wafer to form a plurality of chip packaging structures. According to the method, back surface cracking and layering abnormity during wafer thinning can be avoided.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of semiconductor packaging technology, and specifically relate to a chip packaging method and packaging structure. Background Art

[0002] The existing hybrid bonding technology is widely used. Chips with different functions are prepared with corresponding wafer micro-bumps, and wafers with different functions are permanently bonded at the wafer level to achieve ultra-short interconnection, high performance and miniaturization of chips.

[0003] like Figure 1 As shown, due to the process limitations of micro-bump preparation and hybrid bonding, and to avoid the risk of chipping, steps with a width of 2.5 to 4 mm and a height of 30 to 60 um are cut in the invalid edge area to ensure the bonding quality.

[0004] like Figure 2 As shown, when the wafer package is bonded to the carrier, the functional wafer morphology causes the thermoplastic bonding layer to be uneven, and after bonding to the carrier, there will be an edge glue deficiency abnormality, which will lead to cracks, delamination and other abnormalities in the back process (such as back grinding, chemical mechanical grinding of the whole wafer, chemical vapor deposition), affecting the reliability of the chip.

[0005] In view of the above problems, it is necessary to propose a chip packaging method and packaging structure that are reasonably designed and effectively solve the above problems. Summary of the invention

[0006] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a chip packaging method and packaging structure.

[0007] An aspect of an embodiment of the present disclosure provides a chip packaging method, the method comprising:

[0008] A wafer and a carrier are provided, wherein a hybrid bonding structure is arranged on a functional surface of the wafer, wherein an orthographic projection of the hybrid bonding structure on the wafer falls inside the wafer, and a plurality of vertical conductive structures extending toward a non-functional surface thereof and penetrating a portion of the thickness thereof are arranged on the functional surface of the wafer;

[0009] forming an adhesive layer on the wafer functional surface and the hybrid bonding structure;

[0010] forming a sacrificial layer on the carrier, and forming a light blocking dam around the edge of the sacrificial layer;

[0011] The carrier is bonded to the functional surface of the wafer by the adhesive layer so that the light blocking dam is supported on the edge area of ​​the wafer;

[0012] Thinning the non-functional surface of the wafer to expose the vertical conductive structure;

[0013] Forming a signal output layer electrically connected to the vertical conductive structure on the thinned non-functional surface of the wafer;

[0014] The carrier and the wafer are debonded, the adhesive layer and the light-resistance dam are removed, and the wafer is cut to form a plurality of chip packaging structures.

[0015] Optionally, before forming the adhesive layer on the wafer functional surface and the hybrid bonding structure, the method further includes:

[0016] The edge area of ​​the wafer is cut to a preset depth along its thickness direction to form a cutting groove; wherein,

[0017] When the adhesive layer is formed, the adhesive layer is also formed in the cutting groove.

[0018] Optionally, the thickness of the wafer after thinning is less than the depth of the cutting groove.

[0019] Optionally, before forming a signal output layer electrically connected to the vertical conductive structure on the thinned non-functional surface of the wafer, the method further includes:

[0020] The adhesive layer in the cutting groove is removed.

[0021] Optionally, the signal output layer electrically connected to the vertical conductive structure is formed on the thinned non-functional surface of the wafer, comprising:

[0022] forming a dielectric layer on the thinned non-functional surface of the wafer, and patterning the dielectric layer;

[0023] forming a metal wiring layer electrically connected to the vertical conductive structure on the patterned dielectric layer;

[0024] Solder balls corresponding to the metal wiring layer are formed on the metal wiring layer.

[0025] Optionally, debonding the carrier and the wafer includes:

[0026] Fixing the signal output layer to the first film material layer;

[0027] The sacrificial layer is laser processed to peel off the carrier.

[0028] Optionally, removing the adhesive layer and the light blocking dam includes:

[0029] Removing the adhesive layer and the light blocking dam by washing the adhesive;

[0030] The first film material layer is removed.

[0031] Optionally, the wafer is cut to form a plurality of chip packaging structures, including:

[0032] fixing the hybrid bonding structure to the second film material layer;

[0033] Cutting the wafer from one side of the signal output layer to form a plurality of independent chip packaging structures;

[0034] The second membrane material layer is removed.

[0035] Optionally, the photoresist dam may be made of photoresist material.

[0036] Another aspect of an embodiment of the present disclosure provides a chip packaging structure, which is formed by packaging using the chip packaging method described above.

[0037] The chip packaging method and packaging structure of the embodiments of the present invention, in the chip packaging method, a sacrificial layer is formed on a carrier, and a light-resistance dam is formed at the edge of the sacrificial layer, and the carrier and the functional surface of the wafer are bonded together at the same time through an adhesive layer, so that the light-resistance dam is supported on the edge area of ​​the wafer. In this way, when the non-functional surface of the wafer is thinned, the light-resistance dam can support the edge area of ​​the wafer, avoid bonding deficiency anomalies and back-side process cracking and delamination anomalies due to the wafer morphology, and improve the reliability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A wafer having a hybrid bonding structure in the prior art;

[0039] Figure 2 A schematic diagram of a wafer with a hybrid bonding structure generating cracks during back grinding in the prior art;

[0040] Figure 3 A schematic diagram of a chip packaging method according to an embodiment of the present disclosure;

[0041] Figure 4 is a top view of a carrier board according to another embodiment of the present disclosure;

[0042] Figures 5 to 20 A schematic diagram of a chip packaging method according to another embodiment of the present disclosure;

[0043] Fig.21 It is a structural schematic diagram of a chip packaging structure of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0045] like Figure 3 As shown, one aspect of an embodiment of the present disclosure provides a chip packaging method S100, the chip method S100 comprising:

[0046] S110. Provide a wafer and a carrier, wherein a hybrid bonding structure is arranged on a functional surface of the wafer, wherein the orthographic projection of the hybrid bonding structure on the wafer falls inside the wafer, and a plurality of vertical conductive structures extending toward a non-functional surface thereof and penetrating a portion of its thickness are arranged on the functional surface of the wafer.

[0047] like Figure 4 , Figure 5 and Figure 8 As shown, a wafer 110 and a carrier 120 are provided, and a hybrid bonding structure 130 is disposed on the functional surface of the wafer. The orthographic projection of the hybrid bonding structure 130 on the wafer 110 falls inside the wafer 110, that is, the size of the hybrid bonding structure 130 is smaller than the size of the wafer 110, so that the edge area of ​​the wafer 110 has a step-like structure.

[0048] like Figure 5 As shown, a plurality of vertical conductive structures 140 extending toward the non-functional surface and penetrating a portion of the thickness of the wafer are arranged on the functional surface of the wafer 110. In other words, one end of the vertical conductive structure 140 is exposed on the functional surface of the wafer 110, and the other end of the vertical conductive structure 140 is not exposed but is wrapped in the wafer 110.

[0049] like Figure 5 As shown, in this embodiment, the hybrid bonding structure 130 includes a first oxide layer disposed on the functional surface of the wafer, a second oxide layer disposed on the first oxide layer, and a first microbump and a second microbump disposed on the first oxide layer and the second oxide layer, respectively. The first microbump and the second microbump are aligned and connected. The hybrid bonding structure 130 also includes an optical anti-reflection layer disposed on the second oxide layer.

[0050] like Figure 4 As shown, in this embodiment, the carrier 120 is circular in shape, matching the shape of the wafer 110. The carrier 120 may be a glass carrier.

[0051] S120, forming an adhesive layer on the wafer functional surface and the hybrid bonding structure.

[0052] Exemplarily, before forming the adhesive layer on the wafer functional surface and the hybrid bonding structure, the method further includes:

[0053] like Figure 6 As shown, the edge region of the wafer 110 is cut to a preset depth along the thickness direction thereof to form a cutting groove 111 .

[0054] The specific steps of step S120 include:

[0055] like Figure 7 As shown, an adhesive layer 150 is formed on the edge area of ​​the wafer functional surface, on the surface of the hybrid bonding structure 130 and in the cutting groove 111 through a coating process.

[0056] In this embodiment, the edge area of ​​the wafer is cut to a preset depth along the thickness direction to form a cutting groove. On the one hand, when the carrier and the wafer are temporarily bonded, the excess adhesive can flow into the cutting groove when overflowing, thereby preventing the adhesive from overflowing onto the machine. On the other hand, it ensures that the edge of the wafer after thinning does not exceed the carrier, thereby eliminating the impact of temporary bonding offset.

[0057] S130, forming a sacrificial layer on the carrier, and forming a light-blocking dam around the edge of the sacrificial layer.

[0058] like Fig. 9 As shown, a sacrificial layer 160 is formed on the surface of the carrier 120 by coating, wherein the sacrificial layer 160 can be a laser sacrificial layer. Fig.10 As shown in FIG. 1 , a photoresist dam 170 is formed around the edge of the sacrificial layer 160. Figure 4 As shown, in this embodiment, the photoresist dam 170 is in a ring shape and can be made of photoresist.

[0059] S140, bonding the carrier and the functional surface of the wafer simultaneously through the adhesive layer so that the light blocking dam is supported on the edge area of ​​the wafer.

[0060] like Fig.11 As shown, the side of the carrier 120 formed with the light blocking dam 170 is temporarily bonded to the hybrid bonding structure 130 on the functional surface of the wafer through the adhesive layer 150 , so that the light blocking dam 170 is supported at the edge area of ​​the wafer 110 .

[0061] In this embodiment, the carrier and the functional surface of the wafer are bonded together at the same time through an adhesive layer so that the photoresist dam is supported on the edge area of ​​the wafer. In this way, when the non-functional surface of the wafer is thinned, the photoresist dam can support the edge area of ​​the wafer, avoiding bonding deficiency abnormalities and back-side process cracking and delamination abnormalities due to wafer morphology, thereby improving the reliability of the chip packaging structure.

[0062] S150, thinning the non-functional surface of the wafer to expose the vertical conductive structure.

[0063] like Fig.12 and Fig.13 As shown, the non-functional surface of the wafer is ground and thinned by grinding or other processes to expose the vertical conductive structure 140, so as to form a plurality of silicon vias that penetrate the thickness of the wafer 110. The number and arrangement of the silicon vias are not specifically limited in this embodiment and can be selected according to actual needs.

[0064] Exemplarily, the thickness of the wafer 110 after thinning is less than the depth of the cutting groove 111 , which can ensure that the edge of the wafer 110 after thinning does not exceed the carrier 120 .

[0065] S160, forming a signal output layer electrically connected to the vertical conductive structure on the thinned non-functional surface of the wafer.

[0066] Exemplarily, before forming a signal output layer electrically connected to the vertical conductive structure on the thinned non-functional surface of the wafer, the method further includes:

[0067] like Fig.13 As shown, the adhesive layer 150 in the cutting groove 111 is removed.

[0068] Specifically, the adhesive layer 150 in the cutting groove 111 at the edge of the wafer 110 is removed by a cleaning process to prevent the adhesive at the edge of the wafer from entering the non-functional surface of the thinned wafer, thereby keeping the non-functional surface of the wafer clean so as to better form a signal output layer.

[0069] The step of forming a signal output layer electrically connected to the vertical conductive structure on the thinned non-functional surface of the wafer may specifically include:

[0070] First, if Fig.14 As shown, a dielectric layer 181 is formed on the non-functional surface of the thinned wafer, and the dielectric layer 181 is patterned to form a plurality of openings corresponding to the exposed vertical conductive structures 140 .

[0071] Secondly, if Fig.15 As shown, a metal wiring layer 182 electrically connected to the vertical conductive structure 140 is formed on the patterned dielectric layer 181. That is, the metal wiring layer 182 is formed at the opening.

[0072] Again, if Fig.15 As shown, a corresponding solder ball 183 is formed on the metal wiring layer 182, thereby forming a signal output layer 180. The signal output layer 180 is used to lead out the signal of the entire wafer.

[0073] S170, debonding the carrier and the wafer, removing the adhesive layer and the light-blocking dam, and cutting the wafer to form a plurality of chip packaging structures.

[0074] The step S170 of debonding the carrier 120 and the wafer 110 may specifically include:

[0075] First, if Fig.16 As shown, the signal output layer 180 is fixed to the first film material layer 210. The first film material layer 210 wraps the solder ball 183 to protect the solder ball 183.

[0076] Secondly, if Fig.17 As shown, the sacrificial layer 160 is laser treated to carbonize the sacrificial layer 160 so as to peel off the carrier 120 .

[0077] The step S170 of removing the adhesive layer 150 and the light blocking dam 170 may specifically include:

[0078] First, if Fig.18 As shown, the adhesive layer 150 and the photoresist dam 170 are removed by washing.

[0079] Next, the first film material layer 210 is removed.

[0080] In step S170, a plurality of chip packaging structures are formed, including:

[0081] First, if Fig.19 As shown, the hybrid bonding structure 130 is fixed to the second film material layer 220 to achieve the transfer of the wafer 110 .

[0082] Secondly, if Fig. 20 As shown, the wafer 110 is cut from one side of the signal output layer 180 to form multiple independent chip packaging structures 100. That is, the wafer 110 and the hybrid bonding structure 130 are cut along the side where the solder balls 183 are formed to form multiple chip packaging structures 100 according to packaging requirements.

[0083] Next, after the wafer 110 is cut, the second film material layer 220 is removed.

[0084] The chip packaging method of the disclosed embodiment forms a sacrificial layer on a carrier and forms a photoresist dam at the edge of the sacrificial layer, and the carrier and the functional surface of the wafer are bonded together by an adhesive layer so that the photoresist dam is supported on the edge area of ​​the wafer. In this way, when the non-functional surface of the wafer is thinned, the photoresist dam can support the edge area of ​​the wafer, avoiding bonding deficiency anomalies and back process cracking and delamination anomalies caused by the wafer morphology, thereby improving the reliability of the chip packaging structure.

[0085] like Fig.21As shown, another aspect of the embodiment of the present disclosure provides a chip packaging structure 100, which is formed by packaging using the chip packaging method S100 described above. The specific packaging process of the chip packaging method S100 has been described in detail above, and will not be repeated here.

[0086] like Fig.21 As shown, the chip packaging structure 100 includes a chip A, and the chip A is provided with a plurality of vertical conductive structures 140 that penetrate the thickness thereof. The functional surface of the chip is provided with a hybrid bonding structure 130, and the hybrid bonding of the chip packaging structure 100 with other chip modules can be achieved through the hybrid bonding structure 130. The non-functional surface of the chip A is provided with a signal output layer 180 that is electrically connected to the vertical conductive structure 140, and the signal of the entire chip packaging structure 100 can be led out through the signal output layer 180. Among them, the signal output layer 180 includes a dielectric layer 181 provided on the non-functional surface of the chip, the dielectric layer 181 exposes the silicon through via at the silicon through via, and a metal wiring layer 182 that is electrically connected to the silicon through via is provided on the dielectric layer 181, and a plurality of solder balls 183 corresponding to the metal wiring layer 182 are formed on the metal wiring layer 182.

[0087] The chip packaging structure of the embodiment of the present disclosure is formed by packaging using the chip packaging method described above. The risk of chip cracking will not occur on the non-functional surface of the chip of the chip packaging structure, thereby improving the reliability of the chip packaging structure.

[0088] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A chip packaging method, characterized in that: The method comprises: A wafer and a carrier are provided, wherein a hybrid bonding structure is arranged on a functional surface of the wafer, wherein an orthographic projection of the hybrid bonding structure on the wafer falls inside the wafer, and a plurality of vertical conductive structures extending toward a non-functional surface thereof and penetrating a portion of the thickness thereof are arranged on the functional surface of the wafer; forming an adhesive layer on the wafer functional surface and the hybrid bonding structure; forming a sacrificial layer on the carrier, and forming a light blocking dam around the edge of the sacrificial layer; The carrier is bonded to the functional surface of the wafer by the adhesive layer so that the light blocking dam is supported on the edge area of ​​the wafer; Thinning the non-functional surface of the wafer to expose the vertical conductive structure; Forming a signal output layer electrically connected to the vertical conductive structure on the thinned non-functional surface of the wafer; The carrier and the wafer are debonded, the adhesive layer and the light-resistance dam are removed, and the wafer is cut to form a plurality of chip packaging structures.

2. The method according to claim 1, characterized in that: Before forming the adhesive layer on the wafer functional surface and the hybrid bonding structure, the method further includes: The edge area of ​​the wafer is cut to a preset depth along its thickness direction to form a cutting groove; wherein, When the adhesive layer is formed, the adhesive layer is also formed in the cutting groove.

3. The method according to claim 2, characterized in that The thickness of the wafer after thinning is less than the depth of the cutting groove.

4. The method according to claim 2, characterized in that: Before forming a signal output layer electrically connected to the vertical conductive structure on the thinned non-functional surface of the wafer, the method further comprises: The adhesive layer in the cutting groove is removed.

5. The method according to any one of claims 1 to 4, characterized in that: The signal output layer electrically connected to the vertical conductive structure is formed on the thinned non-functional surface of the wafer, comprising: forming a dielectric layer on the thinned non-functional surface of the wafer, and patterning the dielectric layer; forming a metal wiring layer electrically connected to the vertical conductive structure on the patterned dielectric layer; Solder balls corresponding to the metal wiring layer are formed on the metal wiring layer.

6. The method according to any one of claims 1 to 4, characterized in that: Debonding the carrier and the wafer includes: Fixing the signal output layer to the first film material layer; The sacrificial layer is laser processed to peel off the carrier.

7. The method according to claim 6, characterized in that Removing the adhesive layer and the light blocking dam comprises: Removing the adhesive layer and the light blocking dam by washing the adhesive; The first film material layer is removed.

8. The method according to any one of claims 1 to 4, characterized in that: The wafer is cut to form a plurality of chip packaging structures, including: fixing the hybrid bonding structure to the second film material layer; Cutting the wafer from one side of the signal output layer to form a plurality of independent chip packaging structures; The second membrane material layer is removed.

9. The method according to any one of claims 1 to 4, characterized in that: The photoresist dam may be made of photoresist material.

10. A chip packaging structure, characterized in that: The chip is packaged by the chip packaging method according to any one of claims 1 to 9.

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