Method of manufacturing electronic device

Abstract

A method of manufacturing an electronic device. A method of manufacturing an electronic device includes: receiving a first member, the first member including: a first molding layer; a member conductive layer on a first side of the first molding layer; and a second molding layer on the first side of the first molding layer and on the component conducting layer; mounting a bottom side of the semiconductor die to a top side of the substrate; mounting the first member to the top side of the substrate such that the first side of the first molding layer faces in a transverse direction; and forming a molded encapsulation layer including a molding compound, where the molding compound includes a bottom side covering at least a portion of the top side of the substrate, and the molding compound covers at least a portion of a lateral side of the semiconductor die and at least a portion of the first molding layer and the second molding layer of the first member.

Description

[0001] This case is a divisional application of the invention application with the application date of May 29, 2018, the priority date of March 27, 2018, the application number 201810531343.9, and the invention name of “Method of manufacturing electronic device”. Technical Field

[0002] The present invention relates to an electronic device with adaptive vertical interconnection and a method for manufacturing the same. Background Art

[0003] Current electronic devices and methods of manufacturing electronic devices are inadequate, for example resulting in excessive cost, reduced reliability, and / or too large a package size. Other limitations and disadvantages of known and conventional methods will become apparent to those skilled in the art by comparing such known and conventional methods with the present disclosure as described in the remainder of this application with reference to the accompanying drawings. Summary of the invention

[0004] Various aspects of the present disclosure provide electronic components and electronic devices including one or more of the electronic components, as well as methods of manufacturing electronic components and electronic devices including one or more of the electronic components. As non-limiting examples, various aspects of the present disclosure provide vertical interconnect components and various other vertical electronic components and methods of manufacturing the same, as well as electronic devices including one or more vertical interconnect components and various other vertical electronic components and methods of manufacturing the same.

[0005] One aspect of the present invention is a method for manufacturing an electronic device, the method comprising: receiving a first component, the first component comprising: a first molded layer; a component conductive layer, which is on a first side of the first molded layer; and a second molded layer, which is on the first side of the first molded layer and on the component conductive layer; mounting the bottom side of a semiconductor die to the top side of a substrate; mounting the first component to the top side of the substrate so that the first side of the first molded layer faces laterally; and forming a molded encapsulation layer including a molding compound, wherein the molding compound includes a bottom side covering at least a portion of the top side of the substrate, and the molding compound covers at least a portion of the lateral side of the semiconductor die and at least a portion of the first molding layer and the second molding layer of the first component.

[0006] The method further includes removing the substrate. The method further includes forming a signal distribution structure (SDS) over at least the mold compound, the semiconductor die, and the first component. In the method, the signal distribution structure includes a signal distribution structure conductive layer that electrically connects a die pad of the semiconductor die to a first end of the component conductive layer. In the method, the signal distribution structure includes a dielectric layer that includes a first aperture and a second aperture, the die pad of the semiconductor die is exposed to the dielectric layer through the first aperture, the first end of the component conductive layer is exposed to the dielectric layer through the second aperture; and the signal distribution structure conductive layer extends into the first aperture and the second aperture. In the method, the mold compound of the mold package laterally surrounds the entire semiconductor die and the entire first component. In the method, the top side of the mold compound is coplanar with the top surface of the first component. In the method, the component conductive layer includes a plurality of parallel straight traces, the plurality of parallel straight traces serving as conductive vias extending directly and vertically through the mold package layer. In the method, the component conductive layer is configured as a passive electronic component; a first end of a first lead of the passive electronic component is exposed at a top side of the mounted first component; and a second end of the passive electronic component is exposed at a bottom side of the mounted first component. In the method, the substrate includes a signal distribution structure; and mounting the bottom side of the semiconductor die to the top side of the substrate includes attaching a die pad on the bottom side of the semiconductor die to the signal distribution structure of the substrate.

[0007] Another aspect of the present invention is a method for manufacturing an electronic device, the method comprising: forming a first component, forming the first component comprising: forming a first molding layer; forming a component conductive layer on a first side of the first molding layer; and forming a second molding layer on the first side of the first molding layer and on the component conductive layer; mounting the bottom side of a semiconductor die to a top side of a substrate; and mounting the first component to the top side of the substrate so that the first side of the first molding layer faces laterally.

[0008] The method further includes forming a mold encapsulation layer including a mold compound, wherein the mold compound includes a bottom side covering at least a portion of the top side of the substrate, and the mold compound covers at least a portion of a lateral side of the semiconductor die and at least a portion of the first mold layer and the second mold layer of the first component. In the method, the mold compound includes a top side that is coplanar with the top side of the first component. The method further includes: removing the substrate; and forming a signal distribution structure on the bottom side of the semiconductor die, on the bottom side of the mold compound, and on the first component. In the method, the component conductive layer includes a plurality of parallel linear traces, and the plurality of parallel linear traces serve as conductive vias extending directly vertically through the mold encapsulation layer. In the method, forming the first component includes: forming a component array in wafer form, the component array including the first component; and singulating the first component from the component array.

[0009] Another aspect of the present invention is a method of manufacturing an electronic device, the method comprising: receiving a first component, the first component comprising: a first component side, which includes only a first molded layer; a component conductive layer, which is on the first molded layer; a second component side opposite the first component side, which includes only the second molded layer; a third component side, which extends between the first component side and the second component side and includes an exposed first end of the component conductive layer; and a fourth component side opposite the third component side, which includes an exposed second end of the component conductive layer; and forming the electronic device, forming The electronic device comprises: coupling a bottom side of a semiconductor die to a top side of a carrier, the bottom side of the semiconductor die including a die pad; coupling the third component side to the top side of the carrier; forming a molded package including a molding compound, wherein the molding compound covers at least a portion of the top side of the carrier, at least a portion of a lateral side of the semiconductor die, and at least a portion of the first component side and the second component side; removing the carrier; and forming a signal distribution structure on the bottom side of the die, on the bottom side of the molding compound, and on the third component side.

[0010] In the method, the signal distribution structure includes: a dielectric layer including a first aperture and a second aperture, the die pad is exposed through the first aperture, the first end of the component conductive layer is exposed through the second aperture; and a conductive layer electrically connecting the die pad to the first end of the component conductive layer. In the method, the top side of the mold compound is coplanar with the fourth component side. In the method, the component conductive layer includes a straight trace, the straight trace extending directly from the first end of the component conductive layer to the second end of the component conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A flowchart illustrating an example method of manufacturing an electronic device according to various aspects of the present disclosure is shown.

[0012] Figures 2A to 2F Various views are shown of example connection components and example methods of making example connection components according to various aspects of the present disclosure.

[0013] Figures 3A to 3H Various views are shown of example electronic devices and example methods of making example electronic devices according to various aspects of the present disclosure.

[0014] Figures 4A to 4C Various views are shown of example resistive components and electronic devices and example methods of making the example resistive components and electronic devices according to various aspects of the present disclosure.

[0015] Figures 5A to 5C Various views are shown of example capacitive components and electronic devices and example methods of making example capacitive components and electronic devices according to various aspects of the present disclosure.

[0016] Figures 6A to 6C Various views are shown of example bimetallic connection components and electronic devices and example methods of manufacturing the example bimetallic connection components and electronic devices according to various aspects of the present disclosure.

[0017] Figures 7A to 7C Various views are shown of example shielding components and electronic devices and example methods of making the example shielding components and electronic devices according to various aspects of the present disclosure.

[0018] Figures 8A to 8G Various views are shown of example inductive components and electronic devices and example methods of making the example inductive components and electronic devices according to various aspects of the present disclosure.

[0019] Figures 9A to 9F Various views are shown of example coaxial connection components and electronic devices and example methods of making the example coaxial connection components and electronic devices according to various aspects of the present disclosure.

[0020] Figures 10A to 10G Various views are shown of example insulating coaxial connection components and example methods of making the example insulating coaxial connection components according to various aspects of the present disclosure.

[0021] Figures 11A to 11F Various views are shown of example inductive components and example methods of making example inductive components according to various aspects of the present disclosure.

[0022] Fig.12A flowchart illustrating an example method of manufacturing an electronic device according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The following discussion presents various aspects of the present disclosure by providing examples. These examples are non-limiting, and thus the scope of the various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the examples provided. In the following discussion, the terms "for example," "for example," and "exemplary" are non-limiting and generally synonymous with "by example and not limitation," "for example and not limitation," and the like.

[0024] As used herein, "and / or" refers to any one or more items in a list associated with "and / or". As an example, "x and / or y" means any element in the three-element set {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y and / or z" refers to any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" means "one or more of x, y and z".

[0025] The terms used herein are only for the purpose of describing specific examples and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. It will be further understood that the terms "comprises," "comprising," "having," "having" and the like, when used in this specification, specify the presence of the stated features, wholes, steps, operations, components and / or members, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, components, members and / or groups thereof.

[0026] It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Thus, for example, without departing from the teachings of the present disclosure, the first component, first member, or first section discussed below may be referred to as the second component, second member, or second section. Similarly, various spatial terms such as "above," "below," "side," and the like may be used to distinguish one component from another in a relative manner. However, it should be understood that the components may be oriented in different ways, such as a semiconductor device or package may be turned sideways so that its "top" surface faces horizontally and its "side" surface faces vertically, without departing from the teachings of the present disclosure.

[0027] Various aspects of the present disclosure provide electronic components and / or electronic devices including one or more of the electronic components, as well as methods for manufacturing (or producing) the electronic components and / or electronic devices, which can reduce costs, increase reliability and / or increase the manufacturability of the electronic components and / or electronic devices.

[0028] Various aspects of the present invention provide exemplary methods for manufacturing electronic devices. For example, the exemplary method may include receiving a first component, wherein the first component includes a first molded layer, a component conductive layer on a first side of the first molded layer, and a second molded layer on the first side of the first molded layer and on the component conductive layer. For example, the exemplary method also includes: mounting the bottom side of the semiconductor die to the top side of the substrate; mounting the first component to the top side of the substrate so that the first side of the first molded layer faces laterally; and forming a molded encapsulation layer including a mold compound, wherein the mold compound includes a bottom side covering at least a portion of the top side of the substrate, and the mold compound covers at least a portion of the lateral side of the semiconductor die and at least a portion of the first molded layer and the second molded layer of the first component.

[0029] For example, the example method may further include removing the substrate. For example, the example method may include forming a signal distribution structure at least above the molding compound, the semiconductor die, and the first component. For example, the signal distribution structure may include a conductive layer that electrically connects a die pad of the semiconductor die to a first end of the component conductive layer. For example, the signal distribution structure may include a dielectric layer that includes a first aperture and a second aperture, the die pad of the semiconductor die is exposed to the dielectric layer through the first aperture, the first end of the component conductive layer is exposed to the dielectric layer through the second aperture, and the conductive layer extends into the first aperture and the second aperture.

[0030] As another example, in an exemplary embodiment, a molding compound of the molded package laterally surrounds the entire semiconductor die and the entire first component. For example, the top side of the molding compound may be coplanar with the top surface of the first component. For example, the component conductive layer includes a plurality of parallel linear traces, and the plurality of parallel linear traces serve as conductive vias extending directly vertically through the molded package layer. In an exemplary embodiment, the component conductive layer may be configured as a passive electronic component, and the first end of the first lead of the passive electronic component is exposed at the top side of the mounted first component, and the second end of the passive electronic component is exposed at the bottom side of the mounted first component. Furthermore, in an exemplary embodiment, the substrate includes a signal distribution structure, and mounting the bottom side of the semiconductor die to the top side of the substrate includes attaching a die pad on the bottom side of the semiconductor die to the signal distribution structure of the substrate.

[0031] Various aspects of the present invention provide another exemplary method of manufacturing an electronic device. For example, the exemplary method may include forming a first component, wherein forming the first component includes: forming a first molding layer; forming a component conductive layer on a first side of the first molding layer; and forming a second molding layer on the first side of the first molding layer and on the component conductive layer. For example, the exemplary method may also include mounting a bottom side of a semiconductor die to a top side of a substrate and mounting the first component to the top side of the substrate so that the first side of the first molding layer faces laterally.

[0032] Also by way of example, in an exemplary embodiment, a method may include forming a molded encapsulation layer including a mold compound, wherein the mold compound includes a bottom side covering at least a portion of a top side of a substrate, and the mold compound covers at least a portion of a lateral side of a semiconductor die and at least a portion of a first mold layer and a second mold layer of a first component. Further, by way of example, the mold compound includes a top side that may be coplanar with a top side of the first component. By way of another example, an exemplary method may include removing the substrate and forming a signal distribution structure on a bottom side of the semiconductor die, on a bottom side of the mold compound, and on the first component. By way of example, the component conductive layer includes a plurality of parallel linear traces, the plurality of parallel linear traces serving as conductive vias extending directly vertically through the molded encapsulation layer. By way of another example, forming the first component may include forming a component array in wafer form, the component array including the first component, and singulating the first component from the component array.

[0033] Various aspects of the present invention provide yet another exemplary method of manufacturing an electronic device. For example, the exemplary method may include: receiving a first component, the first component including: a first component side, which includes only a first molded layer; a component conductive layer, which is on the first molded layer; a second component side opposite the first component side, which is only on the second molded layer; a third component side, which extends between the first component side and the second component side and includes an exposed first end of the component conductive layer; and a fourth component side opposite the third component side, which includes an exposed second end of the component conductive layer. For example, the exemplary method may also include forming an electronic device. For example, forming an electronic device may include: coupling a bottom side of a semiconductor die to a top side of a carrier, the bottom side of the semiconductor die including a die pad; coupling a third component side to a top side of the carrier; forming a molded package including a molding compound, the molding compound covering at least a portion of the top side of the carrier, at least a portion of a lateral side of the semiconductor die, and at least a portion of the first component side and the second component side; removing the carrier; and forming a signal distribution structure on the bottom side of the die, on the bottom side of the molding compound, and on the third component side.

[0034] For another example, in an exemplary embodiment, the signal distribution structure may include: a dielectric layer including a first aperture and a second aperture, the die pad being exposed through the first aperture, the first end of the component conductive layer being exposed through the second aperture; and a conductive layer electrically connecting the die pad to the first end of the component conductive layer. For example, the top side of the molding compound may be coplanar with the fourth component side. For example, the component conductive layer includes a straight trace extending directly from the first end of the component conductive layer to the second end of the component conductive layer.

[0035] According to the following description of various exemplary embodiments, the above and other aspects of the present disclosure will be described or obvious. Various aspects of the present disclosure will now be presented with reference to the accompanying drawings so that those skilled in the art can easily practice the various aspects.

[0036] Various inserts (or components) for forming a three-dimensional (3D) connection path between a substrate of a first electronic device and a second electronic device mounted above the first electronic device can be formed in various ways. For example, such inserts (or components) can be formed by drilling holes and filling gaps in various materials (e.g., printed circuit board (PCB) materials, molding compounds, silicon, etc.). However, such connection paths are difficult to generate reliably and consistently. For example, due to factors such as manufacturing process limitations, there are many features that are conical and / or have features that are larger than functionally necessary, unnecessarily increasing the size. Therefore, various aspects of the present disclosure utilize wafer processing capabilities (e.g., chip molding capabilities), signal distribution structure (e.g., RDL layer, conductive layer, dielectric layer, etc.) formation capabilities, singulation capabilities, etc. to provide accurate, reliable, repeatable and economical formation of features in the wafer (or panel) plane. For example, such features formed in the wafer (or panel) plane may then be rotated (eg, rotated to a plane orthogonal to the wafer plane, etc.) and utilized to form electronic devices (eg, 3D electronic devices, etc.).

[0037] Figure 1 Flowchart showing an example method 100 for manufacturing an electronic device according to various aspects of the present disclosure. For example, example method 100 may share any or all features with any other example method(s) discussed herein (e.g., example method shown in FIG. 4 , example method shown in FIG. 5 , example method shown in FIG. 6 , example method shown in FIG. 7 , example method shown in FIG. 8 , example method shown in FIG. 9 , example method shown in FIG. 10 , example method shown in FIG. 11 , Fig.12 Example method 1200, etc.). Figures 2A to 2F Various views are shown of example connection components and example methods of making example connection components according to various aspects of the present disclosure. Figures 3A to 3HVarious views are shown of example electronic devices and example methods of manufacturing example electronic devices according to various aspects of the present disclosure. For example, Figures 2A to 2F and 3A to 3H show the Figure 1 Example electronic components and / or example electronic devices including example electronic components at various blocks (or steps) of the example method 100 of the present invention will now be discussed together. Figure 1 , 2A 2F and 3A to 3H. It should be noted that the order of the example blocks of method 100 may be changed without departing from the scope of the present disclosure.

[0038] The example method 100 may begin execution at block 105. The method 100 may begin execution in response to any of a variety of reasons or conditions, non-limiting examples of which are provided herein. For example, the method 100 may begin execution automatically upon arrival of components and / or manufacturing materials utilized during execution of the method 100 in response to one or more signals from one or more upstream and / or downstream manufacturing sites, in response to signals from a central production line controller. For another example, the method 100 may begin execution in response to an operator command to start. For another example, the method 100 may begin execution in response to an execution flow received from any other method block (or step) discussed herein.

[0039] At block 110, the example method 100 may include forming a first molding layer. Block 110 may include forming the first molding layer in any of a variety of ways, non-limiting examples of which are provided herein. Furthermore, the first molding layer may include any of a variety of characteristics, non-limiting examples of which are provided herein. Various example aspects of block 110 are Figure 2A is presented.

[0040] It is noted that the present disclosure will generally present examples in wafer form (e.g., the circular form is generally similar to the circular form factor used in semiconductor circuit manufacturing and / or package manufacturing, etc.). However, it is noted that the scope of the present disclosure is not limited to this. For example, the scope of the present disclosure can be easily applied to other array forms (e.g., panel and / or strip forms, etc.), such as one and / or two-dimensional configurations of components and / or devices including such components. For another example, the scope of the present disclosure can be applied to a single unit or package. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular shape of structure, any particular component and / or any particular device array parameters, etc.

[0041] exist Figure 2AIn the illustrated example 200A1 / 200A2, an example first mold layer 210 is shown. The top view 200A1 of the first mold layer 210 only shows the first mold layer 210, which completely covers the example carrier 205 (but does not necessarily completely cover the example carrier 205). The side cross-sectional view 200A2 of the first mold layer 210 shows the first mold layer 210 on the carrier 205.

[0042] For example, block 110 may include forming a first molded layer 210 by performing a molding process (e.g., compression molding, injection molding, transfer molding, liquid encapsulation molding, film assisted molding, etc.). Note, however, that block 110 is not limited to utilizing a molding process. For example, block 110 may include forming a first molded layer 210 by vacuum lamination, adhesive printing, spin coating, spray coating, dip coating, pressurization (e.g., pressurization on prepreg material, etc.), etc. For example, although layer 210 is referred to herein as a first molded layer, layer 210 may be formed by any of a variety of processes and may include any of a variety of materials.

[0043] The carrier 205 (or substrate) may include any of a variety of characteristics. For example, the carrier 205 may include a metal carrier, a glass carrier, a plastic carrier, a bulk semiconductor carrier, etc. For example, the carrier 350 may not contain electronic components. For example, the carrier 205 may have a shape similar to the first molded layer 210, but this is not required. For example, the carrier 205 may be a reusable carrier or a disposable carrier. The carrier 205 may have any of a variety of thicknesses, such as a sufficient thickness to provide a desired amount of rigidity during various manufacturing processes. Note that although Figure 2A The first molded layer 210 is shown formed directly on the carrier 205, but there may be one or more intermediate layers (e.g., a release agent layer, a heat-releasable adhesive material, a photo-releasable adhesive material, a chemically dissolvable material, etc.) between the first molded layer 210 and the carrier 205.

[0044] The first molded layer may include any of a variety of encapsulant materials. For example, the first molded layer 210 may include an epoxy mold compound (EMC). For another example, the first molded layer 210 (which may be molded or otherwise formed as discussed herein) may include any one or more layers of various encapsulation or molding materials (e.g., resins, polymers, polymer composites, polymers with fillers, epoxies, epoxy resins with fillers, epoxy acrylates with fillers, silicones, prepregs, combinations thereof, equivalents thereof, etc.).

[0045] For another example, the first molding layer 210 (which may also be referred to as the first dielectric layer 210 herein) may include one or more layers composed of any various dielectric materials, such as inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, siloxanes, acrylate polymers, combinations thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto. Block 110 may include forming the layer(s) using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the disclosed aspects are not limited thereto.

[0046] The first molded layer 210 may include any of a variety of thicknesses (indicated by T1 in the figure). For example, the first molded layer may be 500 μm thick, 500 μm + / - 100 μm thick, 300 μm thick, 300 μm + / - 100 μm thick, etc. As discussed herein, after singulation, the singulated components may be rotated and stand on their original lateral sides. In this embodiment, the thickness T1 of the first molded layer 210 and / or other layers may affect the stability of the singulated components when placed. However, the scope of the present disclosure should not be so limiting. For example, in the case of using a relatively thin dielectric layer (e.g., a spin-coated layer, a spray-coated layer, a vapor-deposited layer, etc.), the thickness of the first molded layer 210 may be 30 μm or less, or 15 μm or less. Note that stability of the singulated component when placed and / or attached to another component may also be achieved by attachment means (eg, by adhesive, by flux, by solder paste, by solder, etc.).

[0047] For the discussion herein, the plane of the wafer (e.g., the plane of the carrier 205, the plane of the first molding layer 210, etc.) will generally be referred to as the wafer plane or horizontal plane. A plane that is orthogonal or perpendicular to the wafer plane will generally be referred to as a vertical plane. For clarity, these orientations (e.g., in an absolute orientation manner) are used herein. Therefore, the scope of the present disclosure is not limited by these orientations.

[0048] For example, it is noted that block 110 may include performing planarization, grinding, and / or thinning operations on the first molding layer 210, such as in preparation for forming the signal distribution layer 220 at block 120, etc.

[0049] Also note that although the first mold layer 210 is illustrated as being smooth, this is not necessarily the case. For example, the block 110 may include forming the first mold layer 210 with surface asperities, raised features or portions, recessed features or portions, etc., which may, for example, enhance adhesion to other materials.

[0050] Generally, block 110 may include forming a first molding layer (or dielectric layer, etc.). Therefore, the scope of the present disclosure should not be limited to any particular manner of forming the first molding layer (or first dielectric layer) or any particular type of characteristics of the first molding layer (or first dielectric layer).

[0051] At block 120, the example method 100 may include forming one or more signal distribution structures on the first molding layer. Block 120 may include forming the one or more signal distribution structures in any of a variety of ways, non-limiting examples of which are provided herein. Furthermore, the signal distribution structures may include any of a variety of characteristics, non-limiting examples of which are provided herein. Various example aspects of block 120 are Figure 2B For example, various example aspects of block 120 are also presented in Figure 4A , 5A , 6A, 7A, 8A to 8C are presented.

[0052] For example, Figure 2B As shown in , block 120 may include forming a signal distribution structure 220 as a straight trace in the plane of the wafer. As will become apparent in the discussion of other examples presented herein, the signal distribution structure may include any of a variety of shapes, sizes, spacings, and / or material properties. The discussion herein also refers to the signal distribution structures shown herein as traces.

[0053] For example, block 120 may include forming traces 220 by electroplating. For example, block 120 may include forming a seed layer 221 on the first mold layer 210. Block 120 may include forming the seed layer 221 using any of a variety of techniques (e.g., sputtering or other physical vapor deposition (PVD) techniques, chemical vapor deposition (CVD), electroless plating, electrolytic plating, etc.). For example, the seed layer 221 may be used during a subsequent electroplating process.

[0054] The seed layer 221 may include any of a variety of materials. For example, the seed layer 221 may include copper. For another example, the seed layer 221 may include one or more layers composed of any of a variety of metals (e.g., copper, silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, titanium, vanadium, etc.) and / or combinations or alloys thereof (e.g., NiV, CrCu, TiW, TiN, etc.).

[0055] After forming the seed layer 221, block 120 may include forming a shielding layer (not shown) on the seed layer 221 to expose only portions of the seed layer 221 on which another (e.g., typically thicker) conductive layer 222 will be plated. For example, block 120 may then include electroplating the conductive layer 222 on the seed layer 221 in the openings of the shielding layer. After plating, block 120 may include stripping the shielding layer and etching (or otherwise removing) portions of the seed layer 221 that are not covered by the plated conductive layer 222. Portions of the seed layer 221 remain under the conductive layer 222. Note that the etching process may cause undercutting of the seed layer 221 under the lateral edges of the conductive layer 222.

[0056] Block 110 is not limited to forming trace 220 by electroplating. Any of a variety of processes may be utilized. For example, block 120 may include forming at least a portion of trace 220 (such as conductive layer 222) by electroless plating, chemical vapor deposition (CVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc., but the scope of the present disclosure is not limited in this regard. In the same or other examples, trace 220 may include conductive layer 222 without seed layer 221.

[0057] Trace 220 may include any of a variety of dimensions. Figure 2B As shown in , traces 220 may vertically span the entire wafer (or a substantial portion thereof) in the plane of the wafer. As will be shown and discussed herein, traces 220 may include any of a variety of shapes, sizes, spacings, and material properties.

[0058] In an exemplary embodiment, trace 220 may have a thickness or height (e.g., in a direction perpendicular to the wafer plane) of 10 μm or in the range of 5 μm to 15 μm. This thickness or height is indicated as H1 in the figure. For another example, trace 220 may have a thickness H1 in the range of 2 μm to 20 μm. As will be discussed herein, the thickness H1 of trace 220 is related to the cut end of trace 220 (e.g., cut during the singulation process of block 140, etc.) will become a pad or platform to which other features can be attached and / or on which other features can be formed.

[0059] In an exemplary embodiment, the trace may have a lateral width (e.g., in a direction parallel to the wafer plane) in the range of 10 μm or 5 μm to 15 μm. This width is indicated in the figure as W1. For another example, trace 220 may have a lateral width in the range of 2 μm to 20 μm. As will be discussed herein, the lateral width W1 of trace 220 is related to the cut end of trace 220 (e.g., cut during the singulation process of block 140) becoming a pad or platform to which other features can be attached and / or on which other features can be formed. Note that, as discussed herein, for example in the shielding example (e.g., as discussed herein with respect to Figures 7A to 7C etc.), the lateral width W1 of the trace 220 may span the entire wafer (or a large portion thereof). Note that the width W1 need not be uniform. For example, any or all of the traces 220 may be formed with a first portion that is wider (e.g., 10% or more) than a second portion. For example, the width of the trace 220 may be set so that after singulation, the middle portion of the trace 220' is narrower (e.g., W1, H1, etc.) than the end portions (e.g., to save metal, induce resistance, increase compliance, create fuses, etc.).

[0060] Figure 2B A cross-sectional view of trace 220 is shown. Figure 2B The example cross-section shown in is square, but the scope of the present disclosure is not limited in this regard. For example, trace 220 may have a non-square rectangular cross-section (e.g., taller than wide, wider than high, etc.). Also note that, as discussed in the bimetallic example herein, trace 220 may include multiple layers (e.g., in addition to the seed layer), which may be composed of the same metal or different metals. In this embodiment and in other embodiments, as in Figure 2B The vertical sides of the trace 220 shown in the example diagram 200B2 need not be vertical. For example, such sides may be slanted, may be hexagonal (or generally polygonal) in shape, may be curved, and so on.

[0061] In an exemplary embodiment, the traces 220 may have a gap between them (e.g., in a direction parallel to the wafer plane) of 10 μm or in the range of 5 μm to 15 μm. This gap is indicated in the figure as G1. As another example, the gap G1 may be in the range of 2 μm to 20 μm. As will be discussed herein, the gap G1 between the traces 220 is related to the cut ends of the traces 220 (e.g., as cut in the singulation process of block 140) becoming pads or platforms to which other features may be attached and / or on which other features may be formed. In an exemplary embodiment, the width W1, thickness T1, and gap G1 may be the same (e.g., within 5% or 10% of each other or manufacturing tolerances), such as 10 μm, but this is not necessarily the case. Any combination of W1, T1, and G1 may be implemented. For example, in another embodiment, the width W1 may be 10 μm, the thickness T1 may be 2 μm, and the gap G1 may be 5 μm. In another embodiment, each of width W1 , thickness T1 , and gap G1 is less than or equal to 5 μm (eg, having the same or different respective values). Note that the distance between the centerlines of traces 220 (which may be referred to herein as pitch) is labeled P1 .

[0062] Generally speaking, block 120 may include forming one or more signal distribution structures 220 (or traces) on the first molding layer 210. The scope of the present disclosure should not be limited by the nature of any particular manner of forming a signal distribution structure or the nature of any particular type of signal distribution structure.

[0063] At block 130, the example method 100 may include forming a second molding layer. Block 130 may include forming the second molding layer in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 130 are described in Figure 2C is presented.

[0064] For example, block 130 may share any or all characteristics with block 110. For example, second mold layer 230 and / or its formation may share any or all characteristics with first mold layer 210 and its formation.

[0065] For example, block 130 may include forming the second molded layer 230 by performing a molding process (e.g., compression molding, injection molding, transfer molding, liquid encapsulation molding, membrane assisted molding, etc.). However, it is noted that block 130 is not limited to utilizing a molding process. For example, block 130 may include forming the second layer 230 by vacuum lamination, adhesive printing, spin coating, spray coating, dip coating, etc.

[0066] The second molded layer 230 may include any of a variety of molding materials. For example, the second molded layer 230 may include an epoxy molding compound (EMC). For another example, the second molded layer 230 (which may be molded or otherwise formed as discussed herein) may include any one or more layers of various encapsulation or molding materials (e.g., resins, polymers, polymer composites, polymers with fillers, epoxies, epoxy resins with fillers, epoxy acrylates with fillers, silicones, prepregs, combinations thereof, equivalents thereof, etc.).

[0067] For another example, the second molding layer 230 (which may also be referred to herein as the second dielectric layer 230) may include one or more layers composed of any various dielectric materials, such as inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, siloxanes, acrylate polymers, combinations thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto. Block 130 may include forming the layer(s) using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the disclosed aspects are not limited thereto.

[0068] The second mold layer 230 may include any of various thicknesses (indicated by T2 in the figure). For example, the second mold layer 230 may be 500 μm thick, 500 μm+ / -100 μm thick, 300 μm thick, 300 μm+ / -100 μm thick, etc. As discussed herein, after singulation, the singulated component may be standing on its side. In this embodiment, the thickness of the second mold layer 230 and / or other layers may affect the stability of the singulated component when placed. However, the scope of the present disclosure should not be so limiting. For example, in the case of using a relatively thin dielectric layer (e.g., spin coating, etc.), the thickness of the second mold layer 230 may be 30 μm or less. Note that the stability of the singulated component when placed and / or attached to another component can be obtained or enhanced by attachment means (e.g., by an adhesive, by a flux, by a solder paste, by a solder, etc.).

[0069] exist Figure 2CIn the illustrated exemplary embodiment, the first mold layer 210, the trace 220 (or signal distribution structure), and the second mold layer 230 are formed such that the amount of mold material above the trace 220 is equal to the amount of mold material below the trace 220. Therefore, the thickness T2 of the second mold layer 230 is thicker than the thickness T1 of the first mold layer 210 by the height H1 of the trace 220 (e.g., to allow a portion of the second mold layer 230 to fill between adjacent traces 220, etc.). For example, this equal thickness can be beneficial for reducing warping and / or enhancing structural stability. However, it is noted that this thickness quality is not necessary and the scope of the present disclosure is not limited thereto. For example, in various exemplary embodiments, the block 230 can be omitted. For another example, the thickness T1 of the first mold layer 210 and the thickness T2 of the second mold layer 230 can be substantially different (e.g., at least 10% different, at least 20% different, at least 50% different, etc.).

[0070] In an exemplary embodiment, the materials used in the first mold layer 210 (or the first dielectric layer) and the second mold layer 230 (or the second dielectric layer) may be the same or substantially similar. For example, such sameness or similarity may be beneficial to reduce warping and / or enhance structural stability. However, it is noted that such material sameness or similarity is not necessary, and the scope of the present disclosure is not limited thereto. For example, in various exemplary embodiments, the first mold layer 210 and the second mold layer 230 may be formed of different respective materials. For example, one of the first mold layer 210 and the second mold layer 230 may be formed of EMC, and the other of the first mold layer 210 and the second mold layer 230 may be formed of non-EMC materials (e.g., any other dielectric material discussed herein, etc.). Similarly, it is noted that the respective processes used by block 110 and block 130 to form the first mold layer 210 (or the first dielectric layer) and the second mold layer 230 (or the second dielectric layer) may be the same or different.

[0071] Furthermore, although Figure 2C The illustrated example embodiment 200C includes only a single first mold layer 210 below the trace 220 and a single second mold layer 230 above the trace 220, but any number of layers (e.g., mold layers, dielectric layers, etc.) composed of any respective material (e.g., the examples provided herein) may be formed above and / or below the trace 220. For example, a non-mold dielectric layer (e.g., any dielectric material mentioned herein, etc.) may be formed above and / or below the trace 220.

[0072] For example, it is noted that block 130 may include performing planarization, grinding, and / or thinning operations on the second mold layer 230 .

[0073] Also note that while the second mold layer 230 is illustrated as being smooth, this is not necessarily the case. For example, block 130 may include forming the second mold layer 230 with surface bumps, raised features or portions, recessed features or portions, etc., which may, for example, enhance adhesion to other materials.

[0074] Generally speaking, block 130 may include forming a second molding layer (or a second dielectric layer, etc.). Therefore, the scope of the present disclosure should not be limited to any particular manner of forming the second molding layer (or the second dielectric layer) or any particular type of characteristics of the second molding layer (or the second dielectric layer).

[0075] At block 140, the example method 100 may include singulating the wafer into singulated components. Block 140 may include singulating the wafer (or panel, etc.) in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 130 are described in detail below. Figure 2D , 4A to 4B, 5A to 5B, 6A to 6B, 7A to 7B, 8E to 8F are presented.

[0076] For example, block 140 may include sawing (e.g., mechanical sawing, etc.) component 200D1 (e.g., including first molding layer 210, traces 220, and second molding layer 230) along a plurality of singulation routes (or a plurality of separation lines). Example singulation routes 241, 242, 243, 244 are Figure 2D Block 140 may include performing singulation using any of a variety of cutting and / or separation techniques (eg, laser cutting, general focused energy cutting, chemical etching or dissolution, punching, etc.).

[0077] exist Figure 2D In the example 200D1 shown in FIG. 1 , block 140 includes singulating components 240 from component 200D1. For example, block 140 may include singulating a plurality of such components 240 from component 200D1. Although each singulated component 240 may be identical, this need not be the case. For example, as discussed herein, any of a variety of different types of components 240 may be formed, each having a respective size and / or having a respective trace configuration (which may be unique).

[0078] Figure 2D The example component 240 shown in FIG. 1 is cut to a length L1 in a first direction (or dimension) in the plane of the wafer and to a length L2 in a second direction (or dimension) in the plane of the wafer. As will be seen, when the example component 240 is subsequently rotated 90 degrees for use in an electronic device, the L1 dimension will become a vertical dimension, while the L2 dimension will remain along the wafer (or horizontal) plane.

[0079] For example, block 140 may include removing the carrier 205 prior to singulation. However, it is noted that this carrier removal may not be necessary. For example, the carrier 205 may be disposable, and a disposable buffer layer may be located between the carrier 205 and the first mold layer 210 so that the carrier 205 can be protected from the singulation process and reused, etc.

[0080] Note that the surface cut during performance of block 140 may be rougher (or smoother) than the top surface of the second mold layer 230 and / or the bottom surface of the first mold layer 210 .

[0081] Generally speaking, block 140 includes singulating the wafer into singulated electronic components. Accordingly, the scope of the present disclosure should not be limited by the nature of any particular manner of performing such singulation or the nature of any particular singulated components.

[0082] At block 150, the example method 100 may include rotating the singulated component. Block 150 may include rotating (or orienting) the singulated component in any of a variety of ways, non-limiting examples of which are provided herein. Various examples of block 150 include: Figure 2E , 4B , 5B, 6B, 7B, and 8F are presented.

[0083] exist Figure 2E In FIG. 2 , a top view 200E1 of a singulated component 240 is shown. Figure 2E 200E1 of the singulated component 240, because the top side of the cut trace 220' is covered by the cut (or singulated) second molded layer 230'. This is shown in the side view 200E2 of the singulated component 240. The side view 200E2 shows the front cut surface of the singulated component 240, including the cut front end of the cut trace 220' (with a similar cut rear end at the rear side of the singulated component 240), the front surface of the cut first molded layer 210' (with a similar cut rear surface at the rear side of the singulated component 240), and the front surface of the cut second molded layer 230' (with a similar cut rear surface at the rear side of the singulated component 240). As shown in front view 200E2 of singulated component 240 , the height of singulated component 240 is labeled T3 , and the width of singulated component 240 is labeled L2 .

[0084] For example, block 150 may include rotating singulated component 240 by 90 degrees. The rotation is shown in side view 200E3 of rotated component 240' relative to side view 200E2 of singulated component 240 prior to rotation. Note that, after the rotation provided by block 150, side view 200E3 of rotated component 240' is similar to top view 200E1 of singulated component 240 prior to rotation. As mentioned in the discussion of example illustration 200E1, in example illustration 200E3, the outline of cut trace 220' is shown (e.g., as a vertical line) even though cut trace 220' is covered by cut second mold layer 230' (or by cut first mold layer 210', depending on the direction of rotation). At this point it should be understood that the cut traces 220' formed in the plane of the wafer (e.g., horizontally) now run in a direction (e.g., vertically) that is orthogonal (or perpendicular) to the plane of the wafer. Example illustration 200E4 shows a cross-sectional view of the rotated member 240' in a vertical plane passing through the cut traces 220'.

[0085] Example illustration 200E4 provides a clearer illustration of the cut trace 220' extending vertically through the cut second mold layer 230'. Example illustration 200E5 shows a perspective view of the rotated component 240'. Example illustration 200E5 shows that when the singulated component 240 is rotated at block 150 to result in the rotated component 240', the dimensions discussed above (e.g., with respect to Figures 2A to 2D and about Figure 2E Note that, although not individually highlighted in example illustration 200E5, one of seed layer 221 and conductive layer 222 of cut trace 220' may be positioned in front of the other of seed layer 221 and conductive layer 222, depending on the direction of the 90 degree rotation at block 150 (and / or other rotations, such as yaw, pitch, and roll rotations that may be performed).

[0086] For example, block 150 may be performed by a pick-and-place machine, but the scope of the present disclosure is not limited in this regard.

[0087] Generally speaking, block 150 includes rotating singulated electronic components (eg, as singulated at block 140). Thus, the scope of the present disclosure should not be limited by the features of any particular manner of performing such rotation and / or any particular type of amount of rotation.

[0088] At block 160, the example method 100 may include mounting one or more semiconductor dies to a carrier. Block 160 may include mounting (or coupling) the semiconductor die to the carrier in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 160 are described in detail below. Figures 3A to 3B , 4C, 5C, 6C, 7C, and 8G are presented.

[0089] Note that while the examples shown herein generally focus on the fabrication of multiple electronic components (e.g., a wafer of electronic components, a multi-dimensional panel, or a one-dimensional strip of electronic components, etc.), the scope of the present disclosure is not limited in this regard. Note also that while the electronic devices discussed herein generally focus on a single die, it should be understood that multiple dies may be incorporated into a single electronic device, one or more passive electronic components may be added, an electronic device may be formed without any semiconductor die or active devices (e.g., including only passive electronic components), etc. For example, if Figure 3B As shown, a plurality of additional devices 361a and 361b (e.g., passive electronic components (e.g., resistors, capacitors, inductors, etc.) and / or active electronic components (e.g., integrated circuit dies, transistor dies, etc.)). Note that such additional devices 361a and / or 316b may have some or all of their terminals attached to the adhesive 355. For example, the additional devices 361a and / or 361b may be mounted in a substantially horizontal configuration with all leads or terminals attached to the adhesive 355 and / or may be arranged in a substantially horizontal configuration such as Figure 3A The device is mounted in the orientation shown, for example with the lower terminals attached to adhesive 355 and the upper terminals exposed at the top surface.

[0090] It is also noted that in various exemplary embodiments, various blocks of the exemplary method 100 may be omitted. For example, in an exemplary embodiment, block 130 may be omitted. For example, after forming the signal distribution structure 220 on the first molding layer 210 at block 120 (e.g., as Figure 2B ), the example implementation may proceed to singulation performed at block 140 (e.g., as shown in the example of Figure 2E ). Figure 2F An example top and cross-sectional illustration 200F1 of the resulting component 240 ′ is shown.

[0091] Also, for example, in an exemplary embodiment, block 110 may be omitted. For example, block 120 may include forming a signal distribution structure 220 on the carrier 205 (or other intervening layer, such as a release layer on the carrier 205). For example, block 130 may then include forming a molding layer 230 over the signal distribution structure 220 and the carrier 205 (or other intervening layer, such as a release layer formed on the carrier 205), such as Figure 2CAs shown, but without the first molding layer 210 . Figure 2F An example top and cross-sectional illustration 200F2 of the resulting component 240" is shown.

[0092] As another example, in an exemplary embodiment, carrier 205 (or portions thereof) need not be removed. For example, after singulation of block 140, singulated carrier 205' (or portions thereof, e.g., carrier 205 is thinned or delaminated) may remain with a completed singulated component. This exemplary embodiment may be combined with any other embodiment discussed herein (e.g., executing all of blocks 110 to 150, skipping block 110, skipping block 130, etc.). Figure 2F An example top and cross-sectional illustration 200F3 of the resulting component 240'" is shown, which in this example is combined with the example implementation of skipping block 110 as discussed above.

[0093] Notice that Figure 2F The example embodiments 200F1, 200F2, and 200F3 shown in the drawings can be readily applied to any example components discussed herein (e.g., Figures 4A to 4C , 5A to 5C, 6A to 6C, 7A to 7C, 8A to 8G, 9, etc.).

[0094] like Figure 3A As shown in the example illustration 300A of , a carrier 350 (which may also be referred to herein as a substrate) may be provided with an adhesive layer 355. The carrier 350 may include any of a variety of properties. For example, the carrier 350 may include a metal carrier, a glass carrier, a bulk semiconductor carrier, a plastic carrier, etc. For example, the carrier 350 may not contain electronic components. For example, the adhesive layer 355 may include a die attach adhesive, a layer of heat releasable adhesive, a layer of UV releasable adhesive (e.g., on a glass carrier, etc.), etc.

[0095] As in Figure 3B The example diagram 300B1 (which is along Figure 3B AA) and Figure 3B 300B2 (which is a top view), block 160 may include mounting semiconductor die 360 ​​to adhesive layer 355. Although in the primary examples discussed herein, the active (or front) side of semiconductor die 360 ​​(e.g., including pads or platforms exposed through apertures in a dielectric layer, etc.) is attached to adhesive layer 355, in other example embodiments, the passive (or back) side of semiconductor die 360 ​​may be attached to adhesive layer 355. For another example, as shown in the figures, semiconductor die 360 ​​may represent or be replaced by one or more electronic devices having one or more semiconductor die, one or more passive electronic components, and / or one or more semiconductor packages.

[0096] For example, block 160 may include performing such die mounting (or other component mounting) with a pick-and-place machine. Non-limiting examples of such die attachment are provided in U.S. Patent Application No. 15 / 469,008, filed on March 24, 2017, entitled “Semiconductor Device and Method of Fabrication Thereof,” which is hereby incorporated by reference in its entirety for all purposes.

[0097] Generally, block 160 may include mounting one or more semiconductor dies to a carrier. Thus, the scope of the present disclosure should not be limited by the nature of any particular manner of performing such mounting.

[0098] At block 170, the example method 100 may include mounting the rotated electronic component (e.g., as rotated at block 150) to a carrier. Block 170 may include mounting (or coupling) the rotated electronic component (e.g., as rotated at block 150) to the carrier in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 170 are described in detail below. Figure 3B , 4C , 5C, 6C, 7C and 8G are presented. Also note that blocks 150 and 170 can be merged. For example, singulated components 240 can be picked up, rotated and placed (e.g., by a pick-and-place machine) in a continuous sequence of manufacturing steps.

[0099] As in Figure 3B The example diagram 300B1 (which is a cross-sectional view) and Figure 3B 300B2 (which is a top view), block 170 may include positioning one or more rotated components 240' to carrier 350 (e.g., to adhesive layer 355). In example illustrations 300B1 and 300B2, block 170 includes mounting a rotated first component 240'-1 laterally adjacent to a first lateral side of a die 360, mounting a rotated second component 240'-2 laterally adjacent to a second lateral side of a die 360, mounting a rotated third component 240'-3 laterally adjacent to a third lateral side of a die 360, and mounting a rotated fourth component 240'-4 laterally adjacent to a fourth lateral side of a die 360.

[0100] Note that block 170 may include any number of rotated components (e.g., two, three, etc.) mounted adjacent to a single lateral side of die 360. Note also that die 360 ​​need not be surrounded by rotated components on all lateral sides. For example, in an example embodiment, only one side of die 360 ​​has one or more rotated components mounted adjacent thereto. Also for example, in another example embodiment, only two opposing lateral sides of die 360 ​​have one or more rotated components mounted adjacent thereto.

[0101] like Figure 3B As shown, the rotated component 240' positions or orients the cut traces 220' for use as vertical via connections in the formed electronic device (or package). Note that, for example, as discussed in more detail in the example of FIG. 8, multiple conductive layers can be formed in the rotated component. For example, this multi-layer configuration can be used in the rotated component to form multiple stacked trace columns that form multiple vertical via columns when rotated. In other words, reference Figure 3B In the example 300B2, one or more of the rotated components 240'-1, 240'-2, 240'-3, and 240'-4 may include a plurality of trace columns.

[0102] like Figure 3B As shown in the example illustrations 300B1 (cross-sectional view) and 300B2 (top view), block 170 may include mounting one or more rotated components 240' (e.g., first rotating component 240'-1, second rotating component 240'-2, third rotating component 240'-3, and fourth rotating component 240'-4) to adhesive layer 355. Although in the main example discussed herein, the die 360 ​​is mounted before the rotated component 240', this mounting order is not required.

[0103] For example, block 170 may include performing this component installation (or installing other components, dies, parts, etc.) with a pick-and-place machine.

[0104] Generally speaking, block 170 may include mounting the rotated electronic component to a carrier. Thus, the scope of the present disclosure should not be limited by the nature of any particular manner of performing such mounting.

[0105] At block 180, the example method 100 may include molding the package array. Block 180 may include molding the package array in a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 180 are presented in Figures 3C1 to 3H, 4C, 5C, 6C, 7C, and 8G.

[0106] For example, block 180 may share any or all characteristics with block 110 and / or block 130. For example, molded encapsulation layer 370 and / or its formation may share any or all characteristics with first molded layer 210 and its formation, second molded layer 230 and its formation, etc.

[0107] For example, block 180 may include forming molded encapsulation layer 370 by performing a molding process (e.g., compression molding, injection molding, transfer molding, liquid encapsulation molding, film assisted molding, etc.). However, it is noted that block 180 is not limited to utilizing a molding process. For example, block 180 may include forming molded encapsulation layer 370 by vacuum lamination, adhesive printing, spin coating, spray coating, dip coating, etc.

[0108] The molded encapsulation layer 370 may include any of a variety of molding materials. For example, the molded encapsulation layer 370 may include an epoxy molding compound (EMC). For another example, the molded encapsulation layer 370 (which may be molded or otherwise formed as discussed herein) may include any one or more layers of various encapsulation or molding materials (e.g., resins, polymers, polymer composites, polymers with fillers, epoxies, epoxy resins with fillers, epoxy acrylates with fillers, silicones, prepregs, combinations thereof, equivalents thereof, etc.).

[0109] For another example, the molded encapsulation layer 370 (also referred to herein as the encapsulation dielectric layer 370) may include one or more layers composed of any various dielectric materials, such as inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, siloxanes, acrylate polymers, combinations thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited to this. Block 180 may include utilizing any one or more of a variety of processes to form the layer(s) (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the disclosed aspects are not limited thereto.

[0110] The molded encapsulation layer 370 may include any of a variety of thicknesses. For example, the molded encapsulation layer 370 may be the same as the dimension L1 of the rotated component 240'. For another example, the molded encapsulation layer 370 may be larger or smaller than the dimension L1 of the rotated component 240'. For another example, the molded encapsulation layer 370 may be thicker than the height of the semiconductor die 360.

[0111] exist Figure 3CIn the example diagram 300C1, the molded encapsulation layer 370 is formed to have a thickness greater than the dimension L1 of the rotated member 240' and greater than the height of the die 360. Figure 3C As shown in example illustrations 300C2 (cross-sectional view) and 300C3 (top view), block 180 may then include thinning (or flattening) the top of molded encapsulation layer 370 (resulting in thinned molded encapsulation layer 370') to expose at least the ends of traces 220' of rotated component 240' and / or the top surface of rotated component 240'. For example, traces 220' may then be used as conductive via connections for formed electronic devices and / or packages. In this example embodiment, the top surface of molded encapsulation layer 370' may be coplanar with the corresponding top surface of the rotated component(s) 240'. Note that in another exemplary embodiment, the molded encapsulation layer 370 may be initially formed at (or thinned to) the precise height of the rotated member 240' (and / or at a lower height, e.g., such that the ends of the traces 220 and / or the top surface of the rotated member 240' may be at least slightly above the molded encapsulation layer 370').

[0112] In another exemplary embodiment, Figure 3C The thinning (or planarization) shown in examples 300C2 and 300C3 may be performed to the extent that the top side of the die 360 ​​is exposed and / or the top side of the die 360 ​​is thinned. In this example embodiment, the top surface of the molded encapsulation layer 370, the top surface of the rotated member 240', and the top surface of the die 360 ​​may be coplanar.

[0113] In an exemplary embodiment, the materials used in the molded encapsulation layer 370 (or encapsulation dielectric layer), in the first molded layer 210 (or first dielectric layer), and in the second molded layer 230 (or second dielectric layer) may be the same or substantially similar. For example, such sameness or similarity may be beneficial in reducing warping and / or enhancing structural stability. However, it is noted that such material sameness or similarity is not necessary, and the scope of the present disclosure is not limited thereto. For example, in various exemplary embodiments, any one or more of the molded encapsulation layer 370, the first molded layer 210, and the second molded layer 230 may be formed of different respective materials.

[0114] For example, the molded encapsulation layer 370 may be formed of an encapsulation EMC compound that is different from the EMC compound used to form the first molded layer 210 and / or the second molded layer 230. In an exemplary embodiment, the encapsulation EMC compound may be substantially the same as the first molded layer 210 and / or the second molded layer 230, but include a larger filler size. In another exemplary embodiment, at least one of the molded encapsulation layer 370, the first molded layer 210, and the second molded layer 230 may be formed of a molding compound, while at least another of the molded encapsulation layer 370, the first molded layer 210, and the second molded layer 230 may be formed of a dielectric material different from the molding compound.

[0115] Similarly, it is noted that the respective processes used by block 180 to form the molded packaging layer 370 (or packaging dielectric layer), block 110 to form the first molding layer 210 (or first dielectric layer), and block 130 to form the second molding layer 230 (or second dielectric layer) may be the same or different.

[0116] As discussed herein, various sides of the rotated component(s) 240' may be formed with surface bumps or other features, for example, to enhance adhesion to such surfaces. For example, the molded encapsulation layer 370 may be attached to such surfaces.

[0117] Generally speaking, block 180 may include a molded package array. Therefore, the scope of the present disclosure should not be limited by the characteristics of any particular manner of forming a molded package layer (or package dielectric layer) or the characteristics of any particular type of molded package layer (or package dielectric layer).

[0118] At block 190, the example method 100 may include forming a front-side signal distribution structure. Block 190 may include forming the front-side signal distribution structure in any of a variety of ways (e.g., including a conductive layer or redistribution layer, a dielectric layer, etc.), non-limiting examples of which are provided herein. Various example aspects of block 190 are described in detail below. Figure 3D and 3E is presented.

[0119] For example, block 190 may share any or all features with U.S. patent application Ser. No. 13 / 709,414, filed on Dec. 10, 2012, and entitled “Semiconductor Package”; U.S. patent application Ser. No. 15 / 634,041, filed on Jun. 27, 2017, and entitled “Encapsulated Semiconductor Package”; U.S. patent application Ser. No. 15 / 173,116, filed on Jun. 3, 2016, and entitled “Semiconductor Device and Method of Fabrication Thereof”; and U.S. patent application Ser. No. 15 / 469,008, filed on Mar. 24, 2017, and entitled “Semiconductor Device and Method of Fabrication Thereof”, each of which is incorporated herein by reference in its entirety for all purposes.

[0120] like Figure 3D As shown in example 300D of FIG. 3 , block 190 may, for example, include removing carrier 350 and adhesive layer 355 from the front side of molded package components 300C2 and 300C3 of FIG. 3 and connecting the molded package components (e.g., the back side of molded package layer 370 ′, the back side of mounted component 240 ′, etc.) to backside carrier 375. During this switching between carriers, as shown by comparing Figure 3D and Figure 3C As illustrated, the assembly may be rotated, for example, so that the active side of the semiconductor die 360 ​​is in the Figure 3D Backside carrier 375 and / or the molded package assembly attached thereto may share any or all features with any carrier discussed herein (eg, carrier 350 , carrier 205 , etc.) and / or components attached thereto.

[0121] For clarity of illustration, various features on the active side of semiconductor die 360 ​​have been omitted from the drawings up to this point. At least a portion of these features are now illustrated. For example, Figure 3E As shown in example 300E in FIG. 1 , the semiconductor die 360 ​​includes a die dielectric layer 382 , and the die dielectric layer 382 includes an aperture 383 , through which individual die pads 381 are exposed.

[0122] For example, block 190 may include forming a dielectric layer 384 over the front side of semiconductor die 360, such as on dielectric layer 382 and / or on a portion of die pad 381, on molded package layer 370, etc. For example, dielectric layer 384 may include aperture 385 through which die pad 381 of semiconductor die 360 ​​is exposed. For example, dielectric layer 384 may also include aperture 386 through which a top end of trace 220' of rotated component 240' is exposed.

[0123] The dielectric layer 384 (as discussed herein) may include one or more layers of any of a variety of dielectric materials, such as inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxies, siloxanes, acrylate polymers, combinations thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited in this regard.

[0124] Block 190 may include forming a dielectric layer using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the present disclosure is not limited to this.

[0125] For example, block 190 may include forming a conductive layer 387 on dielectric layer 384 and / or in apertures 385 and 386 thereof. For example, conductive layer 387 may extend through aperture 385 in dielectric layer 384 and aperture 383 in die dielectric layer 382 to contact die pad 381 of die 360. For example, conductive layer 387 may also extend through aperture 386 in dielectric layer 384 to contact an upper end of trace 220' of rotated component 240'.

[0126] Conductive layer 387 may include any of a variety of materials (eg, copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but aspects of the present disclosure are not limited thereto.

[0127] Block 190 may include forming the conductive layer 387 using any one or more of a variety of processes (e.g., electrolytic plating, electroless plating, chemical vapor deposition (CVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the disclosed aspects are not limited to this.

[0128] Note that in various example embodiments, formation of dielectric layer 384 may be omitted and conductive layer 387 may be formed directly on die pad 381 , die dielectric layer 383 , mold body 370 ′, first mold layer 310 ′ and / or second mold layer 330 ′, and trace 220 ′.

[0129] Block 190 may include forming another dielectric layer 388 on dielectric layer 384 and on conductive layer 387. Dielectric layer 388 and / or its formation may share any or all characteristics with dielectric layer 384 and its formation.

[0130] For example, dielectric layer 388 may include apertures 389 through which portions of conductive layer 387 are exposed. For example, block 190 may include package interconnect structures 391 formed in apertures 389. For example, these conductive interconnect structures 391 may include conductive balls (e.g., solder balls, copper core solder balls, etc.), metal pillars or pillars, etc. For example, these conductive interconnect structures 391 may also include an under bump metallization layer in or around apertures 389 and contacting conductive layer 387.

[0131] Generally speaking, block 190 may include forming a front-side signal distribution structure. Thus, the scope of the present disclosure should not be limited by the nature of any particular manner of forming a signal distribution structure or the nature of any particular type of signal distribution structure.

[0132] Note that after block 180 or various other blocks, a backside signal distribution structure may be formed on the backside of the package component (e.g., Figure 3E Although not shown in the drawings, any or all aspects of block 190 may be utilized to form signal distribution structures on the back side of the package (e.g., the back side of the die, the encapsulation molding layer 370', the component 240', etc.). For example, such backside signal distribution structures may be formed while carrier 350 is attached (e.g., as shown in FIG. 1 ). Figure 3C 300C2, for example after thinning is performed in block 180).

[0133] At block 195, the example method 100 may include segmenting the array of multiple packages into individual packages. Block 195 may include singulating the array of multiple packages in any of a variety of ways, non-limiting examples of which are provided herein. Various example aspects of block 195 are described in detail below. Figures 3F to 3H Presented in.

[0134] For example, Figure 3F The illustrated example 300F shows singulation lines 291 or singulation lanes along which individual electronic device packages may be singulated from an array of such devices (eg, from a wafer of such devices, from a panel or strip of such devices, etc.).

[0135] Block 195 may include performing such singulation by mechanical sawing, laser cutting, punching, using chemical etching, etc. In example 300F, singulation may, for example, make the side surfaces of molded encapsulation layer 370 , dielectric layers 384 , and 388 coplanar.

[0136] Figure 3G The example diagram 300G of FIG. 300 shows a cross-sectional view of the resulting example electronic device (or package) 390. The perspective view 300H of the example electronic device 390 is shown in FIG. Figure 3H Shown in.

[0137] At block 198, the example method 100 may include executing a continued process. This continued process may include any of a variety of characteristics, non-limiting examples of which are provided herein. For example, block 198 may include returning the execution flow of the example method 100 to any block thereof. For another example, block 198 may include directing the execution flow of the example method 100 to any other method block (step) discussed herein (e.g., with respect to the individual example methods shown in Figures 4 to 9, etc.).

[0138] Example method 100 has been developed based on Figures 2A to 3H The exemplary embodiments described are discussed in detail. Figures 2A to 3H The example embodiments shown relate to the formation of straight vias for vertical signal routing in a 3D package. However, as discussed herein, the traces 220' (or signal distribution structures) formed in the component 240' may include any of a variety of characteristics. For example, such characteristics include characteristics of resistors, fuses, delay lines, capacitors, antennas, inductors, shields, etc. The following discussion will provide non-limiting examples of various structures that may be formed, such as instead of (or in addition to) Figures 2A to 3H The structure shown.

[0139] Figures 4A to 4C Various views are shown of example resistive components and electronic devices and the manufacture of example resistive components and electronic devices according to various aspects of the present disclosure.

[0140] For example, refer to Figure 1 and Figures 4A to 4C , block 110 may include forming a first molded layer 410, which may share any or all characteristics with any other first molded layer discussed herein (e.g., first molded layer 210, etc.). For example, block 120 may include forming a trace 420 on the first molded layer 410, which may share any or all characteristics with any other trace discussed herein (e.g., trace 220, trace 420, etc.). Figures 4A to 4CAs shown, trace 420 may include a zigzag pattern to increase the path length of trace 420 when cut. For example, the increased path length may increase resistance, increase signal delay time, etc. Note that block 120 may also include forming trace 420 to have a width that controls the resistance through the trace. For example, a narrower line generally increases resistance. In another example embodiment, block 120 may include controlling the width of trace 420 (at least a portion thereof) to be narrow enough to be used as an electrical fuse, such as for power supply lines, surge protection circuits, input / output line protection, etc. Note that the trace widths do not have to be uniform. For example, a first portion of trace 420 may have a first trace width, and a second portion of trace 420 may have a second trace width that is different from the first trace width.

[0141] Although the example trace 420 (or any trace shown herein) is presented as having sharp corners, it should be understood that rounded corners can be easily formed using trace forming techniques. For example, in various circuits (e.g., in various microwave circuits, etc.), sharp corners can cause signal propagation problems. According to various aspects of the present disclosure, because the trace 420 is formed in the plane of the wafer, there is substantial flexibility in the shape of the trace formed (e.g., before rotating the cut trace 420' to a vertical plane).

[0142] After forming the second molding layer 430 at block 130, block 140 may include singulating components (for example, along Figure 4A 441, 442, 443 and 444 shown in FIG. 4). Block 140 may thus produce a singulated component 440. For example, block 150 may then rotate the singulated component 440 to produce a rotated component 440' having a cross section of Figure 4B An example diagram is shown in FIG400B.

[0143] As in Figure 4C As shown in the example of , blocks 160-195 may thus produce an electronic device 490. For example, the example electronic device 490 may share any or all characteristics with the example device 390 discussed herein. For example, the example electronic device 490 may include one or more rotated components 440', two rotated components (e.g., 440'-1 and 440'-2) in Figure 4C Note that any rotated member 440' may be oriented relative to the die 460 as shown in the perspective cross-section 400C. Figure 4C By way of example and not limitation, the member 440' may be rotated 90 degrees about a vertical axis so that the general plane of the cut traces 420' is parallel to respective lateral sides of the die 460 adjacent to the rotated member 440'.

[0144] Note that although Figure 4C Only the example resistive component 440' is shown in the example device 490 for clarity of illustration, but any of the various components (e.g., any components discussed herein, etc.) may be included in the device 490 (e.g., conductive via components, resistive components, delay line components, fuse components, capacitor components, antenna components, inductive components, etc.).

[0145] Figures 5A to 5C Various views are shown of example capacitive components and electronic devices and example methods of making example capacitive components and electronic devices according to various aspects of the present disclosure.

[0146] For example, refer to Figure 1 and Figures 5A to 5C , block 110 may include forming a first molded layer 510, which may share any or all characteristics with any other first molded layer discussed herein (e.g., first molded layer 210, first molded layer 410, first molded layer 510, etc.). For example, block 120 may then include forming a trace 520 on the first molded layer 510, which may share any or all characteristics with any other trace discussed herein (e.g., trace 220, trace 420, etc.). Figures 5A to 5C As shown, traces 520 may include a pattern of parallel leads (or plates) extending from the connection leads to parallel plates that function as capacitors. For example, the surface area of ​​the parallel plates may be specified to control capacitance.

[0147] After forming the second molding layer 530 at block 130, block 140 may include singulating components (for example, along Figure 5A 541, 542, 543 and 544 are shown in FIG. 1 ). Block 140 may thus produce a singulated component 540. For example, block 150 may then rotate the singulated component 540 to produce a rotated component 540' having a cross section of Figure 5B An example illustration is shown in FIG500B.

[0148] As in Figure 5C As shown in the example of , blocks 160-195 may then produce an electronic device 590. For example, the example electronic device 590 may share any or all characteristics with the example devices 390 and 490 discussed herein. For example, the example electronic device 590 may include one or more rotated components 540', two rotated components (e.g., 540'-1 and 540'-2) in Figure 5C Note that any rotated member 540' may be oriented as shown in the perspective cross-section 500C of the die 560. Figure 5CBy way of example and not limitation, the member 540' may be rotated 90 degrees about a vertical axis so that the general plane of the cut traces 520' is parallel to respective lateral sides of the die 560 adjacent to the rotated member 540'.

[0149] In an example capacitor implementation, example method 100 may include steps or sub-steps (e.g., as part of block 120 and / or as an additional block between blocks 120 and 130) in which a layer of dielectric material having desired capacitor properties (e.g., different from the material used to form second mold layer 530) is formed between parallel plates of the capacitor. Figure 5A , an example of a resulting structure included in an alternative capacitor configuration is provided. For example, a first alternative capacitor configuration 501 is shown with a capacitor dielectric layer 501d between the plates of the capacitor. For another example, a second alternative capacitor configuration 502 is shown with a capacitor dielectric layer 502d between the plates of the capacitor. For another example, a third alternative capacitor configuration 503 is shown with a capacitor dielectric layer 503d between the plates of the capacitor. For example, if the dielectric material (e.g., EMC material or other material) used for the first molded layer 510 and the second molded layer 530 does not contain the dielectric layer properties required for the capacitor, the capacitor dielectric layer may be formed, for example, separately from the first molded layer 510 and the second molded layer 530. Note that any of a variety of capacitive configurations can be formed in addition to those shown. Another example capacitor configuration may include a plurality of spaced-apart teeth, such as a first plate containing a first set of teeth with spaces therebetween and a second plate containing a second set of teeth with spaces therebetween, the first teeth being positioned in the spaces between the second sets of teeth, and the second sets of teeth being positioned in the spaces between the first sets of teeth.

[0150] For example, this additional block 125 may include printing or coating example capacitor dielectric layers 501d, 502d, and 503d. For another example, block 125 may include forming a shield in which the area between the capacitor plates is exposed through openings in the shield, and includes depositing the capacitor dielectric layer in the shield opening and then stripping the shield layer.

[0151] Note that although Figure 5C Only the example capacitive component 540' is shown in the example device 590 for clarity of illustration, but any of the various components (e.g., any components discussed herein, etc.) may be included in the device 590 (e.g., conductive via components, resistive components, delay line components, fuse components, capacitor components, antenna components, inductive components, etc.).

[0152] It is also noted that any of these various components may also be included in the component 540'. For example, a resistor configuration (e.g., Figures 4A to 4C) can be configured with a capacitor (e.g., as Figures 5A to 5C As shown in the figure, a parallel or series RC circuit can be formed. For example, one or more capacitors can be configured in series or in parallel to achieve the desired capacitor characteristics.

[0153] Figures 6A to 6C Various views are shown of example bimetallic connection components and electronic devices and example methods of manufacturing the example bimetallic connection components and electronic devices according to various aspects of the present disclosure.

[0154] For example, refer to Figure 1 and Figures 6A to 6C , block 110 may include forming a first molded layer 610, which may share any or all characteristics with any other first molded layer discussed herein (e.g., first molded layer 210, first molded layer 410, first molded layer 510, etc.). For example, block 120 may then include forming a trace 620 on the first molded layer 610, which may share any or all characteristics with any other trace discussed herein (e.g., trace 220, trace 420, trace 520, etc.). Figures 6A to 6C As shown in FIG. , trace 620 may include Figures 2A to 3H However, traces 620 may include any of a variety of shapes, with many other examples provided herein.

[0155] As this article about Figures 2A to 3H As discussed in the examples presented in , trace 620 may include a conductive layer 622 plated on (but not necessarily on) a seed layer 621. For example, trace 620, seed layer 621, and / or conductive layer 622 (or formations thereof) may share any or all characteristics with trace 220, seed layer 221, and / or conductive layer 222 (or formations thereof). For example, trace 620 may include multiple conductive layers 622 and 623. For example, conductive layers 622 and 623 may include different respective metals. Many examples of such metals are presented herein, such as in the discussion of example conductive layer 222, in the discussion of example seed layer 221, etc., but the scope of the present disclosure is not limited by the characteristics of any such metals or the characteristics of the formations of such metals. For example, conductive layers 622 and 623 may include different respective metals for electromigration reasons, for warpage compensation reasons, for metallic bonding reasons, for adhesive bonding reasons, etc. Note that in an example embodiment, conductive layer 623 may include solder.

[0156] After forming the second molding layer 930 at block 130, block 140 may include singulating the components (for example, along singulation lines), many examples of which are provided herein. Block 140 may thus produce singulated components 640. For example, block 150 may then rotate the singulated components 640 to produce rotated components 640', whose cross-section is Figure 6B An example illustration is shown in FIG600B.

[0157] As in Figure 6C As shown in the example of , blocks 160-195 may thus produce an electronic device 690. For example, the example electronic device 690 may share any or all characteristics with the example devices 590, 490, and 390 discussed herein. For example, the example electronic device 690 may include one or more rotated components 640', two rotated components (e.g., 640'-1 and 640'-2) in Figure 6C A three-dimensional cross section 600C is shown.

[0158] Note that although Figure 6C Only an example bimetallic (or trimetallic) vertical via component 640' is shown in the example device 690 for clarity of illustration, but any of the various components (e.g., any components discussed herein, etc.) may be included in the device 690 (e.g., conductive via components, resistive components, delay line components, fuse components, capacitor components, antenna components, inductive components, etc.).

[0159] Figures 7A to 7C Various views are shown of example shielding components and electronic devices and example methods of making the example shielding components and electronic devices according to various aspects of the present disclosure.

[0160] For example, refer to Figure 1 and Figures 7A to 7C , block 110 may include forming a first molded layer 710, which may share any or all characteristics with any other first molded layer discussed herein (e.g., first molded layer 210, first molded layer 410, first molded layer 510, first molded layer 610, etc.). For example, block 120 may include forming a trace 720 (or traces) on the first molded layer 710, which may share any or all characteristics with any other traces discussed herein (e.g., traces 220, traces 420, traces 520, traces 620, etc.). As described in Figures 7A to 7C As shown in , instead of multiple traces (e.g., extending parallel to each other), (multiple) traces 720 may include a solid conductive layer 722 covering the entire first mold layer 710 (e.g., on the seed layer 721 or not on the seed layer 721). However, the traces 720 may include any of a variety of shapes, and many other examples are provided herein. For example, the traces 720 may include a mesh pattern, etc.

[0161] After forming the second molding layer 730 at block 130, block 140 may include singulating the components (for example, along singulation lines), many examples of which are provided herein. Block 140 may thus produce singulated components 740. For example, block 150 may then rotate the singulated components 740 to produce rotated components 740', whose cross-section is Figure 7B An example example 700B is shown.

[0162] As in Figure 7C As shown in the example of , blocks 160-195 may then produce an electronic device 790. For example, the example electronic device 790 may share any or all characteristics with the example devices 690, 590, 490, and 390 discussed herein. For example, the example electronic device 790 may include one or more rotated components 740', two rotated components 740' (e.g., 740'-1 and 740'-2) in Figure 7C A three-dimensional cross section 700C is shown.

[0163] Note that although Figure 7C Only shielding member 640' is shown in the example device 790 for clarity of illustration, but any of the various components (e.g., any components discussed herein, etc.) may be included in the device 790 (e.g., conductive via components, resistive components, delay line components, fuse components, capacitor components, antenna components, inductive components, etc.).

[0164] In an exemplary embodiment, shielding members 740' may be positioned on each lateral side of the die 760. For example, such shielding members 740' may be electrically connected to each other through a front side signal distribution structure, as discussed herein. For another example, such shielding members 740' may be electrically connected to each other by an upper conductive layer attached to the top side of the device 791 or formed on the top side of the device 790. For another example, the shielding members 740' may be formed with a conductor that extends through either the first mold layer 710 or the second mold layer 730 so that the conductive layer can be directly connected to the conductive layer 720 of the adjacent member 740'. For another example, the shielding members 740' may be electrically connected to each other via a back side signal distribution structure, as discussed herein.

[0165] Non-limiting examples of forming such shielding layers may be found in U.S. patent application Ser. No. 15 / 469,008, filed on Mar. 24, 2017, and entitled “Semiconductor Device and Method of Fabrication Thereof”; and U.S. patent application Ser. No. 15 / 236,664, filed on Aug. 15, 2016, and entitled “Shielded Electronic Component Package”; each of which is hereby incorporated by reference in its entirety.

[0166] Notice that Figure 7B and 7C An example component 740' is presented as including a solid conductive layer 720 for shielding, the configuration of the conductive layer 720 may include any of a variety of characteristics (eg, configured as columns of strips, configured as a grid of columns and rows, configured as a perforated sheet, etc.).

[0167] Figures 8A to 8G Various views are shown of example inductive components and electronic devices and example methods of making the example inductive components and electronic devices according to various aspects of the present disclosure.

[0168] As discussed herein, multilayer conductive structures may be formed to accomplish any of a variety of objectives. Figures 8A to 8G The example inductor implementations shown in provide non-limiting examples.

[0169] For example, refer to Figure 1 and Figures 8A to 8G , block 110 may include forming a first molded layer 810, which may share any or all characteristics with any other first molded layer discussed herein (e.g., first molded layer 210, first molded layer 410, first molded layer 510, first molded layer 610, first molded layer 710, etc.). For example, block 120 may then include forming a first layer trace 820-1 on the first molded layer 810, which may share any or all characteristics with any other trace discussed herein (e.g., trace 220, trace 420, trace 520, trace 620, trace 720, etc.). Fig. 8A As shown in the example diagram 800A1 of , the trace 820-1 may include a spiral pattern, wherein the first connecting lead extends to (or is located at) the outer end of the spiral pattern. As will be discussed, the second conductive layer and / or the third conductive layer may be used to provide electrical connection to the inner end of the spiral pattern.

[0170] When forming the second mold layer 830 at block 130 , an aperture 824 may be formed in the second mold layer 830 to expose the first layer trace 820 - 1 , for example, at the center of each spiral pattern. Figure 8B A top view 800B1 and a cross-sectional view 800B2 of the second molding layer 830 are shown.

[0171] For example, at block 130, after forming the second mold layer 830, a block can be added to the example method 100 to form a second conductive layer 825. For example, the second conductive layer 825 can include the same properties as any conductive layer discussed herein and / or be formed in the same method. For example, the second conductive layer 825 can be formed to contact the center of the spiral pattern (of the first conductive layer 820) via the aperture 824 in the second mold layer 830. Figure 8CAs shown, the second conductive layer 825 may include leads that effectively traverse from the exterior of the spiral pattern to the interior end of the spiral pattern, but in a different plane than the spiral pattern.

[0172] After forming the second conductive layer 825, the example method 100 may include another block to form a third mold layer 837. This block and / or the mold layer 837 formed thereby may share any or all characteristics with the block 130 and / or the second mold layer 830 formed thereby. Fig.8D An example top view 800D1 and a side cross-sectional view 800D2 are provided. Note that the thickness T4 of the third mold layer 837 may be selected to (in combination with the second mold layer 830 ) provide a similar (and opposite) warping force as the first mold layer 810 .

[0173] Block 140 may include singulation components (e.g., Fig. 8E 841, 842, 843 and 844 shown in FIG. 1 ). Block 140 may thus produce a singulated component 840. For example, block 150 may then rotate the singulated component 840 to produce a rotated component 840' having a cross section of Figure 8F An example example 800B is shown. Figure 8F A side view 800B1 and a bottom view 800B2 of the rotated member 840' are shown. Note that the exposed end of the first lead 820'-1 and the exposed end of the second lead 825'-1 provide electrical terminals to the inductor. Note that the second lead 825'-1 can be exposed at the bottom end or the top end of the rotated member 840'-1. In other words, unlike Figure 8F 800B2, the end of lead 825'-1 may be on the opposite side of rotated component 840'-1 as the end of lead 820'-1. Similarly, any or all electronic components discussed herein may include leads on the same side of the formed component or on opposite sides of the formed component.

[0174] As in Figure 8G As shown in the example of , blocks 160-195 may then produce an electronic device 890. For example, the example electronic device 890 may share any or all characteristics with the example devices 390, 490, 590, 690, and 790 discussed herein. For example, the example electronic device 890 may include one or more rotating components 840', two rotating components 740' (e.g., 840'-1 and 840'-2) in Figure 8G Note that any rotated member 840' may be oriented relative to the die 860 as shown in cross section 800G. Figure 8GBy way of example and not limitation, member 840' may be rotated 90 degrees about a vertical axis such that the general planes of cut traces 820' and 825' are parallel to respective lateral sides of die 560 adjacent to rotated member 540'.

[0175] Note that although Figure 8G Only the example inductive component 840' is shown in the example device 890 for clarity of illustration, but any of the various components (e.g., any components discussed herein, etc.) may be included in the device 890 (e.g., conductive via components, resistive components, delay line components, fuse components, capacitor components, antenna components, inductive components, etc.).

[0176] It is also noted that any of these various components may also be included in component 840'. For example, a resistor configuration (e.g., Figures 4A to 4C ) and / or capacitor configuration (e.g., as Figures 5A to 5C ) can be configured with an inductor (e.g., Figures 8E to 8G As shown in the figure, the inductor components can be combined to form a parallel or series RC circuit, LC circuit, RLC circuit, etc. Also for example, one or more inductor configurations can be formed in series or in parallel to achieve the desired inductor characteristics. For example, these components can be formed on the same plane and / or on different respective planes, and / or connected to each other on the same plane and / or on different respective planes.

[0177] like Figures 6A to 6C As shown, a connection member can be formed and utilized, wherein the connection member includes multiple conductive layers. In an exemplary embodiment, the inner metal can be surrounded by the outer metal. Non-limiting examples of the formation and utilization of such connection members will now be presented.

[0178] like Figures 9A to 9F As shown, the center conductor can be surrounded by the outer conductor. Figures 9A to 9F In the example shown in , a peripheral conductor including one or more conductive layers surrounds and conductively contacts a central conductor. However, such conductors may be separated by a dielectric layer.

[0179] Figures 9A to 9F Various views are shown of example coaxial connection components and electronic devices and example methods of making the example coaxial connection components and electronic devices according to various aspects of the present disclosure.

[0180] For example, refer to Fig.9A(e.g., top view 900A1 and cross-sectional view 900A2), block 110 may include forming a first molding layer 910 on the carrier 905. The first molding layer 910 and / or its formation may share any or all characteristics with any other first molding layer discussed herein (e.g., first molding layer 210, 410, 510, 610, 710, 810, etc.) and / or its formation.

[0181] For example, block 120 may then form a first trace 920 (or pattern or layer) on the first molded layer 910. The first trace 920 and / or its formation may share any or all characteristics with any other traces (e.g., 220, 420, 520, 620, 720, 820, etc.) and / or their formation discussed herein. Fig.9A As shown, the first trace 920 may include Figures 2A to 3H , Figures 6A to 6C However, first trace 920 may include any of a variety of shapes, and many other examples are provided herein.

[0182] refer to Fig. 9B (e.g., top view 900B1 and cross-sectional view 900B2), block 120 may, for example, also include forming a second trace 924 (or pattern or layer). The second trace 924 and / or its formation may share any or all characteristics with any other traces discussed herein (e.g., traces 220, 420, 520, 620, 720, 820, 920, etc.) and / or their formation. For example, the second trace 924 may be formed directly on the top side of the first trace 920, for example, following the exact pattern of the first trace 920.

[0183] In an example embodiment, the first trace 920 and the second trace 924 may be formed using different respective metals. Many examples of such metals are presented herein, such as in the discussion of the example conductive layer 222, in the discussion of the example seed layer 221, etc., but the scope of the present disclosure is not limited by any such metals or the properties forming such metals. For example, the first trace 920 and the second trace 924 may include different respective metals for the sake of electron migration, for the sake of warpage compensation, for the sake of metallic bonding, for the sake of adhesive bonding, etc. Note that in an example embodiment, one of the first trace 920 and the second trace 924 may include copper, and the other of the first trace 920 and the second trace 924 may include a metal other than copper (e.g., solder, any other metal discussed herein, etc.).

[0184] In an example implementation, block 120 may include forming first trace 920 and second trace 924 using the same type of formation process, and may, for example, include forming (eg, plating, etc.) first trace 920 and second trace 924 in the same aperture of a shielding layer.

[0185] refer to Fig. 9C (e.g., top view 900C1 and cross-sectional view 900C2), block 120 may, for example, additionally include forming a third trace 926. The third trace 926 and / or its formation may share any or all characteristics with any other traces discussed herein (e.g., traces 220, 420, 520, 620, 720, 820, 920, 924, etc.) and their formation. For example, the third trace 926 may be formed directly on the top side of the second trace 924 and / or may be formed directly on the lateral side surfaces of the second trace 924 and the first trace 920.

[0186] In an example embodiment, the first trace 920 and the third trace 926 may be formed of the same metal, while the second trace 924 is formed of a different metal. Many examples of such metals are presented herein, such as in the discussion of the example conductive layer 222, in the discussion of the example seed layer 221, etc., but the scope of the present disclosure is not limited by the characteristics of any such metals or the characteristics of the metals formed. For example, any or all of the first trace 920, the second trace 924, and the third trace 926 may include different respective metals for the sake of electron migration, for the sake of warpage compensation, for the sake of metallic bonding, for the sake of adhesive bonding, etc. Note that in an example embodiment, the first trace 920 and the third trace 926 may include the same metal and generally coaxially surround the second trace 924 formed of a different metal. For example, the second trace 927 may include copper, and the first trace 920 and the third trace 926 may include a metal other than copper (eg, solder, nickel, any other metal discussed herein, etc.).

[0187] In an example embodiment, block 120 may include forming first trace 920, second trace 924, and / or third trace 926 using the same type of formation process (e.g., electroplating or electroless plating process, etc.), but in alternative embodiments, one or more different respective processes may be used.

[0188] For example, block 130 may then form a second mold layer 930 on the first mold layer 910. The second mold layer 930 and / or its formation may share any or all characteristics with any of the second mold layers discussed herein (e.g., second mold layers 230, 330, 430, 530, 630, 730, 830, etc.) and their formation. For example, block 130 may include forming the second mold layer 930 to cover at least the top side of the first mold layer 910 and the top and lateral sides of the traces (920, 924, and 926). For another example, block 130 may include forming the second mold layer 930 to have a thickness such that the thickness of the second mold layer 930 above the third trace 926 is the same as the thickness of the first mold layer 910 below the first trace 920. For example, such thicknesses reduce or eliminate warping.

[0189] After forming the second molding layer 930 in block 130, block 140 may include singulating out components (for example, along singulation lines). Example singulation lines 941 to 944 are shown in FIG. Fig.9D 900D1 and cross-sectional view 900D2). Block 140 may thus produce a singulated component 940. For example, block 150 may then rotate singulated component 940 to produce a rotated component 940', the perspective view of which is shown in FIG. Fig.9E An example illustration is shown in FIG900E.

[0190] As in Fig.9F As shown in the example diagram of FIG. 1 , blocks 160 to 195 may thus produce an electronic device 990. For example, the example electronic device 990 may share any or all characteristics with the example devices discussed herein (e.g., 890, 790, 690, 590, 490, 390, etc.). For example, the example electronic device 990 may include one or more rotated components 940', two rotated components 940' (e.g., 940'-1 and 940'-2) in Fig.9F A perspective cross-sectional view 900F is shown.

[0191] Note that although Fig.9F Only an example bimetallic (or trimetallic) vertical via component 940' is shown in the example device 990 for clarity of illustration, but any of the various components (e.g., any components discussed herein, etc.) may be included in the device 990 (e.g., conductive via components, resistive components, delay line components, fuse components, capacitor components, antenna components, inductive components, etc.).

[0192] Figures 9A to 9FThe example shown in generally relates to a second trace 924 coaxially surrounded by (and in contact with) a first trace 920 and a third trace 926, with no insulating separation between the traces. In other example embodiments, the first trace 920 and the third trace 926 may still coaxially surround the second trace 924, but may be separated from the second trace 924 by one or more layers of dielectric material, such as to result in coaxial and electrically isolated paths. For example, such a configuration may be beneficial for electromagnetically shielding the second trace 924 and / or providing multiple coaxial signal paths. An example of this embodiment will now be presented.

[0193] Figures 10A to 10G Various views are shown of example insulating coaxial connection components and example methods of making the example insulating coaxial connection components according to various aspects of the present disclosure.

[0194] For example, refer to Fig. 10A (e.g., cross-sectional view 1000A), block 110 may include forming a first molding layer 1010 on the carrier 1005. The first molding layer 1010 and / or its formation may share any or all characteristics with any other first molding layer discussed herein (e.g., first molding layers 210, 410, 510, 610, 710, 810, 910, etc.) and / or its formation.

[0195] For example, block 120 may then form a first trace 1020 on first molded layer 1010. First trace 1020 and / or its formation may share any or all characteristics with any other traces (e.g., traces 220, 420, 520, 620, 720, 820, 920, 924, 926, etc.) and / or their formation discussed herein. Fig. 10A As shown, the first trace 1020 may include Figures 2A to 3H , Figures 6A to 6C , Figures 9A to 9F However, first trace 1020 may include any of a variety of shapes, and many other examples are provided herein.

[0196] After forming the example first trace 1020, refer to Fig. 10B (e.g., cross-sectional view 1000B), block 120 may include forming a first dielectric layer 1027. For example, in an exemplary embodiment, block 110 may include forming the first dielectric layer 1027 on top of the first trace 1020, but narrower than the first trace 1020. Thus, an edge of the top surface of the first trace 1020 may be exposed from the first dielectric layer 1027. However, such exposure is not required. For example, in another exemplary embodiment, the first dielectric layer 1027 may completely cover the top side of the first trace 1020, such as to conform to the contour of the first trace 1020.

[0197] The first dielectric layer 1027 (such as any dielectric layer discussed herein) may include one or more layers composed of any of a variety of dielectric materials, such as inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxies, siloxanes, acrylate polymers, combinations thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto. For example, the first dielectric layer 1027 may include a dielectric material different from the dielectric material of the first molding layer 1010.

[0198] Block 120 may include forming the dielectric layer(s) using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the disclosed aspects are not limited thereto.

[0199] The first dielectric layer 1027 can include any of a variety of thicknesses. For example, the first dielectric layer 1027 can be thicker than the first trace 1020 (or thinner or the same thickness).

[0200] For example, refer to Fig. 10C (e.g., cross-sectional view 1000C), block 120 may also include forming a second trace 1024. The second trace 1024 and / or its formation may share any or all characteristics with any other traces discussed herein (e.g., traces 220, 420, 520, 620, 720, 820, traces 920, 924, 926, 1020, etc.) and / or their formation. For example, the second trace 1024 may be formed directly on the top and lateral sides of the first dielectric layer 1027, for example, following the exact pattern of the first dielectric layer 1027 and / or the first trace 1020. For example, as Fig. 10C As shown, the second trace 1024 can be formed to have the same pattern, including width, as the first dielectric layer 1027. For example, the second trace 1024 can be formed to cover the top side of the first dielectric layer 1027.

[0201] In an example embodiment, the first trace 1020 and the second trace 1024 may be formed using the same respective metal (e.g., copper, etc.), but the scope of the present disclosure is not limited in this regard. Many examples of such metals are presented herein, such as in the discussion of the example conductive layer 222, in the discussion of the example seed layer 221, etc., but the scope of the present disclosure is not limited by the characteristics of any such metals or the characteristics of the metals formed. In another example embodiment, the first trace 1020 and the second trace 1024 may include different respective metals, for example, for reasons of warpage compensation, reasons of bonding, etc. For example, one of the first trace 1020 and the second trace 1024 may include copper, and the other of the first trace 1020 and the second trace 1024 may include a metal other than copper (e.g., solder, any other metal discussed herein, etc.).

[0202] In an exemplary embodiment, block 120 may include forming first trace 1020 and second trace 1024 using the same type of formation process, but the scope of the present disclosure is not limited to this embodiment.

[0203] After forming the example second trace 1024, refer to Fig. 10D (e.g., cross-sectional view 1000D), block 120 may include forming a second dielectric layer 1028. For example, in an exemplary embodiment, block 120 may include forming a second dielectric layer 1027 on top of the first trace 1020, around the side surface of the first dielectric layer 1027, and on top of the second conductive layer 1024 and around the side surface of the second conductive layer 1024. Thus, overall, the first dielectric layer 1027 and the second dielectric layer 1028 may form an insulating tube (or sheath), such as a coaxial insulating tube, through which the second trace 1024 extends while being electrically isolated from the first trace 1020.

[0204] The first dielectric layer 1028 (and any dielectric layer as discussed herein) may include one or more layers of any of a variety of dielectric materials, such as inorganic dielectric materials (e.g., Si3N4, SiO2, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and / or organic dielectric materials (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxies, siloxanes, acrylate polymers, combinations thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto. For example, the second dielectric layer 1028 may include the same dielectric material as the first dielectric layer 1027, but the scope of the present disclosure is not limited thereto.

[0205] Block 120 may include forming the layer(s) using any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporation, etc.), but the disclosed aspects are not limited thereto.

[0206] The second dielectric layer 1028 can include any of a variety of thicknesses. For example, the second dielectric layer 1028 can have substantially the same thickness as the first dielectric layer 1027.

[0207] For example, refer to Fig. 10E (e.g., cross-sectional view 1000E), block 120 may further include forming a third trace 1026. The third trace 1026 and / or its formation may share any or all characteristics with any other traces discussed herein (e.g., traces 220, 420, 520, 620, 720, 820, 920, 924, 1020, 1024, etc.) and their formation. For example, the third trace 1026 may be formed directly on the top side and lateral sides of the second dielectric layer 1028, and directly on the lateral sides of the first trace 1020. Therefore, in general, the first dielectric layer 1027 and the second dielectric layer 1028 can form an insulating tube (or sheath), such as a coaxial insulating tube, through which the second trace 1024 extends; and in general, the first trace 1020 and the third trace 1026 can form a conductive tube (or sheath), such as a coaxial insulating tube, an insulating tube (of the first dielectric layer 1027 and the second dielectric layer 1028) and an conductive tube extending through.

[0208] In an exemplary embodiment, the first trace 1020, the second trace 1024, and the third trace 1026 may be formed of the same metal (e.g., copper, etc.), but the scope of the present disclosure is not limited in this regard. For example, any or all of the first trace 1020, the second trace 1024, and the third trace 1026 may be formed of different respective metals. Many examples of such metals are presented herein, such as in the discussion of the exemplary conductive layer 222, in the discussion of the exemplary seed layer 221, etc., but the scope of the present disclosure is not limited by the properties of any such metals or the properties of the metals formed. For example, any or all of the first trace 1020, the second trace 1024, and the third trace 1026 may include the same or different respective metals for the sake of warpage compensation, for the sake of metallic bonding, for the sake of adhesive bonding, etc.

[0209] It should be noted that any or all of the traces discussed herein may be formed with a seed layer having one or more other metal layers formed thereon, as discussed herein for the example trace 220. For example, a first seed layer may be formed on the first mold layer 1010, with a second portion of the first trace 1020 formed on the first mold layer 1010; a second seed layer may be formed on the first dielectric layer 1027, with a second portion of the second trace 1024 formed on the first dielectric layer 1027; and a third seed layer may be formed on the first dielectric layer 1027, the second dielectric layer 1028, and / or the first conductive layer 1020, with a second portion of the third trace 1026 formed on the first dielectric layer 1027, the second dielectric layer 1028, and / or the first conductive layer 1020.

[0210] In an exemplary embodiment, block 120 may include forming the first trace 1020 , the second trace 1024 , and / or the third trace 1026 using the same type of formation process (eg, electroplating or electroless plating process, etc.), but the scope of the present disclosure is not limited in this regard.

[0211] refer to Fig.10F (e.g., cross-sectional view 1000F), block 130 may then, for example, include forming a second mold layer 1030 on the first mold layer 1010. The second mold layer 1030 and / or its formation may share any or all characteristics with the second mold layers discussed herein (e.g., second mold layers 230, 330, 430, 530, 630, 730, 830, 930, etc.) and their formation. For example, block 130 may include forming the second mold layer 1030 to cover at least the top side of the first mold layer 1010, the traces (1020, 1024, and 1026), and the dielectric layer (1027 and 1028). For another example, block 130 may include forming the second mold layer 1030 to have a thickness such that the thickness of the second mold layer 1030 above the third trace 1026 is the same as the thickness of the first mold layer 1010 below the first trace 1020. For example, such thicknesses reduce or eliminate warping.

[0212] After forming the second molding layer 1030 at block 130, block 140 may include singulation components (for example, along singulation lines), many non-limiting examples of which are provided herein. Example singulation lines 1041-1042 are Fig.10F (eg, at cross-sectional view 1000F). Block 140 may thus produce singulated component 1040. For example, block 150 may then rotate singulated component 1040 to produce rotated component 1040', which is shown in FIG. Figure 10G An example diagram is shown in FIG1000G.

[0213] As with many other example illustrations herein (e.g., Fig.9F , Figure 8G , Figure 7C , Figure 6C , Figure 5C , Figure 4C , Figure 3H As shown in FIG. 1 , blocks 160-195 may then produce an electronic device incorporating one or more components 1040'. For example, this example electronic device may share any or all characteristics with the example devices discussed herein (e.g., example devices 990, 890, 790, 690, 590, 490, 390, etc.). Note that any of the various components (e.g., any of the components discussed herein) may be included in the final device (e.g., conductive via components, resistive components, delay line components, fuse components, capacitor components, antenna components, inductive components, etc.).

[0214] like Figures 8A to 8F As shown in the examples and discussion thereof, various aspects of the present disclosure may be used to form and use an inductor. The inductor may be formed in a variety of ways. Other examples of the formation of the inductor are described in Figures 11A to 11F Shown in.

[0215] Figures 11A to 11F Various views are shown of example inductive components and example methods of making example inductive components according to various aspects of the present disclosure.

[0216] As discussed herein, multilayer conductive structures may be formed to accomplish any of a variety of objectives. Figures 11A to 11F The example inductor implementations shown in provide non-limiting examples.

[0217] For example, refer to Figure 1 and Figures 11A to 11F , block 110 may form a first molded layer 1110, which may share any or all characteristics with any other first molded layer discussed herein (e.g., first molded layers 210, 410, 510, 610, 710, 810, 910, 1010, etc.). For example, block 120 may then include forming a first trace 1120 (or pattern or layer) on the first molded layer 1110, which may share any or all characteristics with any other trace discussed herein (e.g., traces 220, 420, 520, 620, 720, 820, 920, 1020, 1024, 1026, etc.). Fig.11A As shown in the top view illustration 1100A of , the first traces 1120 may include a parallel trace pattern from which the first connecting leads 1198 extend.

[0218] When forming the second mold layer 1130 at the block 130 , an aperture 1127 may be formed in the second mold layer 1130 to expose the first traces 1120 , for example, at the end of each parallel trace. Fig. 11B A top view 1100B is shown of the aperture 1127 in the second molding layer 1130 .

[0219] After forming the second molded layer 1130, for example at block 130, execution of the example method 100 may return to block 120 any number of times to form additional layers (e.g., conductive layers or traces, dielectric layers, etc.). For example, block 120 may include forming a second trace 1128. For example, the second trace 1128 may include having the same properties and / or being formed in the same manner as any conductive layer or trace discussed herein. Fig. 11C (eg, top view 1100C), the second traces 1128 may, for example, include a pattern of parallel traces from which the second connecting leads 1199 extend, each of the second traces 1128 contacting the first trace 1120 through a respective aperture 1127 in the second molding layer 1130 .

[0220] After forming the second trace 1128, the example method 100 may repeat block 130 to form a third mold layer 1137. The mold layer 1137 and / or its formation may share any or all characteristics with any other mold layer and / or its formation discussed herein.

[0221] Example top view 1100D1 and side cross-sectional view 1100D2 (eg, taken along a singulation line) are shown in FIG. Fig.11D Note that the thickness T4 of the third mold layer 1137 may be selected such that the third mold layer 1137 (in combination with the second mold layer 1130 ) provides a similar (and opposite) warping force as the first mold layer 1110 .

[0222] Block 140 may include singulation components (e.g., Fig.11D 1141, 1142, 1143, 1144 shown in FIG. 1142). Block 140 can thus produce a singulated component 1140. For example, block 150 can then rotate the singulated component 1140 to produce a rotated component, many examples of which are provided herein. Note that the exposed ends of the first connecting lead 1198 and the exposed ends of the second connecting lead 1199 provide electrical terminals to the inductor component 1140.

[0223] although Figures 11A to 11DThe exemplary embodiment in FIG. 1 shows that both the connecting leads 1198 and 1199 of the inductor are exposed at the same surface of the member 1140, but the scope of the present disclosure is not limited in this regard. For example, the connecting leads 1198 and 1199 may be exposed at opposite ends of the member. A non-limiting example of this structure is shown in FIG. Fig.11E and 11F Shown.

[0224] refer to Fig.11E , the block 120 may include forming a first trace 1120_alt on the first mold layer 1110 so that the first connecting lead 1198_alt extends to the component and the second connecting lead 1199 (such as Fig. 11C In this configuration, when component 1140_alt is rotated to produce rotated component 1140_alt' (as shown in FIG. Fig.11F 1100F), the first connecting lead 1198_alt extends to the top side of the rotated component 1140_alt', and the second connecting lead 1199 extends to the bottom side of the rotated component 1140_alt'. Similarly, any or all of the electronic components discussed herein may include connecting leads at the same side of the formed component, at opposite sides of the formed component, at adjacent sides of the formed component, or any combination thereof, depending on the desired routing of the connecting leads.

[0225] As with many other example illustrations herein (e.g., Fig.9F , Figure 8G , Figure 7C , Figure 6C , Figure 5C , Figure 4C , Figure 3H As shown in FIG. 1 , blocks 160-195 may then produce an electronic device incorporating one or more components 1140'. For example, this example electronic device may share any or all characteristics with the example devices discussed herein (e.g., example devices 990, 890, 790, 690, 590, 490, 390, etc.). Note that any of the various components (e.g., any of the components discussed herein, etc.) may be included in the final device (e.g., conductive via components, resistive components, delay line components, fuse components, capacitor components, antenna components, inductive components, etc.).

[0226] It is also noted that any of these various components may also be included in member 1140' and / or in any of the components discussed herein. For example, a resistor configuration (e.g., Figures 4A to 4C ) and / or capacitor configuration (e.g., as Figures 5A to 5C ) and inductor configurations (e.g., Figures 8E to 8G11A to 11F) to form parallel or series RL circuits, LC circuits, RLC circuits, etc. Also, for example, one or more inductor configurations may be formed in series or in parallel to obtain desired inductor characteristics. For example, these components may be formed on the same plane and / or on different respective planes, and / or connected to each other on the same plane and / or on different respective planes. In addition, one or more linear components may also be incorporated to provide conductive vias for direct signal transmission.

[0227] like Figures 5A to 5C As shown in , the capacitor components can be formed with the capacitor plates formed in the same conductive layer 520. However, it is noted that in alternative configurations, the capacitor components can be formed with Figures 11A to 11F 1. For example, the first trace 1120 may also be replaced by a plate (or a flat conductive surface). For another example, the second molded layer 1130 may be replaced by a dielectric layer more suitable for use between the plates of a capacitor (many examples of which are provided herein), and the via aperture 1127 may be omitted. Then, the second trace 1128 may also be replaced by a plate (or a flat conductive surface).

[0228] The examples presented herein generally form signal distribution structures (e.g., RDL, substrate, etc.) on semiconductor die(s), rotated component(s), and a molded body. It should be noted that the scope of the present disclosure is not limited by this order. For example, semiconductor die(s) and / or rotated component(s) may be attached to a pre-formed substrate (e.g., having at least a portion of its signal routing capabilities already formed) that will remain as part of the finished package. A non-limiting example of this formation will now be provided.

[0229] Fig.12 A flowchart of an example method of manufacturing an electronic device according to various aspects of the present disclosure is shown. For example, the example method 1200 (or a block thereof) may share any or all characteristics with any method (or a block thereof) shown and discussed herein.

[0230] For example, blocks 1205, 1210, 1220, 1230, 1240, and 1250 may be associated with Figure 1 Blocks 105 , 110 , 120 , 130 , 140 , and 150 shown in and discussed herein share any or all characteristics.

[0231] However, blocks 1260 and 1270 include mounting the semiconductor die(s) (and / or other components) and the rotated components(s) to a substrate that will remain as part of the finished package. For example, this substrate may include at least a portion of a final signal distribution structure that has already been constructed. For example, this substrate may include a printed wiring board (PWB) or printed circuit board (PCB), a silicon wafer (or portion thereof) having a signal distribution structure formed thereon (e.g., in a back-end semiconductor wafer manufacturing process), a stacked coreless signal distribution structure (e.g., as described herein in Figure 3E Non-limiting examples provided at example 300E of the present invention include dielectric layer 384, conductive layer 387, dielectric layer 388, etc. Various non-limiting examples of bonding of substrates on (or formed on) a silicon wafer can be found in U.S. Patent Application No. 15 / 854,095, entitled “Semiconductor Package and Method of Manufacturing the Same,” filed on December 26, 2017, the entire contents of which are incorporated herein by reference.

[0232] Blocks 1260 and 1270 may include mounting the semiconductor die(s) and the rotated component(s) to the substrate (e.g., pads and / or signal distribution structures thereof) in any of a variety of ways. For example, blocks 1260 and 1270 may utilize soldering processes (e.g., mass reflow, thermal compression solder bonding, etc.), direct metal-to-metal solderless bonding, conductive adhesive bonding, etc.

[0233] Note that blocks 1260 and 1270 may utilize different attachment processes to attach the semiconductor die(s) and the rotated component(s) to the substrate. For example, block 1260 may include utilizing a soldering process to attach the semiconductor die(s) to the substrate, and block 1270 may include utilizing a conductive adhesive to attach the rotated component to the substrate. For another example, block 1260 may include utilizing a mass reflow process to attach the semiconductor die(s) to the substrate, and block 1270 may include utilizing thermal compression bonding and / or direct metal-to-metal bonding to attach the rotated component to the substrate.

[0234] Block 1280 (for example, forming a molded encapsulation layer) may share any or all characteristics with block 180. Note, however, that in the case of block 1280, the molded encapsulation layer will cover the die(s), the rotated component(s), and the top side of the substrate. Figure 3C As shown in examples 300C2 and 300C3, the upper end of the trace 220' may be exposed at the top side of the molded body 370'.

[0235] At this point, as shown at block 1290, processing can continue on the component to form signal distribution structures and / or package interconnects on the top and / or bottom sides of the component (e.g., as backside signal distribution structures on a side of the package corresponding to the passive side of the die(s), and / or as additional frontside signal distribution structures on an external side of the substrate). For example, block 1290 can be performed with Figure 1 Block 190 of the example method 100 shown in and discussed herein shares any or all characteristics.

[0236] At block 1295, the example method 1200 may include singulating the package. For example, block 1295 may be associated with Figure 1 Block 195 of the example method 100 shown in and discussed herein shares any or all characteristics.

[0237] At block 1298, the example method 1200 may include performing a continued process. The continued process may include any of a variety of characteristics, non-limiting examples of which are provided herein. For example, block 1298 may include returning the execution flow of the example method 1200 to any block thereof. For another example, block 1298 may include returning the execution flow of the example method 1200 to any other method block (or step) discussed herein (e.g., regarding Figure 1 to 1 1, etc.).

[0238] The discussion herein includes a number of illustrative drawings showing various parts of semiconductor device components (packages) and / or methods of manufacturing the same. For clarity, these figures do not show all aspects of each example component. Any example component presented herein may share any or all characteristics with any or all other components presented herein.

[0239] In general, various aspects of the present disclosure provide electronic components and electronic devices including one or more electronic components, as well as methods for manufacturing electronic components and electronic devices including one or more electronic components. As non-limiting examples, various aspects of the present disclosure provide vertical interconnect components and various other vertical electronic components and methods for manufacturing them, as well as provide electronic devices including one or more vertical interconnect components and various other vertical electronic components and methods for manufacturing them. Although certain aspects and examples have been described above, it should be understood by those skilled in the art that various changes can be made and can be replaced with equivalents without departing from the scope of the present disclosure. In addition, many modifications can be made to adapt specific situations or materials to the teachings of the present disclosure without departing from its scope. Therefore, it is desired that the present disclosure is not limited to the specific (multiple) examples disclosed, and the present disclosure will include all examples that fall within the scope of the appended claims.

[0240] CROSS-REFERENCE TO RELATED APPLICATIONS / INCORPORATED BY REFERENCE

[0241] This application is related to U.S. patent application Ser. No. 15 / 469,008, filed on Mar. 24, 2017, entitled “Semiconductor Device and Method of Fabrication Thereof”; U.S. patent application Ser. No. 13 / 709,414, filed on Dec. 10, 2012, entitled “Semiconductor Package”; U.S. patent application Ser. No. 15 / 634,041, filed on Jun. 27, 2017, entitled “Encapsulated Semiconductor Package”; and U.S. patent application Ser. No. 15 / 634,041, filed on Jun. 3, 2016, entitled “Encapsulated Semiconductor Package”. No. 15 / 173,116, filed on August 15, 2016, and entitled “Semiconductor Device and Method of Fabrication Thereof”; No. 15 / 236,664, filed on August 15, 2016, and entitled “Shielded Electronic Component Package”; and No. 15 / 854,095, filed on December 26, 2017, and entitled “Semiconductor Package and Method of Fabrication Thereof”; each of which is hereby incorporated by reference in its entirety.

Claims

1. An electronic device, comprising: a substrate having a first side and a second side; A first component, the first component comprising: a top member side, a bottom member side, and a cross member side extending between the top member side and the bottom member side, wherein the bottom member side is mounted to the first side of the base plate; at least one row of a plurality of vertical through holes extending between said top member side and said bottom member side; and a molding material laterally surrounding each of the plurality of vertical through-holes, wherein the cross-member side includes only the molding material; a semiconductor die having a top die side, a bottom die side, and a lateral die side extending between the top die side and the bottom die side, the bottom die side coupled to the first side of the substrate; and A molded package includes a molding compound covering at least a portion of the first side of the substrate, at least a portion of the lateral die side, and at least a portion of the lateral member side. 2 . The electronic device of claim 1 , wherein the substrate comprises a conductive layer electrically connecting a die pad of the semiconductor die to a first end of at least one vertical via of the plurality of vertical vias.

3. The electronic device as claimed in claim 2, wherein: The substrate comprises a dielectric layer, the dielectric layer comprises a first aperture and a second aperture, the die pad of the semiconductor die is exposed from the dielectric layer through the first aperture, and the first end of at least one vertical through-hole of the plurality of vertical through-holes is exposed from the dielectric layer through the second aperture; and The conductive layer extends into the first aperture and the second aperture. 4 . The electronic device of claim 1 , wherein the molding compound of the molded package laterally surrounds the entire semiconductor die and the entire first component.

5. The electronic device of claim 4, wherein a top side of the molding compound is coplanar with the top member side.

6. The electronic device of claim 1, wherein the molding compound covers the top die side.

7. The electronic device of claim 1, wherein each of the plurality of vertical through holes is exposed from the molding material at the top member side and the bottom member side.

8. The electronic device of claim 1, wherein each of the plurality of vertical vias is one of a plurality of parallel linear traces of a component conductive layer.

9. The electronic device of claim 1, further comprising a die pad on the bottom die side, wherein: The die pad on the bottom die side is attached to the substrate.

10. An electronic device comprising: Signal distribution structure; A first component mounted to the signal distribution structure, the first component comprising: a plurality of parallel through holes, each through hole in the plurality of parallel through holes having a first end face, a second end face, and a lateral side face; an encapsulation material covering the lateral side of each of the plurality of parallel through holes, the encapsulation material having a top member side, a bottom member side, and a lateral member side extending between the top member side and the bottom member side, the first end face of each of the plurality of parallel through holes being exposed from the top member side of the encapsulation material, and the second end face of each of the plurality of parallel through holes being exposed from the bottom member side of the encapsulation material; a semiconductor die coupled to the signal distribution structure; and A molded package is provided, the molded package comprising a molding compound laterally covering the semiconductor die and the lateral member sides, the molding compound being coplanar with the top member side. 11 . The electronic device of claim 10 , wherein the molding compound of the molded package laterally surrounds the entire semiconductor die.

12. The electronic device of claim 11, wherein the molding compound covers the top die side.

13. The electronic device of claim 10, wherein the signal distribution structure comprises a signal distribution structure conductive path electrically connecting a die pad of the semiconductor die to the first end surface of at least one parallel through-hole of the plurality of parallel through-holes.

14. The electronic device of claim 13, wherein: The signal distribution structure includes a dielectric layer, the dielectric layer includes a first aperture and a second aperture, The die pad of the semiconductor die is exposed from the dielectric layer through the first aperture, and The first end surface of at least one parallel through-hole of the plurality of parallel through-holes is exposed from the dielectric layer through the second aperture; and The signal distribution structure conducting path extends into the first aperture and the second aperture.

15. The electronic device of claim 10, wherein the plurality of parallel through holes comprises at least three parallel through holes arranged in a row.

16. An electronic device comprising: a substrate having a first side and a second side; A first component, the first component comprising: a top member side, a bottom member side, and a cross member side extending between the top member side and the bottom member side, wherein the bottom member side is mounted to the first side of the base plate; a conductive pattern including a first pattern end; and a molding material at least partially laterally surrounding the conductive pattern, wherein the first pattern end emerges from the molding material at the bottom member side; a semiconductor die having a top die side, a bottom die side, and a lateral die side extending between the top die side and the bottom die side, the bottom die side coupled to the first side of the substrate; and A molding compound covers the first side of the substrate, the lateral die side, and at least a portion of the lateral member side, the molding compound being coplanar with the top member side.

17. The electronic device of claim 16, wherein the conductive pattern comprises at least one trace. 18 . The electronic device of claim 16 , wherein the conductive pattern includes a second pattern end exposed from the molding material at the top member side.

19. The electronic device of claim 18, wherein the conductive pattern is one of a resistive member pattern, a capacitor member pattern, a bimetallic connection member pattern, a shielding member pattern, an inductive member pattern, a coaxial connection member pattern, and an insulated coaxial connection member pattern. 20 . The electronic device of claim 16 , wherein the conductive pattern includes a second pattern end exposed from the molding material at the bottom member side, and wherein the conductive pattern is an inductive member pattern.

21. An electronic component, comprising: a first molding layer; a conductive layer on a portion of the first side of the first mold layer, comprising a seed layer and a conductive layer; wherein the seed layer is on a portion of the first side of the first mold layer, the conductive layer is located above the seed layer, and; as well as A second molding layer is on the first side of the first molding layer and on the component conductive layer.

22. The electronic component according to claim 21, wherein The second mold layer has a thickness greater than that of the first mold layer.

23. An electronic component, comprising: a first molding layer; a component conductive layer on the first molding layer; as well as A second molding layer is on the component conductive layer.

24. The electronic component of claim 23, wherein the component conductive layer comprises a mesh pattern.

25. An electronic component, comprising: a first molding layer; a first conductive layer overlying a portion of the first side of the first molding layer; a second molded layer on the component conductive layer and over a portion of the first molded layer; wherein the second molded layer is provided with an aperture to expose a terminal end of the component conductive layer; a second conductive layer contacting an end of the first conductive layer 820 via the aperture of the second molding layer; A third molding layer covers the second conductive layer and the second molding layer.

26. The electronic component according to claim 25, wherein The thickness of the third molding layer is selected to provide, in combination with the second molding layer, a similar and opposite warping force as the first molding layer.

27. An electronic component comprising: a first molding layer; a first conductive layer overlying a portion of the first side of the first molding layer; a second conductive layer on a top side of the first conductive layer; a third conductive layer on a top side of the second conductive layer and on lateral side surfaces of the second conductive layer and the first conductive layer; A second mold layer is on a portion of the first mold layer and covers the third conductive layer.

28. The electronic component according to claim 27, wherein The first conductive layer and the third conductive layer are made of the same metal, while the second conductive layer is made of a different metal.

29. An electronic component comprising: a first molding layer; a first conductive layer overlying a portion of the first side of the first molding layer; a first dielectric layer on a top surface of the first conductive layer with an edge of the top surface exposed from the first dielectric layer; a second conductive layer covering a top side of the first dielectric layer; a second dielectric layer on a top surface of the first conductive layer, surrounding side surfaces of the first dielectric layer, and on a top surface of the second conductive layer and surrounding side surfaces of the second conductive layer; a third conductive layer on the top side and lateral sides of the second dielectric layer and on the lateral sides of the first dielectric layer; a second molding layer; It covers at least the first side of the first mold layer, the first conductive layer, the second conductive layer, the third conductive layer, and the first dielectric layer and the third conductive layer.

30. The electronic component according to claim 29, wherein The second mold layer has a thickness such that a thickness of the second mold layer above the third conductive layer is the same as a thickness of the first mold layer below the first conductive layer.

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