Memory block element with probe pad arrangement and stacked memory device

Abstract

The invention discloses a memory block element with a probe pad array and a stacked memory device. The memory block element has: a first surface and a second surface; the first probe pad group is provided with a first probe pad and is arranged on the first surface; the second probe pad group is provided with a second probe pad and is arranged on the second surface; first conductive connectors, each of the first conductive connectors being connected to a corresponding first probe pad; second conductive connecting pieces, wherein each second conductive connecting piece is connected to the corresponding first conductive connecting piece; each of the third conductive connecting pieces is connected to the corresponding second conductive connecting piece; and fourth conductive connectors, each of which is connected to a corresponding third conductive connector and a corresponding second probe pad. The first probe pad group and the second probe pad group have the same arrangement pattern and the same test signal pattern.

Description

Technical Field

[0001] The present invention relates to a test scheme for a memory device, and in particular to a probe pad arrangement of a memory block cell and a stacked memory device. Background Art

[0002] Stacked semiconductor devices have been well developed. For example, Figure 1A and Figure 1B As shown in , a stacked memory device including a logic chip 110 and a memory chip 120 stacked on each other can be obtained by wafer-on-wafer (WoW) technology and through-silicon via (TSV) technology. The stacked memory device 100 can be a stacked dynamic random access memory (DRAM) memory device, and a single logic chip 110 with a memory controller 112 is stacked face-to-face to the memory chip 120. The memory chip 120 includes a plurality of memory tiles 122 (e.g., M×N memory tiles 122), and a 4×2 configuration is illustrated as an example. The memory tiles 122 generally have the same structure and size.

[0003] The logic chip 110 may be stacked on the memory chip 120 to form a stacked memory device 100. Figure 1B , TSV 124A is provided for signal transmission between logic chip 110 and memory chip 120, and TSV 124B is provided for memory block 122. Logic chip 110 and memory chip 120 can be bonded together via metal pins 128. Memory block 122 also provides internal wiring (internal metal layer) 126 for providing metal interconnection.

[0004] In this structure, when the test engineer is ready to test the memory chip (memory wafer), a probe card with two rows of probe needles is used. The surface of the memory block element 122 is provided with two rows of probe pads. Then, the memory test can be performed by touching the two rows of probes to the two rows of probe pads. There are two types of tests, one is performed from the front of the memory block element 122, and the other is performed from the back of the memory block element 122 (after the WoW manufacturing process). Two types of probe cards need to be provided for front testing and back testing, respectively.

[0005] However, this will increase the test cost, so it is necessary to use a probe card suitable for both front side test and back side test. Summary of the invention

[0006] As described above, according to an embodiment of the present invention, a memory block element with a probe pad arrangement is provided. The memory block element includes: a first surface and a second surface opposite to the first surface; a first probe pad group, having a plurality of first probe pads and arranged on the first surface; a second probe pad group, having a plurality of second probe pads and arranged on the second surface; a plurality of first conductive connections, each of which is electrically connected to a corresponding first probe pad in the first probe pad group; a plurality of second conductive connections, each of which is electrically connected to a corresponding first conductive connection in the plurality of first conductive connections; a plurality of third conductive connections, each of which is electrically connected to a corresponding second conductive connection in the plurality of second conductive connections; and a plurality of fourth conductive connections, each of which is electrically connected to a corresponding third conductive connection in the plurality of third conductive connections and electrically connected to a corresponding second probe pad in the second probe pad group. The first arrangement pattern of the first probe pad group is the same as the second arrangement pattern of the second probe pad group, and the first test signal pattern of the first probe pad group viewed from the first surface is the same as the second test signal pattern of the second probe pad group viewed from the second surface.

[0007] According to another embodiment of the present invention, a stacked memory device is provided. The stacked memory device includes: a memory chip having a plurality of memory blocks; and a logic chip bonded to the memory chip in a face-to-face manner and configured to control the memory chip. The memory block includes: a first surface and a second surface opposite to the first surface; a first probe pad group having a plurality of first probe pads and arranged on the first surface; a second probe pad group having a plurality of second probe pads and arranged on the second surface; a plurality of first conductive connectors, each of which is electrically connected to a corresponding first probe pad in the first probe pad group; a plurality of second conductive connectors, each of which is electrically connected to a corresponding first conductive connector in the plurality of first conductive connectors; a plurality of third conductive connectors, each of which is electrically connected to a corresponding second conductive connector in the plurality of second conductive connectors; and a plurality of fourth conductive connectors, each of which is electrically connected to a corresponding third conductive connector in the plurality of third conductive connectors and electrically connected to a corresponding second probe pad in the second probe pad group. A first arrangement pattern of the first probe pad group is the same as a second arrangement pattern of the second probe pad group, and a first test signal pattern of the first probe pad group viewed from the first surface is the same as a second test signal pattern of the second probe pad group viewed from the second surface.

[0008] According to the above-mentioned embodiment, in the memory block element or the stacked memory device, the test signal pattern of the plurality of third conductive connections viewed from the first surface of the memory block element is mirror-symmetrical to the test signal pattern of the plurality of third conductive connections viewed from the second surface of the memory block element.

[0009] According to the above-mentioned embodiment, in the memory block or the stacked memory device, each of the plurality of first conductive connections is a redistribution layer, and each of the plurality of fourth conductive connections is a redistribution layer.

[0010] According to the above-mentioned embodiment, in the memory block or the stacked memory device, each of the plurality of third conductive connections is a through silicon via (TSV).

[0011] According to the above-mentioned embodiment, in the memory block or the stacked memory device, each of the plurality of second conductive connections is formed by at least one internal metal layer disposed in the memory block.

[0012] According to the above embodiment, in the memory block or the stacked memory device, the plurality of first probe pads are arranged in two rows along the center line of the first arrangement pattern of the first probe pad group, and the plurality of second probe pads are arranged in two rows along the center line of the second arrangement pattern of the second probe pad group.

[0013] According to the above-mentioned embodiment, in the memory block unit or the stacked memory device, the memory block unit is a DRAM block unit.

[0014] According to another embodiment of the present invention, a memory block element having a probe pad arrangement is provided. The memory block element includes: a first surface and a second surface opposite to the first surface; a first probe pad group having a plurality of first probe pads and arranged on the first surface; a second probe pad group having a plurality of second probe pads and arranged on the second surface; and a plurality of connection structures, each of the plurality of connection structures being electrically connected to a corresponding first probe pad among the plurality of first probe pads and electrically connected to a corresponding second probe pad among the plurality of second probe pads. The first arrangement pattern of the first probe pad group is the same as the second arrangement pattern of the second probe pad group, and the first test signal pattern of the first probe pad group viewed from the first surface is the same as the second test signal pattern of the second probe pad group viewed from the second surface.

[0015] According to the above-mentioned embodiment, in the memory block element, each of the multiple connection structures includes: a first redistribution layer, electrically connected to the corresponding first probe pad; an internal connection, electrically connected to the first redistribution layer; a through silicon via (TSV), electrically connected to the internal connection; and a second redistribution layer, electrically connected to the corresponding second probe pad.

[0016] According to the above embodiment, in the memory block, the internal connection may include a plurality of internal metal layers disposed in the memory block.

[0017] According to the above embodiment, in the memory block cell, the test signal pattern of the TSV viewed from the first surface of the memory block cell is mirror-symmetric to the test signal pattern of the TSV viewed from the second surface of the memory block cell.

[0018] According to the embodiment, in the memory block, the plurality of first probe pads are arranged in two columns along a center line of the first arrangement pattern of the first probe pad group, and the plurality of second probe pads are arranged in two columns along a center line of the second arrangement pattern of the second probe pad group.

[0019] According to the embodiment, in the memory block element, the memory block element is a DRAM block element.

[0020] In order to make the foregoing content easier to understand, several embodiments with accompanying drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention.

[0022] Figure 1A is a schematic structural diagram of a stacked memory device;

[0023] Figure 1B for Figure 1A A cross-sectional schematic diagram of a stacked memory device is shown;

[0024] Figure 2A and Figure 2B is a schematic diagram of an arrangement pattern of probe pads and a test signal pattern located on two surfaces of a memory block;

[0025] Figure 3 A schematic cross-sectional view of a memory block according to an embodiment of the present invention, wherein a connection structure is provided between two groups of probe pads located on two surfaces of the memory block;

[0026] Figure 4A and Figure 4B A front view schematic diagram and a rear view schematic diagram of a memory block according to an embodiment of the present invention, wherein a connection structure is provided between two groups of probe pads located on two surfaces of the memory block;

[0027] Figure 5A and Figure 5B For invention Figure 4A and Figure 4B Variations of the front view schematic diagram and the rear view schematic diagram of the memory block element with the connection structure shown.

[0028] Explanation of symbols

[0029] 100: memory device

[0030] 110:Logic chip

[0031] 112: Memory controller

[0032] 120:Memory chip

[0033] 122: memory block element

[0034] 122A: First surface

[0035] 122B: Second surface

[0036] 124A, 124B:TSV

[0037] 126: Internal wiring / internal metal layer

[0038] 128:Metal pin

[0039] 300: Base

[0040] 310: first probe pad group

[0041] 315: First probe pad

[0042] 320: second probe pad group

[0043] 325: Second probe pad

[0044] 330: first conductive connection (front side RDL)

[0045] 332: second conductive connection (inner metal layer)

[0046] 334: third conductive connection (TSV)

[0047] 336: fourth conductive connection (rear side RDL)

[0048] 340: Internal memory element

[0049] A <0> , A <1> , A <2> , A <3> :Address signal (test signal)

[0050] CAS, CKE, CLK, CS, RAS, WE: command signal (test signal)

[0051] DQ <0> :Input / output (I / O) data signal (test signal)

[0052] DQ <1> :Input / output (I / O) data signal (test signal)

[0053] L1, L2: center line

[0054] VDD, VDDQ, VSS, VSSQ: voltage signals (test signals) DETAILED DESCRIPTION

[0055] Figure 2A and Figure 2B Draw the arrangement pattern of the probe pads and the test signal pattern on the two surfaces of the memory block. Figure 1A In the general architecture shown, the memory chip 120 may include a plurality of memory blocks 122. The memory blocks 122 are arranged like bricks on a wafer (not shown). According to the size of the logic chip 110, a specific number of memory blocks 122 (forming the memory chip 120) are cut out from the wafer, and the cut memory blocks are stacked on the logic chip 110 to form the stacked memory device 100.

[0056] Each memory block 122 in the memory chip 120 has a first surface 122A and a second surface 122B, and the second surface 122B and the first surface 122A are opposite to each other, for example, in parallel. Figure 2A and Figure 2B , the memory block 122 further includes a first probe pad group 310. The first probe pad group 310 has a plurality of first probe pads 315 and is disposed on the first surface 122A (e.g., the front surface). Similarly, the memory block 122 further includes a second probe pad group 320. The second probe pad group 320 has a plurality of second probe pads 325 and is disposed on the second surface 122B (e.g., the rear surface). For simplicity, four first probe pads 315 (for receiving input / output (I / O) data signals DQ <0> , DQ <1> and address signal A <0> , A <1> ) and four second probe pads 325 (for receiving I / O data signals DQ <0> , DQ <1> and address signal A <0> , A <1> test signal). Figure 2A and Figure 2B, an example of two rows of first probe pads 315 on the first surface 122A and two rows of second probe pads 325 on the second surface 122B is shown. However, the first probe pads 315 and the second probe pads 325 may also be arranged to have more rows (even number rows).

[0057] The first probe pad group 310 and the second probe pad group 320 have the same arrangement pattern. For example, the arrangement pattern of the first probe pad group 310 has two rows of first probe pads 315, and the two rows of first probe pads 315 are symmetrically arranged with respect to the center line L1 of the first probe pad group 310. Figure 2A and Figure 2B As shown, the second probe pad set 320 also has the same arrangement pattern, that is, the arrangement pattern of the second probe pad set 320 has two columns of second probe pads 325 , and the two columns of second probe pads 325 are symmetrically arranged with respect to the center line L2 of the second probe pad set 320 .

[0058] In addition, the first probe pad group 310 and the second probe pad group 320 have the same test signal pattern. Figure 2A As shown in FIG. 1 , when the memory block 122 is viewed from the first surface 122A, the first probe pad 315 located in the upper row is a DQ <0> 、VDDQ、…、A <2> , A <0> , CAS, RAS, CKE, VDD, and the first probe pad 315 located below is DQ <1> , VSSQ, …, A <3> , A <1> , WE, CS, CLK, VSS. In addition, if Figure 2B As shown in FIG. 1 , when the memory block 122 is viewed from the second surface 122B, the second probe pad 325 in the upper row is a DQ <0> 、VDDQ、…、A <2> , A <0> , CAS, RAS, CKE, VDD, and the second probe pad 325 located below is DQ <1> , VSSQ, …, A <3> , A <1> , WE, CS, CLK, VSS. Among the test signals, DQ <0> , DQ <1> is the I / O data signal, A <0> , …, A <n>(n is an integer) is the address signal, CAS, RAS, CKE, WE, CS, CLK are command signals, VSS, VDD, VDDQ, VSSQ are voltage signals, and these signals are precisely defined in the DRAM specifications.

[0059] Therefore, when the memory block 122 (or wafer) is turned upside down, the test signal pattern of the first probe pad group 310 on the first surface 122A is the same as the test signal pattern of the second probe pad group 320 on the second surface 122B. Therefore, the same probe card can be used for the probe pads on the first surface 122A and the second surface 122B of the memory block 122.

[0060] According to the embodiment of the present invention, in order to provide such a test signal pattern for the first probe pad set 310 and the second probe pad set 320, a connection structure is provided between the first probe pad set 310 and the second probe pad set 320. Next, the connection structure between the first probe pad set 310 and the second probe pad set 320 will be described in detail.

[0061] Figure 3 A cross-sectional view of a memory block according to an embodiment of the present invention is shown, with a connection structure between two groups of probe pads located on two surfaces of the memory block. Figure 4A and Figure 4B A front view and a rear view of a memory block according to an embodiment of the present invention are shown, with a connection structure between two groups of probe pads located on two surfaces of the memory block.

[0062] exist Figure 3 , the memory block 122 is disposed on a substrate 300. The substrate 300 may be, for example, a silicon substrate or other suitable materials. The memory block 122 includes a plurality of first conductive connections 330, a plurality of second conductive connections 332, a plurality of third conductive connections 334, and a plurality of fourth conductive connections 336. The conductive connections 330, 332, 334, and 336 form a connection structure for electrically connecting the first probe pad group 310 to the second probe pad group 320. The plurality of second conductive connections 332 may be further connected to an internal memory element 340, such as a transistor (e.g., as a memory cell).

[0063] Reference Figure 3 and Figure 4A , the number of the plurality of first conductive connections 330 is substantially the same as the number of the first probe pads 315 in the first probe pad group 310 located on the first surface 122A of the memory block 122. Each of the plurality of first conductive connections 330 is electrically connected to a corresponding first probe pad 315 in the first probe pad group 310. In one embodiment, the first conductive connections 330 may be implemented by a redistribution layer / line (RDL) (i.e., a front-side RDL). For example, the front-side RDL 330 (for DQ <0> ) is electrically connected to the corresponding first probe pad 315 (for DQ <0> ), front side RDL 330 (for A <0> ) is electrically connected to the corresponding first probe pad 315 (for A <0> ), front side RDL 330 (for DQ <1> ) is electrically connected to the corresponding first probe pad 315 (for DQ <1> ), and the front side RDL 330 (for A <1> ) is electrically connected to the corresponding first probe pad 315 (for A <1> ).

[0064] exist Figure 3 According to an embodiment of the present invention, each of the plurality of second conductive connections 332 may be formed by a set of a plurality of metal layers (internal metal layers or internal connections), and other components of the memory block 122 may be connected via the set of a plurality of metal layers. In addition, the number of the plurality of second conductive connections 332 is substantially the same as the number of the first conductive connections 330. Each of the plurality of second conductive connections 332 is electrically connected to a corresponding first conductive connection 330 in the plurality of first conductive connections 330. For example, Figure 4A As shown in FIG. , the inner metal layer 332 (for DQ <0> ) is electrically connected to the corresponding front side RDL 330 (for DQ <0> ), inner metal layer 332 (for A <0> ) is electrically connected to the corresponding front side RDL 330 (for A <0> ), inner metal layer 332 (for DQ <1> ) is electrically connected to the corresponding front side RDL 330 (for DQ <1> ), and the inner metal layer 332 (for A <1> ) is electrically connected to the corresponding front side RDL 330 (for A <1> ).

[0065] In addition, if Figure 4A As shown in FIG. 1 , for example, TSV 334 (for DQ <0> ) is arranged on the first probe pad 315 (for DQ <0> ) on the opposite side. That is, the first probe pad 315 (for DQ <0> ) is disposed on one side of the center line L1, and TSV 334 (for DQ <0> ) is located on the other side of the center line L1. Then, through the front side RDL 330 (for DQ <0> ) and inner metal layer 332 (for DQ <0> ) for TSV 334 (for DQ <0> ) and the first probe pad 315 (for DQ <0> ) for electrical connection. Through the internal metal layer 332 (for DQ <0> ), the first probe pad 315 (for DQ <0> ) across the center line L1 to electrically connect to TSV 334 (for DQ <0> ). In addition, Figure 4B As shown in FIG. 1 , when the memory block 122 is flipped, due to the mirror symmetry, the TSV 334 (for DQ <0> ) becomes a TSV 334 (for DQ <0> ). Therefore, the second probe pad 325 on the same side is connected to the TSV 334 (for DQ <0> ) can be electrically connected through the fourth conductive connection member 336, so that the second probe pad 325 can receive the test signal DQ <0> Therefore, the test signal pattern of the second probe pad set 320 located on the second surface 122B is the same as the test signal pattern of the first probe pad set 310 located on the first surface 122A.

[0066] In addition, the number of the plurality of third conductive connections 334 is substantially the same as the number of the second conductive connections 332. Each of the plurality of third conductive connections 334 is electrically connected to a corresponding second conductive connection 332 (i.e., an inner metal layer). In one embodiment, the third conductive connection 334 may be implemented by a through silicon via (TSV). The TSV 334 may pass through the substrate 300 and be connected to at least one layer of the corresponding inner metal layer 332. For example, Figure 4A As shown in FIG. , TSV 334 (for DQ <0> ) is electrically connected to the corresponding inner metal layer 332 (for DQ <0> ), TSV 334 (for A <0> ) is electrically connected to the corresponding internal metal layer 332 (for A <0> ), TSV 334 (for DQ <1> ) is electrically connected to the corresponding inner metal layer 332 (for DQ <1> ), and TSV 334 (for A <1> ) is electrically connected to the corresponding internal metal layer 332 (for A <1> ).

[0067] It should be noted that TSV 334 (for DQ <0> ) is configured for use with DQ <0> The TSV 334 (for DQ <1> )、TSV 334(for A <0> ) and TSV 334 (for A <1> ) are configured for and used for DQ <1> The first probe pad 315 for A <0> The first probe pad 315 and the <1> The opposite side of the first probe pad 315. Figure 4A As shown in FIG. 1 , each of the first probe pads 315 on one side (eg, above the center line L1 ) is electrically connected to a corresponding TSV 334 on the other side (eg, below the center line L1 ) via a corresponding front side RDL 330 and a corresponding inner metal layer 332 .

[0068] In addition, if Figure 3 and Figure 4B As shown in FIG. 1 , the number of the plurality of fourth conductive connections 336 is substantially the same as the number of the third conductive connections 334. Each of the plurality of fourth conductive connections 336 is electrically connected to a corresponding third conductive connection 334 (i.e., TSV 334). In one embodiment, the fourth conductive connection 336 may be implemented by a redistribution layer / redistribution trace (RDL) (i.e., backside RDL). For example, the backside RDL 336 (for DQ <0> ) is electrically connected to the corresponding TSV 334 (for DQ <0> ) and the corresponding second probe pad 325 (for DQ <0> ), rear side RDL 336 (for A <0> ) is electrically connected to the corresponding TSV334 (for A <0> ) and the corresponding second probe pad 325 (for A <0> ), rear side RDL 336 (for DQ <1> ) is electrically connected to the corresponding TSV 334 (for DQ <1> ) and the corresponding second probe pad 325 (for DQ <1> ), and the rear RDL 336 (for A <1> ) is electrically connected to the corresponding TSV 334 (for A <1> ) and the corresponding second probe pad 325 (for A <1> ).

[0069] according to Figure 4A and Figure 4B In the connection structure shown in FIG. 1 , the test signal pattern of the third conductive connection (TSV) 334 viewed from the first surface 122A of the memory block 122 and the test signal pattern of the third conductive connection (TSV) 334 viewed from the second surface 122B of the memory block 122 are mirror-symmetric with respect to the center line L1 or L2. The first probe pad group 310 and the second probe pad group 320 are connected by using the corresponding front side RDL 330, the inner metal layer 332, the TSV 334 and the back side RDL 336. When the memory block 122 (or the wafer) is turned over, the test signal pattern of the first probe pad group 310 is the same as the test signal pattern of the second probe pad group 320. Therefore, no matter which surface of the memory block 122 is to be tested, the same probe card can be used.

[0070] Figure 5A and Figure 5B Show Figure 4A and Figure 4B A variation of the front view schematic diagram and the rear view schematic diagram of the memory block element with the connection structure shown in FIG. Figure 5A and Figure 5B , the connection configuration of the front side RDL 330, the inner metal layer 332, the TSV 334 and the back side RDL 336 is different from Figure 4A and Figure 4B In this structure, relative to the center line L2, the test signal pattern of the TSV 334 observed from the first surface 122A is the same as the test signal pattern of the first probe pad group 310, and the test signal pattern of the TSV 334 observed from the second surface 122B is opposite to the test signal pattern of the second probe pad group 320. Figure 5A and Figure 5B The connection configuration in is different from Figure 4A and Figure 4B , however, the test signal pattern of the TSV 334 viewed from the first surface 122A of the memory block 122 and the test signal pattern of the TSV 334 viewed from the second surface 122B of the memory block 122 are still mirror-symmetric with respect to the center line L1 or L2. Therefore, when the memory block 122 (or wafer) is turned over, the test signal pattern of the first probe pad group 310 is the same as the test signal pattern of the second probe pad group 320. Therefore, no matter which surface of the memory block 122 is to be tested, the same probe card can be used.

[0071] In summary, according to the connection structure of the above embodiment, the arrangement pattern and test signal pattern of the first probe pad group are the same as the arrangement pattern and test signal pattern of the second probe pad group. Therefore, when the memory block element is flipped, the same probe card can be used to perform the back-side test. The test cost can be reduced, and the test procedure can be more flexible.

[0072] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the invention. In summary, the present invention is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.< / n>

Claims

1. A memory block element having a probe pad arrangement, comprising: a first surface and a second surface opposite to the first surface; A first probe pad group, comprising a plurality of first probe pads and arranged on the first surface; A second probe pad group, comprising a plurality of second probe pads and arranged on the second surface; a plurality of first conductive connectors, each of the plurality of first conductive connectors being electrically connected to a corresponding first probe pad in the first probe pad set; a plurality of second conductive connectors, each of the plurality of second conductive connectors being electrically connected to a corresponding first conductive connector among the plurality of first conductive connectors; a plurality of third conductive connections, each of the plurality of third conductive connections being electrically connected to a corresponding second conductive connection of the plurality of second conductive connections; as well as a plurality of fourth conductive connections, each of the plurality of fourth conductive connections being electrically connected to a corresponding third conductive connection of the plurality of third conductive connections and electrically connected to a corresponding second probe pad of the second probe pad set, wherein a first arrangement pattern of the first probe pad group is the same as a second arrangement pattern of the second probe pad group, and A first test signal pattern of the first probe pad group viewed from the first surface is identical to a second test signal pattern of the second probe pad group viewed from the second surface.

2. The memory block element of claim 1, wherein The test signal pattern of the plurality of third conductive connections viewed from the first surface of the memory block cell is mirror-symmetric to the test signal pattern of the plurality of third conductive connections viewed from the second surface of the memory block cell.

3. The memory block element of claim 1, wherein Each of the plurality of first conductive connections is a redistribution layer, and Each of the fourth conductive connections is a redistribution layer.

4. The memory block element of claim 1, wherein Each of the plurality of third conductive connections is a through silicon via (TSV).

5. The memory block element of claim 1, wherein Each of the plurality of second conductive connections is formed by at least one internal metal layer disposed in the memory block cell.

6. The memory block element of claim 1, wherein The plurality of first probe pads are arranged in two rows along a center line of the first arrangement pattern of the first probe pad group, and The plurality of second probe pads are arranged in two rows along a center line of the second arrangement pattern of the second probe pad group.

7. The memory block element of claim 1, wherein The memory block element is a dynamic random access memory block element.

8. A stacked memory device comprising: A memory chip having a plurality of memory blocks; as well as a logic chip, which is bonded to the memory chip in a face-to-face manner and is configured to control the memory chip, Each of the plurality of memory block elements further comprises: a first surface and a second surface opposite to the first surface; A first probe pad group, comprising a plurality of first probe pads and arranged on the first surface; A second probe pad group, comprising a plurality of second probe pads and arranged on the second surface; a plurality of first conductive connectors, each of the plurality of first conductive connectors being electrically connected to a corresponding first probe pad in the first probe pad set; a plurality of second conductive connectors, each of the plurality of second conductive connectors being electrically connected to a corresponding first conductive connector among the plurality of first conductive connectors; a plurality of third conductive connections, each of the plurality of third conductive connections being electrically connected to a corresponding second conductive connection of the plurality of second conductive connections; and a plurality of fourth conductive connections, each of the plurality of fourth conductive connections being electrically connected to a corresponding third conductive connection of the plurality of third conductive connections and electrically connected to a corresponding second probe pad of the second probe pad set, wherein a first arrangement pattern of the first probe pad group is the same as a second arrangement pattern of the second probe pad group, and A first test signal pattern of the first probe pad group viewed from the first surface is identical to a second test signal pattern of the second probe pad group viewed from the second surface.

9. The stacked memory device of claim 8, wherein The test signal patterns of the plurality of third conductive connections viewed from the first surface of each of the plurality of memory cells are mirror-symmetric to the test signal patterns of the plurality of third conductive connections viewed from the second surface of the memory cells.

10. The stacked memory device of claim 8, wherein Each of the plurality of first conductive connections is a redistribution layer, and Each of the fourth conductive connections is a redistribution layer.

11. The stacked memory device of claim 8, wherein Each of the plurality of third conductive connections is a through silicon via (TSV).

12. The stacked memory device of claim 8, wherein Each of the plurality of second conductive connections is formed of at least one internal metal layer disposed in each of the plurality of memory cells.

13. The stacked memory device of claim 8, wherein The plurality of first probe pads are arranged in two rows along a center line of the first arrangement pattern of the first probe pad group, and The plurality of second probe pads are arranged in two rows along a center line of the second arrangement pattern of the second probe pad group.

14. The stacked memory device of claim 8, wherein Each of the plurality of memory blocks is a dynamic random access memory block.

15. A memory block having a probe pad arrangement, comprising: a first surface and a second surface opposite to the first surface; A first probe pad group, comprising a plurality of first probe pads and arranged on the first surface; A second probe pad group, comprising a plurality of second probe pads and arranged on the second surface; as well as a plurality of connection structures, each of the plurality of connection structures being electrically connected to a corresponding first probe pad among the plurality of first probe pads and electrically connected to a corresponding second probe pad among the plurality of second probe pads, wherein a first arrangement pattern of the first probe pad group is the same as a second arrangement pattern of the second probe pad group, and A first test signal pattern of the first probe pad group viewed from the first surface is identical to a second test signal pattern of the second probe pad group viewed from the second surface.

16. The memory block element of claim 15, wherein Each of the plurality of connection structures comprises: a first redistribution layer electrically connected to the corresponding first probe pad; an inner connection line electrically connected to the first redistribution layer; a through silicon via (TSV), electrically connected to the inner connection; as well as The second redistribution layer is electrically connected to the TSV and the corresponding second probe pad.

17. The memory block element of claim 16, wherein The interconnects include a plurality of internal metal layers disposed in the memory block.

18. The memory block element of claim 16, wherein A test signal pattern of the TSV viewed from the first surface of the memory block cell is mirror-symmetric to a test signal pattern of the TSV viewed from the second surface of the memory block cell.

19. The memory block element of claim 15, wherein The plurality of first probe pads are arranged in two rows along a center line of the first arrangement pattern of the first probe pad group, and The plurality of second probe pads are arranged in two rows along a center line of the second arrangement pattern of the second probe pad group.

20. The memory block element of claim 15, wherein The memory block element is a dynamic random access memory block element.

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