Semiconductor package assembly

Abstract

A semiconductor package assembly includes a first semiconductor die having a first surface and a second surface opposite the first surface, and a second semiconductor die having a first interface and a second interface, the semiconductor package assembly includes a first semiconductor die having a first interface and a second interface, the second interface being farther from a corresponding first edge of the first semiconductor die than the first interface, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die being electrically coupled with the first semiconductor die through the second interface, and a first conductive bump and a second conductive bump. The first conductive bump and the second conductive bump on the two sides of the first semiconductor crystal grain are in bidirectional outward connection, and the second interface is arranged not on the edge of the first semiconductor crystal grain, so that the length of an electrical connection path between the second interface and the second semiconductor crystal grain can be shortened, and the signal transmission speed is improved.

Description

[Technical field]

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging component. [Background technology]

[0002] As the demand for small devices with more functions continues to grow, package-on-package (PoP) technology has become more and more popular. PoP technology stacks two or more packages vertically and minimizes the track length between different components (such as controllers and storage devices). This provides better electrical performance because shorter interconnect wiring produces faster signal propagation and reduces noise and crosstalk defects.

[0003] Although existing semiconductor packaging components are generally adequate, they are not satisfactory in various aspects. For example, it is difficult to meet the interface requirements for integrating different components into a single package. Therefore, there is a need to further improve semiconductor packaging components to provide greater flexibility in interface design. [Summary of the invention]

[0004] In view of this, the present invention provides a semiconductor package assembly to solve the above problems.

[0005] An embodiment of the present invention provides a semiconductor packaging component, comprising: a first semiconductor grain having a first surface and a second surface opposite to the first surface, wherein the first semiconductor grain comprises: a first interface arranged on a first edge of the first semiconductor grain; and a second interface located next to the first interface, wherein the second interface is farther away from the first edge of the first semiconductor grain than the first interface; and a second semiconductor grain stacked on the first semiconductor grain; wherein the semiconductor packaging component also comprises: a first conductive bump arranged on the first surface of the first semiconductor grain; and a second conductive bump arranged on the second surface of the first semiconductor grain; wherein the second semiconductor grain is electrically coupled to the first semiconductor grain through the second interface.

[0006] In one embodiment, the first semiconductor crystal grain further includes: a semiconductor substrate; and a first interconnect structure and a second interconnect structure, which are arranged on opposite surfaces of the semiconductor substrate, wherein the first conductive bump is separated from the second conductive bump by the semiconductor substrate, the first interconnect structure and the second interconnect structure. Therefore, the first semiconductor crystal grain has electrical connections that can be made to the outside on two opposite surfaces (e.g., the upper surface and the lower surface) to improve the flexibility of the connection and shorten the connection path to other components.

[0007] In one embodiment, the device further comprises: a first wiring structure in contact with the first conductive bump, wherein the second semiconductor crystal grain is electrically coupled to the second interface of the first semiconductor crystal grain through the first conductive bump and the first wiring structure, thereby connecting to the second semiconductor crystal grain through the second interface to shorten the electrical connection path.

[0008] In one embodiment, it further includes:

[0009] A third conductive bump is disposed on the first surface of the first semiconductor crystal grain and contacts the first wiring structure, wherein the third conductive bump is grounded. The third conductive bump is not used to transmit signals or power, but is grounded to improve heat dissipation.

[0010] In one embodiment, the third conductive bump is located in the center of the first semiconductor crystal grain, so that the layout of the interface at the edge of the first semiconductor crystal grain will not be affected.

[0011] In one embodiment, it also includes: a second wiring structure, arranged under the second conductive bump; and a first through-hole (TV) interconnect, arranged next to the first semiconductor grain and electrically coupled between the first wiring structure and the second wiring structure, wherein the second wiring structure is electrically coupled to the first interface of the first semiconductor grain through the first TV interconnect and the first wiring structure.

[0012] In one embodiment, the second wiring structure is electrically coupled to the first interface of the first semiconductor die through the second conductive bump.

[0013] In one embodiment, it also includes: a second through-via (TV) interconnection, which is arranged next to the first semiconductor grain and electrically coupled between the first wiring structure and the second wiring structure, wherein the second semiconductor grain is electrically coupled to the second wiring structure through the first wiring structure and the second TV interconnection.

[0014] In one embodiment, the second TV interconnect is the power TV interconnect, thereby providing a connection path for power / ground.

[0015] In one embodiment, the first conductive bump is a signal bump and the second conductive bump is a power bump, so that interfaces and connection components with different uses (power / ground and signal) can be arranged separately, thereby improving flexibility and shortening the corresponding connection path.

[0016] In one embodiment, the invention further comprises: a fan-out package, comprising the first semiconductor die, the first wiring structure and the second wiring structure; and a memory package, comprising the third semiconductor die and stacked on the fan-out package, wherein the memory package comprises third conductive bumps arranged in groups and disposed on opposite edges of the memory package, thereby forming a desired stacked package structure.

[0017] In one embodiment, the second interface is located in a central region of the first semiconductor die.

[0018] In one embodiment, the method further includes: a fourth semiconductor grain disposed between the first semiconductor grain and the second wiring structure, wherein the second wiring structure is electrically coupled to the first interface of the first semiconductor grain through the second conductive bump and the fourth semiconductor grain.

[0019] In one embodiment, the fourth semiconductor die further includes: a third through-via (TV) interconnect formed through the fourth semiconductor die, wherein the third TV interconnect overlaps and is electrically coupled to the second interface.

[0020] In one embodiment, the third TV interconnect is a power TV interconnect or a ground TV interconnect.

[0021] In one embodiment, the fourth semiconductor die further includes: a fourth through-via (TV) interconnect formed through the fourth semiconductor die, wherein the fourth TV interconnect overlaps and is electrically coupled to the first interface.

[0022] Another embodiment of the present invention provides a semiconductor package assembly, comprising:

[0023] A fan-out package, comprising: a first wiring structure and a second wiring structure stacked on each other; and a top semiconductor die disposed between the first wiring structure and the second wiring structure; wherein the top semiconductor die comprises: a first interface disposed on a first edge of the top semiconductor die; and a second interface disposed near the first interface, wherein the second interface is further away from the first edge of the top semiconductor die than the first interface; and

[0024] A memory package is provided on the fan-out package,

[0025] wherein the base is electrically coupled to the first interface via at least the second wiring structure, and

[0026] The memory package is electrically coupled to the second interface through the first wiring structure but not the second wiring structure.

[0027] In one embodiment, the base is electrically coupled to the second interface through the second wiring structure instead of the first wiring structure, so that connection structures with different uses are arranged separately, so as to improve the flexibility of layout and shorten the path length of corresponding connections, improve signal transmission speed and avoid crosstalk between signals.

[0028] In one embodiment, the further comprising: a conductive bump, which is arranged away from the second interface and in contact with the first wiring structure, wherein the conductive bump is grounded.

[0029] In one embodiment, the fan-out package further comprises: a bottom semiconductor die disposed between the top semiconductor die and the second wiring structure, wherein the bottom semiconductor die comprises: a through-via (TV) interconnection overlapping and electrically coupled to the second interface.

[0030] The semiconductor package assembly of the present invention comprises: a first semiconductor crystal grain having a first surface and a second surface opposite to the first surface, wherein the first semiconductor crystal grain comprises: a first interface arranged on a first edge of the first semiconductor crystal grain; and a second interface located beside the first interface, wherein the second interface is further away from the first edge of the first semiconductor crystal grain than the first interface; and a second semiconductor crystal grain stacked on the first semiconductor crystal grain; wherein the semiconductor package assembly further comprises: a first conductive bump arranged on the first surface of the first semiconductor crystal grain; and a second conductive bump arranged on the second surface of the first semiconductor crystal grain; wherein the second semiconductor crystal grain is electrically coupled to the first semiconductor crystal grain through the second interface. The present invention performs bidirectional outward connection through the first conductive bump and the second conductive bump respectively on both sides of the first semiconductor crystal grain, and thereby sets the second interface not on the edge of the first semiconductor crystal grain, so that the length of the electrical connection path between the second interface and the second semiconductor crystal grain can be shortened, the signal transmission speed can be improved, and the edge of the relatively scarce first semiconductor crystal grain is reserved for other interfaces, thereby improving the flexibility of layout design.

Brief Description of the Drawings

[0031] For a more complete understanding of the present invention, please read the following detailed description and examples and refer to the accompanying drawings, in which:

[0032] Figure 1A is a cross-sectional view of a semiconductor package assembly according to some embodiments of the present disclosure;

[0033] Figure 1B yes Figure 1A A partial enlarged view of

[0034] Figure 2 According to some embodiments of the present invention Figure 1AA perspective bottom view of a semiconductor package assembly showing an arrangement of interfaces of a semiconductor die and through via (TV) interconnects of a bottom package and an arrangement of conductive structures of a top package stacked on the bottom package;

[0035] Figure 3 is a cross-sectional view of a semiconductor package assembly according to some embodiments of the present disclosure;

[0036] Figure 4 is a cross-sectional view of a semiconductor package assembly according to some embodiments of the present disclosure;

[0037] Figure 5 According to some embodiments of the present invention Figure 4 A perspective bottom view of a semiconductor package assembly showing an interface of a semiconductor die and an arrangement of through-via (TV) interconnects of a bottom package and an arrangement of conductive structures of a top package stacked on the bottom package;

[0038] Figure 6 is a cross-sectional view of a semiconductor package assembly according to some embodiments of the present invention;

[0039] Figure 7 is a cross-sectional view of a semiconductor package assembly according to some embodiments of the present invention; and

[0040] Figure 8 is a cross-sectional view of a semiconductor package assembly according to some embodiments of the present invention. [Specific implementation method]

[0041] In order to make the above-mentioned purposes, features and advantages of some embodiments of the present invention more clearly understood, they are described in detail below with reference to the accompanying drawings.

[0042] Throughout the specification and the claims that follow, certain terms are used to refer to specific components. As will be appreciated by those skilled in the art, electronic device manufacturers may refer to a component by different names. It is not intended herein to distinguish between components that have different names but the same functions. It should be understood that the use of words such as "include", "have" and "comprise" is open ended and should therefore be understood as "including but not limited to ...". Therefore, when the terms "include", "have" and / or "comprise" used in the present invention are used to indicate the presence of specific technical features, values, method steps, operations, units and / or components, it does not exclude the possibility of adding more technical features, values, method steps, workflows, units, components or any combination thereof.

[0043] Advanced integrated circuit (IC) devices have increasingly diverse functions and shrinking sizes. While the process of shrinking size generally improves production efficiency and reduces associated costs, it also increases the complexity of processing and manufacturing IC devices. For example, Fin Field-Effect Transistor (FinFET) has been introduced to replace planar transistors. In these FinFETs, gate-all-around (GAA) structures such as nanosheet or nanowire metal-oxide-semiconductor field-effect transistors (MOSFET) have been developed to have excellent electrical characteristics, such as better power performance and area scaling compared to current FinFET technology. In addition, back-side power supply technology is used in the surround gate (GAA) structure to reduce secondary wiring, thereby reducing the back end of line (BEOL) capacitance and IR drop, thereby improving the performance of the IC. Although the existing integrated circuit (IC) devices are generally sufficient, they are not satisfactory in all aspects. For example, in a package-on-package (PoP) semiconductor package assembly, it is a challenge to arrange sufficient input / output (I / O) interfaces on the limited peripheral edge of the semiconductor die. Therefore, it is necessary to utilize semiconductor dies with backside power rails in the PoP semiconductor package assembly.

[0044] Figure 1A is a cross-sectional view of a semiconductor package assembly 500A according to some embodiments of the present invention. Figure 1B yes Figure 1A In some embodiments, the semiconductor package assembly 500A is a three-dimensional (3D) package on package (POP) semiconductor package assembly. The semiconductor package assembly 500A may include at least two vertically stacked wafer-level semiconductor packages mounted on the base 200. For example, Figure 1AAs shown, in some embodiments, the semiconductor package assembly 500A includes a bottom package 300A and a top package 400 vertically (along direction 12) stacked on the bottom package 300A. In some embodiments, the bottom package 300A includes a fan-out package, such as a system-on-chip (SOC) package. The top package 400 includes a memory package, such as a dynamic random access memory (DRAM) package. In some embodiments, the semiconductor package assembly 500A may not include a base 200; that is, the base 200 is located outside the semiconductor package assembly 500A.

[0045] like Figure 1A As shown, the base 200, such as a printed circuit board (PCB), can be formed of polypropylene (PP), prepreg, FR-4 and / or other epoxy laminate materials. It should also be noted that the base 200 can be a single-layer or multi-layer structure. A plurality of pads 202 and / or conductive traces (not shown) are provided on the base 200. In one embodiment, the conductive traces may include signal trace segments or ground trace segments for input / output (I / O) connections of the bottom package 300A and the top package 400. In addition, the bottom package 300A is directly mounted on the conductive traces. In some other embodiments, the pads 202 are provided on the base 200 and connected to different terminals of the conductive traces. The pads 202 are used for the bottom package 300A directly mounted thereon.

[0046] like Figure 1A As shown, the bottom package 300A is mounted on the base 200 by a bonding process. The bottom package 300A is mounted on the base 200 using a conductive structure 322. The bottom package 300A is a fan-out semiconductor package, including a semiconductor die 140, a first wiring structure 366, a second wiring structure 316, a through-hole (TV) interconnect 314 and a conductive structure 322. The conductive structure 322 is in contact with and electrically connected (or coupled) to the second wiring structure 316. In addition, the conductive structure 322 is electrically connected (or coupled) to the pad 202 of the base 200. In some embodiments, the conductive structure 322 includes a conductive ball structure (e.g., a copper ball), a conductive bump structure (e.g., a copper bump or a solder bump structure), or a conductive column structure (e.g., a copper column structure).

[0047] The semiconductor grain 140 is disposed between the second wiring structure 316 and the first wiring structure 366. In some embodiments, the semiconductor grain 140 has a first surface 140T, a second surface 140B opposite to the first surface 140T, and an edge (edge ​​surface) 140E connected (or coupled) between the first surface 140T and the second surface 140B. In some embodiments, the semiconductor grain 140 adopts back power technology. In addition, the semiconductor grain 140A can be manufactured by a surround gate (GAA) process. In some embodiments, the semiconductor grain 140 can be electrically connected (or coupled) to the first wiring structure 366 and the second wiring structure 316 by a conductive bump (e.g., a microbump, a controlled collapse chip connection (controlled collapse chip connection, C4) bump, or a combination thereof). The conductive bump can be arranged on the first surface 140T and the second surface 140B of the semiconductor grain 140.

[0048] In some embodiments, the semiconductor die 140 includes a semiconductor substrate 100, one or more electronic components 102, a first interconnect structure 110, a second interconnect structure 120, and conductive bumps 114, 124. Figure 1B shown.

[0049] The semiconductor substrate 100 has a front surface 100F and a back surface 100B. In some embodiments, the material of the semiconductor substrate 100 includes Si, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-VI materials, or combinations thereof.

[0050] The electronic component 102 is formed on the front surface 100F of the semiconductor substrate 100. In some embodiments, the electronic component 102 may be composed of transistors (eg, GAA transistors), diodes, resistors, capacitors, and other active / passive devices according to design requirements.

[0051] The front interconnect structure 110 is disposed on the front surface 100F of the semiconductor substrate 100. The back surface interconnect structure 120 is disposed on the back surface 100B of the semiconductor substrate 100, opposite to the front surface interconnect structure 110. The front surface interconnect structure 110 is separated from the back surface interconnect structure 120 by the semiconductor substrate 100. In some embodiments, the front surface interconnect structure 110 is formed to cover the electronic component 102 and is electrically connected to the electronic component 102. The back surface interconnect structure 220 is also electrically connected to the electronic component 102.

[0052] In some embodiments, the front-side interconnect structure 110 may include multiple dielectric layers and conductive wiring (including signal wiring 112) formed in the multiple dielectric layers. The conductive wiring includes conductive lines and vias (not shown), which may be formed of copper or copper alloys and may be formed using one or more damascene processes. The dielectric layer may include an inter-layer dielectric (ILD) layer and an inter-metal dielectric (IMD) layer.

[0053] In some embodiments, the front-side interconnect structure 110 may include a signal wiring 112S. The signal wiring 112S is configured to transmit data signals, control signals, and other user signals.

[0054] In some embodiments, the backside interconnect structure 120 may be similar to the frontside interconnect structure 110 and include multiple dielectric layers and conductive wiring (including power wiring and ground wiring) formed in the multiple dielectric layers. The number of dielectric layers in the frontside interconnect structure 110 and the backside interconnect structure 220 may be the same or different.

[0055] In some embodiments, the backside interconnect structure 120 may include a power wiring 122P and a ground wiring 122G. The power wiring 122P may include a positive power voltage VDD, a ground power voltage VSS, an overdrive voltage signal (e.g., a signal greater than VDD), a negative power voltage signal, and other power voltage signals. The ground wiring is used for grounding the semiconductor die 140.

[0056] In some embodiments, the conductive wiring (including the power wiring 122P and the ground wiring 122G) in the backside interconnect structure 120 is electrically connected (or coupled) to the electronic component 102 through one or more through-substrate vias (TSV) passing through the semiconductor substrate 100. For example, the power wiring 122P is electrically connected (or coupled) to the electronic component 102 through the through-substrate via TSV-P1. The through-substrate via TSV-P1 may have a first end that terminates at the front side 100F and is connected (or coupled) to a corresponding terminal of the electronic component 102. The through-substrate via TSV-P1 may have a second end that terminates at the back side 100F of the semiconductor substrate 100 and is connected (or coupled) to the power wiring 122P. For example, the ground wiring 122G is electrically connected (or coupled) to the electronic component 102 through the through-substrate via TSV-G1. The through-substrate via TSV-G1 may have a first end that terminates at the front side 100F and is connected (or coupled) to a corresponding terminal of the electronic component 102. The through substrate via TSV-G1 may have a second end terminated at the back surface 100F of the semiconductor substrate 100 and connected (or coupled) to the ground wiring 122G.

[0057] The conductive bump 114 is disposed on the first surface 140T of the semiconductor die 140. The conductive bump 114 electrically connects the conductive bump 124 to (or couples to) the signal wiring 112S of the front-side interconnect structure 110. In some embodiments, the conductive bump 114 may be used as a signal bump.

[0058] Conductive bumps 124 are disposed on the second surface 140B of the semiconductor die 140. Conductive bumps 124 are electrically connected (or coupled) to power wiring 122P and ground wiring 122G of the backside interconnect structure 120. In some embodiments, conductive bumps 124 may be used as power bumps, ground bumps, or a combination thereof.

[0059] In some embodiments, the semiconductor die 140 includes a system-on-chip (SOC) die, a logic device, a memory device, a radio frequency (RF) device, etc. or any combination thereof. For example, the semiconductor die 140 may include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a global positioning system (GPS) device, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input-output (IO) die, a dynamic random access memory (DRAM) IP core, a static random access memory (SRAM), a high bandwidth memory (HBM), etc. or any combination thereof.

[0060] In some embodiments, the first wiring structure 366 includes a redistribution layer (RDL) structure or an interposer. For example, the first wiring structure 366 may be an interposer 366. The first wiring structure 366 is disposed on the first surface 140T of the semiconductor die 140. In addition, the first wiring structure 366 is disposed above and in contact with the conductive bump 114. In some embodiments, the first wiring structure 366 includes one or more conductive traces 369, one or more through-holes 368 disposed in one or more dielectric layers 367, and a contact pad 370. In some embodiments, the through-holes 368, the conductive traces 369, and the contact pads 370 include conductive materials, such as metals including copper, gold, silver, or other applicable metals. The dielectric layer 367 may include an extra-low K (ELK) dielectric and / or an ultra-low K (ULK) dielectric. In addition, the dielectric layer 367 may include an epoxy resin. It is noteworthy that Figure 1A The number of vias 368 , the number of conductive traces 369 , the number of contact pads 370 , and the number of dielectric layers 367 shown are merely examples and are not limiting of the present invention.

[0061] In some embodiments, the second wiring structure 316 includes an interposer, a redistribution layer (RDL) structure, or a substrate. For example, the second wiring structure 316 may be an interposer 316. The second wiring structure 316 is disposed on the second surface 140B of the semiconductor die 140, opposite to the first wiring structure 366. The second wiring structure 316 is disposed below and in contact with the conductive bump 124. In addition, the second wiring structure 316 is disposed between the semiconductor die 140 and the base 200. Figure 1B As shown, the second wiring structure 316 may include one or more conductive traces 319, one or more through holes 318 disposed in one or more dielectric layers 317, and contact pads 320. The conductive traces 319 are electrically connected (or coupled) to the corresponding contact pads 320. The contact pads 320 are exposed to the opening of the solder resist layer (not shown) and are close to the base 200. The conductive element 322 is disposed on the corresponding base 200 and contacts it. Contact pads 320. Therefore, the conductive element 322 is electrically connected (or coupled) between the contact pads 320 of the semiconductor package 300A and the pads 202 of the base 200. The semiconductor die 140 is electrically connected (or coupled) to the base 200 using the through holes 318, the conductive traces 319, the contact pads 320 of the second wiring structure 316, and the corresponding conductive elements 322.

[0062] In some embodiments, the materials of vias 318, conductive traces 319, and contact pads 320 may be similar to the materials of vias 368, conductive traces 369, and contact pads 370. In addition, the material of dielectric layer 317 may be similar to the material of dielectric layer 367. It should be noted that the number of vias 318, the number of conductive traces, and the number of contact pads 320 may be similar to the material of dielectric layer 367. Figure 1A The number of through holes 319 , contact pads 320 , and dielectric layers 317 shown in FIG. 3 are merely examples and are not intended to limit the present invention.

[0063] A through-hole (TV) interconnect 314 is disposed on the wiring structure 316, and is located next to the semiconductor die 140. The second wiring structure 316 and the first wiring structure 366 are in contact with opposite ends of the TV interconnect 314, respectively. The TV interconnect 314 is electrically connected (or coupled) between the through-hole 368, the conductive trace 369, and the contact pad 370 of the first wiring structure 366 and the through-hole 318, the conductive trace 319, and the contact pad 320 of the second wiring structure 316. In addition, the semiconductor die 140 and the TV interconnect 314 are sandwiched between the second wiring structure 316 and the first wiring structure 366 in the direction 12.

[0064] In some embodiments, TV interconnect 314 can be electrically connected (or coupled) to semiconductor die 140 using vias 368 and conductive traces 369 within first wiring structure 366. In addition, TV interconnect 314 can be electrically connected (or coupled) to semiconductor die 140 using vias 318 and conductive traces 319 within second wiring structure 316.

[0065] like Figure 1A As shown, the bottom package 300A also includes a molding compound 312 disposed between and in contact with the first wiring structure 366 and the second wiring structure 316. The molding compound 312 can surround the semiconductor die 140 and the TV interconnect 314. The molding compound 312 can surround the conductive bumps 114 and 124. In addition, the TV interconnect 314 passes through the molding compound 312. The opposite terminals of the conductive bumps 114 and 124 can be exposed from the molding compound 312. In some embodiments, the molding compound 312 can be formed of a non-conductive material, such as an epoxy resin, a resin, a moldable polymer, etc. The molding compound 312 can be applied when it is substantially liquid and can then be cured by a chemical reaction, such as in an epoxy resin or a resin. In some other embodiments, the molding compound 312 can be an ultraviolet (UV) or heat-curable polymer, applied in the form of a gel or a plastic solid, which can be arranged around the semiconductor die 140 and can then be cured using a UV or heat curing process. The molding compound 312 can be cured with a mold.

[0066] In some embodiments, the edge 312E of the molding material 312 is flush with the corresponding edge 366E of the first wiring structure 366 and the corresponding edge 316E of the second wiring structure 316. Therefore, the edge 312E of the molding material 312, the edge 366E of the first wiring structure 366, and the edge 316E of the second wiring structure 316 can be used together as the package edge of the bottom package 300A.

[0067] like Figure 1A As shown, the bottom package 300A also includes an electronic component 330 mounted on a second wiring structure 316 opposite to the semiconductor die 140. In some embodiments, the electronic component 330 has a pad 332 and is electrically connected (or coupled) to the conductive trace 319 of the second wiring structure 316. In some embodiments, the electronic component 330 is arranged between the conductive structures 322. The electronic component 330 may not be covered by the molding compound. In some embodiments, the electronic component 330 includes an integrated passive device (IPD) including a capacitor, an inductor, a resistor, or a combination thereof. In some embodiments, the electronic component 330 includes a DRAM die.

[0068] like Figure 1A As shown, the top package 400 is stacked on the bottom package 300A by a bonding process. In some embodiments, the top package 400 includes a memory package, such as a dynamic random access memory (DRAM) package or other applicable memory packages. In some embodiments, the top package 400 includes a substrate 418, at least one semiconductor die (e.g., two semiconductor dies 402 and 404 stacked on the substrate 418), and a conductive structure 422. In some embodiments, each of the semiconductor dies 402 and 404 includes a dynamic random access memory (DRAM) die (e.g., a double data rate 4 (double data rate 4, DDR4) DRAM die, a low power DDR4 (LPDDR4) DRAM die, a double data rate (double data rate, DDR) synchronous dynamic random access memory (synchronous dynamic random access memory, SDRAM) die, etc.) or other applicable memory dies. In some other embodiments, the semiconductor dies 402 and 404 may include the same or different devices. In some embodiments, the top package 400 further includes one or more passive components (not shown), such as resistors, capacitors, inductors, etc., or combinations thereof.

[0069] In this embodiment, if Figure 1AAs shown, there are two semiconductor dies 402 and 404 mounted on a substrate 418 by a paste (not shown). The semiconductor dies 402 and 404 have corresponding pads 408 and 410, respectively. The pads 408 and 410 of the semiconductor dies 402 and 404 can be electrically connected (or coupled) to the substrate 418 using bonding wires 414 and 416, respectively. However, the number of stacked memory dies is not limited to the disclosed embodiments. Alternatively, as Figure 1A The semiconductor dies 402 and 404 shown may be arranged side by side and mounted on a substrate 418 by a paste (not shown).

[0070] like Figure 1A As shown, substrate 418 may include circuit 428 and contact pads 420 and 430, which are disposed in one or more ultra-low K (ELK) and / or ultra-low K (ULK) dielectric layers (not shown). Contact pad 420 is disposed on the top of circuit 428, near the top surface (die attachment surface) of substrate 418. In addition, bonding wires 414 and 416 are electrically connected (or coupled) to corresponding contact pads 420. Contact pad 430 is disposed at the bottom of circuit 428, near the bottom surface (bump mounting surface) of substrate 418. Contact pad 430 is electrically connected (or coupled) to corresponding contact pad 420. In some embodiments, bonding wires 414 and 416, contact pads 420 and 430, and circuit 428 include conductive materials, such as metals including copper, gold, silver, or other suitable metals.

[0071] like Figure 1A As shown, the conductive structure 422 is disposed on the bottom surface of the substrate 418 opposite to the semiconductor dies 402 and 404. For example, the conductive structures 422 can be arranged in groups along a specific direction (e.g., direction 10). The conductive structures 422 are electrically connected (or coupled) to (or in contact with) the corresponding contact pads 430 and the first wiring structure 366 of the substrate 418. In some embodiments, the conductive structure 422 includes a conductive ball structure (e.g., a copper ball), a conductive bump structure (e.g., a copper bump or a solder bump structure), or a conductive pillar structure (e.g., a copper pillar structure).

[0072] In some embodiments, Figure 1A As shown, the top package 400 further includes a molding compound 412 covering the substrate 418, and the molding compound 412 encapsulates the semiconductor dies 402 and 404 and the bonding wires 414 and 416. The top surface of the molding compound 412 can be used as the top surface 400T of the top package 400. In some embodiments, the molding compounds 312 and 412 can include the same or similar materials and manufacturing processes.

[0073] Figure 2 According to some embodiments of the present invention Figure 1A5 is a perspective bottom view (plan view) of a semiconductor package assembly 500A showing the interface of the semiconductor die 140 and the arrangement of the through-via (TV) interconnects 314 of the bottom package 300A and the arrangement of the conductive structures 422 of the top package 400 stacked on the bottom package 300A.

[0074] In some embodiments, the semiconductor die 140 of the bottom package 300A may be used to control the top package 400. The semiconductor die 140 may include various interfaces for external electrical connection between the bottom package 300A and the top package 400. In some embodiments, the interface of the semiconductor die 140 used herein may include circuits and input / output connections (e.g., pads, first interconnect structures 110 and second interconnect structures 120) disposed on the first surface 140T and the second surface 140B of the semiconductor die 140. In some embodiments, the interface of the semiconductor die 140 is used for signal transmission (data transmission) between the bottom package 300A and the top package 400. In addition, the interface of the semiconductor die 140 is used for power transmission and ground path between the bottom package 300A and the base 200.

[0075] It should be noted that Figure 2 Only the semiconductor die 140, the molding material 312, the TV interconnect 314 of the bottom package 300A, and the conductive structure 422 of the top package 400 are shown for illustration only, and the remaining features may be found in Figure 1A and 1B . It will be appreciated that while certain features are shown in certain embodiments but not in other embodiments, those features may be present (or may not be present) in other embodiments, wherever possible. For example, while each of the illustrated example embodiments shows a particular arrangement of the interface of the semiconductor die 140 and the TV interconnect 314 of the bottom package 300A and the conductive structure 422 of the top package 400, any other combination of arrangements of the interface of the semiconductor die 140 and the TV interconnect 314 of the bottom package 300A and the conductive structure 422 of the top package 400 may be used, wherever applicable. Figure 2 The size of the components in may be different from Figure 1A The sizes of the components in the figure are not completely consistent, which is to show the relationship between the components of interest, so that readers can understand. The sizes and relative sizes of the components in the figure do not represent the sizes in the actual product. In addition, the coupling in the embodiments of the present invention can mean that the two are connected to each other via multiple components or features, or directly connected, etc.

[0076] like Figure 2As shown, semiconductor grain 140 may have a rectangular plan view shape. Semiconductor grain 140 may have a peripheral edge 140E, including opposite edges 140E1 and 140E3 extending substantially along direction 11 and opposite edges 140E2 and 140E4 extending substantially along direction 10. Directions 10 and 11 may also be used as lateral directions. Figure 1A and 2 In some of the embodiments shown, the semiconductor grain 140 has a first region R1 and a second region R2. The first region R1 is located near the peripheral edge 140E of the semiconductor grain 140. The first region R1 is continuously arranged along the peripheral edge 140E. Therefore, the first region R1 is also referred to as the peripheral edge region R1. The second region R2 is arranged corresponding to the central portion of the semiconductor grain 140, also referred to as the central region R2. The second region R3 is arranged corresponding to the central portion of the semiconductor grain 140, also referred to as the central region R4. The second region R4 is arranged corresponding to the central portion of the semiconductor grain 140, also referred to as the central region R5. The region R2 is farther away from the corresponding peripheral edge 400E than the first region R1. In addition, the first region R1 may surround the second region R2.

[0077] In some embodiments, the first region R1 may be configured to be used for arranging one or more I / O interfaces 140IO (e.g., interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4) and data interfaces 140DDR (e.g., interfaces 140DDR-1, 140DDR-2, 140DDR-3, 140DDR-4) and an antenna in package (AiP) module (not shown). In some embodiments, the second region R2 is configured to be used for arranging one or more digital intellectual property (IP) blocks (e.g., digital IP block 140PDN (power delivery network)) therein.

[0078] Interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4 may be arranged on the edge of semiconductor die 140. For example, interface 140IO-1 is arranged on edge 140E1 and close to edge 140E2. Interface 140IO-2 is arranged on edge 140E3 and close to edge 140E2. Interface 140IO-3 is arranged on edge 140E3 and close to edge 140E4. Interface 140IO-4 is arranged on edge 140E1 and close to edge 140E4. In some embodiments, interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4 are used to transmit data and digital input / output (I / O) signals to control other external ICs (not shown) connected to base 200. In some embodiments, the edge of semiconductor die 140 may also have interfaces and corresponding bumps for power / ground.

[0079] Interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4 may be arranged next to interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4. In some other embodiments, data interface 140DDR may not be arranged on the edge of semiconductor die 140. In some other embodiments, data interface 140DDR may contact I / O interface 140IO, for example, interface 140DDR-1 may contact interface 140IO-1, and interface 140DDR-2 may contact interface 140IO-2. In some other embodiments, data interface 140DDR may not contact I / O interface 140IO. For example, data interface 140DDR may be separated from I / O interface 140IO, for example, interface 140DDR-1 may be separated from interface 140IO-1, and interface 140DDR-2 may be separated from interface 140IO-2. When the bottom package 300A is a SOC package, the top package 400 includes a double data rate 4 (DDR4) DRAM package, a low power DDR4 (LPDDR4) DRAM package, a double data rate 5 (DDR5) DRAM package, a low-power DDR5 (LPDDR5) DRAM package, or other applicable DRAM packages. The interfaces 140DDR-1, 140DDR-2, 140DDR-3, 140DDR-4 may include a double data rate 4 (DDR4) interface, a low power DDR4 (LPDDR4) DRAM interface, a double data rate 5 (DDR5) DRAM interface, a low power DDR5 (LPDDR5) DRAM interface, or other applicable memory interfaces. The interfaces 140DDR-1, 140DDR-2, 140DDR-3, 140DDR-4 may be used to control the top package 400 (e.g., to transmit data to / from a memory controller in the semiconductor die 140).

[0080] The digital IP block 140PDN may be disposed next to the interfaces 140DDR-1, 140DDR-2, 140DDR-3, 140DDR-4. The digital IP block 140PDN is farther from the corresponding peripheral edge 400E than the interfaces 140DDR-1, 140DDR-2, 140DDR-3, 140DDR-4 and the interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4. The digital IP block 140PDN may provide a power distribution network to ensure stable power delivery to all electronic components of the semiconductor die 140.

[0081] In some embodiments, the conductive structures 422 of the top package 400 (e.g., DDR4 DRAM package) are arranged according to a given arrangement. For example, the conductive structures 422 of the top package 400 are arranged on opposite edges 400E1 and 400E3 of the top package 400 along direction 11, and are divided into two groups 422G1 and 422G2 (including a single column or multiple columns of conductive structures 422), as shown in FIG. Figure 2 As shown. Each of the groups 422G1 and 422G2 of the conductive structure 422 can provide two data channels for the conductive structure 422. That is, the group 422G1 provides two DDR channels (DDR interface from the semiconductor die 140 to the top package 400), and the group 422G2 provides two DDR channels. In some other embodiments, the upper package 400 may also include additional conductive structures 422 (including single-row or multi-row conductive structures 422), which are arranged on the edges 400E2 and 400E4 of the upper package 400 to transmit power and ground. In addition, the additional conductive structures 422 can be arranged according to the data rate standard of DDR. In some other embodiments, the distribution area of ​​the conductive structure 422 (including the additional conductive structure 422) may be a hollow square.

[0082] Since the semiconductor die 140 of the bottom package 300A adopts the backside power supply technology, the semiconductor die 140 may have a first interconnect structure 422. The data channels of the semiconductor die 402 and 404 of the top package 400 may be electrically connected (or coupled) to the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4) of the semiconductor die 140 through the wiring path RP1 composed of the conductive structure 422, the first wiring structure 366, the conductive bump 114, and the first interconnect structure 110 (including the signal wiring 112S). The semiconductor die 402 and 404 may be electrically connected (or coupled) to the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4) of the semiconductor die 140 without using the TV interconnect 314 and the second routing structure 316. More TV interconnects 314, which were originally used as electrical connections between the data interface 140DDR and the top package 400, can be released for electrical connections between the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4) and the base 200, or for electrical connections between the top package 400 and the base 200. In addition, the data interface 140DDR can be arranged 140IO farther from the corresponding edge 140E of the semiconductor die 140 than the I / O interface. The wiring path RP1 for transmitting signals between the data interface 140DDR of the bottom package 300A and the data channel of the top package 400 can be shortened. Since the TV interconnects 314 no longer provide electrical connections between the data interface 140DDR and the top package 400, the conductive structure 422 can provide more DDR channels between the data interface 140DDR of the semiconductor die 140 and the top package 400 while the bottom package 300A remains the same size. In addition, the area originally occupied by the data interface 140DDR on the edge 140E1 to 140E4 of the semiconductor die 140 can be released to free up space for more I / O interfaces. In addition, the layout design of the digital IP block 140PDN will not be affected by the arrangement of the I / O interface 140IO. The performance of the semiconductor package assembly 500A can be improved while maintaining power integrity.

[0083] In addition, the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3 and 140DDR-4) of the bottom package 300A can be electrically connected to the base 200 through the wiring path RP2 composed of the second interconnect structure 120, the conductive bump 124, the second wiring structure 316 and the conductive structure 322 to serve as a power transmission and grounding path. The data interface 140DDR of the semiconductor die 140 can be electrically connected (or coupled) to the base 200 without using the TV interconnect 314. In the current design, the semiconductor die of the bottom package is flipped, the active surface of the semiconductor die faces downward, and the DDR interface of the semiconductor die is set at the edge of the semiconductor die. Therefore, the DDR channel between the DDR interface of the semiconductor die and the top package can only be realized through the second wiring structure 316, the TV interconnect 314 (and the first wiring structure 366, etc.). These DDR channels will occupy a considerable portion of the space of the second wiring structure 316 and the TV interconnection 314. Therefore, due to the limitation of DDR wiring, some conductive structures 322 cannot be used (for example, they cannot be used to transmit power or signals due to wiring requirements), and additional conductive structures 322 need to be added, thereby increasing the size of the bottom package 300. In one embodiment of the present invention, the semiconductor die 140 of the bottom package 300 is not flipped (the active surface of the semiconductor die 140 faces upward), the connection structure (such as the first interconnection structure 110 and the conductive bump 114) is arranged on the first surface (front or active surface) 140T of the semiconductor die 140, and the DDR interface is not arranged at the edge of the semiconductor die. In this way, the DDR channel does not need to occupy the second wiring structure 316 and the TV interconnection 314, but directly communicates with the top package 400 through the first interconnection structure 110 and the conductive bump 114. Therefore, the solution of the embodiment of the present invention can release the second wiring structure 316 and the TV interconnection 314 for other purposes, and can also reserve the valuable edge position of the semiconductor chip for other interfaces. This arrangement not only shortens the circuit path with the DDR, but also releases valuable die edge resources, thereby improving design flexibility. In addition, since the number of unusable conductive structures 322 is reduced, the size of the semiconductor die is also reduced. The volume of the bottom package 300 is also reduced.

[0084] In addition, the semiconductor dies 402 and 404 of the top package 400 can be electrically connected (or coupled) to the base 200 for power transmission and grounding through the wiring path RP3 composed of the conductive structure 422, the first wiring structure 366, the TV interconnect 314, the second wiring structure 316 and the conductive structure 322. Therefore, the TV interconnect 314 electrically connected between the top package 400 and the base 200 can be used as a power TV interconnect, a ground TV interconnect, or a combination thereof.

[0085] Since the semiconductor die 140 of the bottom package 300A adopts the backside power supply technology, the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3 and 140IO-4) of the bottom package 300A can have a variety of wiring paths for signal transmission, power transmission and grounding. For example, the input / output interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3 and 140IO-4) of the bottom package 300A can be electrically connected (or coupled) to an external IC (not shown) connected to the base 200 through the wiring path RP4 formed by the first interconnect structure 110, the conductive bump 114, the first wiring structure 366, the TV interconnect 314, the second wiring structure 316 and the conductive structure 322. Therefore, the TV interconnect 314 electrically connected (or coupled) between the input / output interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4) and the base 200 can be used as a signal TV interconnect, a power TV interconnect, a ground TV interconnect, or a combination thereof. Alternatively, the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4) of the bottom package 300A can be electrically connected (or coupled) to an external IC (not shown) connected to the base 200 through a wiring path RP5 composed of the second interconnect structure 120, the conductive bump 124, the second wiring structure 316, and the conductive structure 322.

[0086] Furthermore, the digital IP block 140PDN may be electrically connected (or coupled) to the base 200 through a wiring path RP6 consisting of the second interconnect structure 120 , the conductive bump 124 , the second wiring structure 316 , and the conductive structure 322 for power transmission.

[0087] In some embodiments, the conductive bumps 114 may be disposed only on the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4) and the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4), but not on the digital IP block 140PDN. In some embodiments, the conductive bumps 124 may be disposed on the data interface 140DDR, the I / O interface 140IO, and the digital IP block 140PDN.

[0088] Since the TV interconnect 314 can be used as an electrical connection for the semiconductor dies 402 and 404 of the top package 400 and the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3 and 140IO-4) of the bottom package 300A, the TV interconnect 314 can be arranged corresponding to the conductive structure 422 and the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3 and 140IO-4) of the bottom package 300A. For example, the TV interconnects 314 may be arranged in a single row or multiple rows on the edge 312E (including the edges 312E1, 312E2, 312E3, and 312E4) of the molding material 312, corresponding to the conductive structure 422 and the I / O interface 140IO (including the interface 140IO-1, 140IO-2, 140IO-3, and 140IO-4) of the bottom package 300A. The distribution area of ​​the TV interconnects 314 may have a hollow square shape, such as Figure 2 As shown. In some embodiments, the I / O interface 140IO may be electrically connected (or coupled) to the conductive structure 322 through the conductive bump 114, the first wiring structure 366, and the TV interconnect 314. In some embodiments, the I / O interface 140IO may not transmit signals to the conductive structure 422. In some embodiments, when the interface on the first surface 140T of the semiconductor die 140 is a DDR interface, the conductive bump 124 corresponding to the DDR interface on the second surface 140B of the semiconductor die 140 may be a power bump for supplying power to the DDR circuit. In some embodiments, when the interface on the first surface 140T of the semiconductor die 140 is an I / O interface, the conductive bump 124 corresponding to the I / O interface on the second surface 140B of the semiconductor die 140 may be a power bump for supplying power to the I / O circuit. In some embodiments, some circuits of the semiconductor die 140 may also be connected (or coupled) to the base 200 through the conductive bumps 114 , the first wiring structure 366 , the TV interconnect 314 and the second wiring structure 316 on the first surface 140T of the semiconductor die 140 to transmit signals.

[0089] Figure 3 FIG. 1 is a cross-sectional view of a semiconductor package 500B assembly according to some embodiments of the present disclosure. Figure 1A , 1B The components described in 2 are the same or similar, and are not repeated for the sake of brevity. Figure 3 As shown, the difference between the semiconductor package assembly 500A and the semiconductor package assembly 500B at least includes: the semiconductor die 140 of the bottom package 300B of the semiconductor package assembly 500B may include a conductive bump 114TB as a heat dissipation bump to dissipate the heat generated by the semiconductor die 140 .

[0090] like Figure 3 As shown, the conductive bump 114TB is disposed on the first surface 140T of the semiconductor die 140 (eg, Figure 1B Since the digital IP block 140PDN is electrically connected (or coupled) to the base 200, the front surface 100F (as shown) of the semiconductor substrate 100 is not used. Figure 1B ) on the conductive bump, so the conductive bump 114TB can be directly disposed on the digital IP block 140PDN in the central region R2 of the semiconductor die 140. In addition, the conductive bump 114TB can be directly disposed on the digital IP block 140PDN in the central region R2 of the semiconductor die 140. The bump 114TB can be disposed in the direction 10 (or as shown in FIG. Figure 2 In the direction 11 shown in the figure, the conductive bump 114TB is offset (separated) from the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3 and 140DDR-4) and the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3 and 140IO-4). The conductive bump 114TB contacts the first wiring structure 366 and the first interconnect structure 110. In some embodiments, the conductive bump 114TB is grounded. In some embodiments, the conductive bump 114TB and the conductive bump 114 can be the same size or different sizes. For example, the size of the conductive bump 114TB can be the same or similar to the size of the conductive bump 114. Alternatively, the size of the conductive bump 114TB can be larger than the size of the conductive bump 114 to further improve the heat dissipation efficiency.

[0091] Since the thermal resistance of the conductive bump 114TB is lower than that of the molding compound 312 , the arrangement of the conductive bump 114TB can help dissipate the heat generated by the semiconductor die 140 , thereby improving the heat dissipation efficiency from the semiconductor die 140 to the external environment of the semiconductor package 500B.

[0092] Figure 4 is a cross-sectional view of a semiconductor package 500C assembly according to some embodiments of the present disclosure. Figure 5 According to some embodiments of the present invention Figure 4 5 is a perspective bottom view of a semiconductor package assembly 500C, showing the interface of the semiconductor die 140 and the arrangement of the through-via (TV) interconnect 314 of the bottom package 300C and the arrangement of the conductive structure 422 of the top package 400 stacked on the bottom package 300C. Figure 1A , 1B The same or similar elements as those described in 2 are not repeated for the sake of brevity. Figure 1A and Figure 2As shown, the difference between the semiconductor package assembly 500A and the semiconductor package assembly 500C is at least that the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3 and 140DDR-4) of the bottom package 300C of the semiconductor package assembly 500C is arranged in the central region R2 of the semiconductor die 140. This embodiment can further shorten the path length of the DDR channel from the top package 400 (or the semiconductor die 402 and 404) to the semiconductor die 140 (e.g., the internal circuit of the semiconductor die 140), thereby further reducing the delay.

[0093] In this embodiment, the interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4 are arranged adjacent to each other. The interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4 are located between the groups 422G1 and 422G2 of the conductive bumps 422 in a plan view. Figure 5 As shown. In some embodiments, multiple data interfaces 140DDR can be adjacent to each other to form an array that only includes DDR interfaces and does not include other types of interfaces. This arrangement allows the position of the DDR interface array to be aligned with other circuit blocks (such as digital circuit blocks) without being affected by the DDR channel, thereby avoiding the waste of die area. Figure 5 In the embodiment, conductive bumps 114TB may also be provided as heat dissipation bumps at locations where interfaces 140DDR-1, 140DDR-2, 140DDR-3, 140DDR-4, etc. are not provided (or at least some idle locations) to improve heat dissipation.

[0094] In this embodiment, for example, when viewed from a top view, the digital IP block 140PDN may surround the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4).

[0095] In some embodiments, the conductive bumps 114 electrically connected (or coupled) to the data interfaces 140DDR (including interfaces 140DDR- 1 , 140DDR- 2 , 140DDR- 3 , and 140DDR- 4 ) may be arranged in the central region R 2 of the semiconductor die 140 .

[0096] According to the arrangement of the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4), the wiring path RP1' for transmitting signals between the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4) of the bottom package 300C (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4) and the data channel of the top package 400 may be shorter than the wiring path RP1 shown in Fig. 1. The semiconductor package assembly 500C may have improved computing performance.

[0097] Figure 6 FIG. 5 is a cross-sectional view of a semiconductor package assembly 500D according to some embodiments of the present invention. Figure 1A , 1B , 2 to 5 described the same or similar elements will not be repeated. Figure 1A As shown, the difference between the semiconductor package assembly 500A and the semiconductor package assembly 500D at least includes that the bottom package 300D of the semiconductor package assembly 500D further includes a semiconductor die 180 .

[0098] In some embodiments, the semiconductor package assembly 500D is a three-dimensional (3D) die group package assembly. In some embodiments, the bottom package 300D uses a die group architecture to divide a large single semiconductor die into multiple smaller functional semiconductor dies (referred to as die groups), which are manufactured at different technology nodes. Each die group can have improved device performance and manufacturing yield. In addition, the bottom package 300D can have reduced manufacturing costs. Figure 6 As shown, the bottom package 300D includes at least two semiconductor dies, such as semiconductor dies 140 and 180 (also referred to as chiplets 140 and 180) stacked on each other along direction 12 (e.g., vertical direction). The semiconductor die 180 is located between the semiconductor die 140 and the second wiring structure 316. The semiconductor die 180 may be surrounded by the TV interconnect 314. The semiconductor die 180 may overlap with the semiconductor die 140 and the upper package 400 along direction 12. Since the semiconductor die 140 and the semiconductor die 180 are respectively close to the first wiring structure 366 and the second wiring structure 316 of the bottom package 300D, the semiconductor die 140 and the semiconductor die 180 may also be respectively referred to as the upper semiconductor die 140 and the lower semiconductor die 180.

[0099] In some embodiments, semiconductor die 180 includes a system-on-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, etc., or any combination thereof. For example, semiconductor die 140 and semiconductor die 180 may each independently include a microcontroller unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a global positioning system (GPS) device, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input output (IO) die, a dynamic random access memory (DRAM) IP core, a static random access memory (SRAM), a high bandwidth memory (HBM), etc., or any combination thereof. In some embodiments, semiconductor die 140 and semiconductor die 180 have different functions.

[0100] The semiconductor die 140 and 180 can be manufactured at different technology nodes. In some embodiments, the semiconductor die 140 has a first critical dimension (CD), and the semiconductor die 180 has a second critical dimension different from the first critical dimension, so as to provide different functions at a reduced cost. For example, the first critical dimension is narrower than the second critical dimension. Therefore, the semiconductor die 140 and 180 can be provided with various interfaces respectively to meet the requirements of internal and external signal transmission of the bottom package 300D.

[0101] In some embodiments, the semiconductor die 180 is manufactured using flip chip technology. The semiconductor die 180 can be flipped to be disposed on the second wiring structure 316 opposite to the conductive structure 322 , and the second wiring structure 316 is disposed between the semiconductor die 180 and the base 200 along the direction 12 .

[0102] The semiconductor die 180 has an active surface 180a and a back surface 180b opposite to the active surface 180a. The pad 152 on the active surface 132as of the semiconductor die 180 is electrically connected (or coupled) to the second wiring structure 316 through a conductive structure 154. In some embodiments, the conductive structure 154 includes a conductive material, such as a metal. The conductive structure 154 may include a micro-bump, a controlled collapse die connection (C4) bump, a ball grid array (BGA) ball, etc., or a combination thereof.

[0103] In some embodiments, the semiconductor die 180 further includes a through-hole (TV) interconnect 180TV1 formed through the semiconductor die 180. Therefore, the semiconductor die 180 may also be referred to as a TV die 180. The TV interconnect 180TV1 may be exposed from the back side 180bs of the semiconductor die 180. In addition, the TV interconnect 180TV1 has substantially vertical sidewalls and extends from the active surface 180as and the back side 180bs of the semiconductor die 180, but the present invention is not limited thereto. The TV interconnect 180TV1 in the semiconductor die 180 may have other configurations and quantities. In some embodiments, the TV interconnect 180TV1 may be formed of a conductive material, such as a metal. For example, the TV interconnect 180TV1 may be formed of copper.

[0104] In some embodiments, the TV interconnect 180TV1 of the semiconductor die 180 may overlap and be electrically connected (or coupled) to the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4) of the semiconductor die 140. The second wiring structure 316 is electrically connected (or coupled) to the data interface 140DDR of the semiconductor die 140 through the conductive bump 124 and the semiconductor die 180. In some embodiments, the data interface 140DDR of the bottom package 300D may be electrically connected (or coupled) to the base 200 through the wiring path RP7 composed of the second interconnect structure 120, the conductive bump 124, the second wiring structure 316, the TV interconnect 180TV1, the pad 152, the conductive structure 154, the second wiring structure 316, and the conductive structure 322, as a power transmission and grounding path. Therefore, the TV interconnect 180TV1 electrically connected (or coupled) to the data interface 140DDR of the semiconductor die 140 can be used as a power TV interconnect, a ground TV interconnect, or a combination thereof. The data interface 140DDR of the semiconductor die 140 can be electrically connected (or coupled) to the base 200 without using the TV interconnect 314. The number of TV interconnects 314 can be further reduced.

[0105] Since the semiconductor die 140 of the bottom package 300D adopts the back side power supply technology, the interfaces 140DDR-1, 140DDR-2, 140DDR-3 and 140DDR-4 of the bottom package 300D can be electrically connected (or coupled) to the data channels of the top package 400 through the wiring path RP1 (similar to the wiring path RP1 shown in Figure 1) without using the TV interconnection formed through the semiconductor die 180 for signal transmission (data transmission). The number of TV interconnections formed through the semiconductor die 180 of the semiconductor package assembly 500D can be reduced compared with the conventional three-dimensional (3D) small die package assembly.

[0106] Since the semiconductor die 140 of the bottom package 300D adopts the backside power supply technology, the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3 and 140IO-4) of the bottom package 300D can have a variety of wiring paths for signal transmission, power transmission and grounding. In some embodiments, the semiconductor die 180 also includes a through-hole (TV) interconnection 180TV2 formed through the semiconductor die 180. The TV interconnection 180TV2 of the semiconductor die 180 can overlap and electrically connect (or couple) with the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3 and 140IO-4) of the semiconductor die 140. The second wiring structure 316 is electrically connected (or coupled) to the I / O interface 140IO of the semiconductor die 140 through the conductive bump 124 and the semiconductor die 180. In some embodiments, the I / O interface 140IO of the bottom package 300D can be electrically connected (or coupled) to the base 200 180TV1, the pad 152, the conductive structure 154, the second wiring structure 316 and the conductive structure 322 for power transmission and grounding paths through the wiring path RP8 composed of the second interconnect structure 120, the conductive bump 124, and the TV interconnect. Therefore, the TV interconnect 180TV2 electrically connected (or coupled) to the interface I / O interface 140IO of the semiconductor die 140 can be used as a signal TV interconnect, a power TV interconnect, a ground TV interconnect, or a combination thereof. The I / O interface 140IO of the semiconductor die 140 can be electrically connected (or coupled) to an external IC (not shown) connected to the base 200 without using the TV interconnect 314. The number of TV interconnects 314 can be further reduced. In addition, the size of the semiconductor die 180 can be further reduced.

[0107] In some other embodiments, the I / O interface 140IO (including interfaces 140IO-1, 140IO-2, 140IO-3 and 140IO-4) of the semiconductor die 140 can be electrically connected (or coupled) to an external IC (not shown) connected to the base 200 through a wiring path RP4' consisting of a first interconnect structure 110, a conductive bump 114, a first wiring structure 366, a TV interconnect 314, a second wiring structure 316 and a conductive structure, which is similar to the wiring path RP4 shown in Figure 1.

[0108] like Figure 6As shown, the bottom package 300D may further include an underfill (not shown) filling the gap (not shown) between the second routing structure 316 and the semiconductor die 180. In some embodiments, the underfill surrounds a portion of the conductive structure 154 and contacts a portion of the second routing structure 316 to further reduce the thermal resistance from the semiconductor die 180 to the second routing structure 316. In addition, the underfill may be provided to compensate for the different coefficients of thermal expansion (CTE) between the semiconductor die 180, the second routing structure 316, and the conductive structure 154. In some embodiments, the underfill includes a capillary underfill (CUF), a molded underfill (MUF), or a combination thereof.

[0109] Figure 7 5 is a cross-sectional view of a semiconductor package assembly 500E according to some embodiments of the present invention. Figure 1A , 1B For the sake of brevity, the same or similar elements described in , 2 to 6 are not repeated. Figure 6 and Figure 7 As shown, the difference between the semiconductor package assembly 500D and the semiconductor package assembly 500E at least includes: the semiconductor die 140 of the bottom package 300E of the semiconductor package assembly 500E may include a conductive bump 114TB as a heat dissipation bump to dissipate the heat generated by the semiconductor die 140. In some embodiments, the arrangement of the conductive bump 114TB of the semiconductor package assembly 500E may be the same as or similar to the conductive bump 114TB of the semiconductor package assembly 500B.

[0110] Figure 8 FIG. 5 is a cross-sectional view of a semiconductor package assembly 500F according to some embodiments of the present invention. Figure 1A , 1B , 2 to 7 described the same or similar elements will not be repeated. Figure 6 and Figure 8As shown, the difference between the semiconductor package assembly 500E and the semiconductor package assembly 500F is at least that the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3 and 140DDR-4) of the bottom package 300F of the semiconductor package assembly 500C is arranged in the central region R2 of the semiconductor die 140. In some embodiments, the arrangement of the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3 and 140DDR-4) of the semiconductor package assembly 500F may be the same as or similar to the data interface 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3 and 140DDR-4) of the semiconductor package assembly 500C. Furthermore, TV interconnects 180TV1 corresponding to data interfaces 140DDR (including interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4) may be arranged in the center region R2 of semiconductor die 140. Semiconductor package assembly 500F may have the same or similar advantages as semiconductor package assembly 500C.

[0111] An embodiment of the present invention provides a semiconductor package assembly, which includes a bottom package (e.g., a SOC package) and a top package (e.g., a memory package) stacked on the bottom package. The bottom package includes at least one semiconductor die (e.g., a logic die) using backside power supply technology. More TV interconnects (e.g., TV interconnects 314) surrounding the semiconductor die can be released for electrical connection between a DDR interface (e.g., interfaces 140DDR-1, 140DDR-2, 140DDR-3, and 140DDR-4) and the top package, for electrical connection between an I / O interface (e.g., interfaces 140IO-1, 140IO-2, 140IO-3, and 140IO-4) and a base, or for electrical connection between the top package and the base.

[0112] In addition, the DDR interface can be farther from the corresponding edge of the semiconductor crystal grain than the I / O interface (for example, the DDR interface can be arranged in the central area of ​​the semiconductor crystal grain). The wiring path (for example, the wiring path RP1) for transmitting signals between the DDR interface of the bottom package and the data channel of the top package can be shortened. More conductive structures of the upper package (for example, conductive structure 422) can be arranged without being restricted by the TV interconnection position of the bottom package. The increased conductive structure can be used for signal transmission (data transmission) between the bottom package and the upper package. In addition, the increased conductive structure can be used for power transmission and grounding paths between the upper package and the base. In addition, the area on the edge of the semiconductor crystal grain of the bottom package that was originally occupied by the DDR interface can be released to make room for more I / O interfaces. The embodiments of the present invention can improve the flexibility of the layout and shorten the path length of the corresponding connection, increase the signal transmission speed and avoid crosstalk between signals, so as to improve the performance of the semiconductor package assembly.

[0113] In addition, the TV interconnect surrounding the semiconductor die can serve as the electrical connection package of the upper package and the I / O interface of the bottom package. The distribution area of ​​the TV interconnect can have a hollow square shape or a hollow circular shape corresponding to the conductive structure of the top package and the I / O interface of the bottom package.

[0114] In some embodiments, the bottom package of the semiconductor package assembly may include a grounded conductive bump disposed directly on a digital IP block (e.g., digital IP block 140PDN) in the central region of the semiconductor die. The grounded conductive bump may help improve the efficiency of heat dissipation from the semiconductor die 140 to the environment outside the semiconductor package assembly.

[0115] In some embodiments, the bottom package of the semiconductor package assembly includes two semiconductor dies (e.g., logic dies) manufactured with different critical dimensions. The top semiconductor die with a narrower critical dimension is used to control the top package and includes an interface for external electrical connection between the bottom package and the top package or between the bottom package and the base. The bottom semiconductor die made with a wider critical dimension may include a TV interconnect (e.g., TV interconnect 180TV1) for power transmission and ground path of the DDR interface of the first semiconductor die. Since the top semiconductor die adopts back power technology, the TV interconnect passing through the bottom semiconductor die is not used for DDR signal transmission and the number is reduced. The size of the bottom semiconductor die can be further reduced.

[0116] An embodiment of the present invention provides a semiconductor package component, which includes a first semiconductor grain and a second semiconductor grain. The first semiconductor grain has a first surface and a second surface opposite to the first surface. The first semiconductor grain includes a first conductive bump, a second conductive bump, a first interface, and a second interface. The first conductive bump is arranged on the first surface of the first semiconductor grain. The second conductive bump is arranged on the second surface of the first semiconductor grain. The first interface is arranged on the first edge of the first semiconductor grain. The second interface is arranged beside the first interface. The second interface is farther away from the corresponding first edge of the first semiconductor grain than the first interface. The second semiconductor grain is stacked on the first semiconductor grain. The second semiconductor grain is electrically coupled to the first semiconductor grain through the second interface. In the embodiment of the present invention, the first conductive bump and the second conductive bump on both sides of the first semiconductor grain are respectively connected bidirectionally outward, and the second interface is set not on the edge of the first semiconductor grain, so that the length of the electrical connection path between the second interface and the second semiconductor grain can be shortened, the signal transmission speed can be improved, and the edge of the relatively scarce first semiconductor grain is left for other interfaces, thereby improving the flexibility of layout design.

[0117] In some embodiments, the first semiconductor die further includes a semiconductor substrate, a first interconnect structure and a second interconnect structure, the first interconnect structure and the second interconnect structure are respectively disposed on opposite surfaces of the semiconductor substrate. The first conductive bump is separated from the second conductive bump by the semiconductor substrate, the first interconnect structure and the second interconnect structure.

[0118] In some embodiments, the semiconductor package assembly further includes a first wiring structure contacting the first conductive bump. The second semiconductor die is electrically coupled to the second interface of the first semiconductor die through the first conductive bump and the first wiring structure.

[0119] In some embodiments, the first wiring structure is disposed between the first semiconductor die and the second semiconductor die.

[0120] In some embodiments, the first semiconductor die further includes a third conductive bump, which is disposed on the first surface of the first semiconductor die and contacts the first wiring structure. The third conductive bump is grounded.

[0121] In some embodiments, the third conductive bump is located in a central region of the first semiconductor die.

[0122] In some embodiments, the semiconductor package assembly further includes a second wiring structure, a first through-hole (TV) interconnection, and a second through-hole (TV) interconnection. The second wiring structure is disposed below the second conductive bump. The first through-hole (TV) interconnection and the second through-hole (TV) interconnection are disposed next to the first semiconductor crystal grain and electrically coupled between the first wiring structure and the second wiring structure. The second wiring structure is electrically coupled to the first interface of the first semiconductor crystal grain through the first TV interconnection and the first wiring structure.

[0123] In some embodiments, the second wiring structure contacts the second conductive bump.

[0124] In some embodiments, the second wiring structure is electrically coupled to the first interface of the first semiconductor die through a second conductive bump.

[0125] In some embodiments, the semiconductor package assembly further includes a second through-hole (TV) interconnect. The second through-hole (TV) interconnect is disposed next to the first semiconductor die and electrically connected to the stack between the first wiring structure and the second wiring structure. The second semiconductor die is electrically coupled to the second wiring structure through the first wiring structure and the second TV interconnect.

[0126] In some embodiments, the second TV interconnect is a power TV interconnect.

[0127] In some embodiments, the semiconductor package assembly further includes a molding compound. The molding compound surrounds the first semiconductor die, wherein the first TV interconnect and the second TV interconnect pass through the molding compound.

[0128] In some embodiments, the first conductive bump is a signal bump, and the second conductive bump is a power bump.

[0129] In some embodiments, the semiconductor package assembly further includes a fan-out package and a memory package. The fan-out package includes a first semiconductor die, a first wiring structure, and a second wiring structure. The memory package includes a third semiconductor die and is stacked on the fan-out package. The memory package includes third conductive bumps arranged in groups and disposed on opposite edges of the memory package.

[0130] In some embodiments, the second interface is located between the third conductive bump groups in a plan view.

[0131] In some embodiments, the second interface is located in a central region of the first semiconductor die.

[0132] In some embodiments, the semiconductor package assembly further includes a fourth semiconductor die. The fourth semiconductor die is disposed between the first semiconductor die and the second wiring structure. The second wiring structure is electrically coupled to the first interface of the first semiconductor die through the second conductive bump and the fourth semiconductor die.

[0133] In some embodiments, the fourth semiconductor die further includes a third through-via (TV) interconnect. The third through-via (TV) interconnect is formed through the fourth semiconductor die. The third TV interconnect overlaps the second interface. The third TV interconnect is electrically coupled to the second interface.

[0134] In some embodiments, the third TV interconnect is a power TV interconnect or a ground TV interconnect.

[0135] In some embodiments, the fourth semiconductor die further includes a fourth through-via (TV) interconnect formed through the fourth semiconductor die, wherein the fourth TV interconnect overlaps the first interface and is electrically coupled to the first interface.

[0136] An embodiment of the present invention provides a semiconductor package assembly, which includes a base, a fan-out package and a memory package. The fan-out package is mounted on the base. The fan-out package includes a first wiring structure, a second wiring structure and a top semiconductor grain. The first wiring structure and the second wiring structure are stacked on each other. The top semiconductor grain is arranged between the first wiring structure and the second wiring structure. The top semiconductor grain includes a first interface and a second interface. The first interface is arranged on a first edge of the top semiconductor grain. The second interface is arranged near the first interface. The second interface is farther from the corresponding first edge of the top semiconductor grain than the first interface. The memory package is arranged on the fan-out package. The base is electrically coupled to the first interface through at least the first wiring structure. The memory package is electrically coupled to the second interface through the first wiring structure but not the second wiring structure.

[0137] In some embodiments, the base is electrically coupled to the second interface through the second wiring structure instead of the first wiring structure.

[0138] In some embodiments, the top semiconductor die further includes a conductive bump. The conductive bump is arranged to be offset from the second interface and in contact with the first wiring structure. The conductive bump is grounded.

[0139] In some embodiments, the fan-out package further includes a bottom semiconductor die. The bottom semiconductor die is disposed between the top semiconductor die and the second wiring structure. The bottom semiconductor die includes a through-via (TV) interconnect overlapping and electrically coupled to the second interface.

[0140] Although the present invention has been described in terms of what are presently considered to be the most practical and preferred embodiments, it should be understood that the present invention is not necessarily limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements, including those within the spirit and scope of the appended claims, which should be given the broadest interpretation to cover all such modifications and similar structures.

Claims

1. A semiconductor package assembly, characterized in that: include: A first semiconductor crystal grain having a first surface and a second surface opposite to the first surface, wherein the first semiconductor crystal grain comprises: a first interface disposed on a first edge of the first semiconductor crystal grain; and a second interface located beside the first interface, wherein the second interface is farther away from the first edge of the first semiconductor crystal grain than the first interface; and A second semiconductor crystal grain is stacked on the first semiconductor crystal grain; Among them, the semiconductor packaging components also include: A first conductive bump is disposed on the first surface of the first semiconductor grain; and A second conductive bump is disposed on the second surface of the first semiconductor grain; The second semiconductor crystal grain is electrically coupled to the first semiconductor crystal grain through the second interface.

2. The semiconductor package assembly according to claim 1, wherein: The first semiconductor crystal grain further includes: semiconductor substrate; and A first interconnect structure and a second interconnect structure are disposed on opposite surfaces of the semiconductor substrate, wherein the first conductive bump is separated from the second conductive bump by the semiconductor substrate, the first interconnect structure and the second interconnect structure.

3. The semiconductor package assembly according to claim 1, wherein: Also includes: The first wiring structure is in contact with the first conductive bump, wherein the second semiconductor crystal grain is electrically coupled to the second interface of the first semiconductor crystal grain through the first conductive bump and the first wiring structure.

4. The semiconductor package assembly according to claim 3, wherein: Also includes: A third conductive bump is disposed on the first surface of the first semiconductor grain and contacts the first wiring structure, wherein the third conductive bump is grounded.

5. The semiconductor package assembly according to claim 4, wherein: The third conductive bump is located in the central region of the first semiconductor grain.

6. The semiconductor package assembly according to claim 3, wherein: Also includes: A second wiring structure is arranged below the second conductive bump; as well as a first through-via (TV) interconnect disposed beside the first semiconductor die and electrically coupled between the first wiring structure and the second wiring structure, The second wiring structure is electrically coupled to the first interface of the first semiconductor grain through the first TV interconnect and the first wiring structure.

7. The semiconductor package assembly according to claim 6, wherein: The second wiring structure is electrically coupled to the first interface of the first semiconductor die through the second conductive bump.

8. The semiconductor package assembly according to claim 6, wherein: Also includes: a second through-via (TV) interconnect disposed next to the first semiconductor die and electrically coupled between the first wiring structure and the second wiring structure, The second semiconductor die is electrically coupled to the second wiring structure through the first wiring structure and the second TV interconnect.

9. The semiconductor package assembly according to claim 8, wherein: The second TV interconnect is the power TV interconnect.

10. The semiconductor package assembly according to claim 1, wherein: The first conductive bump is a signal bump, and the second conductive bump is a power bump.

11. The semiconductor package assembly according to claim 6, wherein: Also includes: A fan-out package, comprising the first semiconductor die, the first wiring structure and the second wiring structure; as well as A memory package includes the third semiconductor die and is stacked on the fan-out package, wherein the memory package includes third conductive bumps arranged in groups and disposed on opposite edges of the memory package.

12. The semiconductor package assembly according to claim 11, wherein: The second interface is located in the central area of ​​the first semiconductor die.

13. The semiconductor package assembly according to claim 6, wherein: Also includes: The fourth semiconductor grain is disposed between the first semiconductor grain and the second wiring structure, wherein the second wiring structure is electrically coupled to the first interface of the first semiconductor grain through the second conductive bump and the fourth semiconductor grain.

14. The semiconductor package assembly according to claim 13, wherein: The fourth semiconductor die also includes: A third through-via (TV) interconnect is formed through the fourth semiconductor die, wherein the third TV interconnect overlaps and is electrically coupled to the second interface.

15. The semiconductor package assembly according to claim 14, wherein: The third TV interconnect is a power TV interconnect or a ground TV interconnect.

16. The semiconductor package assembly according to claim 13, wherein: The fourth semiconductor die further includes: A fourth through-via (TV) interconnect is formed through the fourth semiconductor die, wherein the fourth TV interconnect overlaps and is electrically coupled to the first interface.

17. A semiconductor package assembly, characterized in that: include: A fan-out package, comprising: a first wiring structure and a second wiring structure stacked on each other; and a top semiconductor die disposed between the first wiring structure and the second wiring structure; wherein the top semiconductor die comprises: a first interface disposed on a first edge of the top semiconductor die; and a second interface disposed near the first interface, wherein the second interface is further away from the first edge of the top semiconductor die than the first interface; and A memory package is provided on the fan-out package, wherein the base is electrically coupled to the first interface via at least the second wiring structure, and The memory package is electrically coupled to the second interface through the first wiring structure but not the second wiring structure.

18. The semiconductor package assembly according to claim 17, wherein: The base is electrically coupled to the second interface through the second wiring structure instead of the first wiring structure.

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