Input multiplication amplifier, instrument amplifier, and electronic chip

Abstract

The invention discloses an input multiplication amplifier, an instrument amplifier and an electronic chip, the input multiplication amplifier comprises a first phase inverter and a second phase inverter, the first phase inverter comprises a first normal phase PMOS tube and a first normal phase NMOS tube which are in common-gate and common-source connection, and the second phase inverter comprises a first reverse phase PMOS tube and a first reverse phase NMOS tube which are in common-gate and common-source connection; the input of the first inverter and the input of the second inverter are used as differential inputs of the amplifier, and the output of the first inverter and the output of the second inverter are used as differential outputs of the amplifier. The method is suitable for the Internet of Things chip.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an input multiplier amplifier, an instrument amplifier and an electronic chip. Background Art

[0002] In IoT applications, chips are usually powered by small-capacity batteries or energy-harvesting modules, which requires each circuit module to have the lowest possible power consumption while ensuring performance. In IoT application systems, in addition to limited energy consumption, noise also needs to be limited to the μV level, and the front-end amplifier affects the noise level. Therefore, the noise of the front-end amplifier and the energy consumption of the entire amplifier circuit have an important impact on the service life of the sensor system. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides an input multiplier amplifier, an instrument amplifier and an electronic chip, which have lower input noise and higher amplifier circuit energy efficiency.

[0004] The present invention provides an input multiplier amplifier, comprising: a first inverter and a second inverter, the first inverter comprising a first positive phase PMOS tube and a first positive phase NMOS tube connected with a common gate and a common source, the second inverter comprising a first inverting PMOS tube and a first inverting NMOS tube connected with a common gate and a common source; the input of the first inverter and the input of the second inverter serve as differential inputs of the amplifier, and the output of the first inverter and the output of the second inverter serve as differential outputs of the amplifier.

[0005] The present invention also provides an instrument amplifier, comprising: a first-stage amplifier, a second-stage amplifier and a third-stage amplifier, wherein the first-stage amplifier adopts the above-mentioned input multiplier amplifier, inter-stage coupling capacitors are connected between each stage of the amplifier, a pseudo-resistance is connected to the input end of the second-stage amplifier, and the third-stage amplifier adopts a tailless current biasing method, and the input end is connected to the output of the second stage through a chopper circuit.

[0006] The present invention also provides an electronic chip, comprising the above instrument amplifier.

[0007] The present invention also provides an input multiplier amplifier, comprising: a first inverter and a second inverter, the first inverter comprising a first positive phase PNP transistor and a first positive phase NPN transistor connected with a common base and a common emitter, the second inverter comprising a first inverting PNP transistor and a first inverting NPN transistor connected with a common base and a common emitter; the input of the first inverter and the input of the second inverter serve as differential inputs of the amplifier, and the output of the first inverter and the output of the second inverter serve as differential outputs of the amplifier.

[0008] The present invention doubles the gain of the amplifier by adopting a differential input method, and the common mode is suppressed. As the first stage of the amplifier circuit, it can effectively reduce the noise efficiency factor and the energy efficiency factor, thereby improving the circuit performance, which is conducive to application in the Internet of Things chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0010] Figure 1 Schematic diagram of the principle of gain multiplication in an input multiplier amplifier in an embodiment of the present invention;

[0011] Figure 2 for Figure 1 Schematic diagram of gain multiplication effect;

[0012] Figure 3 A schematic diagram of the structure of an input multiplier amplifier provided by an embodiment of the present invention;

[0013] Figure 4A A schematic diagram of an input multiplier amplifier with bias tail current provided by an embodiment of the present invention;

[0014] Figure 4B for Figure 4A Schematic diagram of the tail PMOS tube and the input PMOS tube sharing bias;

[0015] Figure 4C for Figure 4A Schematic diagram of the middle tail NMOS tube using negative feedback access;

[0016] Figure 5 A schematic diagram of an instrument amplifier provided by an embodiment of the present invention;

[0017] Figure 6 for Figure 5 Schematic diagram of the second stage amplifier in the figure;

[0018] Figure 7 for Figure 5 Schematic diagram of the third stage amplifier;

[0019] Fig. 8A for Figure 5 Schematic diagram of pseudo-resistance current leakage in an embodiment;

[0020] Figure 8B for Figure 5Schematic diagram of substrate current leakage at the third-stage input terminal in the embodiment;

[0021] Figure 8C for Figure 5 Schematic diagram of a pseudo-resistance configuration well bias amplifier in an embodiment;

[0022] Fig.8D for Figure 5 A schematic diagram of a bias adjustment amplifier configured at the third-stage input terminal in an embodiment;

[0023] Fig. 9 A schematic diagram of another input multiplier amplifier provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] In practical applications, amplifiers usually use noise efficiency factor (NEF) and power efficiency factor (PEF) to consider the performance of circuit systems. These two factors are mainly affected by the ratio of current to transconductance (I / gm) of the circuit. In addition, the power supply voltage also has an important influence on the power efficiency factor. In order to reduce energy consumption and the impact of noise on the circuit and effectively improve the service life of the sensor system, the present invention uses an input multiplier amplifier as the first-stage amplifier, and through differential input, its output gain can be doubled, thereby not only reducing the noise efficiency factor, but also having higher energy efficiency.

[0026] To make the technical solution of the present invention clearer, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figure 1 FIG. 1 is a schematic diagram of the principle of gain multiplication in an input multiplier amplifier in an embodiment of the present invention. Figure 2 for Figure 1 Schematic diagram of the gain multiplication effect, Figure 3 A schematic diagram of the structure of an input multiplier amplifier provided by an embodiment of the present invention is shown in FIG. Figure 1 and Figure 2 It can be seen that the use of differential input can make the gate-coupled output and the source-coupled output superimposed, thereby doubling the output gain and suppressing the common-mode output. Figure 3As shown, the input multiplier amplifier in this embodiment includes: a first inverter and a second inverter, the first inverter includes a first positive phase PMOS transistor M connected with a common gate and a common source. P1+ and the first positive phase NMOS tube M N1+ The second inverter includes a first inverting PMOS tube M connected with a common gate and a common source. P1- and the first inverting NMOS tube M N1- The input of the first inverter and the input of the second inverter are used as the differential input of the amplifier (V i+ ,V i- ), the output of the first inverter and the output of the second inverter are used as the differential output of the amplifier (V o+ ,V o- ).

[0028] In this embodiment, the amplifier composed of inverters is configured to have differential input and differential output, so that the gain can be doubled, which is not only conducive to reducing the input noise factor, but also improves the energy efficiency of the amplifier.

[0029] In the above embodiment, the input multiplier amplifier also includes: a gate coupling capacitor Cg and a source coupling capacitor Cs, one end of the differential input is respectively connected to the gate of the first positive phase PMOS tube and the gate of the first positive phase NMOS tube through the gate coupling capacitor, and is respectively connected to the source of the first inverting PMOS tube and the source of the first inverting NMOS tube through the source coupling capacitor; the other end of the differential input is respectively connected to the gate of the first inverting PMOS tube and the gate of the first inverting NMOS tube through the source coupling capacitor, and is respectively connected to the source of the first positive phase PMOS tube and the source of the first positive phase NMOS tube through the gate coupling capacitor.

[0030] Figure 4A A schematic diagram of an input multiplier amplifier with bias tail current provided by an embodiment of the present invention, Figure 4B for Figure 4A Schematic diagram of the tail PMOS tube and the input PMOS tube sharing the bias. Figure 4C for Figure 4A The schematic diagram of the middle tail NMOS tube using negative feedback access is as follows Figures 4A-4C As shown, the above-mentioned input multiplier amplifier also includes: a first tail PMOS tube M p2+ , the second tail PMOS tube M p2- , the first tail NMOS tube M n2+ And the second tail NMOS tube M n2-The drain of the first tail PMOS tube is connected to the power supply, the source is connected to the drain of the first positive phase PMOS tube, and the gate is connected to the first bias voltage; the drain of the second tail PMOS tube is connected to the power supply, the source is connected to the drain of the first negative phase PMOS tube, and the gate is connected to the first bias voltage; the source of the first tail NMOS tube is connected to the ground, the drain is connected to the source of the first positive phase NMOS tube, and the gate is connected to the second bias voltage; the source of the second tail NMOS tube is connected to the ground, the drain is connected to the source of the first negative phase NMOS tube, and the gate is connected to the third bias voltage.

[0031] The first positive phase PMOS tube, the first positive phase NMOS tube, the first negative phase PMOS tube and the first negative phase NMOS tube operate in the subthreshold region, so that the output has a larger I / gm, the first tail PMOS tube, the second tail PMOS tube, the first tail NMOS tube and the second tail NMOS tube operate in the saturation region, and have better matching. The first tail NMOS tube and the second tail NMOS tube are biased through a negative feedback loop so that the differential DC outputs cancel each other out.

[0032] Figure 5 A schematic diagram of an instrument amplifier provided by an embodiment of the present invention, Figure 6 for Figure 5 Schematic diagram of the second stage amplifier in Figure 7 for Figure 5 The schematic diagram of the third stage amplifier is as follows: Figure 5-Figure 7 As shown, the instrument amplifier of this embodiment includes: a first-stage amplifier (input multiplier amplifier), a second-stage amplifier and a third-stage amplifier, wherein the first-stage amplifier adopts the input multiplier amplifier in the above embodiment, inter-stage coupling capacitors are connected between each stage of the amplifier, a pseudo-resistance is connected to the input end of the second-stage amplifier, and the third-stage amplifier adopts a tailless current biasing method, and the input end is connected to the output of the second stage through a chopper circuit.

[0033] In the instrument amplifier, the output end of the third-stage amplifier is positively fed back to the input end of the first-stage amplifier through a chopper circuit.

[0034] Fig. 8A for Figure 5 Schematic diagram of pseudo-resistance current leakage in the embodiment, Figure 8B for Figure 5 Schematic diagram of substrate current leakage at the third-stage input terminal in the embodiment, Figure 8C for Figure 5 Schematic diagram of a pseudo-resistance configuration well bias amplifier in an embodiment, Fig.8D for Figure 5 A schematic diagram of configuring a bias adjustment amplifier at the third input terminal in the embodiment is shown in FIG. Figures 8A-8DAs shown, a bias adjustment amplifier is also provided at the input end of the third-stage amplifier, and the bias adjustment amplifier dynamically adjusts the bias voltage according to the common-mode input voltage of the third-stage amplifier; the pseudo-resistance is formed by a MOS tube, and the instrument amplifier also includes: a well bias amplifier is configured for the MOS tube to reduce the current leakage of the parasitic diode.

[0035] The embodiment of the present invention doubles the gain of the amplifier by adopting a differential input method, and the common mode is suppressed. As the first stage of the amplifier circuit, it can effectively reduce the noise efficiency factor and the energy efficiency factor, thereby improving the circuit performance, which is conducive to application in the Internet of Things chip.

[0036] An embodiment of the present invention further provides an electronic chip, comprising the instrument amplifier in the above embodiment.

[0037] Fig. 9 A schematic diagram of another input multiplier amplifier provided by an embodiment of the present invention is shown in FIG. Fig. 9 As shown, the input multiplier amplifier in the embodiment of the present invention includes: a first inverter and a second inverter, the first inverter includes a first positive phase PNP transistor and a first positive phase NPN transistor connected with a common base and a common emitter, and the second inverter includes a first inverting PNP transistor and a first inverting NPN transistor connected with a common base and a common emitter; the input of the first inverter and the input of the second inverter serve as differential inputs of the amplifier, and the output of the first inverter and the output of the second inverter serve as differential outputs of the amplifier. This embodiment is different from the above Figure 3 The difference between the illustrated embodiments is that a triode is used for implementation, and the multiplication principle is similar to that of a MOS tube.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An input multiplier amplifier, characterized in that: include: A first inverter and a second inverter, the first inverter comprising a first positive phase PMOS tube and a first positive phase NMOS tube connected in common gate and common source, and the second inverter comprising a first negative phase PMOS tube and a first negative phase NMOS tube connected in common gate and common source; The input of the first inverter and the input of the second inverter serve as differential inputs of the amplifier, and the output of the first inverter and the output of the second inverter serve as differential outputs of the amplifier.

2. The input multiplier amplifier according to claim 1, characterized in that: It also includes: a gate coupling capacitor and a source coupling capacitor, one end of the differential input is connected to the gate of the first positive phase PMOS tube and the gate of the first positive phase NMOS tube respectively through the gate coupling capacitor, and is connected to the source of the first negative phase PMOS tube and the source of the first negative phase NMOS tube respectively through the source coupling capacitor; the other end of the differential input is connected to the gate of the first negative phase PMOS tube and the gate of the first negative phase NMOS tube respectively through the source coupling capacitor, and is connected to the source of the first positive phase PMOS tube and the source of the first positive phase NMOS tube respectively through the gate coupling capacitor.

3. The input multiplier amplifier according to claim 1 or 2, characterized in that: It also includes a first tail PMOS tube, a second tail PMOS tube, a first tail NMOS tube and a second tail NMOS tube, wherein the drain of the first tail PMOS tube is connected to a power supply, the source is connected to the drain of the first positive phase PMOS tube, and the gate is connected to a first bias voltage; the drain of the second tail PMOS tube is connected to a power supply, the source is connected to the drain of the first negative phase PMOS tube, and the gate is connected to a first bias voltage; the source of the first tail NMOS tube is connected to the ground, the drain is connected to the source of the first positive phase NMOS tube, and the gate is connected to a second bias voltage; the source of the second tail NMOS tube is connected to the ground, the drain is connected to the source of the first negative phase NMOS tube, and the gate is connected to a third bias voltage.

4. The input multiplier amplifier according to claim 3, characterized in that: The first positive phase PMOS tube, the first positive phase NMOS tube, the first negative phase PMOS tube and the first negative phase NMOS tube operate in the subthreshold region, and the first tail PMOS tube, the second tail PMOS tube, the first tail NMOS tube and the second tail NMOS tube operate in the saturation region.

5. The input multiplier amplifier according to claim 4, characterized in that: The first tail NMOS transistor and the second tail NMOS transistor are biased by a negative feedback loop so that the differential DC outputs cancel each other out.

6. An instrument amplifier, characterized in that: include: A first stage amplifier, a second stage amplifier and a third stage amplifier, wherein the first stage amplifier adopts an input multiplier amplifier as described in any one of claims 1-5, interstage coupling capacitors are connected between each stage of the amplifier, a pseudo resistor is connected to the input end of the second stage amplifier, and the third stage amplifier adopts a tailless current biasing method, and the input end is connected to the output of the second stage through a chopper circuit.

7. The instrument amplifier according to claim 6, characterized in that The output end of the third-stage amplifier is positively fed back to the input end of the first-stage amplifier through a chopper circuit.

8. The instrument amplifier according to claim 6, characterized in that A bias adjustment amplifier is also provided at the input end of the third-stage amplifier, and the bias adjustment amplifier dynamically adjusts the bias voltage according to the common-mode input voltage of the third-stage amplifier; the pseudo-resistance is formed by a MOS tube, and the instrument amplifier also includes: a well bias amplifier is configured for the MOS tube to reduce the current leakage of the parasitic diode.

9. An electronic chip, characterized in that: The invention comprises an instrument amplifier as claimed in any one of claims 6 to 8.

10. An input multiplier amplifier, characterized in that: include: A first inverter and a second inverter, the first inverter includes a first positive phase PNP transistor and a first positive phase NPN transistor connected with a common base and a common emitter, and the second inverter includes a first inverting PNP transistor and a first inverting NPN transistor connected with a common base and a common emitter; the input of the first inverter and the input of the second inverter serve as differential inputs of the amplifier, and the output of the first inverter and the output of the second inverter serve as differential outputs of the amplifier.

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