Low-noise high-gain preamplifier

Abstract

The invention discloses a low-noise high-gain preamplifier which comprises a first differential amplification circuit, a second differential amplification circuit and a secondary amplification module, the first input end of the first differential amplification circuit is electrically connected with a differential input signal, and the output end of the first differential amplification circuit is electrically connected with the input end of the second differential amplification circuit; the output end of the second differential amplification circuit is electrically connected with the second input end of the first differential amplification circuit and the input end of the secondary amplification module, the output end of the secondary amplification module is electrically connected with the input end of the receiving terminal, the first differential amplification circuit comprises a plurality of JFETs, and the second differential amplification circuit comprises a plurality of operational amplifiers; the first differential amplification circuit amplifies the differential signal, the second differential amplification circuit amplifies the amplified differential signal again to obtain a primarily amplified voltage signal, and the secondary amplification module amplifies the primarily amplified voltage signal. According to the invention, low-noise and high-gain amplification processing on the differential input signal is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of preamplifiers, and in particular relates to a low-noise and high-gain preamplifier. Background Art

[0002] In many fields, there are some low-frequency and very weak electrical signals, many of which are at the millivolt level. Usually, these electrical signals are amplified by the amplifier circuit and then processed accordingly, such as human breathing and heartbeat signals, weak light signals, and weak magnetic signal lights. These signals are not only very weak, but also easily interfered by noise. Some of these noise interferences come from external noise interference sources, and some come from the noise of the circuit itself. The circuit itself contains the noise generated by the electronic components itself, the interference between the wires, electromagnetic compatibility, etc. These noise interference signals will become very large after being amplified by the circuit, and will be mixed with the normal signals and output, which will reduce the overall performance of the amplifier circuit, affect the dynamic range, and reduce the accuracy of the extracted signal. Therefore, in the small signal amplifier circuit, the amplifier circuit is not only required to have high gain and good linearity, but also low noise.

[0003] Currently, integrated operational amplifiers have been widely used. Usually, small signal amplifiers are directly composed of high-precision, low-noise integrated operational amplifiers and discrete components such as resistors and capacitors. Although these circuits have the advantages of high gain and good stability, due to process reasons, the base resistance of transistors in integrated circuits is relatively large. The large resistance also leads to large low-frequency noise. Therefore, when the integrated operational amplifier amplifies the initial signal, it introduces excessive additional noise interference, which poses a challenge to subsequent accurate signal processing and analysis. Summary of the invention

[0004] In view of this, the present invention provides a low-noise and high-gain preamplifier, the main purpose of which is to solve the problem that the existing integrated operational amplifier introduces excessive additional noise interference when amplifying the initial signal.

[0005] To solve the above problems, the present application provides a low-noise and high-gain preamplifier, including a primary amplification module and a secondary amplification module, wherein the primary amplification module includes a first differential amplification circuit and a second differential amplification circuit, wherein:

[0006] The first input end of the first differential amplifier circuit is electrically connected to the differential signal output end of the signal terminal, the output end of the first differential amplifier circuit is electrically connected to the input end of the second differential amplifier circuit, the output end of the second differential amplifier circuit is electrically connected to the second input end of the first differential amplifier circuit and the input end of the secondary amplifier module respectively, and the output end of the secondary amplifier module is electrically connected to the input end of the receiving terminal, wherein the first differential amplifier circuit includes a plurality of JFET field effect transistors, and the second differential amplifier circuit includes a plurality of operational amplifiers;

[0007] The first differential amplifier circuit amplifies the differential signal from the signal terminal to obtain a primary amplified differential signal, the second differential amplifier circuit amplifies the primary amplified differential signal to obtain a primary amplified voltage signal, and the secondary amplifier module amplifies the primary amplified voltage signal to obtain and output a secondary amplified voltage signal.

[0008] In one embodiment of the present invention, optionally, the first differential amplifier circuit includes a cascaded differential amplifier unit and a bias current unit, wherein:

[0009] The first input end of the cascaded differential amplifier unit is electrically connected to the differential signal output end of the signal terminal, the second input end of the cascaded differential amplifier unit is electrically connected to the output end of the bias current unit, the output end of the cascaded differential amplifier unit is electrically connected to the input end of the second differential amplifier circuit; the third input end of the cascaded differential amplifier unit is electrically connected to the output end of the second differential amplifier circuit.

[0010] In one embodiment of the present invention, optionally, the cascaded differential amplifier unit includes a first JFET field effect transistor, a second JFET field effect transistor, a third JFET field effect transistor, a fourth JFET field effect transistor, a first bias resistor and a second bias resistor, wherein:

[0011] The gate of the third JFET field effect transistor is electrically connected to the source of the first JFET field effect transistor and the first output end of the second differential amplifier circuit, respectively; the drain of the third JFET field effect transistor is electrically connected to the first output end of the bias current unit and the first input end of the second differential amplifier circuit, the source of the third JFET field effect transistor is electrically connected to the drain of the first JFET field effect transistor, the gate of the first JFET field effect transistor is electrically connected to the first differential signal output end of the signal terminal and the first end of the first bias resistor, respectively; and the second end of the first bias resistor is electrically connected to the ground end of the power supply;

[0012] The gate of the fourth JFET field effect transistor is electrically connected to the source of the second JFET field effect transistor and the second output end of the second differential amplifier circuit, respectively; the drain of the fourth JFET field effect transistor is electrically connected to the second output end of the bias current unit and the second input end of the second differential amplifier circuit, respectively; the source of the fourth JFET field effect transistor is electrically connected to the drain of the second JFET field effect transistor, the gate of the second JFET field effect transistor is electrically connected to the second differential signal output end of the signal terminal and the first end of the second bias resistor, respectively; and the second end of the second bias resistor is electrically connected to the ground end of the power supply.

[0013] In one embodiment of the present invention, optionally, the bias current unit includes a fifth JFET field effect transistor, a sixth JFET field effect transistor, a first adjustable resistor, a second adjustable resistor and a current limiting resistor, wherein:

[0014] The gate of the fifth JFET field effect transistor is electrically connected to the drain of the third JFET field effect transistor, the first end of the first adjustable resistor and the first input end of the second differential amplifier circuit respectively, the drain of the fifth JFET field effect transistor is electrically connected to the positive electrode of the power supply through the current limiting resistor, and the source of the fifth JFET field effect transistor is electrically connected to the second end of the first adjustable resistor;

[0015] The gate of the sixth JFET field effect transistor is electrically connected to the drain of the fourth JFET field effect transistor, the first end of the second adjustable resistor and the second input end of the second differential amplifier circuit, the drain of the sixth JFET field effect transistor is electrically connected to the positive electrode of the power supply through the current limiting resistor, and the source of the sixth JFET field effect transistor is electrically connected to the second end of the second adjustable resistor.

[0016] In one embodiment of the present invention, optionally, the first differential amplifier circuit further includes a first RC phase compensation unit, a first end of the first RC phase compensation unit being electrically connected to the drain of the third JFET field effect transistor, the first output end of the bias current unit and the first input end of the second differential amplifier circuit, and a second end of the first RC phase compensation unit being electrically connected to the drain of the fourth JFET field effect transistor, the second output end of the bias current unit and the second input end of the second differential amplifier circuit.

[0017] In one embodiment of the present invention, optionally, the second differential amplifier circuit includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor and a third resistor, wherein:

[0018] The negative input terminal of the first operational amplifier is electrically connected to the drain of the third JFET field effect transistor, the first output terminal of the bias current unit and the first terminal of the first RC phase compensation unit, respectively; the positive input terminal of the first operational amplifier is electrically connected to a reference voltage; the output terminal of the first operational amplifier is electrically connected to the positive input terminal of the third operational amplifier and the first terminal of the third resistor, respectively; the second terminal of the third resistor is electrically connected to the first terminal of the first resistor, the source of the first JFET field effect transistor and the gate of the third JFET field effect transistor, respectively;

[0019] The negative input terminal of the second operational amplifier is electrically connected to the drain of the fourth JFET field effect transistor, the second output terminal of the bias current unit and the second terminal of the first RC phase compensation unit respectively, the positive input terminal of the second operational amplifier is electrically connected to the reference voltage, the output terminal of the second operational amplifier is electrically connected to the negative input terminal of the third operational amplifier and the first terminal of the second resistor respectively, the second terminal of the second resistor is electrically connected to the second terminal of the first resistor, the source of the second JFET field effect transistor and the gate of the fourth JFET field effect transistor respectively; the output terminal of the third operational amplifier is electrically connected to the input terminal of the receiving terminal.

[0020] In one embodiment of the present invention, optionally, the gain factor of the third operational amplifier is 1.

[0021] In one embodiment of the present invention, optionally, the secondary amplification module includes a third differential amplification unit and a fourth operational amplifier, wherein:

[0022] The first input end of the third differential amplifier unit is electrically connected to the output end of the second differential amplifier circuit, the second input end of the third differential amplifier unit is electrically connected to the output end of the fourth operational amplifier, the first output end of the third differential amplifier unit is electrically connected to the positive input end of the fourth operational amplifier, the second output end of the third differential amplifier unit is electrically connected to the negative input end of the fourth operational amplifier, and the output end of the fourth operational amplifier is also electrically connected to the input end of the receiving terminal.

[0023] In one embodiment of the present invention, optionally, the third differential amplification unit includes a seventh JFET field effect transistor, an eighth JFET field effect transistor, a fourth resistor, a fifth resistor and a sixth resistor, wherein:

[0024] The gate of the seventh JFET field effect transistor is electrically connected to the output end of the second differential amplifier circuit, the drain of the seventh JFET field effect transistor is electrically connected to the positive input end of the fourth operational amplifier and the first end of the fourth resistor respectively, the source of the seventh JFET field effect transistor is electrically connected to the negative electrode of the power supply through the sixth resistor; the second end of the fourth resistor is electrically connected to the positive electrode of the power supply;

[0025] The gate of the eighth JFET field effect transistor is electrically connected to the output end of the fourth operational amplifier, the drain of the eighth JFET field effect transistor is electrically connected to the negative input end of the fourth operational amplifier and the first end of the fifth resistor respectively, the source of the eighth JFET field effect transistor is electrically connected to the positive electrode of the power supply through the sixth resistor, and the second end of the fifth resistor is electrically connected to the positive electrode of the power supply.

[0026] In one embodiment of the present invention, optionally, the third differential amplification unit also includes a second RC phase compensation circuit, a first end of the second RC phase compensation circuit is respectively electrically connected to the drain of the seventh JFET field effect transistor, the positive input terminal of the fourth operational amplifier and the first end of the fourth resistor, and a second end of the second RC phase compensation circuit is respectively electrically connected to the drain of the eighth JFET field effect transistor, the negative input terminal of the fourth operational amplifier and the first end of the fifth resistor.

[0027] The present invention provides a low-noise and high-gain preamplifier, which uses a first differential amplifier circuit composed of discrete JFET field effect tubes to amplify differential input signals, and uses a second differential amplifier circuit composed of a low-noise operational amplifier to further amplify the differential input signals. Since the JFET field effect tube has low noise, the differential amplifier circuit composed of discrete JFET field effect tubes also has low noise. The first differential amplifier circuit extracts and amplifies the input differential signal, which can well suppress noise. The second differential amplifier circuit has a very high common-mode rejection ratio, which enables the differential signal to be amplified more clearly. Finally, the voltage signal output by the first amplifier module is amplified by the second amplifier module to improve the gain, thereby realizing low-noise and high-gain amplification processing of the differential input signal.

[0028] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0030] Figure 1 The figure is a structural block diagram of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0031] Figure 2 The present invention is another structural block diagram of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0032] Figure 3 The present invention is a schematic diagram of the circuit connection of a first-stage amplification module of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0033] Figure 4 This is a graph showing an equivalent input noise curve of a first-stage amplification module of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0034] Figure 5 The present invention is a schematic diagram of the circuit connection of a secondary amplification module of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0035] Figure 6 This is a frequency characteristic curve diagram of a secondary amplification module of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0036] Figure 7 4 is a voltage gain diagram of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0037] Figure 8 1 is a circuit equivalent input noise diagram (frequency from 1 Hz to 1 MHz) of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0038] Fig. 9 1 is a circuit equivalent input noise diagram (frequency from 100 Hz to 100 kHz) of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0039] Fig.10 Graph showing an output offset voltage of a low-noise, high-gain preamplifier according to an exemplary embodiment of the present invention.

[0040] Fig.11 The figure is a graph showing an input-output characteristic curve of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0041] Fig.12 The figure is a frequency characteristic curve diagram of a low-noise and high-gain preamplifier according to an exemplary embodiment of the present invention.

[0042] in,

[0043] The numbers are as follows: 11-first differential amplifier circuit; 12-second differential amplifier circuit; 13-secondary amplifier module; J1A-first JFET field effect transistor; J1B-second JFET field effect transistor; J2A-third JFET field effect transistor; J2B-fourth JFET field effect transistor; Ra-first bias resistor; Rb-second bias resistor; J3A-fifth JFET field effect transistor; J3B-sixth JFET field effect transistor; R4-first adjustable resistor; R5-second adjustable resistor; R10-current limiting resistor; Rx-first phase resistor; Cx-first phase capacitor; U1-first operational amplifier; U2-second operational amplifier; U3-third operational amplifier; R1-first resistor; R2-second resistor; R3-third resistor; U4-fourth operational amplifier; J4A-seventh JFET field effect transistor; J4B-eighth JFET field effect transistor; R17-fourth resistor; R18-fifth resistor; R20-sixth resistor. DETAILED DESCRIPTION

[0044] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0045] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation methods, structures, features and effects of the present invention application are described in detail below in conjunction with the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "embodiment" does not necessarily refer to the same embodiment. In addition, specific features, structures, or characteristics in one or more embodiments may be combined in any suitable form.

[0046] Combine the following Figures 1 to 12 A low-noise and high-gain preamplifier according to some embodiments of the present invention is described.

[0047] In one embodiment, Figure 1 As shown, a low-noise and high-gain preamplifier includes a primary amplification module and a secondary amplification module 13, wherein the primary amplification module includes a first differential amplification circuit 11 and a second differential amplification circuit 12, wherein:

[0048] The first input end of the first differential amplifier circuit 11 is electrically connected to the differential signal output end of the signal terminal, the output end of the first differential amplifier circuit 11 is electrically connected to the input end of the second differential amplifier circuit 12, the output end of the second differential amplifier circuit 12 is electrically connected to the second input end of the first differential amplifier circuit 11 and the input end of the secondary amplifier module 13 respectively, and the output end of the secondary amplifier module 13 is electrically connected to the input end of the receiving terminal, wherein the first differential amplifier circuit 11 includes a plurality of JFET field effect transistors, and the second differential amplifier circuit 12 includes a plurality of operational amplifiers;

[0049] The first differential amplifier circuit 11 amplifies the differential signal from the signal terminal to obtain a primary amplified differential signal. The second differential amplifier circuit 12 amplifies the primary amplified differential signal to obtain a primary amplified voltage signal. The secondary amplifier module 13 amplifies the primary amplified voltage signal to obtain and output a secondary amplified voltage signal.

[0050] Specifically, usually a small signal amplifier is directly composed of a high-precision, low-noise operational amplifier and discrete components such as resistors and capacitors. Although these circuits have high gain and high input impedance, due to process reasons, the base resistance of the transistor in the integrated circuit is much larger than that of the discrete components, so its low-frequency noise is also much larger than that of the discrete components. Therefore, the present invention proposes a preamplifier that uses discrete components to extract signals from signal sources and suppress noise, and is used in weak signal amplification circuits that have extremely high noise requirements and are flexible to use.

[0051] Specifically, a two-stage amplification form is adopted, and the first-stage amplification module includes a first differential amplifier circuit and a second differential amplifier circuit, and the second differential amplifier circuit is an instrument amplifier. The first stage adopts the idea of ​​an extended differential circuit. The main consideration is that although the instrument amplifier has a high common-mode rejection ratio, it is difficult to achieve low noise. Because there are many components in the op amp, if it is used as the initial input device of the signal, it is difficult to achieve low noise. Even if it can be achieved, the price is very expensive. Discrete JFET field effect tubes have excellent low noise characteristics and are low in cost. However, if a traditional JFET (such as a pair of tubes connected to a current source) differential circuit is used, although the low noise advantage can be obtained, the common-mode rejection ratio and gain are often unsatisfactory. Therefore, the advantages of the instrument amplifier and the JFET field effect tube pair are combined to make the best use of their strengths and avoid their weaknesses. Each group of JFET field effect tubes is individually connected to the input op amp of the instrument amplifier to form a composite input structure of JFET-op amp, and the output of the op amp is then combined with the third op amp of the instrument amplifier to form a differential structure. From a macroscopic perspective, it is equivalent to the composite input structure of JFET-op amp (a pair, symmetrical form) forming a generalized differential circuit with the third op amp, thus giving full play to the advantages of low noise of JFET field effect tube and high common mode rejection ratio of instrument amplifier. Figure 2The input stage uses an input differential pair composed of JFET devices and a negative feedback network composed of an operational amplifier to form an input stage amplifier circuit.

[0052] The first-stage amplifier circuit realizes the preliminary amplification of the differential input signal with low noise, and then the second-stage amplifier is used to increase the gain to achieve low noise and high gain. The first differential amplifier circuit composed of discrete component JFET field effect tubes is used as the input device of the preamplifier. The JFET field effect tube has low noise, and the input differential signal is extracted and amplified to suppress noise. Then the second differential amplifier circuit composed of a low-noise operational amplifier is used to further amplify the differential input signal. The second differential amplifier circuit has a high common-mode rejection ratio, so that the differential signal is amplified more clearly. Since the noise of discrete devices is lower than that of integrated operational amplifiers, and the noise of JFET field effect tubes is also low, the preliminary amplification of the differential input signal with low noise is realized. Finally, the voltage signal output by the first-stage amplifier module is amplified by the second-stage amplifier module to improve the gain.

[0053] In one embodiment, the circuit composed of discrete devices can flexibly design its static operating point, input circuit, bias circuit and feedback circuit structure according to actual needs, and obtain an amplifier circuit with better performance by reasonably adjusting the parameters of circuit components and the structure of the circuit.

[0054] In one embodiment, the signal terminal may be a low-frequency weak signal such as a standard power source or a sensor.

[0055] Compared with the prior art, the present application provides a low-noise and high-gain preamplifier, which uses a first differential amplifier circuit composed of discrete component JFET field-effect transistors as the input device of the preamplifier, and uses a second differential amplifier circuit composed of a low-noise operational amplifier to further amplify the differential input signal. Since the JFET field-effect transistor has low noise, the differential amplifier circuit composed of discrete JFET field-effect transistors also has low noise. The first differential amplifier circuit extracts and amplifies the input differential signal, which can well suppress noise. The second differential amplifier circuit has a very high common-mode rejection ratio, so that the differential signal is amplified more clearly. Finally, the voltage signal output by the first-stage amplifier module is amplified by the second-stage amplifier module to improve the gain, thereby realizing low-noise and high-gain amplification processing of the differential input signal.

[0056] In one embodiment, the first differential amplifier circuit 11 includes a cascaded differential amplifier unit and a bias current unit, wherein:

[0057] The first input end of the cascaded differential amplifier unit is electrically connected to the differential signal output end of the signal terminal, the second input end of the cascaded differential amplifier unit is electrically connected to the output end of the bias current unit, the output end of the cascaded differential amplifier unit is electrically connected to the input end of the second differential amplifier circuit 12; the third input end of the cascaded differential amplifier unit is electrically connected to the output end of the second differential amplifier circuit 12.

[0058] In this embodiment, since the amplification factor of the differential amplifier circuit composed of a group of JFET field effect tubes is limited, multiple groups of JFET field effect tubes are used to form a cascade differential amplifier circuit to improve the amplification factor, and a self-biased constant current source circuit is used to provide a suitable static current for the first differential amplifier circuit, thereby ensuring the normal operation of the first differential amplifier circuit. The differential signal of the signal terminal is input to the cascade differential amplifier unit to achieve amplification of the differential signal. Since the noise of the first differential amplifier circuit composed of discrete JFET field effect tubes is very low, a clear amplified differential signal is obtained, and the clear amplified differential signal is transmitted to the second differential amplifier circuit, thereby improving the accuracy of subsequent signal processing.

[0059] In one embodiment, Figure 3 As shown, the cascaded differential amplifier unit includes a first JFET field effect transistor J1A, a second JFET field effect transistor J1B, a third JFET field effect transistor J2A, a fourth JFET field effect transistor J2B, a first bias resistor Ra and a second bias resistor Rb, wherein:

[0060] The gate of the third JFET field effect transistor J2A is electrically connected to the source of the first JFET field effect transistor J1A and the first output end of the second differential amplifier circuit 12, respectively; the drain of the third JFET field effect transistor J2A is electrically connected to the first output end of the bias current unit and the first input end of the second differential amplifier circuit 12, respectively; the source of the third JFET field effect transistor J2A is electrically connected to the drain of the first JFET field effect transistor J1A, the gate of the first JFET field effect transistor J1A is electrically connected to the first differential signal output end of the signal terminal and the first end of the first bias resistor Ra, respectively; and the second end of the first bias resistor Ra is electrically connected to the ground end of the power supply;

[0061] The gate of the fourth JFET field effect transistor J2B is electrically connected to the source of the second JFET field effect transistor J1B and the second output end of the second differential amplifier circuit 12, respectively; the drain of the fourth JFET field effect transistor J2B is electrically connected to the second output end of the bias current unit and the second input end of the second differential amplifier circuit 12, respectively; the source of the fourth JFET field effect transistor J2B is electrically connected to the drain of the second JFET field effect transistor J1B, the gate of the second JFET field effect transistor J1B is electrically connected to the second differential signal output end of the signal terminal and the first end of the second bias resistor Rb, respectively; and the second end of the second bias resistor Rb is electrically connected to the ground end of the power supply.

[0062] Specifically, Figure 3 As shown, the first bias resistor Ra and the second bias resistor Rb are two large resistors (with a value of 10MΩ) to stabilize the bias voltage of the input end. The first JFET field effect transistor J1A, the second JFET field effect transistor J1B, the third JFET field effect transistor J2A, and the fourth JFET field effect transistor J2B are two monolithic dual N-channel JFET field effect transistors, which together constitute a Cascode structure input differential pair, thereby improving the amplification factor. Since the noise of the JFET field effect transistor is low, the noise of the amplifier circuit composed of discrete devices is also low. Therefore, the first differential amplifier circuit realizes low-noise amplification of the differential input signal.

[0063] In one embodiment, Figure 3 As shown, the bias current unit includes a fifth JFET field effect transistor J3A, a sixth JFET field effect transistor J3B, a first adjustable resistor R4, a second adjustable resistor R5 and a current limiting resistor R10, wherein:

[0064] The gate of the fifth JFET field effect transistor J3A is electrically connected to the drain of the third JFET field effect transistor J2A, the first end of the first adjustable resistor R4 and the first input end of the second differential amplifier circuit 12, respectively; the drain of the fifth JFET field effect transistor J3A is electrically connected to the positive electrode of the power supply through the current limiting resistor R10; and the source of the fifth JFET field effect transistor J3A is electrically connected to the second end of the first adjustable resistor R4;

[0065] The gate of the sixth JFET field effect transistor J3B is electrically connected to the drain of the fourth JFET field effect transistor J2B, the first end of the second adjustable resistor R5 and the second input end of the second differential amplifier circuit 12, the drain of the sixth JFET field effect transistor J3B is electrically connected to the positive electrode of the power supply through the current limiting resistor R10, and the source of the sixth JFET field effect transistor J3B is electrically connected to the second end of the second adjustable resistor R5.

[0066] Specifically, the fifth JFET field effect transistor J3A and the sixth JFET field effect transistor J3B form a self-biased constant current source with adjustable ΔI to provide a bias current for the differential pair, thereby ensuring the normal operation of the cascaded differential amplifier unit.

[0067] In one embodiment, Figure 3 As shown, the second differential amplifier circuit 12 includes a first operational amplifier U1, a second operational amplifier U2, a third operational amplifier U3, a first resistor R1, a second resistor R2 and a third resistor R3, wherein:

[0068] The negative input terminal of the first operational amplifier U1 is electrically connected to the drain of the third JFET field effect transistor J2A, the first output terminal of the bias current unit, and the first terminal of the first RC phase compensation unit, respectively; the positive input terminal of the first operational amplifier U1 is electrically connected to the reference voltage; the output terminal of the first operational amplifier U1 is electrically connected to the positive input terminal of the third operational amplifier U3 and the first terminal of the third resistor R3, respectively; the second terminal of the third resistor R3 is electrically connected to the first terminal of the first resistor R1, the source of the first JFET field effect transistor J1A, and the gate of the third JFET field effect transistor J2A, respectively;

[0069] The negative input terminal of the second operational amplifier U2 is electrically connected to the drain of the fourth JFET field effect transistor J2B, the second output terminal of the bias current unit and the second end of the first RC phase compensation unit, respectively; the positive input terminal of the second operational amplifier U2 is electrically connected to the reference voltage; the output terminal of the second operational amplifier U2 is electrically connected to the negative input terminal of the third operational amplifier U3 and the first end of the second resistor R2, respectively; the second end of the second resistor R2 is electrically connected to the second end of the first resistor R1, the source of the second JFET field effect transistor J1B and the gate of the fourth JFET field effect transistor J2B, respectively; the output terminal of the third operational amplifier U3 is electrically connected to the input terminal of the receiving terminal, and the amplification factor of the third operational amplifier U3 is 1.

[0070] Specifically, Figure 3 As shown, the first operational amplifier U 1 and the second operational amplifier U 2 The potential of the non-inverting terminal is the same, so the first operational amplifier U 1 and the second operational amplifier U 2 The inverting terminal potential is also the same, so the resistor R 4 and resistor R 5 The potential of the first operational amplifier U 1 and the second operational amplifier U 2 It plays the role of potential clamp, making the DC voltage on both sides of the differential pair stable. 1 and the second operational amplifier U 2The operational amplifier used has a phase compensation circuit inside, which can prevent oscillation when the amplifier is used alone, adjust the internal signal of the circuit, and maintain the stability of the circuit. However, an external circuit with voltage gain may cause the overall operation of the circuit to be unstable. When the circuit with voltage gain is input to the operational amplifier, applying negative feedback to all of it may deteriorate the stability of the circuit or even cause oscillation. In order to ensure the stability of the entire circuit, a phase compensation circuit is required. This can be done in the third JFET field effect tube J 2A And the fourth JFET field effect transistor J 2B An RC phase compensation circuit is added between the two drains, namely the first RC phase compensation unit, which is composed of R x With C x Connected in series (R x =1kΩ, C x =330pF), the first end of the first RC phase compensation unit is electrically connected to the drain of the third JFET field effect transistor J2A, the first output end of the bias current unit and the first input end of the second differential amplifier circuit, and the second end of the first RC phase compensation unit is electrically connected to the drain of the fourth JFET field effect transistor J2B, the second output end of the bias current unit and the second input end of the second differential amplifier circuit. When the input frequency range is high, the RC phase compensation circuit can attenuate the output signal of the differential pair, so that the first operational amplifier U 1 and the second operational amplifier U 2 The input signal is attenuated, the overall gain of the circuit is reduced, and the stability of the circuit is improved.

[0071] exist Figure 3 In the circuit shown, the resistor R 6 , capacitor C 6 and resistor R 7 , capacitor C 7 As the first operational amplifier U 1 and the second operational amplifier U 2 The low-pass filter before the input of the differential pair is used to reduce the high-frequency signal flowing into the first operational amplifier U 1 and the second operational amplifier U 2 , but its cut-off frequency cannot be too low, otherwise it will limit the frequency bandwidth of the input stage amplifier circuit. As a preferred embodiment, the resistor R 6 and resistor R 7 The value is 100Ω, the capacitance C 6 and capacitor C 7 The value of 2.2nf can be used to obtain a low-pass filter with a cutoff frequency of 723kHz. The input voltage signal is input to the first operational amplifier U through the differential pair. 1 and the second operational amplifier U 2 The first operational amplifier U1 and the second operational amplifier U 2 The output signal passes through the second resistor R 2 , the third resistor R 3 Feedback to the first JFET field effect transistor J of the JFET differential pair 1A , the second JFET field effect transistor J 1B The source of the GS The size of the feedback circuit is reduced, making the net input signal smaller, forming a voltage negative feedback circuit. Since the JFET differential pair has nonlinear characteristics, the output signal is easily distorted. By introducing negative feedback, this distortion can be reduced. The transfer function of the feedback circuit decreases with the change of transistor parameters due to feedback, making the gain more stable and improving the voltage gain sensitivity of the circuit.

[0072] exist Figure 3 In the example, set the resistor R 13 =R 15 =R 14 =R 16 =1kΩ, so that the third operational amplifier U 3 The differential amplifier circuit with a gain of 1 can suppress the first operational amplifier U 1 and the second operational amplifier U 2 The common-mode signal at the output terminal simultaneously enables the first operational amplifier U 1 and the second operational amplifier U 2 The double-ended output signal becomes a single-ended output signal. Therefore, when the first operational amplifier U 1 and the second operational amplifier U 2 When the output signal contains a common-mode signal, it will be suppressed by the amplifier circuit; when the output signal is a differential-mode signal, the two differential-mode signals will be superimposed as one signal output through the amplifier circuit.

[0073] In one embodiment, when the first operational amplifier U 1 and the second operational amplifier U 2 When the gain is less than 5, it is easy to oscillate, and capacitors need to be added to keep the op amp stable.

[0074] exist Figure 3 In the input stage circuit shown in FIG. 1 , when the differential signal output terminal of the signal terminal is also the differential signal input terminal in+ and in- of the first differential amplifier circuit, a common mode signal is inputted, due to the first JFET field effect transistor J 1A And the second JFET field effect transistor J 1B The current and voltage of the two branches are constant, so the first JFET field effect tube J 1A And the second JFET field effect transistor J 1BThe source voltage of the first JFET field effect tube J changes with the input gate voltage. 1A And the second JFET field effect transistor J 1B It plays a voltage following role. At this time, the input signal is reflected in the first resistor R 1 Since the input is a common mode voltage, the first resistor R 1 No current flows through the second resistor R 2 and the third resistor R 3 The two branches are independent of each other. Therefore, the first operational amplifier U 1 and the second operational amplifier U 2 The output signal v out1 and v out2 Equal, and then through the third amplifier U 3 Amplification can be performed to eliminate common-mode signals.

[0075] When the differential signal input terminals in+ and in- input differential signals, due to the first JFET field effect transistor J 1A And the second JFET field effect transistor J 1B The voltage difference is reflected in the first resistor R 1 So the first R 1 There is a current flowing through the first resistor R 1 The current is:

[0076]

[0077] Therefore, the first operational amplifier U 1 , the second operational amplifier U 2 The voltage across the two ends can be expressed as:

[0078]

[0079] The first operational amplifier U 1 , the second operational amplifier U 2 The voltage across the two ends is input to the third operational amplifier U 3 , after differential amplification with an amplification factor of 1, a single-ended output voltage is obtained. Therefore, the differential mode voltage amplification factor of this stage is:

[0080]

[0081] Take R 2 =R 3 =1kΩ, R 1 =40Ω, it can be obtained that the differential mode voltage amplification factor of this stage is 51 times.

[0082] The theoretical value of the common-mode gain of the input stage amplifier circuit is zero. However, in reality, since the components in the circuit cannot be completely matched, it is impossible to achieve this indicator. In order to calculate the common-mode gain, it can be assumed that there is only one V at the input end. cm Common mode voltage (v + =v - =v cm ). At this time, the first resistor R 1 There is no voltage drop across the first operational amplifier U 1 , the second operational amplifier U 2 The output voltage is also equal to v cm , let the first operational amplifier U 1 , the second operational amplifier U 2 The matching is ideal, so the first operational amplifier U 1 , the second operational amplifier U 2 The common-mode voltage gain of the third operational amplifier U 3 is ideal, then the input stage common-mode gain can be obtained as follows:

[0083]

[0084] So the common-mode rejection ratio of the input stage can be calculated as:

[0085]

[0086] In the resistor network of the amplifier, due to component errors, the actual value of the resistor cannot be completely equal to the nominal value, that is, there is a mismatch in the resistor. 13 , R 14 The actual value of the resistor R 15 , R 16 The percentage of the difference is defined as the mismatch of the resistor. The denominator in the above formula can be expressed by the mismatch percentage, that is:

[0087]

[0088] From the above formula, if the four resistors are exactly equal, the denominator will be 0, and the common-mode gain will be infinite. If there is a mismatch between the four resistors, part of the common-mode voltage will be output at the output. It can be seen that any mismatch caused by the temperature drift of the resistor will reduce the CMRR of the entire amplifier circuit, so the resistors R1, R2, R3, R13, R14, R15, and R16 should be high-precision metal film resistors with good heat resistance, small resistance error, small noise coefficient, and good voltage stability.

[0089] like Figure 4As shown in Figure 1, the equivalent input noise curve of the first-stage amplifier module is shown in Figure 2. The noise characteristic of this stage is simulated, and the equivalent input noise is used to characterize the noise characteristic of the circuit. The simulation results are shown in Figure 2. Figure 4 Its equivalent input noise is 23nV / Hz at 1Hz. 0.5 , 8nV / Hz at 10Hz 0.5 , the equivalent input noise is less than 3nV / Hz between 100Hz and 100kHz 0.5 The input stage amplifier circuit is designed with low noise field effect transistors, and the equivalent input noise is 8nV / Hz at a frequency of 10Hz. 0.5 , the equivalent input noise is less than 3nV / Hz between 100Hz and 100kHz 0.5 The simulation results show that when the input stage amplifier circuit and the three-op-amp amplifier circuit have the same voltage gain, the circuit can obtain lower equivalent input noise in the frequency band from 10Hz to 100kHz.

[0090] In one embodiment, the secondary amplification module 13 includes a third differential amplification unit and a fourth operational amplifier U4, wherein:

[0091] The first input terminal of the third differential amplifier unit is electrically connected to the output terminal of the second differential amplifier circuit 12, the second input terminal of the third differential amplifier unit is electrically connected to the output terminal of the fourth operational amplifier U4, the first output terminal of the third differential amplifier unit is electrically connected to the positive input terminal of the fourth operational amplifier U4, the second output terminal of the third differential amplifier unit is electrically connected to the negative input terminal of the fourth operational amplifier U4, and the output terminal of the fourth operational amplifier U4 is also electrically connected to the input terminal of the receiving terminal.

[0092] Specifically, the output stage is a very important part of the entire amplifier design. The sensitivity of the entire system is mainly affected by the first-stage amplifier circuit. Since the input stage of the amplifier circuit has a high voltage gain and suppresses noise well, the purpose of using a second-stage amplifier circuit is mainly to increase the gain of the circuit, obtain a lower output impedance, and have the smallest possible power consumption.

[0093] In one embodiment, Figure 5 As shown, the third differential amplifier unit includes a seventh JFET field effect transistor J4A, an eighth JFET field effect transistor J4B, a fourth resistor R17, a fifth resistor R18 and a sixth resistor R20, wherein:

[0094] The gate of the seventh JFET field effect transistor J4A is electrically connected to the output end of the second differential amplifier circuit 12, the drain of the seventh JFET field effect transistor J4A is electrically connected to the positive input end of the fourth operational amplifier U4 and the first end of the fourth resistor R17 respectively, the source of the seventh JFET field effect transistor J4A is electrically connected to the negative electrode of the power supply through the sixth resistor R20; the second end of the fourth resistor R17 is electrically connected to the positive electrode of the power supply;

[0095] The gate of the eighth JFET field effect transistor J4B is electrically connected to the output end of the fourth operational amplifier U4, the drain of the eighth JFET field effect transistor J4B is electrically connected to the negative input end of the fourth operational amplifier U4 and the first end of the fifth resistor R18 respectively, the source of the eighth JFET field effect transistor J4B is electrically connected to the positive electrode of the power supply through the sixth resistor R20, and the second end of the fifth resistor R18 is electrically connected to the positive electrode of the power supply.

[0096] Specifically, the seventh JFET field effect tube J 1A 、The eighth JFET field effect tube J 4B The differential amplifier circuit of the common source amplifier structure is formed, and the output signal is transmitted through the fourth operational amplifier U 4 Output. The fourth operational amplifier U 4 With resistor R 21 A voltage negative feedback network is formed to apply voltage negative feedback from the signal output terminal to the input differential pair.

[0097] As a preferred embodiment, since the power supply voltage is higher than the V GS is much larger, so the design of the differential circuit can be based on V GS = 0 to calculate the parameters of each part of the circuit. As can be seen from the above, when the source current of the JFET field effect tube is 3mA (lower than the I DSS The appropriate value of the source resistor R 20 The value of 20 The current is 6mA (J 1A and J 1B The source current of the circuit is 3mA). The DC voltage power supply of the circuit is plus or minus 6 volts. If V G =0, then R 3 The voltage drop across is 6V, so R 20 The resistance value can be 1kΩ.

[0098] As a preferred embodiment, the drain resistor is set to a value that makes the voltage drop generated by the drain current approximately a few volts (if the voltage drop is too large, the large signal will be limited; if it is too small, it will exceed the amplifier U behind it). 3Set the drain resistance value R 17 and R 18 The drain resistor is 1kΩ, so the voltage drop across the drain resistor is 3V.

[0099] Due to the introduction of deep voltage negative feedback, the voltage gain of this stage circuit is exactly the same as the reverse amplifier circuit using an amplifier, which can be obtained by the following formula:

[0100]

[0101] Take R 21 =2KΩR 22 = 100Ω This stage can achieve a voltage amplification factor of 21 times. 21 and R 22 It determines the voltage gain of this stage, so high-precision metal film resistors with good heat resistance, small resistance error, small noise factor and good voltage stability should be selected.

[0102] In one embodiment, the third differential amplifier unit also includes a second RC phase compensation circuit, a first end of the second RC phase compensation circuit is electrically connected to the drain of the seventh JFET field effect transistor J4A, the positive input terminal of the fourth operational amplifier U4 and the first end of the fourth resistor R17, and a second end of the second RC phase compensation circuit is electrically connected to the drain of the eighth JFET field effect transistor J4B, the negative input terminal of the fourth operational amplifier U4 and the first end of the fifth resistor R18.

[0103] Specifically, to ensure the stability of the entire circuit, the fourth operational amplifier U 4 A phase compensation circuit needs to be added to the input end. An RC phase compensation circuit, namely the second RC phase compensation unit, can be added between the two drains of the seventh JFET field effect transistor J4A and the eighth JFET field effect transistor J4B. The compensation circuit consists of R 19 With C 12 Connected in series (R 19 =1KΩC 12 =330pF), the first end of the second RC phase compensation unit is electrically connected to the drain of the seventh JFET field effect tube J4A, the positive input terminal of the fourth operational amplifier U4 and the first end of the fourth resistor R17, and the second end of the second RC phase compensation unit is electrically connected to the drain of the eighth JFET field effect tube J4B, the negative input terminal of the fourth operational amplifier U4 and the first end of the fifth resistor R18. When the input frequency range is high, the RC phase compensation circuit can attenuate the output signal of the differential pair, so that the fourth operational amplifier U 4 The input signal is attenuated, the overall gain of the circuit is reduced, and the stability of the circuit is improved.

[0104] Conduct simulation analysis on the secondary amplifier module. Figure 6 The frequency characteristic curve of the secondary amplifier module is shown in Figure 2. The frequency bandwidth simulation of this stage is performed, and the amplitude of v(in) is given to be 50mV at the input end. The circuit is simulated by AC scanning, and the scanning frequency is from 1Hz to 1MHz. The voltage gain curve of this stage is obtained as follows: Figure 6 As shown. The simulation results show that the amplitude of the output signal v(out) is 1.05V, and its upper cutoff frequency is 357kHz. This shows that the output stage amplifier circuit has certain limitations on the bandwidth of the entire circuit. By simulating the two-stage amplifier circuit as a whole, it is found that the output offset voltage of the entire amplifier circuit is about 3.09mV. This bias voltage value is lower than the minimum amplitude range of the digital signal analyzer used in noise measurement. Therefore, the subsequent circuit can not use the DC offset elimination circuit, which can reduce the complexity of the entire circuit and thus reduce power consumption.

[0105] like Figure 7 As shown, Figure 7 The voltage gain of the preamplifier of this application is obtained by performing AC small signal analysis on the overall circuit diagram. The differential input terminals in+ and in- input 1mV and 2mV AC small signal differential mode voltages respectively. The scanning signal frequency starts from 1Hz and ends at 1.5MHz. Ten points are recorded every 10 times the frequency. The voltage gain characteristic curve is as follows: Figure 7 As shown. Figure 7 In the figure, the X-axis is the frequency axis of the AC scan, and the scanning range is from 1Hz to 1MHz; the Y-axis is the ratio of the output voltage to the input voltage difference, which represents the voltage gain of the circuit differential mode AC small signal. As can be seen from the figure, the small signal voltage amplification factor of this amplifier circuit is about 1071 times. When the frequency is 100kHz, the voltage gain can still be stable at 1050 times, and the upper cutoff frequency of the amplifier circuit reaches 585kHz.

[0106] like Figure 8 As shown, Figure 8 The equivalent input noise diagram of the preamplifier of this application (frequency ranges from 1Hz to 1MHz). The noise performance of the amplifier circuit can be represented by the equivalent input noise, which reflects the noise sources inside the entire amplifier circuit, such as electronic thermal noise, shot noise of semiconductor components and low-frequency noise, at the input end. The circuit is tested for equivalent input noise, and the simulation results are as follows: Figure 8 As shown. The vertical axis represents the power spectral density (PSD, in nV / Hz) of the equivalent input noise. 0.5 ).Depend on Figure 8 It can be concluded that the equivalent input noise of the amplifier circuit is only nV level within the designed operating frequency range. The equivalent input noise of the circuit is 40nV / Hz at a frequency of 1Hz. 0.5 When the frequency is increased to 10Hz, the equivalent input noise is reduced to 11nV / Hz 0.5.

[0107] like Fig. 9 As shown, Fig. 9 The equivalent input noise graph with a frequency range from 100Hz to 100kHz. The vertical axis represents the power spectral density (PSD, in nV / Hz) of the equivalent input noise. 0.5 ).Depend on Fig. 9 Can be displayed more clearly. Fig. 9 It can be obtained that when the frequency is 100Hz, the equivalent input noise is only 4.2nV / Hz 0.5 , the noise is 1.6nV / Hz when the frequency is from 10kHz to 100kHz 0.5 It shows that the high-precision and low-noise JFET differential pair is selected as the input device, and the amplifier circuit structure of the low-noise operational amplifier forming a negative feedback network can obtain excellent noise parameters.

[0108] like Fig.10 As shown, Fig.10 The output offset voltage curve of the preamplifier at room temperature for this application is shown in Figure 2. Fig.10 It can be seen from the figure that the output offset voltage of the amplifier is only about 3.09mV. The differential input structure and adjustable △I D The symmetrical constant current source bias and the use of OP amplifiers with extremely low offset voltage effectively suppress the offset voltage.

[0109] Please refer to Table 1, which is the input-output characteristic test data of the amplifier small signal. The signal source is a weak signal, and the frequency range is relatively low, so when testing the input-output characteristics, set a lower signal frequency, input a weak signal with a changing amplitude to the circuit, and test the change in the output voltage amplitude. In this test, the signal source Suin TFG6920A is used to input a sinusoidal signal with a fixed frequency of 1kHz to the circuit board, and the amplitude of the input signal is adjusted within the range of 0.5mV to 5.4mV. The oscilloscope Tektronix DPO3000 is used to test the output voltage amplitude under different input signals. The recorded data is shown in Table 1.

[0110] Table 1 Amplifier small signal input-output characteristic test data (f = 1kHz)

[0111]

[0112] like Fig.11 As shown, Fig.11 By using the test data shown in Table 1, the input-output characteristic curve of the weak signal of the amplifier is obtained by using Matlab software for curve fitting. Fig.11As shown. From the fitting curve obtained from the measured data, it can be seen that for a sinusoidal signal with a frequency of 1kHz and a peak-to-peak value in the range of 500uV to 5.4mV, the linearity of the input-output voltage is very good. This reflects that the amplifier has a good linearity in amplifying weak voltage signals between hundreds of microvolts and millivolts, meeting the design requirements.

[0113] Please refer to Table 2, which shows the frequency characteristic test data of the amplifier small signal (input voltage 2mV). When testing the frequency characteristics of the circuit, the amplitude of the signal source can be fixed and its frequency can be adjusted to test the output voltage amplitude of the amplifier circuit at different frequencies. A sinusoidal signal with a fixed amplitude of 2mV is input to the circuit through a signal generator, and the frequency of the signal is changed. The output voltage amplitude at different frequencies is tested using an oscilloscope. The test data is shown in Table 2.

[0114] Table 2 Amplifier small signal frequency characteristic test data (v in =2mV)

[0115]

[0116] like Fig.12 As shown, Fig.12 The frequency characteristic curve of the preamplifier of this application is shown in Table 2. The test data shown in Table 2 is used to perform curve fitting using Matlab software, where the Y axis is v o / v i (i.e. the gain of the amplifier), the X-axis is the frequency, and the frequency characteristic curve of the small signal amplifier is obtained as follows Fig.12 The fitting curve obtained from the amplifier frequency characteristic test data table 2 and the measured data Fig.12 It can be seen that for the amplification of a weak signal of 2mV, when the frequency is lower than 4Hz, the voltage gain is lower than 1000 times. In the frequency range of 4Hz to 160kHz, the voltage gain of the amplifier fluctuates between 1000 and 1100, and the voltage gain gradually decreases as the frequency continues to increase. There is a slight deviation between the measured voltage gain within the designed operating frequency range and the theoretical voltage gain of 1071 times. This error is mainly caused by the parameter errors and insufficient precision of the active devices and resistors used in the discrete circuit.

[0117] The above measured data and analysis show that the preamplifier of the present application has a stable amplification factor, little voltage fluctuation, and good stability within the operating frequency range, and can stably amplify weak small signals to a range that the measuring instrument can normally process.

[0118] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0119] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0120] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0121] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.

[0122] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

[0123] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.

[0124] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.

[0125] The above embodiments are only exemplary embodiments of the present application and are not intended to limit the present application. The protection scope of the present application is defined by the claims. Those skilled in the art may make various modifications or equivalent substitutions to the present application within the essence and protection scope of the present application, and such modifications or equivalent substitutions shall also be deemed to fall within the protection scope of the present application.

Claims

1. A low-noise, high-gain preamplifier, characterized in that: include: A primary amplification module and a secondary amplification module, wherein the primary amplification module includes a first differential amplification circuit and a second differential amplification circuit, wherein: The first input end of the first differential amplifier circuit is electrically connected to the differential signal output end of the signal terminal, the output end of the first differential amplifier circuit is electrically connected to the input end of the second differential amplifier circuit, the output end of the second differential amplifier circuit is electrically connected to the second input end of the first differential amplifier circuit and the input end of the secondary amplifier module respectively, and the output end of the secondary amplifier module is electrically connected to the input end of the receiving terminal, wherein the first differential amplifier circuit includes a plurality of JFET field effect transistors, and the second differential amplifier circuit includes a plurality of operational amplifiers; The first differential amplifier circuit amplifies the differential signal from the signal terminal to obtain a primary amplified differential signal, the second differential amplifier circuit amplifies the primary amplified differential signal to obtain a primary amplified voltage signal, and the secondary amplifier module amplifies the primary amplified voltage signal to obtain and output a secondary amplified voltage signal.

2. The low-noise, high-gain preamplifier according to claim 1, characterized in that: The first differential amplifier circuit includes a cascaded differential amplifier unit and a bias current unit, wherein: The first input end of the cascaded differential amplifier unit is electrically connected to the differential signal output end of the signal terminal, the second input end of the cascaded differential amplifier unit is electrically connected to the output end of the bias current unit, the output end of the cascaded differential amplifier unit is electrically connected to the input end of the second differential amplifier circuit; the third input end of the cascaded differential amplifier unit is electrically connected to the output end of the second differential amplifier circuit.

3. The low-noise, high-gain preamplifier according to claim 2, characterized in that: The cascaded differential amplifier unit includes a first JFET field effect transistor, a second JFET field effect transistor, a third JFET field effect transistor, a fourth JFET field effect transistor, a first bias resistor and a second bias resistor, wherein: The gate of the third JFET field effect transistor is electrically connected to the source of the first JFET field effect transistor and the first output end of the second differential amplifier circuit, respectively; the drain of the third JFET field effect transistor is electrically connected to the first output end of the bias current unit and the first input end of the second differential amplifier circuit, the source of the third JFET field effect transistor is electrically connected to the drain of the first JFET field effect transistor, the gate of the first JFET field effect transistor is electrically connected to the first differential signal output end of the signal terminal and the first end of the first bias resistor, respectively; and the second end of the first bias resistor is electrically connected to the ground end of the power supply; The gate of the fourth JFET field effect transistor is electrically connected to the source of the second JFET field effect transistor and the second output end of the second differential amplifier circuit, respectively; the drain of the fourth JFET field effect transistor is electrically connected to the second output end of the bias current unit and the second input end of the second differential amplifier circuit, respectively; the source of the fourth JFET field effect transistor is electrically connected to the drain of the second JFET field effect transistor, the gate of the second JFET field effect transistor is electrically connected to the second differential signal output end of the signal terminal and the first end of the second bias resistor, respectively; and the second end of the second bias resistor is electrically connected to the ground end of the power supply.

4. The low-noise, high-gain preamplifier according to claim 3, characterized in that: The bias current unit includes a fifth JFET field effect transistor, a sixth JFET field effect transistor, a first adjustable resistor, a second adjustable resistor and a current limiting resistor, wherein: The gate of the fifth JFET field effect transistor is electrically connected to the drain of the third JFET field effect transistor, the first end of the first adjustable resistor and the first input end of the second differential amplifier circuit respectively, the drain of the fifth JFET field effect transistor is electrically connected to the positive electrode of the power supply through the current limiting resistor, and the source of the fifth JFET field effect transistor is electrically connected to the second end of the first adjustable resistor; The gate of the sixth JFET field effect transistor is electrically connected to the drain of the fourth JFET field effect transistor, the first end of the second adjustable resistor and the second input end of the second differential amplifier circuit, the drain of the sixth JFET field effect transistor is electrically connected to the positive electrode of the power supply through the current limiting resistor, and the source of the sixth JFET field effect transistor is electrically connected to the second end of the second adjustable resistor.

5. The low-noise, high-gain preamplifier according to claim 3, characterized in that: The first differential amplifier circuit also includes a first RC phase compensation unit, a first end of the first RC phase compensation unit is electrically connected to the drain of the third JFET field effect transistor, the first output end of the bias current unit and the first input end of the second differential amplifier circuit, and a second end of the first RC phase compensation unit is electrically connected to the drain of the fourth JFET field effect transistor, the second output end of the bias current unit and the second input end of the second differential amplifier circuit.

6. The low-noise, high-gain preamplifier according to claim 5, characterized in that: The second differential amplifier circuit includes a first operational amplifier, a second operational amplifier, a third operational amplifier, a first resistor, a second resistor and a third resistor, wherein: The negative input terminal of the first operational amplifier is electrically connected to the drain of the third JFET field effect transistor, the first output terminal of the bias current unit and the first terminal of the first RC phase compensation unit, respectively; the positive input terminal of the first operational amplifier is electrically connected to a reference voltage; the output terminal of the first operational amplifier is electrically connected to the positive input terminal of the third operational amplifier and the first terminal of the third resistor, respectively; the second terminal of the third resistor is electrically connected to the first terminal of the first resistor, the source of the first JFET field effect transistor and the gate of the third JFET field effect transistor, respectively; The negative input terminal of the second operational amplifier is electrically connected to the drain of the fourth JFET field effect transistor, the second output terminal of the bias current unit and the second terminal of the first RC phase compensation unit respectively, the positive input terminal of the second operational amplifier is electrically connected to the reference voltage, the output terminal of the second operational amplifier is electrically connected to the negative input terminal of the third operational amplifier and the first terminal of the second resistor respectively, the second terminal of the second resistor is electrically connected to the second terminal of the first resistor, the source of the second JFET field effect transistor and the gate of the fourth JFET field effect transistor respectively; the output terminal of the third operational amplifier is electrically connected to the input terminal of the receiving terminal.

7. The low-noise, high-gain preamplifier according to claim 6, characterized in that: The amplification factor of the third operational amplifier is 1.

8. The low-noise, high-gain preamplifier according to claim 1, characterized in that: The secondary amplification module includes a third differential amplification unit and a fourth operational amplifier, wherein: The first input end of the third differential amplifier unit is electrically connected to the output end of the second differential amplifier circuit, the second input end of the third differential amplifier unit is electrically connected to the output end of the fourth operational amplifier, the first output end of the third differential amplifier unit is electrically connected to the positive input end of the fourth operational amplifier, the second output end of the third differential amplifier unit is electrically connected to the negative input end of the fourth operational amplifier, and the output end of the fourth operational amplifier is also electrically connected to the input end of the receiving terminal.

9. The low-noise, high-gain preamplifier according to claim 8, characterized in that: The third differential amplifier unit includes a seventh JFET field effect transistor, an eighth JFET field effect transistor, a fourth resistor, a fifth resistor and a sixth resistor, wherein: The gate of the seventh JFET field effect transistor is electrically connected to the output end of the second differential amplifier circuit, the drain of the seventh JFET field effect transistor is electrically connected to the positive input end of the fourth operational amplifier and the first end of the fourth resistor respectively, the source of the seventh JFET field effect transistor is electrically connected to the negative electrode of the power supply through the sixth resistor; the second end of the fourth resistor is electrically connected to the positive electrode of the power supply; The gate of the eighth JFET field effect transistor is electrically connected to the output end of the fourth operational amplifier, the drain of the eighth JFET field effect transistor is electrically connected to the negative input end of the fourth operational amplifier and the first end of the fifth resistor respectively, the source of the eighth JFET field effect transistor is electrically connected to the positive electrode of the power supply through the sixth resistor, and the second end of the fifth resistor is electrically connected to the positive electrode of the power supply.

10. The low-noise, high-gain preamplifier according to claim 9, characterized in that: The third differential amplification unit also includes a second RC phase compensation circuit, a first end of the second RC phase compensation circuit is electrically connected to the drain of the seventh JFET field effect tube, the positive input terminal of the fourth operational amplifier and the first end of the fourth resistor, and a second end of the second RC phase compensation circuit is electrically connected to the drain of the eighth JFET field effect tube, the negative input terminal of the fourth operational amplifier and the first end of the fifth resistor.

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