Two-stage bidirectional millimeter wave CMOS amplifier with enhanced output power

Abstract

The invention discloses an output power enhanced two-stage bidirectional millimeter wave CMOS amplifier. A circuit structure comprises a matching network, a driving amplification stage and a PA / LNA stage, the PA / LNA level adopts a three-stack cascode PA and cascode level LNA cross coupling structure, and in a power amplification mode, the three-stack structure realizes higher output power and output load impedance; a series capacitor is added to a grid electrode of a common-source LNA, the grid electrode of the common-source LNA and a drain electrode of a three-stack PA are isolated, a grid electrode and a source electrode of an LNA transistor are reversely biased to improve a signal coupled by a power amplification part, a threshold of the LNA transistor is started, and degradation of signal output power in a power amplification mode is avoided; in a low-noise amplification mode, the parasitic capacitance under the turn-off of the three-stack PA transistor and the Cgd of the common-source LNA generate a capacitance neutralization effect, which is beneficial to low-noise amplification and stability maintenance. The problem of compromise between output power and low noise in the bidirectional amplifier is solved, and the amplifier has excellent area efficiency and cost advantages and is suitable for bidirectional amplification application of millimeter wave frequency bands.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and in particular to a two-stage bidirectional millimeter wave CMOS amplifier with enhanced output power. Background Art

[0002] The wide range of available bandwidth in the millimeter wave band significantly increases the data transmission rate. In order to compensate for the higher free space path loss in the millimeter wave, a large-scale multi-input multi-output array is required to improve communication performance, such as signal-to-noise ratio. This array requires high power consumption and high hardware cost for transmission and reception, which are the outstanding challenges that need to be solved in its promotion and application.

[0003] A Chinese patent (CN 118399899 A) discloses a millimeter wave frequency band dual-path synthesis bidirectional amplifier, chip and electronic equipment. The single array element structure of the solution adopts the traditional front end composed of a low noise amplifier, a power amplifier and a transceiver switch, and uses a switch to control the transceiver signal. This switch control method obviously does not save any hardware cost, because the matching networks required for the unidirectional PA and LNA are independent, resulting in a large chip area occupation;

[0004] Represented by the bidirectional amplifier in the above patent, the prior art uses an area-sharing efficiency improvement technology, that is, the transformers of the transmitter amplifier and the receiver amplifier are nested, one is a conventional ring design, and the other is an 8-shaped structure. When the two are embedded together, isolation can be obtained between transmission and reception, because of the cancellation of the magnetic flux between the 8-shaped inductor and the conventional ring inductor. The advantage of this solution is that it saves the layout area occupied by a single array element. However, the disadvantages are also obvious. The magnetic flux cannot be ideally eliminated due to process deviations, and the resulting signal leakage from the PA signal to the receiving side is bound to affect the performance of the LNA. In addition, the low Q value problem of the 8-shaped inductor will also deteriorate the efficiency or noise performance of the amplifier;

[0005] Therefore, through the bidirectional amplifier proposed in the above technical solution, the prior art utilizes the bidirectional amplification work to be controlled by the timing switch. When the PA of the transmitter is working, the LNA is in the off state, and vice versa. In particular, the passive matching network in the above technical solution is used for transmission and reception sharing, and adopts a conventional toroidal inductor transformer structure. There is no problem of magnetic flux cancellation leakage, which makes the overall structure area simple and advantageous. However, it should be noted that the PA and LNA of the above structure are exactly the same size, and both are differential common source level structures. This is obviously not an optimized power amplifier and low noise device size selection and topology design. It is also not difficult to see that the optimal output impedance required in the power amplification mode is usually greatly different from the noise optimized source impedance in the low noise amplification mode in most cases. This makes the structure either sacrifice output power to take care of low noise. On the contrary, the output power is increased, but the noise is paid. Therefore, the structure has a serious compromise problem in transceiver performance, which limits its application value.

[0006] Based on the above discussion, it is urgent to propose a new solution to achieve low-cost area of ​​a single element of the MIMO array and avoid the compromise design of noise and power between bidirectional amplifiers as much as possible. To this end, the present application provides a two-stage bidirectional amplifier structure, and through the topology of a three-stacked PA and a common source LNA cross-coupled, the compromise relationship between output power in the power amplification mode and NF in the low-noise amplification mode is effectively alleviated. The passive transformer network is a conventional shared structure, which makes the circuit have better area efficiency. Summary of the invention

[0007] The present invention discloses a two-stage bidirectional millimeter wave CMOS amplifier with enhanced output power, wherein the circuit structure of the two-stage bidirectional millimeter wave CMOS amplifier comprises a matching network, a driving amplifier stage, and a PA / LNA stage;

[0008] The matching network includes a left port matching network, a right port matching network and an inter-stage matching network; the left end of the left port matching network is provided with a port Port1, and the right end is provided with a differential port; the left end of the right port matching network is provided with a port differential port, and the right end is provided with a port Port2; and the two ends of the inter-stage matching network are provided with differential ports;

[0009] The driver amplifier stage is provided with ports a and a′ on the left side and ports b and b′ on the right side;

[0010] The PA / LNA stage is provided with ports c and c′ on the left side and ports d and d′ on the right side;

[0011] The differential port at the right end of the left port matching network is connected to the ports a and a′ on the left side of the driver amplifier stage; the ports b and b′ on the right side of the driver amplifier stage are connected to the differential ports on one side of the inter-stage matching network; the differential port on the other side of the inter-stage matching network is connected to the ports c and c′ on the left side of the PA / LNA stage; the ports d and d′ on the right side of the PA / LNA stage are connected to the differential ports of the right port matching network; the above structure forms a two-stage bidirectional millimeter-wave CMOS amplifier circuit structure;

[0012] The PA / LNA stage adopts a cross-coupling structure of three stacked PAs and a common source LNA;

[0013] The left-port matching network in the matching network adopts transformer TR1, the right-port matching network adopts transformer TR2, and the inter-stage matching network adopts transformer TR3; the transformers in the matching network adopt a coupling structure; the transformer TR1 of the left-port matching network includes ports a1, b1, c1, d1, and e1; the transformer TR2 of the inter-stage matching network includes ports a2, b2, c2, d2, e2, and f2; the transformer TR3 of the right-port matching network includes ports a3, b3, c3, d3, and e3.

[0014] Preferably, the driving amplifier stage is based on a common source stage structure, and the driving amplifier stage includes a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, an NMOS tube M14, an NMOS tube M15, an NMOS tube M16, an NMOS tube M17, an NMOS tube M18, an NMOS tube M19, an NMOS tube M20, an NMOS tube M30, an NMOS tube M40, an NMOS tube M51, an NMOS tube M6 10 、PMOS tube M 11 、PMOS tube M 12 、PMOS tube M 13 、PMOS tube M 14 , bias voltage V G , bias voltage V G1 , bias voltage V TRX , bias voltage Resistor R1, resistor R2, power supply voltage VDD 1V ;

[0015] The port a of the driving amplifier stage is formed by connecting the source of the NMOS tube M3, the gate of the NMOS tube M6 and the drain of the NMOS tube M9, and is connected to the d1 port of the transformer TR1; the port a′ is formed by connecting the source of the NMOS tube M4, the gate of the NMOS tube M7 and the drain of the NMOS tube M8, and is connected to the c1 port of the transformer TR1;

[0016] The port b of the driver amplifier stage is composed of a PMOS tube M 11The source of the NMOS tube M6 is connected to the drain of the NMOS tube M8 and the gate of the NMOS tube M8, and is connected to the a2 port of the transformer TR2; the port b' is formed by the PMOS tube M 12 The source of the PMOS tube M1 is connected to the drain of the NMOS tube M7 and the gate of the NMOS tube M9, and connected to the port b of the transformer TR2; the source of the PMOS tube M1 is connected to the bias voltage V G The gate of the PMOS tube M1 is connected to the bias voltage The drain of the PMOS tube M1 is connected to the drain of the PMOS tube M2 and connected to the e1 port of the transformer TR1; the source of the PMOS tube M2 is connected to the power supply voltage VDD 1V The gate of the PMOS tube M1 is connected to the bias voltage V TRX The gate of the NMOS tube M3 is connected to the bias voltage V G1 The drain of the NMOS tube M3 is connected to one end of the resistor R1, the drain of the NMOS tube M4 is connected to the other end of the resistor R1, and the gate of the NMOS tube M4 is connected to the bias voltage V G1 The source of the NMOS tube M6 is connected to the drain of the NMOS tube M5 and the source of the NMOS tube M7, the source of the NMOS tube M5 is grounded, and the gate of the NMOS tube M5 is connected to the bias voltage V TRX The source of the NMOS tube M8 is connected to the NMOS tube M 10 The drain of the NMOS tube M9 is connected to the source of the NMOS tube M9. 10 The source of the NMOS tube M is grounded. 10 The gate bias voltage The PMOS tube M 11 The gate bias voltage The PMOS tube M 11 The drain of the PMOS tube M is connected to one end of the resistor R2. 12 The drain of the PMOS tube M is connected to the other end of the resistor R2. 12 The gate bias voltage The PMOS tube M 13 The source is connected to the bias voltage V G , the PMOS tube M 13 The gate is connected to the bias voltage V TRX , the PMOS tube M 13 The drain of the PMOS tube M 14 The drain of the PMOS tube M is connected to the e2 port of the transformer TR2. 14 The source is connected to the power supply voltage VDD 1V , the PMOS tube M 14 The gate bias voltage

[0017] Preferably, the PA / LNA stage is mainly composed of three stacked common source and common gate PAs and a common source LNA with source degeneration inductance; the PA / LNA stage includes a PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 、NMOS tube M 19 、NMOS tube M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 28 、PMOS tube M 29 , bias voltage V G , bias voltage V G1 , bias voltage V G2 , bias voltage V G3 , bias voltage V TRX , bias voltage Resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, power supply voltage VDD 1V , capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, inductor L1, inductor L2;

[0018] The PA / LNA stage port c is composed of a PMOS transistor M 17 The source of NMOS tube M 20 The gate and NMOS tube M 27 The drain of the PA / LNA stage is connected to the drain of the transformer TR2 and connected to the d2 port of the transformer TR2; the port c′ of the PA / LNA stage is composed of a PMOS tube M 18 The source of NMOS tube M 21 The gate and NMOS tube M 26 The drain of the PA / LNA stage is connected to the drain of the transformer TR2, and the port d ... 24 The drain of the PA / LNA stage is connected to the drain of the transformer TR3, and the port d′ ... 25 The drain of the transformer TR3 is connected to the b3 terminal;

[0019] The PMOS tube M 15The source is connected to the bias voltage V G , the PMOS tube M 15 The gate bias voltage The PMOS tube M 15 The drain of the PMOS tube M 16 The drain of the PMOS tube M is connected to the f2 port of the transformer TR2. 16 The source is connected to the power supply voltage VDD 1V , the PMOS tube M 16 The gate is connected to the bias voltage V TRX , the PMOS tube M 17 The gate is connected to the bias voltage V TRX , the PMOS tube M 17 The drain of the PMOS tube M is connected to one end of the capacitor C2. 18 The drain of the PMOS tube M is connected to the other end of the capacitor C2. 18 The gate bias voltage The NMOS tube M 20 The source of NMOS tube M 21 The source and NMOS tube M 19 The drain of the NMOS tube M 20 The drain of NMOS tube M 22 The source of the NMOS tube M 21 The drain of NMOS tube M 23 The source of the NMOS tube M 22 The gate of the NMOS tube M is connected to one end of the resistor R3 and one end of the capacitor C3. 23 The gate is connected to one end of the resistor R4 and one end of the capacitor C4, and the other end of the resistor R3 and the other end of the resistor R4 are connected to the bias voltage V G1 The other end of the capacitor C3 and the other end of the capacitor C4 are grounded, and the NMOS tube M 22 The drain of NMOS tube M 24 The source of the NMOS tube M 23 The drain of NMOS tube M 25 The source of the NMOS tube M 24 The gate of the NMOS tube M is connected to one end of the resistor R5 and one end of the capacitor C5. 25 The gate is connected to one end of the resistor R6 and one end of the capacitor C6, and the other end of the resistor R5 and the other end of the resistor R6 are connected to the bias voltage V G2 The other end of the capacitor C5 and the other end of the capacitor C6 are grounded, and the other end of the capacitor C7 is connected to one end of the resistor R7 and the NMOS tube M 26The gate of the capacitor C8 is connected to one end of the resistor R8 and the NMOS tube M 27 The gate of the resistor R7 and the other end of the resistor R8 are connected to the bias voltage V G3 , the NMOS tube M 26 The source of the NMOS tube M is connected to one end of the inductor L1. 27 The source of the inductor L1 is connected to one end of the inductor L2, and the other end of the inductor L1 is connected to the other end of the inductor L2 and the NMOS tube M 28 The drain and PMOS tube M 29 The drain of the NMOS tube M 28 The source of the NMOS tube M is grounded. 28 The gate bias voltage The PMOS tube M 29 The source is connected to the power supply voltage V G , the PMOS tube M 29 The gate bias voltage

[0020] Compared with the prior art, the technical solution of this application has the following technical effects:

[0021] The present invention adopts a cross-coupling structure of a three-stacked common-source common-gate PA and a differential common-source LNA inductive degeneration structure, so that the optimized load impedance of the power amplifier is close to the optimized noise source impedance of the low-noise amplifier, resulting in both output power enhancement and low noise design being taken into account.

[0022] The present invention isolates the gate of the common source LNA and the drain of the three-stack PA by adding a series capacitor at the gate of the common source LNA. The gate source of the common source LNA transistor is reverse biased, so that the PA large signal leaks in and the threshold of turning on the LNA is increased, thereby avoiding the degradation of output power in the power amplification mode.

[0023] The passive matching network of the circuit of the present invention is a bidirectional amplifier sharing multiplexing structure, which occupies a small area and has low cost.

[0024] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application so that it can be implemented in accordance with the contents of the specification, and to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following is a detailed description of the preferred embodiments of the present application in conjunction with the accompanying drawings as follows.

[0025] Based on the detailed description of the specific embodiments of the present application in combination with the accompanying drawings below, those skilled in the art will become more aware of the above and other objects, advantages and features of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.

[0027] Figure 1 It is a structural schematic diagram of the present invention;

[0028] Figure 2 A circuit diagram of a three-stack two-stage bidirectional amplifier of the present invention;

[0029] Figure 3 is a circuit diagram of the present invention in a power amplification mode;

[0030] Figure 4 is a circuit diagram of the present invention in a low-noise amplification mode;

[0031] Figure 5 It is a schematic diagram of S parameters of the present invention in the power amplification mode;

[0032] Figure 6 The output power P of the present invention in the power amplification mode sat and linearity OP 1dB Schematic diagram;

[0033] Figure 7 It is a schematic diagram of the efficiency PAE of the present invention in the power amplification mode;

[0034] Figure 8 It is a schematic diagram of S parameters of the present invention in the low noise amplification mode;

[0035] Fig. 9 A schematic diagram of the noise coefficient NF in the low noise amplification mode of the present invention;

[0036] Fig.10 The linearity IP of the present invention in the low noise amplification mode is 1dB and IIP3 schematic diagram. DETAILED DESCRIPTION

[0037] To make the purpose, technical scheme and advantages of the embodiment of the present application clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present application. Obviously, the described embodiment is a part of the embodiment of the present application, rather than all of the embodiments. In the following description, specific details such as specific configuration and components are provided only to help fully understand the embodiments of the present application. Therefore, it should be clear to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, for clarity and brevity, the description of known functions and structures is omitted in the embodiment.

[0038] It should be understood that the references to "one embodiment" or "this embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "one embodiment" or "this embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0039] In addition, the present application may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0040] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" in this article describes another type of association object relationship, indicating that there can be two relationships. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0041] The term "at least one" in this article is merely a description of the association relationship of associated objects, indicating that there may be three relationships. For example, at least one of A and B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0042] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusions.

[0043] Example 1

[0044] This embodiment mainly describes a two-stage bidirectional millimeter-wave CMOS amplifier with enhanced output power, such as Figure 1 As shown, the two-stage bidirectional millimeter wave CMOS amplifier circuit structure includes a matching network, a driver amplifier stage, and a PA / LNA stage;

[0045] The matching network includes a left port matching network, a right port matching network and an inter-stage matching network; the left end of the left port matching network is set with port Port1, and the right end is set with a differential port; the left end of the right port matching network is set with a port differential port, and the right end is set with port Port2; differential ports are set at both ends of the inter-stage matching network;

[0046] Ports a and a′ are arranged on the left side of the driver amplifier stage, and ports b and b′ are arranged on the right side;

[0047] Ports c and c′ are provided on the left side of the PA / LNA stage, and ports d and d′ are provided on the right side;

[0048] The differential port at the right end of the left port matching network is connected to the ports a and a′ on the left side of the driver amplifier stage; the ports b and b′ on the right side of the driver amplifier stage are connected to the differential ports on one side of the inter-stage matching network; the differential port on the other side of the inter-stage matching network is connected to the ports c and c′ on the left side of the PA / LNA stage; the ports d and d′ on the right side of the PA / LNA stage are connected to the differential ports of the right port matching network; the above structure forms a two-stage bidirectional millimeter wave CMOS amplifier circuit structure;

[0049] The PA / LNA stage uses a three-stack PA and a common-source LNA cross-coupled structure;

[0050] The left-port matching network in the matching network adopts transformer TR1, the right-port matching network adopts transformer TR2, and the inter-stage matching network adopts transformer TR3; the transformer in the matching network adopts a coupling structure; the transformer TR1 of the left-port matching network includes ports a1, b1, c1, d1, and e1; the transformer TR2 of the inter-stage matching network includes ports a2, b2, c2, d2, e2, and f2; the transformer TR3 of the right-port matching network includes ports a3, b3, c3, d3, and e3.

[0051] Furthermore, the driving amplifier stage is based on a common source stage structure, and the driving amplifier stage includes a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, an NMOS tube M13, an NMOS tube M14, an NMOS tube M15, an NMOS tube M16, an NMOS tube M17, an NMOS tube M18, an NMOS tube M19, an NMOS tube M20, an NMOS tube M30, an NMOS tube M40, an NMOS tube M51, an NMOS tube M6 10 、PMOS tube M 11 、PMOS tube M 12 、PMOS tube M 13 、PMOS tube M 14 , bias voltage V G, bias voltage V G1 , bias voltage V TRX , bias voltage Resistor R1, resistor R2, power supply voltage VDD 1V ;

[0052] The port a of the driving amplifier stage is formed by connecting the source of the NMOS tube M3, the gate of the NMOS tube M6 and the drain of the NMOS tube M9, and is connected to the d1 port of the transformer TR1; the port a′ is formed by connecting the source of the NMOS tube M4, the gate of the NMOS tube M7 and the drain of the NMOS tube M8, and is connected to the c1 port of the transformer TR1;

[0053] The port b of the driving amplifier stage is composed of a PMOS tube M 11 The source of the NMOS tube M6 is connected to the drain of the NMOS tube M8 and the gate of the NMOS tube M8, and is connected to the a2 port of the transformer TR2; the port b' is connected to the PMOS tube M 12 The source of the PMOS tube M1 is connected to the drain of the NMOS tube M7 and the gate of the NMOS tube M9, and connected to the b port of the transformer TR2; the source of the PMOS tube M1 is connected to the bias voltage V G , the gate of PMOS tube M1 is connected to the bias voltage The drain of the PMOS tube M1 is connected to the drain of the PMOS tube M2 and connected to the e1 port of the transformer TR1; the source of the PMOS tube M2 is connected to the power supply voltage VDD 1V , the gate of PMOS tube M1 is connected to the bias voltage V TRX , the gate of NMOS tube M3 is connected to the bias voltage V G1 The drain of NMOS tube M3 is connected to one end of resistor R1, the drain of NMOS tube M4 is connected to the other end of resistor R1, and the gate of NMOS tube M4 is connected to bias voltage V G1 The source of NMOS tube M6 is connected to the drain of NMOS tube M5 and the source of NMOS tube M7, the source of NMOS tube M5 is grounded, and the gate of NMOS tube M5 is connected to the bias voltage V TRX , the source of NMOS tube M8 and NMOS tube M 10 The drain of the NMOS tube M9 is connected to the source of the NMOS tube M9. 10 The source of NMOS tube M is grounded. 10 The gate bias voltage PMOS tube M 11 The gate bias voltage PMOS tube M 11 The drain of the PMOS tube M is connected to one end of the resistor R2. 12 The drain of the PMOS tube M is connected to the other end of the resistor R2. 12 The gate bias voltage PMOS tube M 13 The source is connected to the bias voltage V G , PMOS tube M 13 The gate is connected to the bias voltage V TRX , PMOS tube M 13 The drain of the PMOS tube M 14 The drain of the PMOS tube M is connected to the e2 port of the transformer TR2. 14 The source is connected to the power supply voltage VDD 1V , PMOS tube M 14 The gate bias voltage

[0054] Furthermore, the PA / LNA stage is mainly composed of a three-stacked common-source common-gate PA and a common-source LNA with a source degeneration inductor; the PA / LNA stage includes a PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 、NMOS tube M 19 、NMOS tube M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 28 、PMOS tube M 29 , bias voltage V G , bias voltage V G1 , bias voltage V G2 , bias voltage V G3 , bias voltage V TRX , bias voltage Resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, power supply voltage VDD 1V , capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, inductor L1, inductor L2;

[0055] The port c of PA / LNA stage is composed of PMOS tube M 17 The source of NMOS tube M 20 The gate and NMOS tube M 27 The drain of the PA / LNA stage is connected to the drain of the transformer TR2 and connected to the d2 port of the transformer TR2; the port c′ of the PA / LNA stage is composed of a PMOS tube M 18 The source of NMOS tube M 21The gate and NMOS tube M 26 The drain of the PA / LNA stage is connected to the drain of the transformer TR2, and the port d .... 24 The drain of the PA / LNA stage is connected to the drain of the transformer TR3, and the port d' ... 25 The drain of the transformer TR3 is connected to the b3 terminal;

[0056] PMOS tube M 15 The source is connected to the bias voltage V G , PMOS tube M 15 The gate bias voltage PMOS tube M 15 The drain of the PMOS tube M 16 The drain of the PMOS tube M is connected to the f2 port of the transformer TR2. 16 The source is connected to the power supply voltage VDD 1V , PMOS tube M 16 The gate is connected to the bias voltage V TRX , PMOS tube M 17 The gate is connected to the bias voltage V TRX , PMOS tube M 17 The drain of PMOS tube M is connected to one end of capacitor C2. 18 The drain of the PMOS tube M is connected to the other end of the capacitor C2. 18 The gate bias voltage NMOS tube M 20 The source of NMOS tube M 21 The source and NMOS tube M 19 The drain connection of NMOS tube M 20 The drain of NMOS tube M 22 The source of NMOS tube M 21 The drain of NMOS tube M 23 The source of NMOS tube M 22 The gate of the NMOS tube M is connected to one end of the resistor R3 and one end of the capacitor C3. 23 The gate is connected to one end of the resistor R4 and one end of the capacitor C4, and the other end of the resistor R3 and the other end of the resistor R4 are connected to the bias voltage V G1 , the other end of capacitor C3 and the other end of capacitor C4 are grounded, and NMOS tube M 22 The drain of NMOS tube M 24 The source of NMOS tube M 23 The drain of NMOS tube M 25 The source of NMOS tube M 24The gate of the NMOS tube M is connected to one end of the resistor R5 and one end of the capacitor C5. 25 The gate is connected to one end of the resistor R6 and one end of the capacitor C6, and the other end of the resistor R5 and the other end of the resistor R6 are connected to the bias voltage V G2 The other end of capacitor C5 and the other end of capacitor C6 are grounded, and the other end of capacitor C7 is connected to one end of resistor R7 and NMOS tube M 26 The gate of the capacitor C8 is connected to one end of the resistor R8 and the NMOS tube M 27 The gate of the resistor R7 and the other end of the resistor R8 are connected to the bias voltage V G3 , NMOS tube M 26 The source of is connected to one end of the inductor L1, and the NMOS tube M 27 The source of the inductor L1 is connected to one end of the inductor L2, and the other end of the inductor L1 is connected to the other end of the inductor L2 and the NMOS tube M 28 The drain and PMOS tube M 29 The drain connection of NMOS tube M 28 The source of NMOS tube M is grounded. 28 The gate bias voltage PMOS tube M 29 The source is connected to the power supply voltage V G , PMOS tube M 29 The gate bias voltage

[0057] This embodiment effectively eases the trade-off between output power in power amplification mode and NF in low noise amplification mode through a topology structure of a three-stack PA and a common source LNA cross-coupled. The passive transformer network is a conventional shared structure, so that the circuit has good area efficiency.

[0058] Example 2

[0059] This embodiment is based on Embodiment 1 and describes in detail an optimization solution for a two-stage bidirectional millimeter-wave CMOS amplifier with enhanced output power, specifically including:

[0060] like Figure 2 As shown, a complete circuit structure diagram is given. The circuit uses a switch control method to complete the bidirectional signal amplification enable and shutdown of transmission and reception;

[0061] like Figure 3 As shown, in PA transmit mode, the level control signal is set to: V TRX =1V, V G =0.75V, V G1 =1.7V, V G2 =2.7V, V G3=0V, in the driver amplifier, the PMOS tube M 2，13 and NMOS tube M 8，9，10 The remaining MOS tubes are turned on, and in PA, the PMOS tube M 16～18 and NMOS tube M 26～29 The RF signal is input from the single-ended port Port1, and firstly passes through the transformer TR1, the signal is converted into a differential signal, and then input into the differential common source drive amplifier with tail current source, where the amplifier tube is NMOS tube M. 6，7 .

[0062] Cut-off transistor M 8，9 The parasitic capacitance C gd , M 6，7 With M 8，9 The equal-size design and cross-coupling connection make M 8，9 C gd Put M 6，7 The corresponding parasitic effects are neutralized, thereby improving the stability of the emission direction of the driver stage and the amplification ability.

[0063] NMOS tube M 3，4 And PMOS tube M 11，12 As switches, the resistors R1 and R2 are controlled to be turned on respectively to achieve better matching performance.

[0064] After the signal is amplified, it is further coupled to the PA by transformer TR2, where the amplifier tube is NMOS tube M 20～25 , also with differential input, but the three-stacked common source and common gate structure can significantly improve the signal output power and gain. At the same time, adjusting the stacked transistor gate capacitance C 3～6 , the source impedance of the cascode can be equivalently changed, and finally the drain-source swing of the cascode transistor is made consistent, saving more voltage swing space for the load end.

[0065] In addition, a series capacitor C is added at the gate of the common source LNA. 7，8 , isolating the gate of the common-source LNA and the drain of the three-stack PA. 26，27 The gate and source voltages are 0V and 0.75V respectively. This reverse bias setting helps to avoid the power amplifier signal from passing through the coupling capacitor to M 26，27 The differential signal output by the PA is converted into a single-ended signal through the transformer TR3, and then passes through the NMOS tube M 30 The impedance adjustment network composed of the switch and capacitor C9 (to fine-tune the load impedance of the power amplifier) ​​is connected to port 2 to achieve power enhancement output and efficiency improvement in the power amplifier mode;

[0066] like Figure 4 As shown, in LNA receiving mode, the level control signal is set to: V TRX =0V, V G =0.75V, V G1 =1V, V G2 =2V, V G3 =0.75V, in the driver amplifier, the PMOS tube M 1，14 and NMOS tube M 5～7 The remaining MOS tubes are turned on, and in the LNA, the PMOS tube M 15 and NMOS tube M 19～25，30 Cut off, and the other MOS tubes are turned on.

[0067] The RF signal is input from port Port2 at a single end, and first passes through transformer TR3, where the signal is converted into a differential signal and then input into the differential common source LNA with source degeneration inductance. 26，27 For the amplifier tube, PMOS tube M 29 and NMOS tube M 28 The voltage at the right end of the control inductor L1 and L2 is 0V reference ground. 17，18 As a switch to control the capacitor C2 to conduct, it is also to achieve better matching performance. After the signal is amplified, it is coupled and transmitted to the driver amplifier by transformer TR2. At this time, the NMOS tube M 8，9 The signal is further amplified by the transformer TR1, which converts the differential signal into a single-ended signal and outputs it from port Port1. In the low-noise amplification mode, the parasitic capacitance of the three-stack PA is still roughly equivalent to the C of the common-source LNA. gd , similar to the capacitor technology used in the driver stage above, it is still applicable here, which is beneficial to the stability and amplification ability of the LNA; at the same time, V G1 =1V, V G2 =2V, VDD 3V =3V, so when the three-stack PA transistor is turned off, the M 24 Drain to M 20 The equivalent parasitic capacitance of the gate has a higher Q value than the conventional single common source structure, which is conducive to achieving a smaller NF min .

[0068] The PA / LNA of the present invention adopts different transistor sizes. Compared with the traditional single common source stage structure, the PA here adopts a three-stack structure, which provides higher output power with appropriate transistor size and is not highly dependent on negative resistance impedance. In order to provide high power, the traditional single common source power amplifier requires a proportionally reduced load impedance and a large transistor size. In short, in the power amplification mode, the three-stack structure of the present application achieves higher output power and a moderate load impedance, which is conducive to connecting the noise impedance required by the low noise amplifier. In addition, the NMOS tube M 30 The impedance adjustment network composed of the switch and capacitor C9 plays a role in fine-tuning the load impedance of the power amplifier. At this time, the simulation at 30GHz shows that the normalized optimal load impedance Z load The center of the optimized value is 0.34+0.5j;

[0069] In addition, degeneration inductors L1 and L2 are added to the LNA source for impedance matching and noise matching. At this time, the simulation at 30GHz shows that the normalized noise source impedance Z source The center of the optimized value position is 0.28+0.6j, because Z load , Z source The two impedances are relatively close and are both in the direction of port 2, so the compromise problem between the transmission power of the power amplifier and the low noise design of the low noise amplifier in the traditional bidirectional amplifier is solved here.

[0070] The three-stack structure of this embodiment achieves higher output power and a moderate load impedance, which is conducive to connecting the noise impedance required by the low-noise amplifier, and at the same time solves the compromise problem between the transmission power of the power amplifier and the low-noise design of the low-noise amplifier in the traditional bidirectional amplifier.

[0071] Example 3

[0072] This embodiment is based on Embodiment 1 and describes in detail the comparative effect of a two-stage bidirectional millimeter-wave CMOS amplifier with enhanced output power, specifically including:

[0073] The circuit of the present invention is simulated to verify its performance. The circuit is designed and implemented using a 28nm CMOS process. The circuit parameters are shown in Table 1, where * power amplification mode / low noise amplification mode;

[0074] Table 1 Circuit parameters

[0075]

[0076] In power amplifier mode, the power supply voltage VDD PA =3V, the operating frequency can cover 27.3-35.4GHz, achieving 17.3dBm saturated output power and 15.2dBm output 1dB compression point OP 1dB , peak efficiency PAEpeak PAE is 15.9% 1dB 9%;

[0077] At the same time, in the low noise amplifier mode, the power supply voltage VDD LNA =1V, the operating frequency can cover 28-36GHz, the overall power consumption of the circuit is 63mW, and it maintains 5.3dB NF and -3dBm IIP3.

[0078] like Figure 5 As shown in the figure, the S parameter simulation results of the present invention in the power amplification mode are as follows: 11 All less than -10dB, S 21 All are greater than 17dB, with a maximum value of 20.4dB, S 22 All less than -2dB, S 12 All less than -57dB;

[0079] like Figure 6 As shown, the output power P of the present invention in the power amplification mode is given. sat and linearity OP 1dB The simulation results show that in the frequency band of 27.3-35.4GHz, P sat All are greater than 16.3dBm, with a maximum of 17.3dBm, while OP 1dB All are greater than 12.6dBm, with a maximum of 15.2dBm;

[0080] like Figure 7 As shown in the figure, the efficiency PAE simulation results of the present invention in the power amplification mode are given. In the frequency band range of 27.3-35.4GHz, PAE peak All are greater than 12.5%, with a maximum of 15.9%, while PAE 1dB All are greater than 6.4%, with the maximum value being 9%;

[0081] like Figure 8 As shown in the figure, the S parameter simulation results of the present invention in the low noise amplification mode are given. In the frequency band range of 28-36GHz, S 11 All less than -10dB, S 21 All are greater than 10dB, with a maximum value of 17.3dB, S 22 Less than -4dB, S 12 All less than -54dB;

[0082] like Fig. 9 As shown, the simulation results of the noise factor NF of the present invention in the low noise amplification mode are given, and the lowest NF is 5.3dB in the frequency band range of 28-36GHz;

[0083] like Fig.10As shown, the linearity IP of the present invention in the low noise amplification mode is given. 1dB The simulation results of IIP3 and IP in the frequency band of 28-36GHz 1dB Greater than -10.2dBm, IIP3 greater than -3dBm.

[0084] Since the PA-LNA of the present invention adopts a three-stack PA and a common source LNA cross-coupling structure, and there is no compromise between the transmit power and the receive noise, and switch resistors and capacitors are added to improve the matching performance, the present invention has significant advantages in output power and efficiency. As can be seen from the following Table 2, * is the power amplification mode / low noise amplification mode;

[0085] Table 2 Parameter performance comparison

[0086]

[0087] The prior art in Table 2 is the data recorded in Cheng Depen et al. Design of an Ultra-Compact 60-GHz Bi-Directional Amplifier in 65-nm CMOS[J]. IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2022, 32(4): 343-346.

[0088] It can be seen from the above table that the noise coefficient of the present invention is better than that of the prior art, making the present invention an advantageous solution for bidirectional high output power PA-LNA applied in the millimeter wave frequency band.

[0089] The above are only preferred embodiments of the present invention, which do not limit the scope of protection of the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any changes, modifications, replacements, integrations and parameter changes to these embodiments within the spirit and principles of the present invention through conventional substitutions or without departing from the principles and spirit of the present invention fall within the scope of protection of the present invention.

Claims

1. A two-stage bidirectional millimeter-wave CMOS amplifier with enhanced output power, characterized in that: The two-stage bidirectional millimeter wave CMOS amplifier circuit structure includes a matching network, a driver amplifier stage, and a PA / LNA stage; The matching network includes a left port matching network, a right port matching network and an inter-stage matching network; the left end of the left port matching network is provided with a port Port1, and the right end is provided with a differential port; the left end of the right port matching network is provided with a port differential port, and the right end is provided with a port Port2; and the two ends of the inter-stage matching network are provided with differential ports; The left side of the driver amplifier stage is provided with ports a and a ′ , set ports b and b on the right ′ ; The PA / LNA stage has ports c and c on the left side. ′ , set ports d and d on the right ′ ; The differential port on the right end of the left port matching network is connected to the ports a and a on the left side of the driver amplifier stage. ′ Connect the right side ports b and b of the driver amplifier stage ′ The other side differential port of the interstage matching network is connected to the left side ports c and c of the PA / LNA stage. ′ Connect the right side ports d and d of the PA / LNA stage ′ Connected to the differential port of the right port matching network; the above structure forms a two-stage bidirectional millimeter wave CMOS amplifier circuit structure; The PA / LNA stage adopts a cross-coupling structure of three stacked PAs and a common source LNA; The left-port matching network in the matching network adopts transformer TR1, the right-port matching network adopts transformer TR2, and the inter-stage matching network adopts transformer TR3; the transformers in the matching network adopt a coupling structure; the transformer TR1 of the left-port matching network includes ports a1, b1, c1, d1, and e1; the transformer TR2 of the inter-stage matching network includes ports a2, b2, c2, d2, e2, and f2; the transformer TR3 of the right-port matching network includes ports a3, b3, c3, d3, and e3.

2. The two-stage bidirectional millimeter-wave CMOS amplifier with enhanced output power according to claim 1, characterized in that: The driving amplifier stage is based on a common source stage structure, and the driving amplifier stage includes a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M 10 、PMOS tube M 11 、PMOS tube M 12 、PMOS tube M 13 、PMOS tube M 14 , bias voltage V G , bias voltage V G1 , bias voltage V TRX , bias voltage Resistor R1, resistor R2, power supply voltage VDD 1V ; The port a of the driving amplifier stage is formed by connecting the source of the NMOS tube M3, the gate of the NMOS tube M6 and the drain of the NMOS tube M9, and is connected to the d1 port of the transformer TR1; the port a ′ The source of the NMOS tube M4 is connected to the gate of the NMOS tube M7 and the drain of the NMOS tube M8, and is connected to the c1 port of the transformer TR1; The port b of the driver amplifier stage is composed of a PMOS tube M 11 The source of the NMOS tube M6 is connected to the drain of the NMOS tube M8 and the gate of the NMOS tube M8, and is connected to the a2 port of the transformer TR2; the port b' is formed by the PMOS tube M 12 The source of the PMOS tube M1 is connected to the drain of the NMOS tube M7 and the gate of the NMOS tube M9, and connected to the port b of the transformer TR2; the source of the PMOS tube M1 is connected to the bias voltage V G The gate of the PMOS tube M1 is connected to the bias voltage The drain of the PMOS tube M1 is connected to the drain of the PMOS tube M2 and connected to the e1 port of the transformer TR1; the source of the PMOS tube M2 is connected to the power supply voltage VDD 1V The gate of the PMOS tube M1 is connected to the bias voltage V TRX The gate of the NMOS tube M3 is connected to the bias voltage V G1 The drain of the NMOS tube M3 is connected to one end of the resistor R1, the drain of the NMOS tube M4 is connected to the other end of the resistor R1, and the gate of the NMOS tube M4 is connected to the bias voltage V G1 The source of the NMOS tube M6 is connected to the drain of the NMOS tube M5 and the source of the NMOS tube M7, the source of the NMOS tube M5 is grounded, and the gate of the NMOS tube M5 is connected to the bias voltage V TRX The source of the NMOS tube M8 is connected to the NMOS tube M 10 The drain of the NMOS tube M9 is connected to the source of the NMOS tube M9. 10 The source of the NMOS tube M is grounded. 10 The gate bias voltage The PMOS tube M 11 The gate bias voltage The PMOS tube M 11 The drain of the PMOS tube M is connected to one end of the resistor R2. 12 The drain of the PMOS tube M is connected to the other end of the resistor R2. 12 The gate bias voltage The PMOS tube M 13 The source is connected to the bias voltage V G , the PMOS tube M 13 The gate is connected to the bias voltage V TRX , the PMOS tube M 13 The drain of the PMOS tube M 14 The drain of the PMOS tube M is connected to the e2 port of the transformer TR2. 14 The source is connected to the power supply voltage VDD 1V , the PMOS tube M 14 The gate bias voltage 3. The two-stage bidirectional millimeter-wave CMOS amplifier with enhanced output power according to claim 1, characterized in that: The PA / LNA stage is mainly composed of three stacked common source and common gate PAs and a common source LNA with source degeneration inductance; the PA / LNA stage includes a PMOS tube M 15 、PMOS tube M 16 、PMOS tube M 17 、PMOS tube M 18 、NMOS tube M 19 、NMOS tube M 20 、NMOS tube M 21 、NMOS tube M 22 、NMOS tube M 23 、NMOS tube M 24 、NMOS tube M 25 、NMOS tube M 26 、NMOS tube M 27 、NMOS tube M 28 、PMOS tube M 29 , bias voltage V G , bias voltage V G1 , bias voltage V G2 , bias voltage V G3 , bias voltage V TRX , bias voltage Resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, power supply voltage VDD 1V , capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor C7, capacitor C8, inductor L1, inductor L2; The PA / LNA stage port c is composed of a PMOS transistor M 17 The source of NMOS tube M 20 The gate and NMOS tube M 27 The drain of the PA / LNA stage is connected to the d2 port of the transformer TR2; the port c of the PA / LNA stage is connected to the d2 port of the transformer TR2; ′ By PMOS tube M 18 The source of NMOS tube M 21 The gate and NMOS tube M 26 The drain of the PA / LNA stage is connected to the drain of the transformer TR2, and the port d ... 24 The drain connection is formed and connected to the a3 port of the transformer TR3, the port d of the PA / LNA stage ′ One end of capacitor C8 is connected to NMOS tube M 25 The drain of the transformer TR3 is connected to the b3 terminal; The PMOS tube M 15 The source is connected to the bias voltage V G , the PMOS tube M 15 The gate bias voltage The PMOS tube M 15 The drain of the PMOS tube M 16 The drain of the PMOS tube M is connected to the f2 port of the transformer TR2. 16 The source is connected to the power supply voltage VDD 1V , the PMOS tube M 16 The gate is connected to the bias voltage V TRX , the PMOS tube M 17 The gate is connected to the bias voltage V TRX , the PMOS tube M 17 The drain of the PMOS tube M is connected to one end of the capacitor C2. 18 The drain of the PMOS tube M is connected to the other end of the capacitor C2. 18 The gate bias voltage The NMOS tube M 20 The source of NMOS tube M 21 The source and NMOS tube M 19 The drain of the NMOS tube M 20 The drain of NMOS tube M 22 The source of the NMOS tube M 21 The drain of NMOS tube M 23 The source of the NMOS tube M 22 The gate of the NMOS tube M is connected to one end of the resistor R3 and one end of the capacitor C3. 23 The gate is connected to one end of the resistor R4 and one end of the capacitor C4, and the other end of the resistor R3 and the other end of the resistor R4 are connected to the bias voltage V G1 The other end of the capacitor C3 and the other end of the capacitor C4 are grounded, and the NMOS tube M 22 The drain of NMOS tube M 24 The source of the NMOS tube M 23 The drain of NMOS tube M 25 The source of the NMOS tube M 24 The gate of the NMOS tube M is connected to one end of the resistor R5 and one end of the capacitor C5. 25 The gate is connected to one end of the resistor R6 and one end of the capacitor C6, and the other end of the resistor R5 and the other end of the resistor R6 are connected to the bias voltage V G2 The other end of the capacitor C5 and the other end of the capacitor C6 are grounded, and the other end of the capacitor C7 is connected to one end of the resistor R7 and the NMOS tube M 26 The gate of the capacitor C8 is connected to one end of the resistor R8 and the NMOS tube M 27 The gate of the resistor R7 and the other end of the resistor R8 are connected to the bias voltage V G3 , the NMOS tube M 26 The source of the NMOS tube M is connected to one end of the inductor L1. 27 The source of the inductor L1 is connected to one end of the inductor L2, and the other end of the inductor L1 is connected to the other end of the inductor L2 and the NMOS tube M 28 The drain and PMOS tube M 29 The drain of the NMOS tube M 28 The source of the NMOS tube M is grounded. 28 The gate bias voltage The PMOS tube M 29 The source is connected to the power supply voltage V G , the PMOS tube M 29 The gate bias voltage

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