Discrete time integrator
By using a second switch combination in the discrete time integrator operation amplifier to disconnect the second differential operation amplifier circuit during the sampling period, the problem of constant power consumption and dynamic bias circuits in the prior art are solved, and significant power consumption reduction and circuit symmetry improvement are achieved.
Patent Information
- Application Number
- CN202411810076.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-03-25
AI Technical Summary
The existing discrete time integrators do not change in power consumption during sampling periods and integration periods, and traditional dynamic bias circuits tend to cause common-mode voltage floating and circuit asymmetry.
A discrete time integrator is designed, employing an operational amplifier, including a first differential operational amplifier circuit and a second differential operational amplifier circuit, and by combining the second switches, only the first differential operational amplifier circuit is kept running to reduce power consumption.
It significantly reduces the power consumption of discrete time integrators, saves more than 40% of the power consumption, and avoids common-mode voltage floating and circuit asymmetry problems.
Smart Images
Figure CN119696562A_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to the field of integrators, and in particular to a discrete time integrator. [Background technology]
[0002] The power consumption of the discrete time integrator in the prior art remains unchanged in the sampling period and the integration period. The power consumption of the conventional discrete time integrator is higher.
[0003] In addition, traditional dynamic bias circuits are prone to common-mode voltage floating and circuit asymmetry.
[0004] Therefore, it is urgent to propose a new technical solution to solve the above problems. [Summary of the invention]
[0005] One of the objects of the present invention is to provide a discrete time integrator with lower power consumption.
[0006] According to one aspect of the present invention, the present invention provides a discrete time integrator, which includes: an operational amplifier, including a first differential operational amplifier circuit, a second differential operational amplifier circuit and a second switch combination, wherein the first differential operational amplifier circuit is connected between a power supply terminal and a ground terminal, and the second switch combination controls the connection of the second differential operational amplifier circuit between the power supply terminal and the ground terminal. During the integration period, the second switch combination is turned on, so that the second differential operational amplifier circuit is connected between the power supply terminal and the ground terminal, and during the sampling period, the second switch combination is turned off, so that the second differential operational amplifier circuit is disconnected from the power supply terminal and the ground terminal.
[0007] In a further embodiment, the first differential operational amplifier circuit includes a first input terminal, a second input terminal and an output terminal, and the second differential operational amplifier circuit includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first differential operational amplifier is connected to the first input terminal of the second differential operational amplifier circuit and serves as the first input terminal of the operational amplifier. The second input terminal of the first differential operational amplifier is connected to the second input terminal of the second differential operational amplifier circuit and serves as the second input terminal of the operational amplifier. The output terminal of the first differential operational amplifier is connected to the output terminal of the second differential operational amplifier circuit and serves as the output terminal of the operational amplifier.
[0008] In a further embodiment, the first differential operational amplifier circuit is symmetrical to the second differential operational amplifier circuit, and the operational amplifier further comprises a first switch combination, the first switch combination and the second switch combination are symmetrical, the first switch combination controls the connection of the first differential operational amplifier circuit between the power supply terminal and the ground terminal, and during the integration period and the sampling period, the first switch combination is always turned on, so that the first differential operational amplifier circuit is always connected between the power supply terminal and the ground terminal.
[0009] In a further embodiment, the symmetry between the first switch combination and the second switch combination means that the number, connection positions and connection methods of the first switches included in the first switch combination are the same as or relative to the number, connection positions and connection methods of the second switches included in the second switch combination, and the symmetry between the first differential operational amplifier circuit and the second differential operational amplifier circuit means that the number, connection positions and connection methods of the MOS transistors included in the first differential operational amplifier circuit are the same as or relative to the number, connection positions and connection methods of the MOS transistors included in the first differential operational amplifier circuit.
[0010] Compared with the prior art, the present invention turns off the second differential operational amplifier circuit in the operational amplifier during the sampling period. At this time, the first differential operational amplifier circuit in the operational amplifier can also ensure the output signal of the discrete time integrator.
Brief Description of the Drawings
[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:
[0012] Figure 1 It is a structural schematic diagram of a discrete time integrator in the present invention;
[0013] Figure 2 for Figure 1 A circuit diagram of an operational amplifier in one embodiment;
[0014] Figure 3 for Figure 1 and Figure 2 Timing diagram of each signal in . [Specific implementation method]
[0015] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0016] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The "in one embodiment" that appears in different places in this specification does not all refer to the same embodiment, nor is it a separate or selective embodiment that is mutually exclusive with other embodiments. In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", "coupled" and other terms indicating electrical connection should be understood in a broad sense; for example, it can be a direct electrical connection, or it can be indirectly electrically connected through an intermediate medium, and the intermediate medium can be an electronic component, a functional circuit, etc. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.
[0017] The output signal of the existing discrete time integrator hardly changes during the sampling period. Therefore, the power consumption of the operational amplifier can be lower during the sampling period.
[0018] Figure 1 It is a structural schematic diagram of a discrete time integrator in the present invention. Figure 2 for Figure 1 A circuit diagram of an operational amplifier in one embodiment; Figure 3 for Figure 1 and Figure 2 Timing diagram of each signal in .
[0019] like Figure 1 As shown, the discrete time integrator 100 includes an operational amplifier 110. The operational amplifier 110 includes a first input terminal, a second input terminal and an output terminal. The positive phase input terminal of the operational amplifier 110 can be used as the first input terminal or the second input terminal, and the negative phase input terminal of the operational amplifier 110 can be used as the second input terminal or the first input terminal.
[0020] like Figure 1As shown, the discrete time integrator 100 also includes: a first capacitor C1; a second capacitor C2 coupled between the first input terminal and the output terminal of the operational amplifier; a third capacitor C3 whose second terminal is connected to the ground terminal; a first sampling switch SS1 coupled between the signal input terminal IN of the discrete time integrator and the first end of the first capacitor C1; a second sampling switch SS2 coupled between the second end of the first capacitor C1 and the ground terminal; a first integration switch Si1 coupled between the first end of the first capacitor C1 and the ground terminal; a second integration switch Si2 coupled between the second end of the first capacitor C1 and the first input terminal of the operational amplifier; a third integration switch Si3 coupled between the output terminal of the operational amplifier and the first end of the third capacitor C3. During the sampling period, the first sampling switch SS1 and the second sampling switch SS2 are turned on, and each integration switch is turned off. During the integration period, each sampling switch is turned off, and each integration switch is turned on. The output terminal of the operational amplifier serves as the signal output terminal OUT of the discrete time integrator.
[0021] like Figure 3 As shown, the second sampling switch SS2 is controlled by the sampling control signal P1, and the first sampling switch SS1 is controlled by the delayed signal P1D of the sampling control signal P1, so that the second sampling switch SS1 is turned on and off before the first sampling switch SS2. The second integration switch Si2 is controlled by the sampling control signal P2, and the first integration switch Si1 and the third integration switch Si3 are controlled by the delayed signal P2D of the integration control signal P2, so that the second integration switch Si2 is turned on and off before the first integration switch Si1 and the third integration switch Si3. In this embodiment, when P1 / P1D is high level, the corresponding sampling switch is turned on, when P1 / P1D is low level, the corresponding sampling switch is turned off, when P2 / P2D is high level, the corresponding integration switch is turned on, and when P2 / P2D is low level, the corresponding integration switch is turned off.
[0022] like Figure 2 As shown, the operational amplifier 110 includes a first differential operational amplifier circuit, a second differential operational amplifier circuit and a second switch combination S21-S25, wherein the first differential operational amplifier circuit is connected between the power supply terminal VDD and the ground terminal GND, and the second switch combination controls the connection of the second differential operational amplifier circuit between the power supply terminal and the ground terminal.
[0023] During the integration period, the second switch combination S21-S25 is turned on, so that the second differential operational amplifier circuit is connected between the power supply terminal and the ground terminal. At this time, the operational amplifier 110 operates based on the first differential operational amplifier circuit and the second differential operational amplifier circuit. During the sampling period, the second switch combination S21-S25 is turned off, so that the second differential operational amplifier circuit is disconnected from the power supply terminal and the ground terminal. At this time, the operational amplifier 110 operates based on the first differential operational amplifier circuit. At this time, the second differential operational amplifier circuit has no power consumption, and the first differential operational amplifier circuit can ensure the output signal of the discrete time integrator, and does not affect the normal operation of the discrete time integrator 100. In this way, the power consumption of the discrete time integrator 100 can be significantly reduced, for example, more than 40% of the power consumption can be saved.
[0024] The first differential operational amplifier circuit includes a first input terminal INPUT+, a second input terminal INPUT- and an output terminal, and the second differential operational amplifier circuit includes a first input terminal INPUTc+, a second input terminal INPUTc- and an output terminal. The first input terminal INPUT+ of the first differential operational amplifier is connected to the first input terminal INPUTc+ of the second differential operational amplifier circuit and serves as the first input terminal of the operational amplifier, the second input terminal INPUT- of the first differential operational amplifier is connected to the second input terminal INPUTc- of the second differential operational amplifier circuit and serves as the second input terminal of the operational amplifier, and the output terminal of the first differential operational amplifier is connected to the output terminal of the second differential operational amplifier circuit and serves as the output terminal Vout of the operational amplifier.
[0025] The first differential operational amplifier circuit is symmetrical to the second differential operational amplifier circuit.
[0026] In a preferred embodiment, the operational amplifier 100 further includes a first switch combination S11-S15, and the first switch combination S11-S15 is symmetrical to the second switch combination S21-S25. The first switch combination S11-S15 controls the connection of the first differential operational amplifier circuit between the power supply terminal VDD and the ground terminal GND. During the integration period and the sampling period, the first switch combination S11-S15 is always turned on, so that the first differential operational amplifier circuit is always connected between the power supply terminal and the ground terminal. The first switch combination S11-S15 remains turned on for a long time, and its function is to ensure symmetry with the second switch combination S21-S25. If there is no first switch combination S11-S15, there is no circuit symmetrical with the second switch combination S21-S25, which affects the symmetry of the circuit, and there will be even harmonics in the spectrum of the output signal of the discrete time integrator 100.
[0027] In one embodiment, the first switch combination S11-S15 and the second switch combination S21-S25 are symmetrical, which means that the number, connection position and connection mode of the first switches included in the first switch combination are the same as or relative to the number, connection position and connection mode of the second switches included in the second switch combination. The first differential operational amplifier circuit is symmetrical to the second differential operational amplifier circuit, which means that the number, connection position and connection mode of the MOS transistors included in the first differential operational amplifier circuit are the same as or relative to the number, connection position and connection mode of the MOS transistors included in the first differential operational amplifier circuit.
[0028] In a specific embodiment, Figure 2 As shown, the first differential operational amplifier circuit includes PMOS transistors M3, Mi1, Mi2, M4, M5, M6, M7, and NMOS transistors M8, M9, M1, M2. The first switch combination includes first switches S11, S12, S13, S14, S15. The second differential operational amplifier circuit includes PMOS transistors M3c, Mi1c, Mi2c, M4c, M5c, M6c, M7c, and NMOS transistors M8c, M9c, M1c, M2c. The second switch combination includes second switches S21, S22, S23, S24, S25. The PMOS transistors M3, Mi1, Mi2, M4, M5, M6, M7, and the NMOS transistors M8, M9, M1, M2 in the first differential operational amplifier circuit are symmetrical with the PMOS transistors M3c, Mi1c, Mi2c, M4c, M5c, M6c, M7c, and the NMOS transistors M8c, M9c, M1c, M2c in the second differential operational amplifier circuit. The first switches S11, S12, S13, S14, S15 in the first switch combination are symmetrical with the second switches S21, S22, S23, S24, S25 in the second switch combination.
[0029] like Figure 2 As shown, the source of the PMOS transistor M3 is coupled to the power supply terminal through the first switch S11, the drain thereof is coupled to the sources of the PMOS transistor Mi1 and the PMOS transistor Mi2, and the gate of the PMOS transistor M3 is connected to the bias voltage Vbias.
[0030] The drain of the PMOS transistor Mi1 is coupled to the drain of the NMOS transistor M1, the drain of the PMOS transistor Mi2 is coupled to the drain of the NMOS transistor M2, the gate of the PMOS transistor Mi1 serves as the first input terminal of the first differential operational amplifier, and the gate of the PMOS transistor Mi2 serves as the second input terminal of the first differential operational amplifier.
[0031] The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2 , the source of the NMOS transistor M1 is coupled to the ground terminal through the first switch S14 , and the source of the NMOS transistor M2 is coupled to the ground terminal through the first switch S15 .
[0032] The source of the PMOS transistor M4 is coupled to the power supply terminal through the first switch S12 , the gate thereof is connected to the gate of the PMOS transistor M5 , and the drain thereof is connected to the source of the PMOS transistor M6 .
[0033] The source of the PMOS transistor M5 is coupled to the power supply terminal through the first switch S13 , and the drain thereof is connected to the source of the PMOS transistor M7 .
[0034] The gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M7 , and the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M8 and the gate of the PMOS transistor M4 .
[0035] The drain of the PMOS transistor M7 is connected to the drain of the NMOS transistor M9 .
[0036] The gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M9 , and the source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M1 .
[0037] The source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M2 .
[0038] The drain of the PMOS transistor M7 serves as the output terminal of the first differential amplifier circuit.
[0039] The source of the PMOS transistor M3c is coupled to the power supply terminal through the first switch S21, the drain thereof is coupled to the sources of the PMOS transistor Mi1c and the PMOS transistor Mi2c, and the gate of the PMOS transistor M3c is connected to the bias voltage Vbias.
[0040] The drain of the PMOS transistor Mi1c is coupled to the drain of the NMOS transistor M1c, the drain of the PMOS transistor Mi2c is coupled to the drain of the NMOS transistor M2c, the gate of the PMOS transistor Mi1c serves as the first input terminal of the second differential operational amplifier, and the gate of the PMOS transistor Mi2c serves as the second input terminal of the second differential operational amplifier.
[0041] The gate of the NMOS transistor M1c is connected to the gate of the NMOS transistor M2c, the source of the NMOS transistor M1c is coupled to the ground terminal through the second switch S24, and the source of the NMOS transistor M2c is coupled to the ground terminal through the second switch S25.
[0042] The source of the PMOS transistor M4c is coupled to the power supply terminal through the second switch S22, the gate thereof is connected to the gate of the PMOS transistor M5c, and the drain thereof is connected to the source of the PMOS transistor M6c.
[0043] The source of the PMOS transistor M5c is coupled to the power supply terminal through the second switch S23, and the drain thereof is connected to the source of the PMOS transistor M7c.
[0044] The gate of the PMOS transistor M6c is connected to the gate of the PMOS transistor M7c, and the drain thereof is connected to the drain of the NMOS transistor M8c and the gate of the PMOS transistor M4c.
[0045] The drain of the PMOS transistor M7c is connected to the drain of the NMOS transistor M9c.
[0046] The gate of the NMOS transistor M8c is connected to the gate of the NMOS transistor M9c, and the source thereof is connected to the drain of the NMOS transistor M1c.
[0047] The source of the NMOS transistor M9c is connected to the drain of the NMOS transistor M2c.
[0048] The drain of the PMOS transistor M7c serves as the output terminal of the second differential amplifier circuit.
[0049] The operational amplifier 100 further includes an NMOS transistor M10 , the gate of the NMOS transistor M10 is connected to its drain, the gate of the NMOS transistor M10 is connected to the gates of the NMOS transistors M1 and M1c, the source of the NMOS transistor M10 is grounded, and the drain of the NMOS transistor M10 receives a bias current Ibias.
[0050] The NMOS transistors M1, M2, the NMOS transistors M1c and M2c, and the NMOS transistor M10 together form a current mirror, and the currents on the NMOS transistors M1, M2, M1c, and M2c can be controlled based on the bias current Ibias. The present invention controls the overall current of the operational amplifier 100 through the current mirror and the bias current, which belongs to current mode control, and can therefore be adapted to high-speed applications.
[0051] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.
[0052] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify and vary the above embodiments within the scope of the present invention.
Claims
1. A discrete time integrator, characterized in that: It includes: The operational amplifier comprises a first differential operational amplifier circuit, a second differential operational amplifier circuit and a second switch combination, wherein the first differential operational amplifier circuit is connected between a power supply terminal and a ground terminal, and the second switch combination controls the second differential operational amplifier circuit to be connected between the power supply terminal and the ground terminal. During the integration period, the second switch combination is turned on, so that the second differential operational amplifier circuit is connected between the power supply terminal and the ground terminal. During the sampling period, the second switch combination is turned off, so that the second differential operational amplifier circuit is disconnected from the power supply terminal and the ground terminal.
2. The discrete-time integrator according to claim 1, characterized in that The first differential operational amplifier circuit includes a first input terminal, a second input terminal and an output terminal, and the second differential operational amplifier circuit includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first differential operational amplifier is connected to the first input terminal of the second differential operational amplifier circuit and serves as the first input terminal of the operational amplifier. The second input terminal of the first differential operational amplifier is connected to the second input terminal of the second differential operational amplifier circuit and serves as the second input terminal of the operational amplifier. The output terminal of the first differential operational amplifier is connected to the output terminal of the second differential operational amplifier circuit and serves as the output terminal of the operational amplifier. The first differential operational amplifier circuit is symmetrical to the second differential operational amplifier circuit.
3. The discrete-time integrator according to claim 2, characterized in that The operational amplifier further includes a first switch combination, wherein the first switch combination and the second switch combination are symmetrical. The first switch combination controls the connection of the first differential operational amplifier circuit between the power supply terminal and the ground terminal. During the integration period and the sampling period, the first switch combination is always turned on, so that the first differential operational amplifier circuit is always connected between the power supply terminal and the ground terminal.
4. The discrete-time integrator according to claim 3, characterized in that The symmetry between the first switch combination and the second switch combination means that the number, connection position and connection mode of the first switches included in the first switch combination are the same as or opposite to the number, connection position and connection mode of the second switches included in the second switch combination. The symmetry between the first differential operational amplifier circuit and the second differential operational amplifier circuit means that the number, connection position and connection method of the MOS transistors included in the first differential operational amplifier circuit are the same as or relative to the number, connection position and connection method of the MOS transistors included in the second differential operational amplifier circuit.
5. The discrete-time integrator according to claim 3, characterized in that: The first differential operational amplifier circuit includes PMOS transistors M3, Mi1, Mi2, M4, M5, M6, M7, and NMOS transistors M8, M9, M1, M2. The first switch combination includes first switches S11, S12, S13, S14, and S15, The second differential operational amplifier circuit includes PMOS transistors M3c, Mi1c, Mi2c, M4c, M5c, M6c, M7c, and NMOS transistors M8c, M9c, M1c, M2c. The second switch combination includes second switches S21, S22, S23, S24, and S25. The PMOS transistors M3, Mi1, Mi2, M4, M5, M6, and M7 and the NMOS transistors M8, M9, M1, and M2 in the first differential operational amplifier circuit are symmetrical with the PMOS transistors M3c, Mi1c, Mi2c, M4c, M5c, M6c, and M7c and the NMOS transistors M8c, M9c, M1c, and M2c in the second differential operational amplifier circuit, respectively. The first switches S11, S12, S13, S14, S15 in the first switch combination are symmetrical with the second switches S21, S22, S23, S24, S25 in the second switch combination, respectively.
6. The discrete-time integrator according to claim 5, characterized in that The source of the PMOS transistor M3 is coupled to the power supply terminal through the first switch S11, the drain thereof is coupled to the sources of the PMOS transistor Mi1 and the PMOS transistor Mi2, and the gate of the PMOS transistor M3 is connected to the bias voltage. The drain of the PMOS transistor Mi1 is coupled to the drain of the NMOS transistor M1, the drain of the PMOS transistor Mi2 is coupled to the drain of the NMOS transistor M2, the gate of the PMOS transistor Mi1 serves as the first input terminal of the first differential operational amplifier, and the gate of the PMOS transistor Mi2 serves as the second input terminal of the first differential operational amplifier. The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2, the source of the NMOS transistor M1 is coupled to the ground terminal through the first switch S14, and the source of the NMOS transistor M2 is coupled to the ground terminal through the first switch S15. The source of the PMOS transistor M4 is coupled to the power supply terminal through the first switch S12, the gate thereof is connected to the gate of the PMOS transistor M5, and the drain thereof is connected to the source of the PMOS transistor M6. The source of the PMOS transistor M5 is coupled to the power supply terminal through the first switch S13, and the drain thereof is connected to the source of the PMOS transistor M7. The gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M7, and the drain thereof is connected to the drain of the NMOS transistor M8 and the gate of the PMOS transistor M4. The drain of the PMOS transistor M7 is connected to the drain of the NMOS transistor M9. The gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M9, and the source thereof is connected to the drain of the NMOS transistor M1. The source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M2. The drain of the PMOS transistor M7 serves as the output terminal of the first differential amplifier circuit. The source of the PMOS transistor M3c is coupled to the power supply terminal through the first switch S21, the drain thereof is coupled to the sources of the PMOS transistor Mi1c and the PMOS transistor Mi2c, and the gate of the PMOS transistor M3c is connected to the bias voltage. The drain of the PMOS transistor Mi1c is coupled to the drain of the NMOS transistor M1c, the drain of the PMOS transistor Mi2c is coupled to the drain of the NMOS transistor M2c, the gate of the PMOS transistor Mi1c serves as the first input terminal of the second differential operational amplifier, and the gate of the PMOS transistor Mi2c serves as the second input terminal of the second differential operational amplifier. The gate of the NMOS transistor M1c is connected to the gate of the NMOS transistor M2c, the source of the NMOS transistor M1c is coupled to the ground terminal through the second switch S24, and the source of the NMOS transistor M2c is coupled to the ground terminal through the second switch S25. The source of the PMOS transistor M4c is coupled to the power supply terminal through the second switch S22, the gate thereof is connected to the gate of the PMOS transistor M5c, and the drain thereof is connected to the source of the PMOS transistor M6c. The source of the PMOS transistor M5c is coupled to the power supply terminal through the second switch S23, and the drain of the PMOS transistor M5c is connected to the source of the PMOS transistor M7c. The gate of the PMOS transistor M6c is connected to the gate of the PMOS transistor M7c, and the drain thereof is connected to the drain of the NMOS transistor M8c and the gate of the PMOS transistor M4c. The drain of the PMOS transistor M7c is connected to the drain of the NMOS transistor M9c. The gate of the NMOS transistor M8c is connected to the gate of the NMOS transistor M9c, and the source thereof is connected to the drain of the NMOS transistor M1c. The source of the NMOS transistor M9c is connected to the drain of the NMOS transistor M2c. The drain of the PMOS transistor M7c serves as the output terminal of the second differential amplifier circuit. The first input terminal of the first differential amplifier is connected to the first input terminal of the second differential amplifier as the first input terminal of the operational amplifier. The second input terminal of the first differential amplifier is connected to the second input terminal of the second differential amplifier as the second input terminal of the operational amplifier. The output end of the first differential amplifier is connected to the output end of the second differential amplifier as the output end of the operational amplifier, The operational amplifier further includes an NMOS transistor M10 , the gate of the NMOS transistor M10 is connected to its drain, the gate of the NMOS transistor M10 is connected to the gates of the NMOS transistors M1 and M1c, the source of the NMOS transistor M10 is grounded, and the drain of the NMOS transistor M10 receives a bias current.
7. The discrete-time integrator according to claim 1, characterized in that The operational amplifier comprises a first input terminal, a second input terminal and an output terminal; The discrete time integrator further comprises: A first capacitor C1; A second capacitor C2 coupled between the first input terminal and the output terminal of the operational amplifier; A third capacitor C3, a second end of which is connected to the ground; a first sampling switch coupled between the signal input terminal of the discrete time integrator and the first terminal of the first capacitor C1; a second sampling switch coupled between the second end of the first capacitor C1 and the ground; a first integrating switch coupled between a first terminal of the first capacitor C1 and a ground terminal; a second integrating switch coupled between the second terminal of the first capacitor C1 and the first input terminal of the operational amplifier; and a third integrating switch coupled to the output terminal of the operational amplifier and the first terminal of the third capacitor C3, During the sampling period, the first sampling switch and the second sampling switch are turned on, and each integration switch is turned off. During the integration period, each sampling switch is turned off, and each integration switch is turned on. The output terminal of the operational amplifier serves as the signal output terminal of the discrete time integrator.
8. The discrete-time integrator according to claim 7, characterized in that The second sampling switch is controlled by the sampling control signal P1, and the first sampling switch is controlled by the delayed signal P1D of the sampling control signal P1, so that the second sampling switch is turned on and off before the first sampling switch. The second integration switch is controlled by the sampling control signal P2, and the first and third integration switches are controlled by the delayed signal P2D of the integration control signal P2, so that the second integration switch is turned on and off before the first and third integration switches.