Memory element

Abstract

The invention provides a memory element. The memory element includes a substrate, an interconnect structure, a step structure, a dielectric layer and a stop structure. An interconnect structure is located over the substrate, a step structure is located over the interconnect structure, and a dielectric layer is located over the interconnect structure and covers the step structure. A stop structure is located between the interconnect structure and the step structure, and between the interconnect structure and the dielectric layer. The stop structure is provided with an opening, and the interconnection structure is exposed. A first contact window extends through the dielectric layer and the opening and is connected with an interconnect of the interconnect structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening. The memory element can be a 3D NAND flash memory with high capacity and high performance.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated circuit, and more particularly to an integrated circuit including a memory element. Background Art

[0002] Non-volatile memory elements (eg, flash memory) have become a widely used memory element in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after power is turned off.

[0003] The flash memory arrays that are commonly used in the industry include NOR flash memory, NAND flash memory, and read-only (ROM) memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory. For example, the through array contact window is often tilted or offset, and even causes a short circuit with other components. Summary of the invention

[0004] The invention provides a memory element, which can reduce or avoid the contact window from being offset or tilted and causing short circuit with other components.

[0005] An embodiment of the present invention provides a memory element, comprising: a substrate, an internal connection structure, a step structure, a dielectric layer and a stop structure. The internal connection structure is located above the substrate, the step structure is located above the internal connection structure, and the dielectric layer is located above the internal connection structure and covers the step structure. The stop structure is located between the internal connection structure and the step structure, and between the internal connection structure and the dielectric layer, and the stop structure has an opening to expose the internal connection structure. A first contact window extends through the dielectric layer and the opening, and is connected to the internal connection of the internal connection structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening.

[0006] An embodiment of the present invention provides a memory element, comprising: a substrate, an internal connection structure, a step structure, a dielectric layer, a stop structure, a first contact window, and a second contact window. The internal connection structure is located above the substrate, and the step structure is located above the internal connection structure. The dielectric layer is located above the internal connection structure and covers the step structure. The stop structure is located between the internal connection structure and the step structure, and between the internal connection structure and the dielectric layer, and the stop structure has an opening to expose the internal connection structure. The first contact window and the second contact window extend through the dielectric layer and the opening, and are connected to the internal connection of the internal connection structure. A plurality of liner layers are located on the sidewalls of the opening.

[0007] An embodiment of the present invention provides a memory element, comprising: a substrate, an internal connection structure, a step structure, a dielectric layer, a stop structure, a first contact window and a second contact window. The internal connection structure is located above the substrate, and the step structure is located above the internal connection structure. The dielectric layer is located above the internal connection structure and covers the step structure. The stop structure is located between the internal connection structure and the step structure, and between the internal connection structure and the dielectric layer, and the stop structure has an opening to expose the internal connection structure. The first contact window and the second contact window extend through the dielectric layer and the opening, and are connected to the internal connection of the internal connection structure. The bottom angle of the opening is 84° to 86° or greater than 90°.

[0008] Based on the above, the embodiments of the present invention design the opening of the stop structure to have various profiles and angles, or form a liner on the sidewall, so that even if the contact window is offset or tilted, the occurrence of short circuit can be reduced or prevented. In this way, the yield of the memory element can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a cross-sectional schematic diagram of a semiconductor device with a complementary metal oxide semiconductor device under a memory array (CMOS-Under-Array, CUA) structure according to an embodiment of the present invention.

[0010] Figures 2A to 2G Schematic diagram showing various adjacent contact windows.

[0011] FIG. 3A to FIG. 3E Schematic cross-sectional view of a stop structure showing the profiles of various openings according to an embodiment of the present invention.

[0012] FIG. 4A to FIG. 4C Schematic cross-sectional view showing a stop structure and a contact window according to some embodiments of the present invention.

[0013] Description of Reference Numerals

[0014] 10: Base

[0015] 20: Component layer

[0016] 30: Internal connection structure

[0017] 36: Wire

[0018] 95: Stop structure, source line, common source conductor layer

[0019] 96: Cone

[0020] 97: Rectangular part

[0021] 98: Lining

[0022] 99, 99A, 99B, 99C, 99D, 99E: Open

[0023] 102: Insulation layer

[0024] 103: Dielectric layer

[0025] 108: Charge storage structure

[0026] 110: Channel layer

[0027] 112: Insulation column

[0028] 114: Conductor plug

[0029] 126: Conductor layer

[0030] ARY: memory array

[0031] COA1, COA2: Contact window

[0032] CSL: Common Source Line

[0033] Ct, Ct′, Cb, Cb′: center

[0034] D1, Db, dt, dt′, db, db′: distance

[0035] DP: Support column

[0036] H: Height

[0037] LP: Lower Level

[0038] MC: Storage Unit

[0039] OP1, OP2, OP3: contact holes

[0040] Pt: Top spacing

[0041] Pb: Bottom spacing

[0042] SK: Stacked structure

[0043] SSLC: Select source line cutting wall

[0044] SW1, SW2, SW3, SW4: side wall

[0045] TAC, TAC′: Contact window

[0046] UP: Upper level

[0047] VC: Vertical Channel Column

[0048] VL: Vertical Center Line

[0049] WL: Word Line

[0050] Wt: Top width

[0051] Wm: middle width

[0052] Wb: bottom width

[0053] Wct, Wct′: top width

[0054] Wcx, Wcx′: Maximum width of the arch

[0055] Wcb, Wct′: bottom width DETAILED DESCRIPTION

[0056] Figure 1 The cross-sectional view of a semiconductor element in a memory block having a complementary metal oxide semiconductor element structure below a memory array according to an embodiment of the present invention is shown.

[0057] Reference Figure 1 The semiconductor device of the embodiment of the present invention is a complementary metal oxide semiconductor device under memory array (CUA) structure. The CUA structure includes a substrate 10, a lower level LP and an upper level UP. The lower level LP is formed above the substrate 10, and the upper level UP is formed above the lower level LP.

[0058] The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. The lower level LP may include a component layer 20 and an internal wiring structure 30. The component layer 20 may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor device (CMOS). The component layer 20 may include a plurality of peripheral circuits, a plurality of row decoders and column decoders, and a plurality of page buffers (not shown).

[0059] The interconnect structure 30 may include a multi-layer dielectric layer 32 and an interconnect 33 formed in the multi-layer dielectric layer 32. The interconnect 33 includes a plurality of plugs 34 and a plurality of wires 36. The dielectric layer 32 separates adjacent wires 36. The wires 36 may be connected to each other through the plugs 34, and the wires 36 may be connected to the device layer 20 through the plugs 34. Figure 1 The number of layers of the plugs 34 and the conductive lines 36 of the interconnect 33 is shown for illustration only, but the present invention is not limited thereto, and the interconnect 33 may include more or fewer layers of plugs 34 and conductive lines 36. For example, Figure 1 The illustrated internal connection 33 includes three layers of wires 36. In other embodiments, the internal connection 33 may include seven layers of wires 36.

[0060] The upper level UP includes a stacking structure SK, a step structure SC and a stop structure 95. The stacking structure SK includes a plurality of conductor layers 126 and a plurality of insulating layers 102 that are alternately stacked. The material of the conductor layer 126 includes tungsten (W), molybdenum (Mo), ruthenium (Ru), aluminum (Al), titanium (Ti), titanium nitride (TiN) or a combination thereof. The material of the insulating layer 102 includes silicon oxide. The step structure SC includes a plurality of conductor layers 126 and a plurality of insulating layers 102 that are alternately stacked. The step structure SC is formed by performing a multi-stage patterning process on the stacking structure SK, but the present invention is not limited thereto. The patterning process may include processes such as photolithography, etching and trimming.

[0061] A plurality of vertical channel pillars VC extend through the stack structure SK. The vertical channel pillars VC may include a channel layer 110, an insulating pillar 112, and a conductor plug 114. The charge storage structure 108 may be an oxide / nitride / oxide (ONO) composite layer. The plurality of conductor layers 126 in the stack structure SK serve as a plurality of word lines WL. The charge storage structure 108 is disposed between the word lines WL and the vertical channel pillars VC, and the intersections thereof are memory cells MC. Therefore, in the stack structure SK, there are a plurality of memory arrays ARY consisting of a plurality of memory cells MC.

[0062] The dielectric layer 103 covers the step structure SC and the stacked structure SK. The dielectric layer 103 can be a multilayer. The material of the dielectric layer 103 is, for example, silicon oxide, silicon nitride or a combination thereof. The method of forming the dielectric layer 103 is, for example, to form a dielectric material layer to cover the step structure SC. Afterwards, a planarization process, such as a chemical mechanical polishing process, is performed to remove excess dielectric material layers.

[0063] The stop structure 95 is disposed between the stack structure SK and the interconnect structure 30, between the step structure SC and the interconnect structure 30, and between the dielectric layer 103 and the interconnect structure 30. The stop structure 95 may be a single-layer or multi-layer semiconductor layer (not shown). The stop structure 95 may be used as a source line 95, and may also be referred to as a common source conductor layer 95. The stop structure 95 has an opening 99, exposing the dielectric layer 32 of the interconnect structure 30.

[0064] A source line slit CSL extends through the stack structure SK and is connected to the source line 95 . The source line slit CSL may be used to conduct current from the source line 95 .

[0065] A plurality of support columns DP extend through the dielectric layer 103 and the step structure SC and land on the stop structure 95. The plurality of support columns DP can prevent the step structure SC from collapsing during the gate replacement process. The support columns DP can be formed at the same time as the vertical channel columns VC are formed, and therefore, they can have a similar structure to the vertical channel columns VC. However, the present invention is not limited thereto. In other embodiments, the support columns DP can be formed separately, and their structure can be different from the structure of the combination of the charge storage structure 108 and the vertical channel column CP, for example, they are composed of insulating materials.

[0066] A plurality of contact windows COA1, COA2, TAC, TAC′ extend through the dielectric layer 103 and are electrically connected to the conductor plug 114 of the vertical channel column VC, the conductor layer 126 of the step structure SC, and the wire 36 of the interconnect structure 30, respectively. The contact windows TAC, TAC′ may also be referred to as array through-hole contact windows. The plurality of contact windows COA1, COA2, TAC, TAC′ may include a barrier layer and a conductor layer. The material of the barrier layer may be, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), or a combination thereof, and the material of the conductor layer may be, for example, tungsten (W), ruthenium (Ru), or a combination thereof. The method for forming multiple contact windows COA1, COA2 and TAC, TAC′ is, for example, first forming multiple contact window holes OP1, OP2, OP3, OP3′ by photolithography and etching processes, then sequentially forming a barrier layer and a conductor layer in the multiple contact window holes OP1, OP2, OP3, OP3′, and then performing a planarization process by chemical mechanical polishing.

[0067] Since the contact windows TAC and TAC' are electrically connected to the conductive line 36 of the interconnect structure 30, they have a relatively large height H. During the etching process of forming the contact holes OP3 and OP3', the contact holes OP3 and OP3' often shift, so that the formed contact windows TAC and TAC' have various tilts or shifts.

[0068] Figures 2A to 2G Schematic diagrams showing various adjacent contact windows TAC, TAC'. The inclinations of the contact windows TAC, TAC' may be the same or different.

[0069] Reference Figure 2A , the center point Ct of the top width Wct of the contact window TAC and the center point Cb of the bottom width Wcb form a center line CL. The center point Ct' of the top width Wct' of the contact window TAC' and the center point Cb' of the bottom width Wcb' form a center line CL'. The spacing between the center points Ct and Ct' is Pt. The spacing between the center points Cb and Cb' is Pb. The distances between the center points Ct, Ct' and the vertical center line VL are dt and dt' respectively. The vertical center line VL refers to a line perpendicular to the substrate 10 (shown in FIG. 1 ). Figure 1 ) and between the center line that makes the distances dt and dt' equal. The distances between the center points Cb, Cb' and the vertical center line VL are db, db' respectively. In this embodiment, the distance dt is equal to the distance db. The distances dt, dt', db, db' are equal. There is no offset between the contact windows TAC and TAC', and the distances between them are equal from top to bottom. This is referred to as the standard type.

[0070] Reference Figure 2B In this embodiment, the top pitch Pt is not equal to the bottom pitch Pb, and the top pitch Pt is smaller than the bottom pitch Pb. The distances dt and dt' are smaller than the distances db and db'. The distances dt and dt' are equal. The distances db and db' can be equal or different. The distance between the contact windows TAC and TAC' increases from top to bottom. In this embodiment, compared with Figure 2A In the standard type shown, the contact windows TAC and TAC' are tilted outward. That is, the contact windows TAC and TAC' are double-outward offset, and the cross-section of the part of the space between them is roughly conical. The degree of tilt of the contact windows TAC and TAC' can be roughly equal or different.

[0071] Reference Figure 2C In this embodiment, the top pitch Pt is not equal to the bottom pitch Pb, and the top pitch Pt is smaller than the bottom pitch Pb. The distances dt and dt' are equal. The distances db and db' are not equal. The distance dt is equal to db. The distance dt' is smaller than the distance db', and the distance between the contact windows TAC and TAC' increases gradually from top to bottom. In this embodiment, compared with Figure 2A In the standard type shown, the contact window TAC has no inclination, and the contact window TAC' gradually deviates outward from top to bottom, that is, it is a single outward deviated type.

[0072] Reference Figure 2DIn this embodiment, the top pitch Pt is not equal to the bottom pitch Pb, and the top pitch Pt is greater than the bottom pitch Pb. The difference between the top pitch Pt and the bottom pitch Pb is, for example, in the range of 1nm to 50nm. The distances dt and dt' are greater than the distances db and db'. The distances dt and dt' are equal. The distances db and db' can be equal or unequal. The distance between the contact windows TAC and TAC' gradually decreases from top to bottom. In this embodiment, compared to Figure 2A In the standard type shown, both the contact windows TAC and TAC' are inclined or offset inward. The degree of inclination of the contact windows TAC and TAC' can be equal or different.

[0073] Reference Figure 2E In this embodiment, the top pitch Pt is not equal to the bottom pitch Pb, and the top pitch Pt is greater than the bottom pitch Pb. The difference between the top pitch Pt and the bottom pitch Pb ranges from 1nm to 50nm, for example. The distances dt and dt′ are equal. The distances db and db′ are not equal. The distances dt and db are equal. The distances dt′ and db′ are not equal, and the distance between the contact windows TAC and TAC′ gradually decreases from top to bottom. The contact window TAC is not tilted, while the contact window TAC′ gradually tilts inward from top to bottom. That is, it presents a single inward offset type.

[0074] Reference Figure 2F In this embodiment, the top spacing Pt is equal to the bottom spacing Pb. The distance dt is equal to dt′. The distance db is not equal to dt, and the distance db is smaller than the distance dt.

[0075] The distance db′ is not equal to dt′, and the distance db′ is greater than the distance dt′. The distance db is not equal to db′, and the distance db′ is greater than the distance db. In this embodiment, compared to Figure 2A In the standard type shown, the contact window TAC is inclined inwardly, and the contact window TAC′ is inclined outwardly. The contact windows TAC and TAC′ are both inclined. The inclination degrees of the contact windows TAC and TAC′ are the same.

[0076] Reference Figure 2G In this embodiment, the top spacing Pt is not equal to the bottom spacing Pb, and the bottom spacing Pb is greater than the top spacing Pt. The distances dt and dt' are equal. The distances db and dt are not equal, and the distance db is less than the distance dt. The distances db' and dt' are not equal, and the distance db' is greater than the distance dt'. The distances db and db' are not equal, and the distance db' is greater than the distance db. Figure 2G The difference between the distance db′ and the distance db in Figure 2F The difference between the distance db′ and the distance db in . In this embodiment, compared with Figure 2AIn the standard type shown, the contact window TAC is inclined inwardly, and the contact window TAC′ is inclined outwardly. Both the contact windows TAC and TAC′ are inclined. The inclination degrees of the contact windows TAC and TAC′ are different. The inclination degree of the contact window TAC′ is greater than the inclination degree of the contact window TAC. Figure 2G The inclination of the contact window TAC′ is greater than Figure 2F The inclination degree of the contact window TAC′.

[0077] above Figures 2A to 2G The various contact windows TAC and TAC′ shown in the figure can control the anisotropy of etching by the power of the plasma enhanced etching process during the etching process for forming the contact window holes OP3 and OP3′. For example, a plasma enhanced etching process with a higher power is used to improve the anisotropy of etching. A plasma enhanced etching process with a lower power is used to reduce the anisotropy of etching. When a lower power is used, the deviation between the top spacing 'Pt and the bottom spacing Pb of the contact window TAC (or TAC′) is greater than 80nm or even greater than 100nm. When a higher power is used, the deviation between the top spacing Pt and the bottom spacing Pb of the contact window TAC (or TAC′) is less than 50nm or even less than 20nm. The minimum distance D2 between the side walls sw3 and sw4 of the contact windows TAC and TAC′ and the adjacent stop structure 95 can be maintained at a level greater than 80nm, as shown in FIG. Figure 1 shown.

[0078] Figures 2A to 2G The various contact windows TAC and TAC′ shown can reduce the bottom width Wcb and Wcb′ with various etching chemicals. Using a heavier polymer during the etching process can cause the minimum deviation between the maximum width Wcx (Wcx′) of the bow of the contact TAC (or TAC′) and the bottom width Wcb (Wcb′) to expand from less than 20nm to more than 120nm, or even more than 140nm, and the contact TAC (or TAC′) has a tapered profile. In addition, in some embodiments, in order to reduce the contact sheet resistance, the bottom width Wcb (Wct′) of the contact window TAC (or TAC′) is maintained at more than 50nm, or even more than 10nm, and the minimum distance D2 between the contact windows TAC and TAC′ and the sidewalls sw3 and sw4 of the adjacent stop structure 95 can be maintained at a level of more than 80nm, as shown in FIG. Figure 1 shown.

[0079] Reference Figure 1In the embodiment of the present invention, the contact windows TAC and TAC′ pass through the dielectric layer 103 and the opening 99. In the embodiment where the stop structure 95 is made of a conductive material, in order to prevent the contact windows TAC and TAC′ from contacting the stop structure 95, an opening 99 is first formed in the stop structure 95 so that the contact windows TAC and TAC′ can pass through the opening 99.

[0080] In terms of technology, if the contact window TAC and TAC' are above Figure 2A , Figure 2D and Figure 2E In the standard type, double inner offset type and single inner offset type, within the process margin range, the contact windows TAC and TAC' are less likely to contact the stop structure 95, and the short circuit phenomenon is less likely to occur. However, if the contact windows TAC and TAC' are both offset outward (such as Figure 2B The double outward offset type shown in the figure) or one of the contact windows TAC and TAC' is offset outward (such as Figure 2C , Figure 2F or Figure 2G In the single offset type shown in the figure, the contact windows TAC and TAC′ are likely to contact with the stop structure 95 and cause a short circuit.

[0081] In order to reduce or avoid short circuit between the contact windows TAC and TAC′ and the stop structure 95, the top width Wt of the opening 99 can be increased. However, the extent to which the top width Wt of the opening 99 can be increased is very limited. This is because support columns DP are provided on the stop structure 95 on both sides of the opening 99, and the top width Wt of the opening 99 is limited by the distance D1 between the support columns DP. Since there must be enough support columns DP in the process to prevent the step structure SC from collapsing during the etching process of gate replacement, the distance D1 between the support columns DP cannot be increased arbitrarily. Therefore, the top width Wt of the opening 99 is limited by the distance D1 between the support columns DP and cannot be significantly increased.

[0082] FIG. 3A to FIG. 3E A schematic cross-sectional view of a stop structure showing the profiles of various openings 99A to 99E according to an embodiment of the present invention. The stop structure 95 having openings 99A to 99E can reduce or avoid contact with the contact window TAC and TAC′ (eg Figure 1The openings 99A to 99E may include a rectangular portion 97, a conical portion 96, or a combination thereof. The openings 99A to 99E may be funnel-shaped, inverted funnel-shaped, or bowl-shaped. The support posts DP pass through the dielectric layer 103 and land on the stop structure 95, or even extend into part of the stop structure 95. The top width Wt of the openings 99A to 99E is less than the distance D1 between the support posts DP. The bottom angle α of some of the openings 99A to 99E is 84° to 86°, or even 90°. In some embodiments, the bottom angle α of other openings 99A to 99E may be greater than 90°. The ratio of the distance D1 between the support posts DP to the top width Wt of the openings 99A to 99E is in the range of 1.03 to 1.15, and the ratio of the top width Wt of the openings 99A to 99E to the bottom width Wb of the openings 99A to 99E is in the range of 1.1 to 0.9.

[0083] Reference Figure 3A The middle width Wm of the opening 99A is not equal to the top width Wt, and the middle width Wm is not equal to the bottom width Wb. The opening 99A includes a tapered portion 96 that tapers from top to bottom (toward the substrate 10). The bottom angle α of the opening 99A is 84° to 86°.

[0084] Reference Figure 3B The middle width Wm of the opening 99B is equal to the top width Wt, and the middle width Wm is equal to the bottom width Wb. The opening 99B includes a rectangular portion 97. The bottom angle α of the opening 99B is 90°.

[0085] Reference Figure 3C , the top width Wt of the opening 99C is equal to the middle width Wm. The middle width Wm is not equal to the bottom width Wb, and the middle width Wm is greater than the bottom width Wb. The opening 99B includes a rectangular portion 97 and a tapered portion 96. The tapered portion 96 is closer to the base 10 than the rectangular portion 97, and the tapered portion 96 gradually tapers toward the base 10. The bottom angle α of the opening 99C is 84° to 86°.

[0086] Reference Figure 3D , the middle width Wm of the opening 99D is equal to the bottom width Wb. The top width Wt is not equal to the middle width Wm, and the top width Wt is greater than the middle width Wm. The rectangular portion 97 is closer to the base 10 than the tapered portion 96, and the tapered portion 96 gradually tapers toward the base 10. The bottom angle α of the opening 99D is 90°.

[0087] Reference Figure 3E , the middle width Wm of the opening 99E is equal to the top width Wt. The middle width Wm is not equal to the bottom width Wb, and the bottom width Wb is greater than the middle width Wm. The cone 96 is closer to the base 10 than the rectangular portion 97, and the cone 96 gradually widens toward the base 10. The bottom angle α of the opening 99E is greater than 90°.

[0088] FIG. 4A to FIG. 4C Schematic cross-sectional view showing a stop structure and a contact window according to some embodiments of the present invention.

[0089] Reference FIG. 4A to FIG. 4C The stop structure 95 has an opening 99A, and the sidewall of the opening 99A is covered by a liner 98. In some embodiments, the stop structure 95 includes polysilicon, doped polysilicon, or a combination thereof, and the liner 98 includes a dielectric material, such as SiON, SiC, SiOC, SiOCN, or a combination thereof.

[0090] Reference Figure 4A The contact windows TAC and TAC' pass through the dielectric layer 103 and the opening 99A and land on the conductive line 33. The contact windows TAC and TAC' are of the above-mentioned standard type and do not contact the liner 98, but are separated by a non-zero distance.

[0091] Reference Figure 4B , the contact windows TAC and TAC′ pass through the dielectric layer 103 and the opening 99A, and land on the conductive line 33. The contact windows TAC and TAC′ are not tilted, and are of the above-mentioned standard type. The contact windows TAC and TAC′ are both in contact with the liner 98. The contact window TAC contacts the liner 98 in a smaller portion, and the contact window TAC′ contacts the liner 98 in a larger portion. In the process of forming the contact window holes OP3 and OP3′ of the contact windows TAC and TAC′, the liner 98 can protect the stop structure 95 and prevent the stop structure 95 from being damaged by etching. Moreover, the liner 98 can be retained to prevent the contact windows TAC and TAC′ from short-circuiting with the stop structure 95.

[0092] Reference Figure 4C , the contact windows TAC, TAC' pass through the dielectric layer 103 and the opening 99A, and land on the conductive line 33. The contact windows TAC, TAC' are offset and belong to the above-mentioned single external offset type. The contact window TAC is not tilted, does not contact the liner 98, and is separated from the liner 98 by a large distance. The contact window TAC' is offset outward and is seriously tilted, and has a large area of ​​contact with the liner 98. Similarly, in the process of forming the contact window holes OP3 and OP3' of the contact windows TAC, TAC', the liner 98 can protect the stop structure 95 and prevent the stop structure 95 from being damaged by etching.

[0093] The above description is based on a 3D NAND flash memory as an example, however, the present invention is not limited thereto and can also be applied to other 3D flash memories, such as a 3D NOR flash memory.

[0094] The embodiments of the present invention design the opening of the stop structure to have various contours and angles, or form a liner on the sidewall, so that even if the contact window is offset or tilted, the occurrence of short circuit can be reduced or prevented. In this way, the yield of the memory element can be improved.

Claims

1. A memory element, comprising: substrate; An internal connection structure, located above the substrate; A step structure, located above the inner connecting structure; A dielectric layer, located above the interconnect structure and covering the stepped structure; A stop structure, located between the inner connection structure and the step structure, and between the inner connection structure and the dielectric layer, the stop structure having an opening to expose the inner connection structure; A first contact window extends through the dielectric layer and the opening and is connected to an inner connection of the inner connection structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening. 2 . The memory element according to claim 1 , wherein the opening comprises a rectangular portion and a tapered portion, and the rectangular portion and the tapered portion form a funnel shape, an inverted funnel shape, or a bowl shape. 3 . The memory element according to claim 2 , wherein the tapered portion is closer to the base than the rectangular portion, and the tapered portion tapers toward the base. 4 . The memory element according to claim 2 , wherein the tapered portion is closer to the base than the rectangular portion, and the tapered portion gradually becomes wider toward the base. 5 . The memory element according to claim 2 , wherein the rectangular portion is closer to the base than the tapered portion, and the tapered portion tapers toward the base. 6 . The memory device according to claim 1 , further comprising a second contact window extending through the dielectric layer and the opening and connected to the interconnect of the interconnect structure. 7 . The memory element according to claim 6 , wherein a bottom distance between the first contact window and the second contact window is greater than a top distance between the first contact window and the second contact window. 8 . The memory device according to claim 7 , wherein the first contact window and the second contact window are tilted to different degrees. 9 . The memory device according to claim 6 , wherein a bottom distance between the first contact window and the second contact window is smaller than a top distance between the first contact window and the second contact window, and the difference ranges from 1 nm to 50 nm.

10. A memory element comprising: substrate; An internal connection structure, located above the substrate; A step structure, located above the inner connecting structure; A dielectric layer, located above the interconnect structure and covering the stepped structure; A stop structure, located between the inner connection structure and the step structure, and between the inner connection structure and the dielectric layer, the stop structure having an opening to expose the inner connection structure; A first contact window and a second contact window extending through the dielectric layer and the opening and connected to an inner connection of the inner connection structure; as well as A plurality of lining layers are located on the side walls of the opening. 11 . The memory device according to claim 10 , wherein the plurality of liner layers are spaced apart from the first contact window and the second contact window by a non-zero distance. 12 . The memory element according to claim 10 , wherein the first contact window is spaced apart from an adjacent liner by a non-zero distance, and the second contact window is in contact with the adjacent liner. 13 . The memory element according to claim 10 , wherein a bottom distance between the first contact window and the second contact window is greater than a top distance between the first contact window and the second contact window. The memory element according to claim 13 , wherein the first contact window and the second contact window are tilted to different degrees.

15. The memory element of claim 10, wherein the stopping structure comprises a conductor material and the plurality of liner layers comprises a dielectric material. 16 . The memory element according to claim 10 , wherein the stop structure comprises polysilicon, and the plurality of liner layers comprises at least one of SiON, SiC, SiOC, and SiOCN.

17. The memory element of claim 10, further comprising a plurality of support posts extending through the dielectric layer and landing on the stop structure adjacent to the plurality of liner layers.

18. A memory element comprising: substrate; An internal connection structure, located above the substrate; A step structure, located above the inner connecting structure; A dielectric layer, located above the interconnect structure and covering the stepped structure; A stop structure, located between the inner connection structure and the step structure, and between the inner connection structure and the dielectric layer, the stop structure having an opening to expose the inner connection structure; as well as A first contact window and a second contact window extend through the dielectric layer and the opening and are connected to the inner connection of the inner connection structure. The bottom angle of the opening is 84° to 86° or greater than 90°.

19. The memory element of claim 18, further comprising: A plurality of support posts extend through the dielectric layer and land on the stop structure around the opening. 20 . The memory element of claim 19 , wherein a ratio of a distance of the plurality of support pillars to a top width of the opening ranges from 1.03 to 1.15, and a ratio of the top width of the opening to a bottom width of the opening ranges from 1.1 to 0.9.

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