Asymmetric groove SiC MOSFET structure capable of improving short circuit capability

Abstract

An asymmetric trench SiC MOSFET structure capable of improving short circuit capability comprises a substrate, two opposite sides of the substrate are respectively a drain electrode and a drift region, one side of the drift region far away from the substrate is provided with a current expansion layer, one side of the current expansion layer far away from the drift region is provided with a first P well, a P base region, a gate oxide layer and a second P well, the first P well and the second P well are located at two ends and are asymmetric, and the gate oxide layer is arranged between the first P well and the second P well. One side, far away from the current expansion layer, of the grid electrode is flush with the gate oxide layer to form an asymmetric structure, and other surfaces of the grid electrode are surrounded by the gate oxide layer except the side far away from the current expansion layer; the P base region serves as a device channel structure, an N base region is arranged on the side, away from the current expansion layer, of the P base region, a first N + source region and a P + source region are arranged on the side, away from the P base region, of the N base region, a second N + source region is arranged on the side, away from the current expansion layer, of the second P well, and the P + source region, the N base region and the P base region form a JFET. According to the invention, the short-circuit saturation current can be reduced, the short-circuit tolerance time is longer, the bottom of the trench gate is better protected, and the electric field is lower.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to an asymmetric trench SiC MOSFET structure with improved short-circuit capability. Background Art

[0002] SiC power MOSFETs are widely used in medium and high voltage fields, but they have been plagued by reliability issues due to the relatively high current density and electric field in practice. For devices with trench structures, since the trench gate goes deep into the drift region, the gate oxide layer is subjected to more severe electrical stress than the planar gate oxide layer, making the trench device more fragile and showing different damage phenomena. Among the stresses that SiC MOSFET may be subjected to during application, short-circuit stress is the most serious one. However, this is inevitable due to misoperation caused by oscillation and delay during the switching process. When in a short-circuit state, high drain-source voltage and saturation current are applied to the device at the same time, resulting in extremely high power consumption of the SiC power MOSFET. This severe stress may lead to degradation or even failure. In short, the existing structure has the following main problems:

[0003] 1. The cell pitch of the double trench structure is difficult to reduce and the short circuit withstand time is very short.

[0004] 2. The asymmetric trench structure requires an ultra-high energy implantation process, and the short-circuit withstand time is better than that of the double trench but is still limited.

[0005] To address this problem, the prior art has proposed many new short-circuit reinforcement structures to improve the short-circuit withstand time of the device, but these structures are mostly based on SiC planar gate MOSFETs, and lack improvement and research on the SiC trench gate MOSFETs that are also widely used. Although these structures have improved the short-circuit withstand time to a certain extent, this is mainly achieved by sacrificing part of the device's conduction capability. Summary of the invention

[0006] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide an asymmetric trench SiC MOSFET structure with improved short-circuit capability, so that on the basis of the asymmetric trench structure, the transfer characteristics can be made equivalent to those of the asymmetric trench structure, while improving the short-circuit tolerance of the device and enhancing the robustness of the device.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is:

[0008] An asymmetric trench SiC MOSFET structure for improving short-circuit capability comprises a substrate, wherein two opposite sides of the substrate are respectively a drain and a drift region, a current expansion layer is arranged on a side of the drift region away from the substrate, a P-well 1, a P-base region, a gate oxide layer and a P-well 2 are arranged on a side of the current expansion layer away from the drift region, the P-well 1 and the P-well 2 are located at two ends and are asymmetric, a side away from the current expansion layer is flush with the gate oxide layer to form an asymmetric structure, and except for the side away from the current expansion layer, the remaining sides of the gate are surrounded by the gate oxide layer;

[0009] The P base region serves as a device channel structure, and an N base region is arranged on the side away from the current spreading layer, an N+ source region 1 and a P+ source region are arranged on the side of the N base region away from the P base region, and an N+ source region 2 is arranged on the side of the P well 2 away from the current spreading layer. The P+ source region, the N base region and the P base region form a JFET.

[0010] In one embodiment, the distance between the drift region and the P-well 1 and the P-well 2 is a, the distance between the drift region and the P-base region is b, and the distance between the drift region and the gate oxide layer is c, where a<c<b.

[0011] In one embodiment, a portion of the gate oxide layer near the drift region is connected to the current spreading layer, and another portion is connected to the P-well 2, that is, the P-well 2 extends to a side of the trench near the current spreading layer.

[0012] In one embodiment, the current spreading layer has the same doping type as the drift region, but has a different doping concentration from the drift region.

[0013] In one embodiment, the N+ source region 1 is connected to the P well 1, the P+ source region is connected to the gate oxide layer, the N+ source region 2 is connected to the gate oxide layer, and the sides of the N+ source region 1, the P+ source region and the N+ source region 2 away from the current spreading layer are all flush with the gate oxide layer.

[0014] In one embodiment, the doping concentration of the drift region is 5*10 15 cm -3 ~1*10 16 cm -3 , the doping concentration of the P base region is 1*10 16 cm -3 ~5*10 16 cm -3 , the doping concentration of the current spreading layer is 1*10 16 cm -3 ~1*10 17 cm -3 .

[0015] The present invention defines the direction from P well 1 to P well 2 as the device width, and the direction from the drain to the gate as the device thickness. In one embodiment, the device width is 3 μm, the thickness of the drift region is 13 μm, the thickness of the gate oxide layer surrounding the gate is 75 nm, the width of the N+ source region 1 and the N+ source region 2 are both 0.5 μm, and the thickness is 0.2 μm, the width of the P+ source region is 0.25 μm, and the thickness is 0.2 μm, the width of the N base region is 0.55 μm, and the thickness is 0.1 μm, the width of the N base region is 0.55 μm, and the thickness is 0.4 μm, and the thickness of the current spreading layer is 0.8 μm.

[0016] The doping concentration of the substrate is 1*10 20 cm -3 , the doping concentration of the drift region is 1*10 16 cm -3 The doping concentration of P well 1 and P well 2 is 5*10 18 cm -3 , the doping concentration of N+ source region 1 and N+ source region 2 is 1*10 20 cm -3 , the doping concentration of the P+ source region is 1*10 20 cm -3 , the doping concentration of the N base region is 1*10 19 cm -3 , the doping concentration of the P base region is 1.2*10 16 cm -3 The doping concentration of the current spreading layer is 5*10 16 cm -3 , the device achieves a blocking voltage of over 1000V.

[0017] The present invention also provides a method for preparing the asymmetric trench SiC MOSFET structure with improved short-circuit capability, the steps being as follows:

[0018] Step 1, selecting a wafer with a current spreading layer, a drift region and a substrate, and forming a P-well 1 and a P-well 2 on the current spreading layer through an ion implantation process;

[0019] Step 2, forming a P base region on the current spreading layer through an ion implantation process;

[0020] Step 3, forming an N-base region on the P-base region through an ion implantation process;

[0021] Step 4, forming a P+ source region on the N base region through an ion implantation process;

[0022] Step 4, forming an N+ source region 1 on the N base region and the P well 1, and forming an N+ source region 2 on the P well 2 by an ion implantation process;

[0023] Step 5, high temperature annealing after ion implantation to activate doping;

[0024] Step 6, performing trench gate etching on the P+ source region, the N base region, the P base region, the N+ source region 2, the P well 2 and the current extension layer to form a gate region;

[0025] Step 7, depositing a gate oxide layer in the gate region to form a gate oxide, followed by annealing;

[0026] Step 8, forming source-drain ohmic contacts, followed by annealing.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. Due to the existence of JFET, when the drain-source voltage reaches 400V and above, the current channel in the JFET region becomes narrower and the current decreases. Therefore, the present invention reduces the short-circuit (since the device has no load, the drain-source voltage reaches hundreds of volts) saturation current and the short-circuit tolerance time is longer.

[0029] 2. Due to the existence of the current extension layer, the current path under the channel is optimized and the thermal stress inside the device is reduced. Therefore, the bottom of the trench gate is better protected, the electric field is lower, and the thermal stress is smaller. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the overall structure of the present invention.

[0031] Figure 2 It is a schematic diagram of the top structure of the present invention.

[0032] Figure 3 It is a schematic diagram of the ATMOS structure in the prior art.

[0033] Figure 4 The present invention and Figure 3 Schematic diagram comparing the transfer characteristics of the two ATMOS structures.

[0034] Figure 5 The present invention and Figure 3 Schematic diagram comparing the output characteristics of the two ATMOS structures.

[0035] Figure 6 The present invention and Figure 3 Schematic diagram comparing the blocking characteristics of the two ATMOS structures.

[0036] Figure 7 The present invention and Figure 3 Schematic diagram comparing the short-circuit characteristics of two ATMOS structures.

[0037] Figure 8 The present invention and Figure 3 Schematic diagram comparing the short-circuit temperature characteristics of two ATMOS structures. DETAILED DESCRIPTION

[0038] The embodiments of the present invention are described in detail below with reference to the accompanying drawings and examples.

[0039] Silicon carbide (SiC) power MOSFETs have faster switching speeds, lower switching losses, and a higher operating temperature range. However, due to their greater power density and smaller chip size than Si IGBTs, SiC MOSFETs have a shorter short-circuit withstand time.

[0040] On the other hand, SiC trench gate MOSFET has lower specific on-resistance, narrower cell pitch, and higher channel mobility compared to planar gate MOSFET. However, the high electric field in the gate oxide layer at the trench corners causes device degradation and even device failure.

[0041] To this end, the present invention provides an asymmetric trench SiC MOSFET capable of improving short-circuit capability. Based on the asymmetric trench structure, the short-circuit withstand time of the device is improved by controlling the electron conduction path under different bus voltages. Unlike the traditional asymmetric trench structure, the present invention improves the source region, channel region and drift region.

[0042] For details, please refer to Figure 1 and Figure 2 As shown, the SiC MOSFET of the present invention has a drain on the lower side of its substrate and a drift region on the upper side. A current expansion layer is provided on the upper side of the drift region, and the design of the current expansion layer can make the current more evenly distributed at the top of the drift region, effectively avoiding the current crowding phenomenon. It is helpful to improve the drift region resistance, thereby improving the overall performance of the device. P-well one, P-base region, gate region and P-well two are provided on the upper side of the current expansion layer. The P-well is used to ease the electric field at the corner of the groove. Specifically, P-well one and P-well two are located at both ends, and the two are asymmetrically designed, with the P-base region and the gate region located in the middle. Among them, P-well one can play the role of electric field modulation. By reasonably designing the structure and position of P-well one, the electric field distribution inside the device can be optimized, the electric field strength in the oxide layer at the bottom of the gate groove can be reduced, and the reliability and breakdown voltage of the device can be improved. P-well two can also play the role of electric field modulation. By reasonably designing the distance between P-well two and P-well one, the electric field strength in the oxide layer at the bottom of the gate groove can be further reduced.

[0043] In the structure of the present invention, the P base region is adjacent to the P well 1 and the gate region, and the gate region is adjacent to the P well 2 and the P base region. The tops of the P well 1, the P well 2 and the gate region are flush, forming an asymmetric trench gate structure. The gate region includes a gate oxide layer and a gate, and except for the top surface, the remaining surfaces of the gate are surrounded by the gate oxide layer.

[0044] In the structure of the present invention, the P base region is used as a device channel structure, and an N base region is arranged on its upper side, and an N+ source region 1 and a P+ source region are arranged on the upper side of the N base region. The N+ source region 1 is an N-type region with a high doping concentration, which serves as a supply source of electrons and provides a large number of electrons for the channel. When the gate voltage is high enough, the electrons in the N+ source region 1 are injected into the channel to form a current. The high doping concentration of the N+ source region 1 can reduce the source resistance, reduce the resistance to current transmission, and improve the conductive characteristics and response speed of the device. Among them, the P+ source region, N base region and P base region form a JFET. The JFET changes the conduction path of electrons. The current flowing through the N base region will be affected by the drain-source voltage. When the drain-source voltage reaches the JFET channel, the depletion layer widens and the current channel narrows due to the increase in voltage at one end (typically above 200V), the electric field strength at one end of the N base region close to the gate region is high, causing the P+ source region and the N base region depletion layer to widen, and the P base region and the N base region depletion layer to widen, thereby reducing the conduction path of electrons and changing the saturation current when the device is short-circuited. When the device is short-circuited, the electrons pass through the N+ source region 1 through the N base region, and then enter the vertical channel P base region, flowing through the current expansion layer, drift region, substrate, and finally reaching the drain end. For example, the N+ source region 1 is connected to the P well 1, and the P+ source region is connected to the gate oxide layer, and the top is flush.

[0045] In the embodiment of the present invention, the doping type of the current spreading layer is the same as that of the drift region, but the doping concentration is different from that of the drift region. The doping concentration of the current spreading layer can be adjusted to 1*10 16 cm -3 Up to 1*10 17 cm -3 The current spreading layer changes the on-resistance of the device by optimizing the current path. The uniform current distribution helps reduce the thermal stress inside the device, thereby improving the thermal stability and reliability of the device.

[0046] In an embodiment of the present invention, an N+ source region 2 is provided on the upper side of a partial area of ​​the P-well 2, and the N+ source region 2 is flush with the top of the P-well 2 and connected to the gate region. The design of the N+ source region 2 helps to optimize the electric field distribution inside the device. The electric field peak is effectively transferred from the gate dielectric layer to the shielding layer (P-well 2), thereby reducing the electric field strength borne by the gate dielectric layer and improving the breakdown voltage and reliability of the device. In terms of manufacturing process, the N+ source region 2 of the asymmetric trench SiC MOSFET can be compatible with other process steps, such as ion implantation, annealing, etc. This helps to simplify the manufacturing process and improve production efficiency and yield.

[0047] In the embodiment of the present invention, the distance between the bottom sides of the P-well 1 and the P-well 2 and the drift region is equal and greater than the distance between the gate oxide layer and the drift region, while the distance between the P-base region and the drift region is the smallest.

[0048] In the embodiment of the present invention, a portion of the gate oxide layer near the drift region is connected to the current spreading layer, and the other portion is connected to the P-well 2, that is, the P-well 2 extends to the lower side of the trench and can play the role of a body diode. The gate of the present invention adopts a trench structure, so the channel on the side of the trench gate is vertical. Figure 1 and Figure 2 In the structure shown, P-well 1 is located at the left end and P-well 2 is located at the right end. P-well 1 and P-well 2 are asymmetric in overall structure. P-well 2 completely surrounds the lower right corner of the trench gate, which can shield the electric field and protect the oxide at the corner of the gate. The left side of the bottom of P-well 2 is close to P-well 1, and works together with P-well 1 to reduce the electric field at the lower left corner of the gate oxide, thereby protecting the trench gate oxide.

[0049] The SiC MOSFET structure of the present invention has the following preparation process:

[0050] 1. Select a wafer with a current spreading layer / drift region / substrate.

[0051] 2. Injection and formation of P-WELL1 and P-WELL2.

[0052] 3. P base region injection and formation.

[0053] 4. N-base region implantation and formation.

[0054] 5. P+ source region injection and formation.

[0055] 6. N+ source region implantation and formation.

[0056] 7. Post-annealing after ion implantation.

[0057] 8. Groove gate etching forms the gate region.

[0058] 9. After the oxide layer is deposited to form gate oxide, annealing is performed.

[0059] 10. Form source-drain ohmic contacts and anneal.

[0060] All of the above steps can be implemented through existing technologies and will not be described in detail here.

[0061] Figure 3 The figure shows an existing asymmetric trench structure (ATMOS). The present invention simulates and analyzes the static characteristics of the device based on the Sentaurus semiconductor numerical analysis tool and compares it with the traditional asymmetric trench structure. For comparison, the present invention provides a specific embodiment of the following parameters, except for Figure 3 Except for the parts added on the structural basis, the doping concentration in the remaining areas remains consistent.

[0062] The device width is 3 μm. In order to achieve a blocking voltage of more than 1000 V, the doping concentration and thickness of the drift region are selected to be 1*10 16 cm -3 and 13μm. The thickness of the gate oxide layer is selected to be 75nm. The doping concentration of the P well is 5*10 18 cm -3 , the substrate doping concentration is 1*10 20 cm -3 The width of the N+ source region is 0.5μm, the thickness is 0.2μm, and the doping concentration is 1*10 20 cm -3 The width of the P+ source region is 0.25μm, the thickness is 0.2μm, and the doping concentration is 1*10 20 cm -3 The width of the N base region is 0.55 μm, the thickness is 0.1 μm, and the doping concentration is 1*10 19 cm -3 The width of the P base region is 0.55 μm, the thickness is 0.4 μm, and the doping concentration is 1.2*10 16 cm -3 The thickness of the current spreading layer is 0.8 μm and the doping concentration is 5*10 16 cm -3 .

[0063] The device material of the embodiment of the present invention is silicon dioxide for the gate oxide layer, aluminum for the drain-source contact, and other materials can all be silicon carbide.

[0064] Figure 4 The figure shows the transfer characteristics comparison between the structure of the present invention and the ATMOS structure. Due to the presence of JFET, the on-resistance of the new structure is different from that of ATMOS. By adjusting the thickness of JFET and the doping concentration of the current spreading layer, the transfer characteristics of the new structure and ATMOS can be basically the same. Figure 5 The figure shows the output characteristics comparison between the structure of the present invention and the ATMOS structure. Under large drain-source voltage, the output characteristics of the device are obviously different from those of ATMOS due to the narrowing of the electron channel. Under the same drain-source voltage, the higher the drain voltage, the greater the current difference between the new structure and the ATMOS structure. Figure 6 The figure shows the blocking characteristics comparison between the structure of the present invention and the ATMOS structure. Due to the existence of the current spreading layer, the breakdown voltage of the new structure is lower than that of the ATMOS structure. Figure 7 The figure shows the short-circuit characteristics comparison between the structure of the present invention and the ATMOS structure. Under the short-circuit condition of drain-source voltage of 400V, gate-source voltage of 18V and short-circuit pulse of 10μs, the new structure has lower short-circuit peak current and lower short-circuit energy. Figure 8The figure shows the short-circuit temperature variation characteristics of the structure of the present invention and the ATMOS structure. The temperature of the structure of the present invention is lower during the short-circuit process. Therefore, under the same short-circuit working conditions as the ATMOS structure, the structure of the present invention has a smaller current, smaller short-circuit energy, smaller heat generated, and lower thermal stress inside the device, so it has a longer short-circuit tolerance time.

[0065] In summary, the structure of the present invention suppresses the current of the output characteristic under high voltage without affecting the transfer characteristic, so the short-circuit peak current in the short-circuit condition is reduced, thereby increasing the short-circuit withstand time.

Claims

1. An asymmetric trench SiC MOSFET structure with improved short-circuit capability, comprising a substrate, wherein two opposite sides of the substrate are a drain and a drift region, respectively, and characterized in that: A current spreading layer is arranged on a side of the drift region away from the substrate, a P-well 1, a P-base region, a gate oxide layer and a P-well 2 are arranged on a side of the current spreading layer away from the drift region, the P-well 1 and the P-well 2 are located at two ends and are asymmetrical, the side away from the current spreading layer is flush with the gate oxide layer to form an asymmetric structure, and except for the side away from the current spreading layer, the other sides of the gate are surrounded by the gate oxide layer; The P base region serves as a device channel structure, and an N base region is arranged on the side away from the current spreading layer, an N+ source region 1 and a P+ source region are arranged on the side of the N base region away from the P base region, and an N+ source region 2 is arranged on the side of the P well 2 away from the current spreading layer. The P+ source region, the N base region and the P base region form a JFET.

2. The asymmetric trench SiC MOSFET structure with improved short-circuit capability according to claim 1, characterized in that: The distance between the drift region and the P well 1 and the P well 2 is a, the distance between the drift region and the P base region is b, and the distance between the drift region and the gate oxide layer is c, where a<c<b.

3. The asymmetric trench SiC MOSFET structure with improved short-circuit capability according to claim 1, characterized in that: A portion of the gate oxide layer near the drift region is connected to the current spreading layer, and another portion is connected to the second P-well, that is, the second P-well extends to a side of the trench near the current spreading layer.

4. The asymmetric trench SiC MOSFET structure with improved short-circuit capability according to claim 1, characterized in that: The doping type of the current spreading layer is the same as that of the drift region, but the doping concentration is different from that of the drift region.

5. The asymmetric trench SiC MOSFET structure with improved short-circuit capability according to claim 1, characterized in that: The N+ source region 1 is connected to the P well 1, the P+ source region is connected to the gate oxide layer, the N+ source region 2 is connected to the gate oxide layer, and the sides of the N+ source region 1, the P+ source region and the N+ source region 2 away from the current expansion layer are all flush with the gate oxide layer.

6. The asymmetric trench SiC MOSFET structure with improved short-circuit capability according to claim 1, characterized in that: The direction from P well 1 to P well 2 is defined as the device width, and the direction from drain to gate is defined as the device thickness. The device width is 3μm, the thickness of the drift region is 13μm, the thickness of the gate oxide layer surrounding the gate is 75nm, the width of N+ source region 1 and N+ source region 2 are both 0.5μm, and the thickness is 0.2μm, the width of the P+ source region is 0.25μm, and the thickness is 0.2μm, the width of the N base region is 0.55μm, and the thickness is 0.1μm, the width of the N base region is 0.55μm, and the thickness is 0.4μm, and the thickness of the current spreading layer is 0.8μm.

7. The asymmetric trench SiC MOSFET structure with improved short-circuit capability according to claim 1, characterized in that: The doping concentration of the drift region is 5*10 15 cm -3 ~1*10 16 cm -3 , the doping concentration of the P base region is 1*10 16 cm -3 ~5*10 16 cm -3 , the doping concentration of the current spreading layer is 1*10 16 cm -3 ~1*10 17 -3 cm.

8. The asymmetric trench SiC MOSFET structure with improved short-circuit capability according to claim 1, characterized in that: The doping concentration of the substrate is 1*10 20 cm -3 , the doping concentration of the drift region is 1*10 16 cm -3 The doping concentration of P well 1 and P well 2 is 5*10 18 cm -3 , the doping concentration of N+ source region 1 and N+ source region 2 is 1*10 20 cm -3 , the doping concentration of the P+ source region is 1*10 20 cm -3 , the doping concentration of the N base region is 1*10 19 cm -3 , the doping concentration of the P base region is 1.2*10 16 cm -3 The doping concentration of the current spreading layer is 5*10 16 cm -3 , the device achieves a blocking voltage of over 1000V.

9. A method for preparing an asymmetric trench SiC MOSFET structure with improved short-circuit capability as described in claim 1, comprising the following steps: Step 1, selecting a wafer with a current spreading layer, a drift region and a substrate, and forming a P-well 1 and a P-well 2 on the current spreading layer through an ion implantation process; Step 2, forming a P base region on the current spreading layer through an ion implantation process; Step 3, forming an N-base region on the P-base region through an ion implantation process; Step 4, forming a P+ source region on the N base region through an ion implantation process; Step 4, forming an N+ source region 1 on the N base region and the P well 1, and forming an N+ source region 2 on the P well 2 by an ion implantation process; Step 5, annealing after ion implantation to activate doping; Step 6, performing trench gate etching on the P+ source region, the N base region, the P base region, the N+ source region 2, the P well 2 and the current extension layer to form a gate region; Step 7, depositing a gate oxide layer in the gate region to form a gate oxide, followed by annealing; Step 8, forming source-drain ohmic contacts, followed by annealing.

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