Layout layout structure of power MOSFET (metal-oxide-semiconductor field effect transistor) gate driving chip

Abstract

A layout structure of a power MOSFET gate drive chip relates to the field of integrated circuit design, and comprises a power supply module, a current mirror module, a logic control module, a bias module, a turn-on module and a turn-off module, the turn-on module comprises a charging NMOS group, and the turn-off module comprises a discharging NMOS group; the modules are interconnected through the third metal conductive layer M3, the fourth metal conductive layer M4 and the top metal conductive layer TM1; in the layout, a top metal conductive layer TM1 and a fourth metal conductive layer M4 which are interconnected with a port VDD1 and a port GND surround the layout, so that good stability is provided. According to the layout structure, the top metal TM1 interconnected with the port Vout and the port GND2 is electrically connected in a short distance, so that the parasitic inductance and the parasitic resistance are reduced on the basis of realizing functions, the area required by layout is reduced while the high through-current capability is realized, and the requirement of manufacturers in the industry on high power density of power electronic devices is met.

Description

Technical Field

[0001] The patent of this invention relates to the field of integrated circuit design, and specifically to a layout structure of a power MOSFET gate driver chip. Background Art

[0002] Power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is an indispensable key power device in power electronic devices. It is the core of power conversion and circuit control in electronic devices and is used to drive various types of motor loads and electronic loads. The power MOSFET gate driver chip integrates circuit modules such as power module, current mirror module, logic control module, bias module, turn-on module, and turn-off module. Among them, the turn-on module and the turn-off module have large currents and occupy large areas. Therefore, the layout of the driver chip is particularly critical to improving the power density. Therefore, in order to meet the high power density requirements of power electronic devices by industry manufacturers, it is necessary to design a new layout scheme to reduce the area required for layout while achieving high current capacity. Summary of the invention

[0003] The present invention is to meet the high power density requirements of power electronic devices by industry manufacturers, and also to meet the requirements of designing a new layout scheme to achieve high current capacity while reducing the area required for layout. A layout structure of a power MOSFET gate driver chip is provided.

[0004] The technical solution adopted by the present invention is:

[0005] A layout structure of a power MOSFET gate drive chip, comprising a power module (1), a logic control module (2), a current mirror module (3), a bias module (4), an opening module (5), a closing module (6), an input port Vin (10), an input port VDD1 (11), an input port VDD2 (12), an output port Vout (13), a port GND (14), a port PARA (15) and a port GND2 (16),

[0006] The input end of the power supply module (1) is connected to the port VDD1 (11), and the output end thereof is connected to the input end of the logic control module (2), the current mirror module (3), the bias module (4) and the port GND (14);

[0007] The input end of the logic control module (2) is connected to the input port Vin (10), and the output end thereof is connected to the input ends of the opening module (5), the closing module (6) and the port GND (14);

[0008] The input end of the current mirror module (3) is connected to the output end of the power module (1), and the output end thereof is connected to the input ends of the opening module (5), the closing module (6) and the port GND (14);

[0009] The input end of the bias module (4) is connected to the output end of the power module (1) and the port PARA (15), and the output end thereof is connected to the input ends of the opening module (5) and the closing module (6) and the port GND (14);

[0010] The opening module (5) comprises a charging NMOS group (NLDMOS1), the input end of the opening module (5) is connected to the output end of the logic control module (2), the output end of the bias module (4) and the input port VDD2 (12), and the output end of the opening module (5) is connected to the output port Vout (13) and the port GND (14);

[0011] The shutdown module (6) comprises a discharge NMOS group (NLDMOS2), an input end of which is connected to the output end of the logic control module (2), the output end of the bias module (4) and the port GND2 (16).

[0012] Further, it also includes a fourth metal conductive layer (M4) and a top metal conductive layer (TM1);

[0013] The input port Vin (10) is used to connect the switch PWM signal, and the input port Vin (10) is connected to the logic control module (2) through the fourth metal conductive layer (M4);

[0014] The port VDD1 (11) is used to connect the power supply voltage VDD1, the input port VDD1 (11) is connected to the top metal conductive layer (TM1) and is arranged around the inside, and is used to avoid the top metal conductive layer (TM1) through the fourth metal conductive layer (M4) above the opening module (5) and the closing module (6); the port VDD1 (11) is connected to the power module (1) through the top metal conductive layer (TM1);

[0015] The port VDD2 (12) is used to connect the supply voltage VDD2, and the input port VDD2 (12) is connected to the opening module (5) through the top metal conductive layer (TM1);

[0016] The port PARA (15) is used to connect an external input bias voltage, and the port PARA (15) is connected to the bias module (4) through a fourth metal conductive layer (M4);

[0017] The output port Vout (13) is used to connect to the gate of an external power MOSFET, and the output port Vout (13) is connected to the turn-on module (5) and the turn-off module (6) through the top metal conductive layer (TM1);

[0018] The port GND (14) is used to connect to the digital ground, and the port GND (14) is connected to the top metal conductive layer (TM1) and is arranged around the outside; the port GND (14) is connected to the power module (1), the logic control module (2), the current mirror module (3), the bias module (4) and the enable module (5) through the top metal conductive layer (TM1);

[0019] The port GND2 (16) is used to connect to the analog ground. The port GND2 (16) is connected to the top metal conductive layer (TM1) and is connected to the shutdown module (6) through the top metal conductive layer.

[0020] Furthermore, it also includes a second metal conductive layer (M2) and a third metal conductive layer (M3),

[0021] The power module (1) is connected to a port VDD1 (11) via a top metal conductive layer (TM1) above the power module (1); the power module (1) is connected to a logic control module (2), a current mirror module (3), and a bias module (4) via a fourth metal conductive layer (M4); the power module (1) is connected to a port GND (14) via a top metal conductive layer (TM1);

[0022] The logic control module (2) is connected to the power module (1) via a fourth metal conductive layer (M4) above the logic control module (2), connected to the input port Vin (10) via the fourth metal conductive layer, connected to the opening module (5) and the closing module (6) via the third metal conductive layer (M3), and connected to the port GND (14) via the top metal conductive layer (TM1);

[0023] The current mirror module (3), the current mirror module (3) is connected to the power module (1) through the fourth metal conductive layer (M4), connected to the bias module (4) through the second metal conductive layer (M2), and connected to the port GND (14) through the top metal conductive layer (TM1);

[0024] The bias module (4), the bias module (4) is connected to the power module (1) through the fourth metal conductive layer (M4), connected to the current mirror module (3) through the second metal conductive layer (M2), and connected to the port GND (14) through the top metal conductive layer (TM1);

[0025] The opening module (5) is connected to the port VDD2 (12) through the top metal conductive layer (TM1) above the opening module (5), connected to the logic control module (2) through the third metal conductive layer (M3), connected to the bias module (4) through the third metal conductive layer (M3), connected to the port GND (14) through the top metal conductive layer (TM1), and connected to the port Vout (13) through the top metal conductive layer (TM1);

[0026] The shutdown module (6) extends from the top of the shutdown module (6) to the top of the opening module (5) through the top metal conductive layer (TM1), and is connected to the port Vout (13) through the top metal conductive layer (TM1); is connected to the port GND2 (16) through the top metal conductive layer (TM1), is connected to the logic control module (2) through the third metal conductive layer (M3), and is connected to the bias module (4) through the third metal conductive layer (M3).

[0027] Furthermore, it also includes a hole (M4-TM1), and the charging NMOS group (NLDMOS1) in the opening module (5) includes multiple charging NMOS, whose drains extend through the fourth metal conductive layer (M4) to below the top metal conductive layer (TM1) connected to the upper port VDD2 (12), and complete the metal interconnection between the drain of the charging NMOS group and the port VDD2 (12) through the hole (M4-TM1).

[0028] Furthermore, the discharge NMOS group (NLDMOS2) in the shutdown module (6) includes a plurality of discharge NMOSs, the drain of which extends through the fourth metal conductive layer (M4) to below the top metal conductive layer (TM1) of the upper connection port Vout (13), and completes the metal interconnection between the drain of the discharge NMOS group and the output port Vout (13) through the hole (M4-TM1).

[0029] Furthermore, the port VDD1 (11) is not only arranged around the inner side by the top metal conductive layer (TM1), but also extends longitudinally to above the power module (1) through the top metal conductive layer (TM1);

[0030] The port VDD2 (12) extends longitudinally through the top metal conductive layer (TM1) to the top of the opening module (5), and the fourth metal conductive layer (M4) below it is interconnected with the top metal conductive layer (TM1) connected to the port VDD1 through the hole (M4-TM1);

[0031] The port Vout (13) extends laterally through the top metal conductive layer (TM1) to above the charging NMOS group (NLDMOS1) in the turn-on module (5), and then extends longitudinally to above the turn-off module (6);

[0032] The port GND (14) is not only arranged around the outside through the top metal conductive layer (TM1), but also extends longitudinally through the top metal conductive layer (TM1) to above the current mirror module (3) and the power module (1);

[0033] The port GND2 (16) extends laterally through the top metal conductive layer (TM1) to above the discharge NMOS group (NLDMOS2) in the shutdown module (6);

[0034] The power module (1) is horizontally extended through the fourth metal conductive layer (M4) through the current mirror module (3) and the logic control module (2), and vertically extended to the top of the bias module (4); and the port VDD1 (11) is vertically connected through the top metal conductive layer (TM1);

[0035] The logic control module (2) is longitudinally extended through the third metal conductive layer (M3) to the bias module (4), then transversely extended to the top of the shutdown module (6), and then longitudinally extended to the opening module (5);

[0036] The current mirror module (3) is horizontally extended to the power module (1) through the fourth metal conductive layer (M4); it is vertically extended to the bias module (4) through the second metal conductive layer (M2); and it is interconnected with the top metal conductive layer extending vertically from the port GND (14) through the top metal conductive layer (TM1);

[0037] The bias module (4) is longitudinally extended through the fourth metal conductive layer (M4) to the power module (1); the second metal conductive layer (M2) is longitudinally extended to the current mirror module (3); the third metal conductive layer (M3) is transversely extended to the shutdown module (6), and then longitudinally extended to the opening module (5); and the top metal conductive layer (TM1) is transversely connected to the top metal conductive layer (TM1) extending longitudinally from the port GND (14) through the top metal conductive layer (TM1);

[0038] The top metal conductive layer (TM1) is connected to the port VDD2 (12) vertically above the on module (5); the top metal conductive layer (TM1) is connected to the port Vout (13) horizontally; the top metal conductive layer (TM1) is interconnected with the output port Vout (13) and vertically extends to the top of the off module (6); a plurality of third metal conductive layers (M3) are firstly vertically extended to the top of the off module (6), and then horizontally extended to the top of the bias module (4) and the logic control module (2);

[0039] The shutdown module (6) is laterally connected to the port GND2 (16) through the top metal conductive layer (TM1) above, and is vertically extended to the top of the enable module (5) through the top metal conductive layer (TM1), and is interconnected with the top metal conductive layer (TM1) extending from the output port Vout (13); and is laterally extended to the top of the bias module (4) and the logic control module (2) through multiple third metal conductive layers (M3).

[0040] Furthermore, the current mirror module (3) is between the power module (1) and the logic control module (2); the bias module (4) is above the power module, the current mirror module and the logic control module; the enable module (5) is at the lower left of the layout, and the disable module is at the upper left of the layout; and the disable module (6) is above the enable module (5).

[0041] Furthermore, the port VDD1 (11), the port VDD2 (12), the port GND (14), the port GND2 (16), the port Vout (13), the power module (1), the logic control module (2), the current mirror module (3), the bias module (4), the turn-on module (5) and the turn-off module (6) are connected to the top metal conductive layer (TM1) and the fourth metal conductive layer (M4).

[0042] Beneficial effects: The present invention discloses a layout structure of a power MOSFET gate driver chip, which includes a power module, a current mirror module, a logic control module, a bias module, an opening module and a closing module, wherein the opening module includes a charging NMOS group, and the closing module includes a discharge NMOS group; the modules are interconnected through a third metal conductive layer M3, a fourth metal conductive layer M4 and a top metal conductive layer TM1; the top metal conductive layer TM1 and the fourth metal conductive layer M4 interconnected with the port VDD1 and the port GND in the layout surround the layout, providing good stability. The top metal TM1 interconnected with the port Vout and the port GND2 in the layout structure completes electrical connection at a short distance, reduces parasitic inductance and parasitic resistance on the basis of realizing the function, realizes high current capacity and reduces the area required for the layout, and meets the high power density requirements of industry manufacturers for power electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of the connection relationship of the layout structure of the power MOSFET gate driver chip according to an embodiment of the present invention;

[0044] Figure 2 A simplified schematic diagram of the layout structure of a power MOSFET gate driver chip according to an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of the metal interconnection of ports of a layout structure of a power MOSFET gate driver chip according to an embodiment of the present invention;

[0046] Figure 4 A schematic diagram of the metal interconnection between ports and modules of the layout structure of the power MOSFET gate driver chip according to an embodiment of the present invention;

[0047] Figure 5 A schematic diagram of the drain-source connection of NLDMOS1 in the enable module of the layout structure of the power MOSFET gate driver chip according to an embodiment of the present invention;

[0048] Figure 6 The diagram is a drain-source connection diagram of NLDMOS2 in a shutdown module of a layout structure of a power MOSFET gate driver chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following is combined with Figure 1-6 The technical solution of the embodiment of the present invention is further described.

[0050] The main purpose of the present invention is to provide a layout of a power MOSFET gate driver chip, aiming to achieve high current-carrying capacity through the layout while reducing the layout area, promoting the miniaturization of the driver chip, and meeting the high power density requirements of modern power electronic devices.

[0051] Embodiment 1

[0052] The present invention discloses a layout of a power MOSFET gate drive chip, including a power module, a logic control module, a current mirror module, a bias module, an opening module and a closing module. Figure 1-Figure 2 As shown, where:

[0053] The power module has an input end connected to the port VDD1, and an output connected to the logic control module, the current mirror module, the bias module and the port GND;

[0054] The logic control module has an input end connected to the port Vin, and an output connected to the opening module, the closing module and the port GND;

[0055] The current mirror module has an input end connected to the output of the power module, and an output connected to the opening module, the closing module and the port GND;

[0056] The bias module has an input connected to the output of the power module and the port PARA, and an output connected to the opening module, the closing module and the port GND;

[0057] The opening module comprises a charging NMOS group NLDMOS1, an input connected to the output of the logic control module, the output of the bias module and the port VDD2, and an output connected to the port Vout and the port GND;

[0058] The shutdown module comprises a discharge NMOS group NLDMOS2, an input of which is connected to the output of the logic control module and the output of the bias module, and an output of which is connected to the port GND2.

[0059] The layout of the power MOSFET gate driver chip includes an input port VDD, an input port Vin, an input port PARA, an output port Vout, an output port GND, and an output port GND2, wherein there is a criss-cross connection relationship of metal conductive layers, such as Figure 3 As shown, the specific performance is:

[0060] The port Vin inputs a PWM switch digital signal and is connected to a logic control module through a fourth metal conductive layer M4;

[0061] The port VDD1 inputs the supply voltage VDD1, connects to the top metal conductive layer TM1 and surrounds the layout on the inside, wherein the top metal conductive layer TM1 is avoided above the turn-on module and the turn-off module through the fourth metal conductive layer; the power module is connected through the top metal conductive layer TM1. Specifically, the port VDD1 not only surrounds the layout on the inside through the top metal conductive layer (TM1), but also extends vertically to the top of the power module through the top metal conductive layer;

[0062] The port VDD2 inputs the supply voltage VDD2 and is connected to the opening module through the top metal conductive layer TM1. Specifically, the port VDD2 extends longitudinally through the top metal conductive layer (TM1) to the top of the opening module, and the fourth metal conductive layer (M4) below it is interconnected with the top metal conductive layer (TM1) connected to the port VDD1 through the hole (M4-TM1);

[0063] The port PARA inputs a bias voltage and is connected to a bias module through a fourth metal conductive layer M4;

[0064] The port Vout outputs current to the gate of the external power MOSFET, and connects the on module and the off module through the top metal conductive layer TM1. Specifically, the port Vout extends horizontally through the top metal conductive layer TM1 to above the charging NMOS group NLDMOS1 in the on module, and then extends vertically to above the off module;

[0065] The port GND is connected to the digital ground, connected to the top metal conductive layer TM1 and surrounds the layout on the outside; the port GND is connected to the power module, the logic control module, the current mirror module, the bias module and the enable module through the top metal conductive layer TM1. Specifically, the port GND not only surrounds the layout on the outside through the top metal conductive layer TM1, but also extends vertically to the top of the current mirror module and the power module through the top metal conductive layer.

[0066] The port GND2 is connected to the analog ground, connected to the top metal conductive layer TM1, and connected to the shutdown module through the top metal conductive layer. Specifically, the port GND2 extends laterally through the top metal conductive layer TM1 to above the discharge NMOS group NLDMOS2 in the shutdown module.

[0067] In the layout of the power MOSFET gate driver chip, there is a crisscross metal conductive layer connection relationship between the modules, such as Figure 4 As shown, the specific performance is:

[0068] The power module is connected to port VDD1 through the top metal conductive layer TM1; connected to the logic control module, the current mirror module, and the bias module through the fourth metal conductive layer M4; and connected to port GND through the top metal conductive layer TM1. Specifically, the power module is extended horizontally through the fourth metal conductive layer M4 through the current mirror module and the logic control module, and vertically extends to the top of the bias module; and vertically connected to port VDD1 through the top metal conductive layer TM1;

[0069] The logic control module is connected to the power module through the fourth metal conductive layer M4, connected to the port Vin through the fourth metal conductive layer, connected to the opening module and the closing module through the third metal conductive layer M3, and connected to the port GND through the top metal conductive layer TM1. Specifically, the logic control module is longitudinally extended to the bias module through the third metal conductive layer M3, then laterally extended to the top of the closing module, and then longitudinally extended to the opening module again;

[0070] The current mirror module is connected to the power module through the fourth metal conductive layer M4, connected to the bias module through the third metal conductive layer, and connected to the port GND through the top metal conductive layer. Specifically, the current mirror module is horizontally extended to the power module through the fourth metal conductive layer M4; is vertically extended to the bias module through the third metal conductive layer M2; and is interconnected with the top metal conductive layer that is vertically extended to the port GND through the top metal conductive layer TM1;

[0071] The bias module is connected to the power module through the fourth metal conductive layer M4, connected to the current mirror module through the second metal conductive layer M2, and connected to the port GND through the top metal conductive layer. Specifically, the bias module is longitudinally extended to the power module through the fourth metal conductive layer M4; longitudinally extended to the current mirror module through the second metal conductive layer M2; transversely extended to the shutdown module through the third metal conductive layer M3, and then longitudinally extended to the opening module; and is interconnected with the top metal conductive layer longitudinally extended to the port GND through the top metal conductive layer TM1;

[0072] The opening module is connected to port VDD2 through the top metal conductive layer TM1, connected to the logic control module through the third metal conductive layer M3, connected to the bias module through the third metal conductive layer, connected to port GND through the top metal conductive layer TM1, and connected to port Vout through the top metal conductive layer TM1. Specifically, the opening module is connected to port VDD2 vertically through the top metal conductive layer TM1; the port Vout is horizontally connected through the top metal conductive layer; the top metal conductive layer TM1 is vertically extended to the top of the shutdown module through interconnection with port Vout; the third metal conductive layers M3 are firstly vertically extended to the top of the shutdown module, and then horizontally extended to the top of the bias module and the logic control module;

[0073] The shutdown module is extended to the top of the opening module through the top metal conductive layer TM1, and the top metal conductive layer is used to connect the port Vout; the top metal conductive layer TM1 is used to connect the port GND2, the third metal conductive layer M3 is used to connect the logic control module, and the third metal conductive layer M3 is used to connect the bias module. Specifically, the shutdown module is horizontally connected to the port GND2 through the top metal conductive layer TM1, and vertically extends to the top of the opening module through the top metal conductive layer TM1, and forms an interconnection with the top metal conductive layer extending the port Vout; and multiple third metal conductive layers M3 are used to horizontally extend to the bias module and the logic control module.

[0074] In the layout of the power MOSFET gate driver chip, the charging NMOS group NLDMOS1 included in the opening module is composed of multiple charging NMOS, and its drain extends through the fourth metal conductive layer M4 to the bottom of the top metal conductive layer TM1 connected to the upper port VDD2, and completes the metal interconnection between the drain of the charging NMOS and the port VDD through the hole M4-TM1, such as Figure 5 shown.

[0075] In the layout of the power MOSFET gate driver chip, the discharge NMOS group NLDMOS2 included in the shutdown module is composed of multiple discharge NMOS, and its drain extends through the fourth metal conductive layer M4 to below the top metal conductive layer TM1 connected to the upper port Vout, and completes the metal interconnection between the drain of the discharge NMOS and the port Vout through the hole M4-TM1, such as Figure 6 shown.

[0076] The current mirror module 3 is between the power module 1 and the logic control module 2; the bias module 4 is above the power module, the current mirror module and the logic control module; the turn-on module 5 is at the lower left of the layout, and the turn-off module is at the upper left of the layout; the turn-off module 6 is above the turn-on module 5.

[0077] The port VDD1 (11), the port VDD2 (12), the port GND (14), the port GND2 (16), the port Vout (13), the power module (1), the logic control module (2), the current mirror module (3), the bias module (4), the turn-on module (5) and the turn-off module (6) are connected to the top metal conductive layer (TM1) and the fourth metal conductive layer (M4).

[0078] The described embodiments are only part of the embodiments of the present invention and do not represent all the embodiments; all other embodiments obtained by those skilled in the art without making creative work are included in the protection scope of the embodiments of the present invention; but it is not limited to this, any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention should be included in the protection scope of the present invention.

[0079] In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "up", "down", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only simplified descriptions for the convenience of describing the present invention, rather than indicating or implying that a device or component must have a specific direction, be constructed and operate in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0080] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

Claims

1. A layout structure of a power MOSFET gate driver chip, the driver chip is used to drive an external power MOSFET, characterized in that: It includes a power module (1), a logic control module (2), a current mirror module (3), a bias module (4), an enable module (5), a shutdown module (6), an input port Vin (10), an input port VDD1 (11), an input port VDD2 (12), an output port Vout (13), a port GND (14), a port PARA (15) and a port GND2 (16). The input end of the power supply module (1) is connected to the port VDD1 (11), and the output end thereof is connected to the input end of the logic control module (2), the current mirror module (3), the bias module (4) and the port GND (14); The input end of the logic control module (2) is connected to the input port Vin (10), and the output end thereof is connected to the input ends of the opening module (5), the closing module (6) and the port GND (14); The input end of the current mirror module (3) is connected to the output end of the power module (1), and the output end thereof is connected to the input ends of the opening module (5), the closing module (6) and the port GND (14); The input end of the bias module (4) is connected to the output end of the power module (1) and the port PARA (15), and the output end thereof is connected to the input ends of the opening module (5) and the closing module (6) and the port GND (14); The opening module (5) comprises a charging NMOS group (NLDMOS1), the input end of the opening module (5) is connected to the output end of the logic control module (2), the output end of the bias module (4) and the input port VDD2 (12), and the output end of the opening module (5) is connected to the output port Vout (13) and the port GND (14); The shutdown module (6) comprises a discharge NMOS group (NLDMOS2), an input end of which is connected to the output end of the logic control module (2), the output end of the bias module (4) and the port GND2 (16).

2. The layout structure of a power MOSFET gate driver chip according to claim 1, characterized in that: It also includes a fourth metal conductive layer (M4) and a top metal conductive layer (TM1); The input port Vin (10) is used to connect the switch PWM signal, and the input port Vin (10) is connected to the logic control module (2) through the fourth metal conductive layer (M4); The port VDD1 (11) is used to connect the power supply voltage VDD1, the input port VDD1 (11) is connected to the top metal conductive layer (TM1) and is arranged around the inside, and is used to avoid the top metal conductive layer (TM1) through the fourth metal conductive layer (M4) above the opening module (5) and the closing module (6); the port VDD1 (11) is connected to the power module (1) through the top metal conductive layer (TM1); The port VDD2 (12) is used to connect the supply voltage VDD2, and the input port VDD2 (12) is connected to the opening module (5) through the top metal conductive layer (TM1); The port PARA (15) is used to connect an external input bias voltage, and the port PARA (15) is connected to the bias module (4) through a fourth metal conductive layer (M4); The output port Vout (13) is used to connect to the gate of an external power MOSFET, and the output port Vout (13) is connected to the turn-on module (5) and the turn-off module (6) through the top metal conductive layer (TM1); The port GND (14) is used to connect to the digital ground, and the port GND (14) is connected to the top metal conductive layer (TM1) and is arranged around the outside; the port GND (14) is connected to the power module (1), the logic control module (2), the current mirror module (3), the bias module (4) and the enable module (5) through the top metal conductive layer (TM1); The port GND2 (16) is used to connect to the analog ground. The port GND2 (16) is connected to the top metal conductive layer (TM1) and is connected to the shutdown module (6) through the top metal conductive layer.

3. The layout structure of a power MOSFET gate driver chip according to claim 2, characterized in that: It also includes a second metal conductive layer (M2) and a third metal conductive layer (M3), The power module (1) is connected to a port VDD1 (11) via a top metal conductive layer (TM1) above the power module (1); the power module (1) is connected to a logic control module (2), a current mirror module (3), and a bias module (4) via a fourth metal conductive layer (M4); the power module (1) is connected to a port GND (14) via a top metal conductive layer (TM1); The logic control module (2) is connected to the power module (1) via a fourth metal conductive layer (M4) above the logic control module (2), connected to the input port Vin (10) via the fourth metal conductive layer, connected to the opening module (5) and the closing module (6) via the third metal conductive layer (M3), and connected to the port GND (14) via the top metal conductive layer (TM1); The current mirror module (3), the current mirror module (3) is connected to the power module (1) through the fourth metal conductive layer (M4), connected to the bias module (4) through the second metal conductive layer (M2), and connected to the port GND (14) through the top metal conductive layer (TM1); The bias module (4), the bias module (4) is connected to the power module (1) through the fourth metal conductive layer (M4), connected to the current mirror module (3) through the second metal conductive layer (M2), and connected to the port GND (14) through the top metal conductive layer (TM1); The opening module (5) is connected to the port VDD2 (12) through the top metal conductive layer (TM1) above the opening module (5), connected to the logic control module (2) through the third metal conductive layer (M3), connected to the bias module (4) through the third metal conductive layer (M3), connected to the port GND (14) through the top metal conductive layer (TM1), and connected to the port Vout (13) through the top metal conductive layer (TM1); The shutdown module (6) extends from the top of the shutdown module (6) to the top of the opening module (5) through the top metal conductive layer (TM1), and is connected to the port Vout (13) through the top metal conductive layer (TM1); is connected to the port GND2 (16) through the top metal conductive layer (TM1), is connected to the logic control module (2) through the third metal conductive layer (M3), and is connected to the bias module (4) through the third metal conductive layer (M3).

4. The layout structure of a power MOSFET gate driver chip according to claim 3, characterized in that: It also includes a hole (M4-TM1), and the charging NMOS group (NLDMOS1) in the opening module (5) includes multiple charging NMOS, whose drain extends through the fourth metal conductive layer (M4) to below the top metal conductive layer (TM1) connected to the upper port VDD2 (12), and completes the metal interconnection between the drain of the charging NMOS group and the port VDD2 (12) through the hole (M4-TM1).

5. The layout structure of a power MOSFET gate driver chip according to claim 3, characterized in that: The discharge NMOS group (NLDMOS2) in the shutdown module (6) comprises a plurality of discharge NMOSs, the drain of which extends through the fourth metal conductive layer (M4) to below the top metal conductive layer (TM1) of the upper connection port Vout (13), and completes the metal interconnection between the drain of the discharge NMOS group and the output port Vout (13) through the hole (M4-TM1).

6. The layout structure of a power MOSFET gate driver chip according to claim 2 or 3, characterized in that: The port VDD1 (11) is not only arranged around the inner side by the top metal conductive layer (TM1), but also extends longitudinally to above the power module (1) through the top metal conductive layer (TM1); The port VDD2 (12) extends longitudinally through the top metal conductive layer (TM1) to the top of the opening module (5), and the fourth metal conductive layer (M4) below it is interconnected with the top metal conductive layer (TM1) connected to the port VDD1 through the hole (M4-TM1); The port Vout (13) extends laterally through the top metal conductive layer (TM1) to above the charging NMOS group (NLDMOS1) in the turn-on module (5), and then extends longitudinally to above the turn-off module (6); The port GND (14) is not only arranged around the outside through the top metal conductive layer (TM1), but also extends longitudinally through the top metal conductive layer (TM1) to above the current mirror module (3) and the power module (1); The port GND2 (16) extends laterally through the top metal conductive layer (TM1) to above the discharge NMOS group (NLDMOS2) in the shutdown module (6); The power module (1) is horizontally extended through the fourth metal conductive layer (M4) through the current mirror module (3) and the logic control module (2), and vertically extended to the top of the bias module (4); and the port VDD1 (11) is vertically connected through the top metal conductive layer (TM1); The logic control module (2) is longitudinally extended through the third metal conductive layer (M3) to the bias module (4), then transversely extended to the top of the shutdown module (6), and then longitudinally extended to the opening module (5); The current mirror module (3) is horizontally extended to the power module (1) through the fourth metal conductive layer (M4); it is vertically extended to the bias module (4) through the second metal conductive layer (M2); and it is interconnected with the top metal conductive layer extending vertically from the port GND (14) through the top metal conductive layer (TM1); The bias module (4) is longitudinally extended through the fourth metal conductive layer (M4) to the power module (1); the second metal conductive layer (M2) is longitudinally extended to the current mirror module (3); the third metal conductive layer (M3) is transversely extended to the shutdown module (6), and then longitudinally extended to the opening module (5); and the top metal conductive layer (TM1) is transversely connected to the top metal conductive layer (TM1) extending longitudinally from the port GND (14) through the top metal conductive layer (TM1); The top metal conductive layer (TM1) is connected to the port VDD2 (12) vertically above the on module (5); the top metal conductive layer (TM1) is connected to the port Vout (13) horizontally; the top metal conductive layer (TM1) is interconnected with the output port Vout (13) and vertically extends to the top of the off module (6); a plurality of third metal conductive layers (M3) are firstly vertically extended to the top of the off module (6), and then horizontally extended to the top of the bias module (4) and the logic control module (2); The shutdown module (6) is laterally connected to the port GND2 (16) through the top metal conductive layer (TM1) above, and is vertically extended to the top of the enable module (5) through the top metal conductive layer (TM1), and is interconnected with the top metal conductive layer (TM1) extending from the output port Vout (13); and is laterally extended to the top of the bias module (4) and the logic control module (2) through multiple third metal conductive layers (M3).

7. The layout structure of a power MOSFET gate driver chip according to claim 3, characterized in that: The current mirror module (3) is located between the power module (1) and the logic control module (2); the bias module (4) is located above the power module, the current mirror module and the logic control module; the on module (5) is located at the lower left of the layout, and the off module is located at the upper left of the layout; and the off module (6) is located above the on module (5).

8. A layout structure of a power MOSFET gate driver chip according to claims 1-3, characterized in that: The port VDD1 (11), the port VDD2 (12), the port GND (14), the port GND2 (16), the port Vout (13), the power module (1), the logic control module (2), the current mirror module (3), the bias module (4), the turn-on module (5) and the turn-off module (6) are connected to the top metal conductive layer (TM1) and the fourth metal conductive layer (M4).

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