Electrostatic discharge / electrical overload protection circuit

Abstract

The invention discloses an electrostatic discharge / electrical overload protection circuit, and belongs to the field of integrated circuits, the protection circuit is arranged between a voltage source and electronic equipment, the electrostatic discharge / electrical overload protection circuit adopts a metal-oxide semiconductor field effect transistor to set a clamping voltage, and when electrostatic discharge / electrical overload comes, the electrostatic discharge / electrical overload protection circuit is switched off. The voltage can be clamped at the breakdown voltage of the source and the drain of the metal oxide semiconductor field effect transistor, a parasitic diode is used as a clamping circuit, and the current can be quickly discharged. The protection circuit solves the problems that in the prior art, due to the fact that a plurality of diodes are connected in series and in parallel, the occupied area is large, and the current discharging capacity is poor.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an electrostatic discharge / electrical overload protection circuit. Background Art

[0002] In today's era when all kinds of electronic components have entered thousands of households, electrostatic discharge / electrical overstress (ESD / EOS) is a major killer of electronic components. It can cause semiconductor devices (diodes, transistors, etc.) in electronic circuits to burn or break down, affecting the normal function of the circuit. There are many scenarios that can produce ESD / EOS, from natural lightning strikes to simple circuit switches, and even people may carry tens of thousands of volts of high voltage on their bodies after moving. Therefore, the direct or indirect economic losses caused by it every year are very huge. Therefore, it is of great practical value to take protective measures when ESD / EOS strikes and build ESD / EOS protection circuits between electronic components and voltage sources.

[0003] Existing ESD / EOS protection circuits usually work in a diode breakdown mode, that is, multiple Zener diodes are connected in series to limit the clamping voltage so that the voltage received by the protected circuit is not greater than its breakdown voltage. Metal oxide semiconductor (MOS) tubes are used as switches to open the discharge circuit when the external ESD / EOS voltage is greater than the clamping voltage, thereby playing the role of ESD / EOS protection.

[0004] This type of ESD / EOS protection circuit has defects. Since multiple Zener diodes are connected in series and parallel, they occupy a large layout area, which is not conducive to the miniaturization of chips in high-voltage ESD / EOS protection circuits. In addition, after the circuit plays a clamping role, the Zener diode is broken down and has a certain resistance value. If ESD / EOS fluctuates after clamping, the circuit cannot clamp the voltage well, and the clamping ability is unstable. Summary of the invention

[0005] The present invention provides an electrostatic discharge / electrical overload protection circuit, which adopts a metal oxide semiconductor field effect transistor (MOSFET) to set an ESD / EOS protection circuit with a clamping voltage. When ESD / EOS strikes, the voltage can be clamped at the breakdown voltage of the MOSFET source and drain, and the parasitic diode itself is used as the clamping circuit, and the current can be discharged quickly, thereby overcoming the problem in the prior art that a large area is occupied by using a large number of diodes in series and parallel and the current discharge capacity is poor.

[0006] An embodiment of the present invention provides an electrostatic discharge / electrical overload protection circuit, which is connected between a voltage source and an electronic device, and includes: a reference circuit, which is used to turn on a feedback control circuit when the voltage of an external voltage source is higher than a clamping voltage, so as to clamp the voltage at a set voltage; and a feedback control circuit, which is used to quickly discharge current when an electrostatic discharge / electrical overload voltage strikes.

[0007] Optionally, in one embodiment of the present invention, the reference circuit is composed of a P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 and a first resistor R0;

[0008] The feedback control circuit is composed of a Zener diode D0, a second resistor R1, and an N-type lateral double diffused metal oxide semiconductor field effect transistor NM0.

[0009] Optionally, in one embodiment of the present invention, in the reference circuit, the gate of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is connected to one end of the first resistor R0, the other end of the first resistor R0 and the source of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 are both connected to the positive electrode of the voltage source, the drain of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is connected to the cathode of the Zener diode D0, one end of the second resistor R1, and the gate of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0; the second resistor R1 is connected in parallel with the Zener diode D0, the anode of the Zener diode D0, the other end of the second resistor R1 and the source of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 are all connected to the negative electrode of the voltage source, and the drain of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 is connected to the positive electrode of the voltage source.

[0010] Optionally, in one embodiment of the present invention, the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is used as a breakdown transistor to generate a turn-on voltage of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 on the second resistor R1, and the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 is used as a discharge tube to release electrostatic discharge / electrical overload current.

[0011] Optionally, in one embodiment of the present invention, the ground terminal of the protected electronic device is grounded, and the high voltage terminal is connected to the drain of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0.

[0012] The electrostatic discharge / electrical overload protection circuit of the embodiment of the present invention is arranged between the voltage source and the electronic device, and adopts a metal oxide semiconductor field effect transistor to set the electrostatic discharge / electrical overload protection circuit of the clamping voltage. When electrostatic discharge / electrical overload occurs, the voltage can be clamped at the breakdown voltage of the source and drain of the metal oxide semiconductor field effect transistor, and the parasitic diode of the self is used as the clamping circuit, and the current can be discharged quickly. Therefore, the protection circuit of the present invention can discharge a large amount of current in a relatively fast time, making it more difficult for the protected circuit to be damaged by high voltage breakdown, and can provide more stable ESD / EOS protection, and the clamping voltage is more stable.

[0013] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram of an electrostatic discharge / electrical overload protection circuit provided according to an embodiment of the present invention;

[0016] Figure 2 A circuit diagram of an electrostatic discharge / electrical overload protection circuit according to an embodiment of the present invention;

[0017] Figure 3 This is a clamping effect diagram of Example 1 of an ESD / EOS protection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0019] The embodiment of the present invention discloses a novel ESD / EOS protection circuit, which can clamp the voltage of the protected circuit to the normal working voltage when the protected circuit is subjected to a high ESD / EOS voltage shock, thereby ensuring that the protected circuit is not affected by external ESD / EOS and maintains normal operation. It should be noted that in the embodiment of the present invention, the protected circuit generally includes but is not limited to MOS, capacitors, inductors, resistors, etc. It should be pointed out that in the embodiment of the present invention, high voltage and low voltage are relative concepts. For example, if the protected circuit is a circuit that can work normally at a voltage below 50V, then a voltage with a peak voltage exceeding 50V is a high ESD / EOS voltage, and the ESD / EOS protection circuit is required to play a clamping role and clamp the voltage to 50V. It should be pointed out that only the distinction criteria between high voltage and low voltage are pointed out here. According to actual conditions, the protected circuit can also be a circuit that works at other voltages, and the corresponding clamping voltage can also be changed accordingly.

[0020] Based on the types of protected circuits and application scenarios described above, an electrostatic discharge / electrical overload protection circuit according to an embodiment of the present invention is introduced.

[0021] like Figure 1 and Figure 2As shown, the ESD / EOS protection circuit of the embodiment of the present invention is composed of a reference circuit and a feedback control circuit. The ESD / EOS protection circuit of the embodiment of the present invention should be placed between the voltage source and the electronic device. When the ESD / EOS protection circuit of the embodiment of the present invention is applied, it should be connected in parallel at both ends of the electronic device to be protected. Its components include: the electrostatic discharge / electrical overload protection circuit includes: a reference circuit, which is used to turn on the feedback control circuit when the voltage of the external voltage source is higher than the clamping voltage, and clamp the voltage at the set voltage; a feedback control circuit, which is used to quickly discharge the current when the electrostatic discharge / electrical overload voltage strikes.

[0022] The reference circuit is composed of a P-type lateral double diffused metal oxide semiconductor field effect transistor (PLDMOS) PM0 and a first resistor R0, and its clamping voltage is determined by the parameters and type of the PLDMOS. The feedback control circuit is composed of a Zener diode D0, a second resistor R1, and an N-type lateral double diffused metal oxide semiconductor field effect transistor (NLDMOS) NM0.

[0023] In the reference circuit, the gate of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is connected to one end of the first resistor R0, the other end of the first resistor R0 and the source of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 are both connected to the positive electrode of the voltage source, the drain of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is connected to the cathode of the Zener diode D0, one end of the second resistor R1, and the gate of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0; the second resistor R1 is connected in parallel with the Zener diode D0, the anode of the Zener diode D0, the other end of the second resistor R1 and the source of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 are all connected to the negative electrode of the voltage source, and the drain of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 is connected to the positive electrode of the voltage source.

[0024] As an implementation method, the reference circuit is composed of a P-type lateral double diffused metal oxide semiconductor field effect transistor (referred to as PM0) and a Zener diode D0. The gate and source of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 are connected to the positive electrode of the voltage source, and the drain is connected to the cathode of the Zener diode D0.

[0025] As an implementation method, the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is used as a breakdown transistor to generate a turn-on voltage of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 on the second resistor R1, and the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 is used as a discharge tube to release electrostatic discharge / electrical overload current.

[0026] As an implementation mode, the ground terminal of the protected working circuit is connected to the ground, and the high voltage terminal is connected to the drain of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0.

[0027] The working principle of the embodiment of the present invention is: when the voltage of the external voltage source is greater than the specified clamping voltage, the source and drain of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 are broken down, generating a reference voltage, and the voltage remains unchanged. The drain of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 generates a driving current, and the driving current flows through the second resistor R1, increasing the voltage across the second resistor R1, so that the gate of the high-voltage discharge tube NM0 is greater than its threshold voltage, turning on the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0, discharging a large amount of current, and clamping the entire circuit at a certain voltage. And unlike the diode clamping, the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 for clamping and driving can adjust the gate voltage to a certain extent while clamping because of the existence of the gate resistor R0 to provide a higher driving current. It should be noted that the value of the first resistor R0 needs to be carefully designed to prevent the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 from turning on and the circuit losing its clamping ability.

[0028] It should be noted that the clamping voltage value in the embodiment of the present invention should be the same as the source-drain breakdown voltage value of the PLDMOS transistor PM0, so the type of the PLDMOS transistor can be selected according to the required clamping voltage value.

[0029] The embodiment of the present invention does not limit the value of the second resistor R1, and does not limit the types of NLDMOS and PLDMOS, which can be determined according to actual application requirements; optionally, the specific circuit connection relationship of the device that needs ESD / EOS protection can also be flexibly set according to actual application requirements; optionally, for the value of the PM0 gate resistance R0, it is recommended to select a range of 50Ω to 500Ω to ensure high driving current and stable clamping capability.

[0030] It is worth noting that, in order to reduce the chip area, the embodiment of the present invention uses PLDMOS as a breakdown transistor, and the source-drain breakdown voltage of the PLDMOS is used to define the clamping voltage value.

[0031] Example 1:

[0032] It should be pointed out that the ESD / EOS protection circuit shown in Example 1 is an embodiment of the invention with a certain clamping voltage, which is completely the same as the above-mentioned embodiment of the invention except for the source-drain breakdown voltage value of PM0.

[0033] Example 1: When a high voltage ESD / EOS is applied, the clamping voltage capability is as follows: Figure 3 As shown in the figure, it can clamp the voltage at a certain value and quickly discharge the current in a short time. This shows that the circuit has good ESD / EOS protection capability.

[0034] It should be emphasized that the circuit of the embodiment of the present invention is not limited to the clamping voltage of Example 1. For the embodiment of the present invention, the clamping voltage can be limited by replacing LDMOS with different breakdown voltages. It should be emphasized that in other applications of the present invention, NLDMOS / PLDMOS can be replaced with other types of MOS tubes or switch devices according to the specific form of implementation, and it is still regarded as a derivative of the present invention.

[0035] According to the electrostatic discharge / electrical overload protection circuit proposed in the embodiment of the present invention, the clamping voltage can be changed by changing the MOS model of the reference circuit, and the adjustment capability is flexible. Compared with the increase in circuit area caused by multiple Zener diodes connected in series, the present invention only uses one LDMOS, which greatly reduces the chip area. The present invention can discharge a large amount of current in a relatively fast time, making it more difficult for the protected circuit to be broken down by high voltage. The embodiment of the present invention can provide more stable ESD / EOS protection, and the clamping voltage is more stable.

[0036] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0037] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. An electrostatic discharge / electrical overload protection circuit connected between a voltage source and an electronic device, characterized in that: include: A reference circuit is used to start a feedback control circuit when the voltage of the external voltage source is higher than the clamping voltage, so as to clamp the voltage at a set voltage; Feedback control circuit, used to quickly discharge current when electrostatic discharge / electrical overload voltage occurs.

2. The circuit according to claim 1, characterized in that The reference circuit is composed of a P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 and a first resistor R0; The feedback control circuit is composed of a Zener diode D0, a second resistor R1, and an N-type lateral double diffused metal oxide semiconductor field effect transistor NM0.

3. The circuit according to claim 2, characterized in that In the reference circuit, the gate of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is connected to one end of the first resistor R0, the other end of the first resistor R0 and the source of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 are both connected to the positive electrode of the voltage source, the drain of the P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 is connected to the cathode of the Zener diode D0, one end of the second resistor R1, and the gate of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0; the second resistor R1 is connected in parallel with the Zener diode D0, the anode of the Zener diode D0, the other end of the second resistor R1 and the source of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 are all connected to the negative electrode of the voltage source, and the drain of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 is connected to the positive electrode of the voltage source.

4. The circuit according to claim 2, characterized in that The P-type lateral double diffused metal oxide semiconductor field effect transistor PM0 acts as a breakdown transistor to generate a turn-on voltage of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 on the second resistor R1. The N-type lateral double diffused metal oxide semiconductor field effect transistor NM0 acts as a discharge tube to release electrostatic discharge / electrical overload current.

5. The circuit according to claim 1, characterized in that The ground terminal of the protected electronic device is grounded, and the high voltage terminal is connected to the drain of the N-type lateral double diffused metal oxide semiconductor field effect transistor NM0.

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