Optimized start-up scheme for isolated cascaded AC / DC power converters

Abstract

In one embodiment, a method includes receiving DC bus voltage conditions for a plurality of AC-to-DC converters of an input-series-output-parallel power converter during a rectification phase; detecting that a peak voltage of each DC bus of the plurality of AC-to-DC converters has reached a first threshold voltage, and a phase-locked loop lock signal; upon detecting the PLL lock signal, enabling a first voltage regulation to charge an AC-to-DC output of each of the plurality of AC-to-DC converters to reach a first reference voltage; determining operating conditions including a load condition and an output voltage condition of the plurality of dual active bridge (DAB) converters, and a monitored voltage of each AC-to-DC converter of the plurality of AC-to-DC converters; based on the operating condition, a second voltage regulation of each DAB converter of the plurality of DAB converters is enabled to charge the DAB output to reach a second reference voltage.

Description

[0001] Related Applications

[0002] This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 63 / 357,325, filed on June 30, 2022, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to power converters and, in particular, to cascaded multiphase power converter regulation. Background Art

[0004] Given the increasing popularity of DC loads and sources, the efficiency, control, and protection of medium voltage three-phase distribution systems (such as those based on 50 / 60Hz and operating at 11 / 13kV) and high power, isolated DC conversion present considerable challenges. Notably, power distribution to large data centers and emerging electric vehicle (EV) DC fast charging stations exemplifies the need for DC loads. Solar photovoltaic (PV) and battery energy storage are typical DC power sources that require direct connection and conversion to the medium voltage (MV) grid. In this context, modular and isolated cascade power converters with input series and output parallel (ISOP) configuration are increasingly recognized as the best solution for using currently available power devices. The ISOP configuration offers multiple advantages, including enhanced control flexibility of integrated DC sources and loads, a smaller physical footprint, and higher efficiency. This topology with a high-frequency transformer for isolation is often referred to as a solid-state transformer (SST).

[0005] The SST topology consists of a set of series-connected active front-end (AFE) converters responsible for rectifying the input AC power to DC, and a set of parallel-connected isolated dual active bridges (DABs) for generating output DC power. When the AFE capacitors of the SST are pre-charged from the medium voltage (MV) grid, the pre-charge resistor circuit effectively limits the inrush current and charges the series-connected AFEs. However, when charging the output capacitors and supplying power to the connected load, the peak current must be limited to protect the device, balance the AFE DC voltage to not exceed the power device rating and capacitor voltage, and prevent transformer core saturation. This precaution is critical because dual active bridge (DAB) operation is necessary for the AFEs to share the input voltage in a cascade configuration. Summary of the invention

[0006] The present disclosure proposes a comprehensive pre-charging and startup process for charging the output DC link capacitors of a cascaded AFE DC link and a cascaded H-bridge based SST. The present disclosure proposes a phase shift control method for DAB and system control for AFE and DAB to (a) limit inrush current, (b) avoid voltage inequality between AFEs, (c) avoid saturation of transformer core by controlled parallel charging of output converters with cascaded input converters, and smoothly charge the AFE and DAB capacitors under (a) no load at the output, (b) partial load conditions during startup, (c) no voltage on the output DC bus capacitor, and (d) partial voltage on the output DC bus capacitor.

[0007] In a specific embodiment, one or more computing systems may receive a DC bus voltage condition of a plurality of AC to DC converters of an ISOP power converter during a rectification phase for precharging the DC bus of the plurality of AC to DC converters. The AC to DC converter may be a single-phase or multi-phase AC to DC converter. In a specific embodiment, the plurality of AC to DC converters may be a plurality of AFE converters connected in series. The ISOP power converter may be bidirectional, which may be used for both AC to DC charging from an AC input side to a DC load side and DC to AC charging from a DC load side to an AC input side. One or more computing systems may detect that a peak voltage of each DC bus of a plurality of AC to DC converters during a rectification phase has reached a first threshold voltage, and a phase-locked loop (PLL) signal indicates a locked state with an AC grid voltage. When the PLL signal indicates a locked state with an AC grid voltage, one or more computing systems may enable a first voltage regulation to charge the AC to DC output of each AC to DC converter of a plurality of AC to DC converters to reach a first reference voltage. One or more computing systems may determine an operating condition of the ISOP power converter. The operating condition may include a load condition and an output voltage condition associated with a plurality of DAB converters, and a monitoring voltage condition of each AC to DC converter in a plurality of AC to DC converters. The DAB converter may be implemented as an isolated resonant converter. One or more computing systems may enable a second voltage regulation of each DAB converter in a plurality of DAB converters based on the operating condition to charge the DAB output to reach a second reference voltage within the current limit. One or more computing systems may maintain a second reference voltage for the output voltage condition. The load condition may include a no-load condition and a partial load condition. The output voltage condition may include a zero output voltage condition and a partial output voltage condition. One or more computing systems may monitor an initial voltage value associated with a partial output voltage condition. The monitoring voltage condition of each AC to DC converter in a plurality of AC to DC converters may include that the monitoring voltage condition of the AC to DC output of each AC to DC converter in a plurality of AC to DC converters has reached a first reference voltage, and the monitoring voltage condition of the AC to DC output of each AC to DC converter in a plurality of AC to DC converters has reached a peak voltage, while the PLL signal indicates a locked state with the AC grid voltage. When detecting that the monitored voltage condition of each of the plurality of AC to DC converters has reached the first reference voltage, the one or more computing systems may simultaneously enable second voltage regulation of each of the plurality of DAB converters to charge the DAB output to reach the second reference voltage.Additionally or alternatively, when it is detected that the monitored voltage condition of each of the plurality of AC to DC converters has reached a peak voltage while the PLL signal indicates a locked state with the AC grid voltage and the AC to DC output DC voltage is being regulated to the reference voltage, the one or more computing systems may simultaneously enable second voltage regulation of each of the plurality of DAB converters to charge the DAB AC to DC to reach the second reference voltage.

[0008] In a particular embodiment, one or more computing systems may generate a control variable for a second voltage regulation based on an operating condition, wherein the control variable includes a first pulse width of a primary H-bridge output voltage of each DAB converter, a second pulse width of a secondary H-bridge output voltage in each DAB converter, and a phase shift angle between the primary H-bridge output voltage and the secondary H-bridge output voltage. One or more computing systems may enable a second voltage regulation of each of a plurality of DAB converters to reach a second reference voltage within a current limit based on the control variable. One or more computing systems may further precharge a DC bus of a plurality of AC to DC converters using a power source connected to the output of the DAB converter. One or more computing systems may enable reverse charging voltage regulation of each of a plurality of AC to DC converters within a current limit based on the control variable.

[0009] In a particular embodiment, maintaining the second reference voltage for the output voltage condition may include enabling at least one of AC to DC output voltage regulation and enabling DAB DC voltage regulation. In a particular embodiment, a rectification phase for precharging a DC bus of a plurality of AC to DC converters may be enabled via a pre-charge switch system. The pre-change switch system may include a first switch and a resistor for reducing an inrush current, and a second bypass switch that operates when a peak voltage of each DC bus of the plurality of AC to DC converters has reached a first threshold voltage during the rectification phase.

[0010] The embodiments disclosed herein are merely examples, and the scope of the present disclosure is not limited thereto. A particular embodiment may include all or some of the components, elements, features, functions, operations or steps of the embodiments disclosed herein, or may not include the components, elements, features, functions, operations or steps of the embodiments disclosed herein. Embodiments according to the present invention are particularly disclosed in the accompanying claims relating to methods, storage media, systems and computer program products, wherein any feature mentioned in one claim category (e.g., method) may also be claimed in another claim category (e.g., system). Dependencies or references in the accompanying claims are selected for formal reasons only. However, any subject matter resulting from an intentional reference to any previous claim (especially multiple dependencies) may also be claimed, such that any combination of claims and their features is disclosed and may be claimed, regardless of the dependencies selected in the accompanying claims. The subject matter that may be claimed includes not only the combination of features as set out in the accompanying claims, but also any other combination of features in the claims, wherein each feature mentioned in a claim may be combined with any other feature or combination of other features in the claims. Furthermore, any embodiment or feature described or depicted herein may be claimed in a separate claim and / or in any combination with any embodiment or feature described or depicted herein or with any features of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments according to the present disclosure will now be described with reference to the accompanying drawings, in which:

[0012] Figure 1 An exemplary single-phase configuration of an AC / DC power converter system having N levels is shown.

[0013] Figure 2 An exemplary flow chart of a soft start method for charging a DC bus of an AC / DC power converter system is shown.

[0014] Figure 3 An exemplary timing diagram of a startup scenario for an AC / DC power converter system is shown.

[0015] Figure 4A An exemplary flow chart illustrating a controller architecture for managing soft-start charging of a single phase of an AC / DC power converter system is shown.

[0016] Figure 4B An exemplary flow chart illustrating a controller architecture for managing soft-start charging of a DAB converter is shown.

[0017] Figure 5An exemplary timing diagram of DAB AC voltage and inductor current when primary and secondary duty cycles are used in addition to phase angle is shown.

[0018] Figure 6 An exemplary three-phase AC / DC power converter system configuration is shown.

[0019] Figure 7 An exemplary computer system is shown. DETAILED DESCRIPTION

[0020] Figure 1 An exemplary single-phase configuration of an AC / DC power converter system with N levels is shown. The AC / DC power converter system 100 may include an ISOP converter with a cascaded H-bridge-based SST. The AC / DC power converter system 100 may include a pre-charge switch system 110. The pre-charge connector may include a first switch 103 and a second switch 105 connected in parallel with the first switch 103, and the first switch 103 may also be connected in series to a pre-charge resistor 107. The charging current may be limited by the pre-charge resistor 107. The AC / DC power converter system may further include an inductor 109 to limit the inrush of the charging current, so that the capacitor of the AC / DC power conversion system 100 may be charged slowly. The pre-charge switch system may be connected to an AC power source 101, wherein an active front end (AFE) converter 120 may be used first to convert the AC input to DC. The AFE converter may actively control the power flow from the AC power source 101. The AC / DC power converter system 100 may incorporate switching devices, such as insulated gate bipolar transistors (IGBTs) or MOSFETs, to achieve precise control of the input current waveform. The AFE converter 120 may allow bidirectional power flow, which may be used in situations where both AC-DC power conversion and DC-AC power conversion are required. Figure 1 In the configuration shown, the AC input can be first converted to internal DC using an AFE converter 120 through an AC-DC rectifier stage. The AC / DC power converter system 100 can include a series of N AFE converters for rectification. The DC output at the capacitor 125 from the AFE converter 120 can be connected to N DC-DC converters arranged in parallel, where N can depend on the input AC voltage. SST can be used for lower voltage applications and may not be limited to medium voltage. This configuration can be a dual active bridge (DAB) converter 130 with a high frequency transformer (HFT) 131 in each level. DAB can be used in the DC-DC conversion stage of the circuit and produce a DAB DC output at the capacitor 135. The output DC can be connected to an energy storage unit 140.

[0021] The two-stage multi-level ISOP structure can meet the requirements of connecting to MV AC using currently widely available power MOSFETs, and this structure can provide electrical isolation between the load and the input power supply. In addition, the two-stage multi-level ISOP structure can achieve bidirectional power flow and scalability to meet different power and voltage levels. Figure 1 The multi-level topology shown may allow the use of low blocking voltage switching devices with low on-state resistance, which may result in reduced conduction losses and the ability to operate at higher switching frequencies. The multi-level configuration may help reduce current and voltage harmonics, which may directly result in the use of smaller filter components, thereby reducing the system footprint. To meet the AC voltage requirements, a modular structure for a multi-level system may be achieved through the series cascading of multiple modules. Since the system can be adjusted for different voltage levels and power ratings, the modular structure for a multi-level system may be easier to manage in the event of a module failure. In addition, one of the main requirements for a medium voltage AC-DC system may be the integration of galvanic isolation between the AC grid and the DC side load, which may be achieved through an ISOP DAB converter.

[0022] Conventional startup procedures for limiting inrush current during startup include using zero voltage switching (ZVS) for SST systems. While implementing ZVS can limit inrush current during startup, SST-based systems include additional switches and passive components at the front-end stage and use auxiliary power supplies in the implemented startup scheme, resulting in an increase in system size. Additionally, conventional startup procedures may include using a step-by-step startup method that may result in increased leakage current, precharging the AC-DC and DC-DC stages simultaneously, adding additional DC-DC converters to the SST system to facilitate precharging of the LV DC link stage, and using an auxiliary power unit (APU) for precharging. However, load conditions may affect the inrush current during precharging of the DC bus capacitors of the solid-state transformer (SST). The size of the load, reactive load components, switching dynamics, and load variations all affect the behavior of the inrush current. A robust control strategy is essential to manage the inrush current and ensure optimal SST performance under varying load conditions.

[0023] According to Figure 1 The SST configuration shown, the present disclosure proposes a soft start process for a modular two-stage SST powered from the MV AC side or the LV DC side. The DC-DC converter stage is used to play a key role in pre-charging the MV DC link or the LV DC link and mitigating the inrush overcurrent problem of the HFT. The soft start method can eliminate the need for the APU to limit the inrush current.

[0024] In a particular embodiment, the soft start charging of the DC bus of the AC / DC power converter system 100 can be a two-step process. The first step can start with connecting the AC-DC converter (e.g., AFE converter 120) to the AC power source 101. The MV DC link of the DC output at capacitor 125 can be energized via pre-charge resistor 107 and inductor 109 to reduce inrush current. The LV DC link pre-charging of the DAB DC output at capacitor 135 can be a key condition for starting the regulation of the DAB converter 130, while the regulated MV DC link of the DC output at capacitor 125 supplies power to the input port of the DAB stage. The uncharged LV capacitor can act as a short circuit, which can cause a rapid increase in leakage current that can exceed the rated and safe operating limits of the device.

[0025] Figure 2 An exemplary flow chart of a soft start method for charging a DC bus of an AC / DC power converter system is shown. In a particular embodiment, at step 210, one or more computing systems may begin a soft start method for charging a DC bus of an AC / DC power converter system. At step 220, one or more computing systems may receive communication feedback associated with the status of the AC / DC power converter system. In a particular embodiment, the communication feedback may include one or more of the following indications: all gate drive power supplies are healthy, the availability of the AC / DC power converter system grid, an indication that there are no faults in the system after sending a reset signal, an indication that the controller reports healthy communications, an indication that the protection relay for the AC / DC power converter system grid is communicating correctly, an indication that the pre-charge control is ready to operate, or an indication for receiving a phase-locked loop (PLL) lock signal. At step 230, once the one or more computing systems have checked the communication feedback, such as the input voltage waveform from the AC power source 101 is within the expected parameters and suitable for proper operation of the AC / DC power converter system 100 and the PLL is locked, the one or more computing systems may begin precharging the DC output at the capacitor 125 for the output at the N AFE converters, and precharging the DC bus link of the DAB DC output at the capacitor 135. At step 230, the first switch 103 may be closed and the second switch may remain open. Once precharging begins, the one or more computing systems may continue to receive the DC bus voltage conditions of each AFE converter, such as the DC bus voltage V at the capacitor 125 for the N levels of the AC / DC power converter system 100. dc1 At step 240 , one or more computing systems may determine the peak voltage V of each DC bus of the N AFE converters during the rectification phase. dc1 、V dc2 …and V dcnWhen the PLL lock signal is detected, one or more computing systems may further adjust the DC bus voltage V dc1 、V dc2 , … and V dcn , until V dc1 、V dc2 , … and V dcn At step 250, once all voltages at capacitors for the N AFE converters (such as capacitor 125) have reached a first threshold voltage, the one or more computing systems may enable parallel charging of the DAB DC output at capacitor 135 by the DAB converter, and regulation of the DAB converter may begin.

[0026] In certain embodiments, one or more computing systems may determine operating conditions of the AC / DC power converter system 100 for parallel charging. The operating conditions of the AC / DC power converter system 100 may include load conditions and output voltage conditions V associated with the DAB converter. dcO , and the monitored voltage condition V of each of the N AFE converters dc1 、V dc2 , … and V dcn At step 260, when charging the DAB converter based on the operating conditions of the AC / DC power converter system 100, the computing system may adjust the output voltage V dcO and limit the inrush overcurrent of the HFT. In a particular embodiment, the computing system may calculate the control variables based on the operating conditions. The control variables may include a first pulse width D1 for the primary H-bridge output voltage of each DAB converter, a second pulse width D2 for the secondary H-bridge output voltage of each DAB converter, and a phase shift angle between the primary H-bridge output voltage and the secondary H-bridge output voltage. One or more computing systems can constantly adjust the control parameters so that the DC output voltage can increase at a constant rate until the DC output voltage V at capacitor 135 reaches dcO One or more computing systems may continue to monitor the DC output voltage V at the capacitor 135 converted by the DAB. dcO , and maintain a stable state. In step 270, one or more computing systems may determine the DC output voltage V dcO The second reference voltage has been reached. In order to maintain a steady state and limit the inrush current of the HFT, one or more computing systems may enable at least one of the AFE DC bus regulation and the DAB bus regulation in step 280. When the AFE internal DC link V dc1 、V dc2 , … and Vdcn and DAB output DC link V dcO When its steady state has been maintained, the soft start process may end at step 290 .

[0027] In a particular embodiment, the operating conditions of the AC / DC power converter system 100 may include a load condition associated with the DAB converters connected in parallel, an output voltage condition, and a monitored voltage condition of each AFE converter in the plurality of AFE converters. In a particular embodiment, the load condition may include a no-load condition and a partial load condition. The load may be connected to the DAB output terminal. In a particular embodiment, when the DAB converters initially begin to ramp up, the output voltage condition associated with the DAB converters connected in parallel may be zero. Additionally or alternatively, the initial voltage of the output voltage condition associated with the DAB converters connected in parallel may be greater than zero. As an example and not a limitation, when adjusting the AFE internal bus link voltage V dc1 、V dc2 , … and V dcn and DAB output DC link V dcO When a glitch occurs, capacitors for the AFE and DAB (such as capacitor 125 and capacitor 135) may discharge, which may cause the DAB output DC link V dcO The voltage level at is greater than zero. The monitoring voltage condition V of each AFE converter in the N AFE converters dc1 、V dc2 , … and V dcn A first condition may be included in which the internal bus link voltage V dc1 、V dc2 , … and V dcn The peak voltage has been reached when the PLL is locked. Additionally or alternatively, the monitored voltage condition V dc1 、V dc2 , … and V dcn A first condition may be included in which the internal bus link voltage V dc1 、V dc2 , … and V dcn The first reference voltage for the steady state has been reached. One or more computing systems may calculate the voltage based on the V applied to capacitor 135. dcO load conditions, AFE internal DC link V dc1 、V dc2 , … and V dcn Conditions and DAB output DC link V dcO The initial value to start the DAB output DC link V dcO Perform pre-charge.

[0028] Figure 3 310 shows an exemplary timing diagram of a startup scenario for an AC / DC power converter system. The AFE soft start is shown by a voltage-time curve 310. In a specific embodiment, as shown in FIG. Figure 1 As shown, the AFE as a rectifier can first charge the internal DC bus via the body diode of the MOSFET. The charging current can be limited by a charging resistor. The diode rectification state can be between t0 and t1. At t1, one or more computing systems can detect that the peak voltage of each DC bus of the N AFE converters during the rectification phase has reached a first threshold voltage. At time t2, the PLL is locked to the grid, and the computing system begins to actively control the MV DC bus. At t3, the desired internal DC link can be equal to the first reference voltage, and the first stage of pre-charging the internal DC link via the AFE can operate in a stable state.

[0029] In certain embodiments, the one or more computing systems may determine a first operating condition in which there may be no load connected to the output of the DAB converter and the internal DC link V dc1 、V dc2 …and V dcn The first reference voltage and its steady state have been reached, and the initial DAB output voltage at the DC bus is zero. DAB soft start is shown by curve 320. When the internal DC link reaches its steady state operation at t3, one or more computing systems may enable DAB soft start, and when the output voltage V dcO When the steady state is reached, the pre-charging of DAB can be terminated at t5.

[0030] In certain embodiments, the one or more computing systems may determine a second operating condition in which there may be a partial load connected to the output of the DAB converter and the internal DC link V dc1 、V dc2 …and V dcn The first reference voltage and its steady state have been reached, and the initial DAB output voltage at the DC bus is zero. DAB soft start is shown by curve 320. When the internal DC link reaches its steady state operation at t3, one or more computing systems may enable DAB soft start, and when the output voltage V dcO When the steady state is reached, the pre-charging of DAB can be terminated at t5.

[0031] In certain embodiments, the one or more computing systems may determine a third operating condition in which there may be no load connected to the output of the DAB converter and the internal DC link V dc1 、V dc2 …and V dcnThe peak voltage of the internal bus link associated with the AFE converter has been reached during the rectification phase, and the initial DAB output voltage at the DC bus is zero. DAB soft start is shown by curve 330. When the internal DC link reaches the peak voltage and the PLL signal is detected at t2, one or more computing systems can enable DAB soft start, and when the output voltage V dcO When the steady state is reached, the pre-charging of DAB can be terminated at t4. The internal DC link V dc1 、V dc2 , … and V dcn Can be compared to the output DC V dcO reach their steady state more quickly.

[0032] In certain embodiments, the one or more computing systems may determine a fourth operating condition in which there may be a partial load connected to the output of the DAB converter and the internal DC link V dc1 、V dc2 …and V dcn The peak voltage of the internal bus link associated with the AFE converter has been reached during the rectification phase, and the initial DAB output voltage at the DC bus is zero. DAB soft start is shown by curve 330. When the internal DC link reaches the peak voltage and the PLL signal is detected at t2, one or more computing systems can enable DAB soft start, and when the output voltage V dcO When the steady state is reached, the pre-charging of DAB can be terminated at t4. The internal DC link V dc1 、V dc2 , … and V dcn Can be compared to the output DC V dcO reach their steady state more quickly.

[0033] In certain embodiments, the one or more computing systems may determine a fifth operating condition in which there may be no load connected to the output of the DAB converter and the internal DC link V dc1 、V dc2 …and V dcn The first reference voltage and its steady state have been reached, and the initial DAB output voltage at the DC bus is greater than zero. The DAB soft start is shown by curve 340. When the internal DC link reaches its steady state operation at t3, one or more computing systems may obtain an initial value V of the DAB output voltage. i and DAB soft start is enabled, and when the output voltage V dcO When the steady state is reached, the pre-charging of DAB can be terminated at t5.

[0034] In certain embodiments, the one or more computing systems may determine a sixth operating condition in which there may be a partial load connected to the output of the DAB converter and the internal DC link V dc1 、V dc2 …and V dcn The first reference voltage and its steady state have been reached, and the initial DAB output voltage at the DC bus is greater than zero. The DAB soft start is shown by curve 340. When the internal DC link reaches its steady state operation at t3, one or more computing systems may obtain an initial value V of the DAB output voltage. i and DAB soft start is enabled, and when the output voltage V dcO When the steady state is reached, the pre-charging of DAB can be terminated at t5.

[0035] In certain embodiments, the one or more computing systems may determine a seventh operating condition in which there may be no load connected to the output of the DAB converter and the internal DC link V dc1 、V dc2 …and V dcn The peak voltage of the internal bus link associated with the AFE converter has been reached during the rectification phase, and the initial DAB output voltage at the DC bus is greater than zero. The DAB soft start is shown by curve 350. When the internal DC link reaches the peak voltage and the PLL signal is detected at t2, one or more computing systems can obtain an initial value V of the DAB output voltage. i and DAB soft start is enabled, and when the output voltage V dcO When the steady state is reached, the pre-charging of DAB can be terminated at t4. The internal DC link V dc1 、V dc2 , … and V dcn Can be compared to the output DC V dcO reach their steady state more quickly.

[0036] In certain embodiments, the one or more computing systems may determine an eighth operating condition in which there may be a partial load connected to the output of the DAB converter and the internal DC link V dc1 、V dc2 …and V dcn The peak voltage of the internal bus link associated with the AFE converter has been reached during the rectification phase, and the initial DAB output voltage at the DC bus is greater than zero. The DAB soft start is shown by curve 350. When the internal DC link reaches the peak voltage and the PLL signal is detected at t2, one or more computing systems can obtain an initial value V of the DAB output voltage. i and DAB soft start is enabled, and when the output voltage V dcOWhen steady state is reached, the pre-charging of DAB can be ended at t4. The DAB converter can start ramping up simultaneously with the AFE stage and reach the steady state value at t4. The internal DC link V dc1 、V dc2 , … and V dcn Can be compared to the output DC V dcO The UPSs reach their steady state faster. Soft-start control keeps inrush and peak currents low.

[0037] Figure 4A 1 shows an exemplary flow chart of a controller architecture for managing soft start charging of a single phase of an AC / DC power converter system. The control system 400A of the single-phase AC / DC power converter system 100 may include an AFE control subsystem 410 and a DAB control subsystem 420. The AFE control loop 411 may receive an AC grid voltage V g 401. Monitored AFE internal DC bus link voltage V dc1 、V dc2 , … and V dcn (403, ... and 405) and the first reference voltage V of the AFE internal bus link dc * 407. The AFE control loop 411 may include one or more controllers for standard DQ control, SOGI PLL, and cascade specific voltage balancing control of the AFE DC bus. The AFE control loop 411 may generate duty cycles D1, ..., D2 for each AFE converter. n (415, ...417). The AFE duty cycle may be received by a pulse width modulation (PWM) generator, and the PWM generator may generate a corresponding first PWM signal 419 using the specified duty cycle. The monitored AFE internal DC bus link voltage V dc1 、V dc2 , … and V dcn (403, ... and 405) can also be provided to the control variable calculation and operating condition detection module 447 of the DAB control subsystem 420. The control variable calculation module 421 can also receive the second reference voltage V of the DAB output DC bus link. O * 423. Monitored DC output voltage V dcO 425. Switching frequency F of AC / DC power converter system 100 s 427. Allowable time for charging the DC capacitor µ 429. Saturation value of duty cycle D nom431. The control variable calculation module 421 can detect the operating conditions of the AC / DC power converter system 100. The operating conditions may include load conditions and output voltage conditions associated with the DAB converter, and the monitoring voltage conditions of each AFE converter. The operating condition may be one of the eight operating conditions as described above. The control variable calculation module 421 may generate control variables for each of the N levels of the AC / DC power converter system 100. The control variable calculation module 421 may generate a first pulse width D1 of the primary H-bridge output voltage associated with the DAB converter, a second pulse width D2 of the secondary H-bridge output voltage of each DAB converter, and a phase shift angle between the primary H-bridge output voltage and the secondary H-bridge output voltage. 1. The control variable calculation module 421 can generate D for the N levels of the AC / DC power converter system 100 1n , D 2n and n The first pulse width [D1, D 12 , …D 1n ] 433. The first pulse width of each DAB converter primary H-bridge output voltage [D2, D 22 , …D 2n ] 435 and the phase shift angle between each primary H-bridge output voltage and each secondary H-bridge output voltage [ 1, 2.… n ] 437. The PWM generator 439 may generate a second PWM signal 441 for precisely controlling and modulating power delivery to the load.

[0038] Figure 4B An exemplary flow chart of a controller architecture for managing soft start charging of a DAB converter is shown. In a particular embodiment, the DAB control subsystem 420 may include an average phase shift generation module 443, a power sharing calculation module 445, and a control variable calculation and operating condition detection module 447. The average phase shift generation module 443 may receive a second reference voltage V of the DAB output DC bus link. O * 423 and monitors the DC output voltage V dcO 425, and based on the DAB output DC bus link second reference voltage V O * 423 and monitors the DC output voltage V dcO 425 to calculate the average initial phase angle of each DAB converter 1_int 449, ... and n_int 451. The power sharing calculation module 445 can be based on the monitored DC output voltage V dcO 425 and the output current associated with each DAB converter [I O_1 , I O_2 ,…,I O_n ] 453 to calculate the power mismatch and generate the enhancement angle for each DAB converter [ 1, 2, ..., n ] 453 and duty cycle[ D1, D 12 , …, D 1n ]455 and [ D2, D 22 , …, D 2n ] 457. The control variable calculation and operating condition detection module 447 may receive the average initial phase angle of each DAB converter 1_int 449, ... and n_int 451. Enhancement angle of each DAB converter 1. 2. … n ] 453 and duty cycle[ D1, D 12 , …, D 1n ]455 and duty cycle[ D2, D 22 , …, D 2n ] 457, AFE internal DC bus link voltage V dc1 、V dc2 , … and V dcn (403, ... and 405), the switching frequency F of the AC / DC power converter system 100 s 427. Allowable time for charging the DC capacitor μ 429. Saturation value of duty cycle D nom 431 , and an operating condition for determining a control variable of a DAB converter (eg, the first DAB converter 130 ) of the AC / DC power converter system 100 .

[0039] In certain embodiments, the AFE control subsystem 410 may be operated when the computing system detects that the peak voltage of each DC bus of the plurality of AFE converters has reached a first threshold voltage and a phase-locked loop (PLL) lock signal during the rectification phase. For example, the AFE control subsystem 410 may be operated in the following manner: Figure 3 The DAB control subsystem 420 may start operating at t2 in the curve 310 shown in FIG. Figure 3 The operation is performed when the DAB converters simultaneously start ramping up at t2 as shown by curves 330 and 350 or at t3 as shown by curves 320 and 340 .

[0040] In a particular embodiment, the AC / DC power converter system 100 may include a power source (e.g., a battery) instead of the energy storage unit 140 connected to the DC output at 135. The power source may reverse charge the AC / DC power converter system 100 from the load side of the AC / DC power converter system 100. During the reverse charging process, the DC output voltage may be fed back to the AC input side, which may allow power to flow in the opposite direction when necessary to return power from the load side of the DAB DC output at the connection capacitor 135 to the power side of the connection AC power source 101. One or more computing systems may employ the DAB control subsystem 420 and the AFE control subsystem 410 to prevent excessive current from flowing through the AC / DC power converter system 100. The control system 400A of the single-phase AC / DC power converter system 100 may detect power flow detection of the phase shift angle.

[0041] Figure 5 An exemplary timing diagram of DAB AC voltage and inductor current when primary duty cycle and secondary duty cycle are used in addition to phase angle is shown. Figure 5 As shown, the rise time and fall time of the primary voltage V1 of the primary H-bridge output voltage of DAB can be expressed as x1 and x2. The rise time and fall time of the secondary voltage V2 of the secondary H-bridge output voltage of DAB can be expressed as y1 and y2. The time to rise from negative V2 can be expressed as y3.

[0042] (1a)

[0043] (1b)

[0044] (1c)

[0045] (1d)

[0046] (1e)

[0047] The instantaneous current is calculated for each operating region segment based on the following formula:

[0048] (2)

[0049] Z A and Z B Can be 0, x1, x2, y1, y2, y3 or 2, depending on the operating region and current segment. The output current may not be vertically symmetrical. However, after the transient, the current is symmetrical about the time axis. Therefore, the average value of the current can be calculated and subtracted from the instantaneous current. The average current can be calculated in a segmented manner:

[0050] (3)

[0051] The average power can be calculated segmentally in each region, where V1 and I are variables depending on the segment in each region:

[0052] (4)

[0053] In a particular embodiment, the power transfer for bidirectional pre-charging of DAB can be formulated by the following formula:

[0054] (5)

[0055] (6)

[0056] (7)

[0057] (8)

[0058] (9)

[0059] The expression of the average power behind the common term of is unit power. Controlling the duty cycle while keeping the phase shift controller idle can achieve pre-charging from any port of the AC / DC power converter system 100. In a particular embodiment, one or more computing systems can apply a power constraint to the duty cycle:

[0060] P1=0.5 in ( ) (10)

[0061] (11)

[0062] (12)

[0063] Once the MV or LV DC link is charged and regulated, the HFT 131 of the DAB converter 130 can be magnetized to pre-charge the desired DC bus. A switched three-level voltage with a gradually increasing duty cycle is applied to the two bridges of the DAB converter 130, which can apply a gradually increasing current in the HFT 131. In order to maintain a symmetrical current in the HFT 131, the duty cycles D1 and D2 are increased every two switching cycles. Once the converter startup is enabled, both the primary side switch and the secondary side switch are turned on, and the duty cycle increases smoothly according to equation (11), where D' is the desired startup duty cycle and D init is the calculated initial duty cycle. D init It is very important to determine at what duty cycle the precharge needs to start. The calculation system can be based on the following Figure 3 The initial duty cycle D calculated under the operating conditions shown in curves 340 and 350 init To determine at what duty cycle pre-charging needs to start. nom is the saturation value of the duty cycle, K is a constant, and µ is the time allowed for charging the DC capacitor.

[0064] In a specific embodiment, when the charging direction is MV to LV, the AFE converter 120 and other AFEs for the N levels of the AC / DC power converter system 100 can establish connections with the MV AC grid and the MV DC link. The DAB converter 130 and other DABs for the N levels of the AC / DC power converter system 100 can be used to achieve bidirectional operation. The AFE converter can first be synchronized with the MV AC grid. In a specific embodiment, the first pulse width D1 of the primary H-bridge output voltage of the DAB converter can be used to slowly change the primary side AC voltage of the HFT to a full square wave, and the second pulse width D2 of the secondary H-bridge output voltage of the DAB converter can be used to slowly ramp up the voltage on the secondary side of the HFT to a second reference value. When both sides reach the desired voltage ratio, the phase shift controller can be enabled to start steady-state operation. The multi-level soft-start charging method can prevent saturation of the HFT by reducing the inrush current.

[0065] In certain embodiments, the LV DC link is used to precharge and establish the MV DC link. One or more computing systems may receive an output voltage V associated with the DAB. dcO To the AFE internal DC link V of the control system 400A dc1 、V dc2 , … and V dcn The output voltage V can be increased by using an external power source (e.g., a battery). dcOMaintain constant at the reference voltage value. The external power supply can be current limited. The external current limited power supply can include a pre-charge DC resistor and a bypass switch. AFE internal DC link V dc1 、V dc2 , … and V dcn The voltages can be slowly ramped up to their reference values ​​while keeping the AFE disabled. Once the MV DC link reaches the voltage threshold and operates in steady state, the grid connection is established.

[0066] Figure 6 An exemplary three-phase AC / DC power converter system configuration is shown. The AC / DC power converter system 100 can be expanded to a three-phase AC / DC power converter system 500. The three-phase AC / DC power converter system 500 may include N series-connected AFE converters and N parallel-connected DAB levels for SST phase a. Similarly, the three-phase AC / DC power converter system 500 may further include another N series-connected AFE converters and N parallel-connected DAB levels for each SST phase b and SST phase c. The control system 400A and / or the DAB control system 400B may be used for each level of the AFE and DAB converter of each SST phase a, SST phase b, and SST phase c.

[0067] In a particular embodiment, one or more computing systems can enable the DAB converter 130 to ramp up under three-phase shift (TPS) modulation, which can optimize the efficiency of different operating areas and modes of DAB using unified three-degree-of-freedom control. The primary converter and secondary converter of DAB can use three-degree-of-freedom control variables to generate a three-level switching voltage waveform. One or more computing systems can independently adjust the duty cycle and phase shift ratio of the two full bridges to generate a three-level voltage waveform. When the inductor current is equal to zero, the voltage can be aligned and the secondary voltage can be turned off, wherein the secondary H bridge can be switched under zero current switching (ZCS). In a particular embodiment, one or more computing systems can detect that the current has reached the highest peak, and can automatically switch from TPS modulation to extended phase shift (EPS) modulation to remove the current offset in the transformer current based on detecting that the current has reached the highest peak, wherein the secondary H bridge of each DAB converter can be switched to a 50% duty cycle. In certain embodiments, one or more computing systems can detect that the output voltage of the DAB converter AC / DC power converter system 100 has reached a steady state and automatically switch from EPS modulation to single phase shift (SPS) modulation, which can use one degree of freedom control to regulate the output power flow of the DAB. By way of example and not limitation, the switch pairs in the two full bridges are gated to obtain a phase-shifted square waveform with a 50% duty cycle, and the phase shift angle between the bridges is The phase shift angle between the primary voltage and the secondary voltage is adjusted. This causes the leakage inductance of the transformer to change, thereby changing the direction and magnitude of power flow.

[0068] Figure 7 An exemplary computer system 700 is shown. In a particular embodiment, one or more computer systems 700 perform one or more steps of one or more methods described or shown herein. In a particular embodiment, one or more computer systems 700 provide the functionality described or shown herein. In a particular embodiment, software running on one or more computer systems 700 performs one or more steps of one or more methods described or shown herein, or provides the functionality described or shown herein. A particular embodiment includes one or more portions of one or more VAS computer systems 700. Herein, references to computer systems may include computing devices, and vice versa, where appropriate. In addition, references to computer systems may include one or more computer systems, where appropriate.

[0069] The present disclosure contemplates any suitable number of computer systems 700. The present disclosure contemplates computer systems 700 taking any suitable physical form. By way of example and not limitation, computer system 700 may be an embedded computer system, a system on a chip (SOC), a single board computer system (SBC) (such as, for example, a computer on a module (COM) or a system on a module (SOM)), a desktop computer system, a laptop or notebook computer system, an interactive kiosk, a mainframe, a network of computer systems, a mobile phone, a personal digital assistant (PDA), a server, a tablet computer system, or a combination of two or more of these. Where appropriate, computer system 700 may include one or more computer systems 700; single or distributed; across multiple locations; across multiple machines; across multiple data centers; or reside in a cloud, which may include one or more cloud components in one or more networks. Where appropriate, one or more computer systems 700 may perform one or more steps of one or more methods described or illustrated herein without substantial spatial or temporal limitations. By way of example and not limitation, one or more computer systems 700 may perform one or more steps of one or more methods described or illustrated herein in real time or in batch mode. Where appropriate, one or more computer systems 700 may perform at different times or different locations one or more steps of one or more methods described or illustrated herein.

[0070] In a particular embodiment, computer system 700 includes a processor 702, a memory 704, a storage device 706, an input / output (I / O) interface 708, a communication interface 710, and a bus 712. Although this disclosure describes and illustrates a particular computer system having particular numbers of particular components in a particular arrangement, this disclosure contemplates any suitable computer system having any suitable numbers of any suitable components in any suitable arrangement.

[0071] In a particular embodiment, the processor 702 includes hardware for executing instructions, such as those that constitute a computer program. By way of example and not limitation, to execute instructions, the processor 702 may retrieve (or fetch) instructions from an internal register, an internal cache, memory 704, or storage 706; decode and execute them; and then write one or more results to an internal register, an internal cache, memory 704, or storage 706. In a particular embodiment, the processor 702 may include one or more internal caches for data, instructions, or addresses. Where appropriate, the present disclosure contemplates that the processor 702 includes any suitable number of any suitable internal caches. By way of example and not limitation, the processor 702 may include one or more instruction caches, one or more data caches, and one or more translation lookaside buffers (TLBs). The instructions in the instruction cache may be copies of the instructions in the memory 704 or storage 706, and the instruction cache may speed up the retrieval of those instructions by the processor 702. The data in the data cache may be a copy of data in the memory 704 or storage 706 for instructions executed at the processor 702 to operate thereon; the results of previous instructions executed at the processor 702 for access by subsequent instructions executed at the processor 702 or for writing to the memory 704 or storage 706; or other suitable data. The data cache may speed up read or write operations of the processor 702. The TLB may speed up virtual address translation of the processor 702. In a particular embodiment, the processor 702 may include one or more internal registers for data, instructions, or addresses. Where appropriate, the present disclosure contemplates that the processor 702 includes any suitable number of any suitable internal registers. Where appropriate, the processor 702 may include one or more arithmetic logic units (ALUs); be a multi-core processor; or include one or more processors 702. Although the present disclosure describes and illustrates a particular processor, the present disclosure contemplates any suitable processor.

[0072] In particular embodiments, the memory 704 includes a main memory for storing instructions for execution by the processor 702 or data for operation by the processor 702. By way of example and not limitation, the computer system 700 may load instructions from the storage device 706 or another source (such as, for example, another computer system 700) to the memory 704. The processor 702 may then load the instructions from the memory 704 to an internal register or an internal cache. To execute the instructions, the processor 702 may retrieve the instructions from the internal register or the internal cache and decode them. During or after execution of the instructions, the processor 702 may write one or more results (which may be intermediate results or final results) to the internal register or the internal cache. The processor 702 may then write one or more of those results to the memory 704. In particular embodiments, the processor 702 executes only instructions in one or more internal registers or internal caches or memory 704 (as opposed to the storage device 706 or elsewhere) and operates only on data in one or more internal registers or internal caches or memory 704 (as opposed to the storage device 706 or elsewhere). One or more memory buses (which may each include an address bus and a data bus) may couple the processor 702 to the memory 704. The bus 712 may include one or more memory buses, as described below. In a particular embodiment, one or more memory management units (MMUs) reside between the processor 702 and the memory 704 and facilitate access to the memory 704 requested by the processor 702. In a particular embodiment, the memory 704 includes a random access memory (RAM). Where appropriate, the RAM may be a volatile memory. Where appropriate, the RAM may be a dynamic RAM (DRAM) or a static RAM (SRAM). In addition, where appropriate, the RAM may be a single-port or multi-port RAM. The present disclosure contemplates any suitable RAM. Where appropriate, the memory 704 may include one or more memories 704. Although the present disclosure describes and illustrates specific memories, the present disclosure contemplates any suitable memory.

[0073] In a particular embodiment, the storage device 706 includes a mass storage device for data or instructions. As an example and not a limitation, the storage device 706 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the storage device 706 may include a removable or non-removable (or fixed) medium. Where appropriate, the storage device 706 may be inside or outside the computer system 700. In a particular embodiment, the storage device 706 is a non-volatile solid-state memory. In a particular embodiment, the storage device 706 includes a read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically alterable ROM (EAROM), or a flash memory, or a combination of two or more of these. The present disclosure contemplates a mass storage device 706 in any suitable physical form. Where appropriate, the storage device 706 may include one or more storage control units that facilitate communication between the processor 702 and the storage device 706. Where appropriate, storage 706 may include one or more storage devices 706. Although this disclosure describes and illustrates particular storage devices, this disclosure contemplates any suitable storage devices.

[0074] In a particular embodiment, the I / O interface 708 includes hardware, software, or both, providing one or more interfaces for communication between the computer system 700 and one or more I / O devices. Where appropriate, the computer system 700 may include one or more of these I / O devices. One or more of these I / O devices can enable communication between a person and the computer system 700. As an example and not a limitation, the I / O device may include a keyboard, a keypad, a microphone, a monitor, a mouse, a printer, a scanner, a speaker, a static camera, a stylus, a tablet computer, a touch screen, a trackball, a camera, another suitable I / O device, or a combination of two or more of these. The I / O device may include one or more sensors. The present disclosure contemplates any suitable I / O device and any suitable I / O interface 708 for them. Where appropriate, the I / O interface 708 may include one or more devices or software drivers that enable the processor 702 to drive one or more of these I / O devices. Where appropriate, the I / O interface 708 may include one or more I / O interfaces 708. Although the present disclosure describes and illustrates a specific I / O interface, the present disclosure contemplates any suitable I / O interface.

[0075] In a particular embodiment, the communication interface 710 includes hardware, software, or both, providing one or more interfaces for communication (such as, for example, packet-based communication) between the computer system 700 and one or more other computer systems 700 or one or more networks. As an example and not a limitation, the communication interface 710 may include a network interface controller (NIC) or a network adapter for communicating with an Ethernet or other wired network, or a wireless NIC (WNIC) or a wireless adapter for communicating with a wireless network such as a WI-FI network. The present disclosure contemplates any suitable network and any suitable communication interface 710 for it. As an example and not a limitation, the computer system 700 can communicate with one or more parts of a self-organizing network, a personal area network (PAN), a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), or the Internet, or a combination of two or more of these. One or more parts of one or more of these networks may be wired or wireless. As an example, the computer system 700 may communicate with a wireless PAN (WPAN) (such as, for example, a Bluetooth WPAN), a WI-FI network, a WI-MAX network, a cellular telephone network (such as, for example, a Global System for Mobile Communications (GSM) network), or other suitable wireless networks, or a combination of two or more of these. Where appropriate, the computer system 700 may include any suitable communication interface 710 for any of these networks. Where appropriate, the communication interface 710 may include one or more communication interfaces 710. Although the present disclosure describes and illustrates particular communication interfaces, the present disclosure contemplates any suitable communication interface.

[0076] In a particular embodiment, bus 712 includes hardware, software, or both that couples components of computer system 700 to each other. By way of example and not limitation, bus 712 may include an accelerated graphics port (AGP) or other graphics bus, an enhanced industry standard architecture (EISA) bus, a front side bus (FSB), a hypertransport (HT) interconnect, an industry standard architecture (ISA) bus, an InfiniBand interconnect, a low pin count (LPC) bus, a memory bus, a microchannel architecture (MCA) bus, a peripheral component interconnect (PCI) bus, a PCI-Express (PCIe) bus, a serial advanced technology attachment (SATA) bus, a video electronics standard association local (VLB) bus, or another suitable bus or a combination of two or more of these. Where appropriate, bus 712 may include one or more buses 712. Although the present disclosure describes and illustrates a particular bus, the present disclosure contemplates any suitable bus or interconnect.

[0077] Herein, where appropriate, the one or more computer-readable non-transitory storage media may include one or more semiconductor-based or other integrated circuits (ICs) (such as, for example, field programmable gate arrays (FPGAs) or application-specific ICs (ASICs)), hard disk drives (HDDs), hybrid hard disk drives (HHDs), optical disks, optical disk drives (ODDs), magneto-optical disks, magneto-optical disk drives (FDDs), floppy disks, floppy disk drives (FDDs), magnetic tapes, solid-state drives (SSDs), RAM drives, secure digital cards or drives, any other suitable computer-readable non-transitory storage media, or any suitable combination of two or more of these. Where appropriate, the computer-readable non-transitory storage media may be volatile, non-volatile, or a combination of volatile and non-volatile.

[0078] As used herein, "or" is inclusive rather than exclusive, unless expressly indicated otherwise or the context indicates otherwise. Thus, as used herein, "A or B" means "A, B, or both," unless expressly indicated otherwise or the context indicates otherwise. Additionally, "and" is both conjunctive and singular, unless expressly indicated otherwise or the context indicates otherwise. Thus, as used herein, "A and B" means "A and B, jointly or singly," unless expressly indicated otherwise or the context indicates otherwise.

[0079] The scope of the present disclosure includes all changes, substitutions, variations, alterations and modifications to the exemplary embodiments described or shown herein that will be understood by those of ordinary skill in the art. The scope of the present disclosure is not limited to the exemplary embodiments described or shown herein. In addition, although the present disclosure describes and illustrates the corresponding embodiments herein as including specific parts, elements, features, functions, operations or steps, any of these embodiments may include any combination or arrangement of any parts, elements, features, functions, operations or steps described or shown anywhere herein that will be understood by those of ordinary skill in the art. In addition, in the appended claims, references to devices or systems or parts of devices or systems adapted, arranged, capable, configured, enabled, operable or operated to perform specific functions include the device, system, component, whether or not it or the specific function is activated, turned on or unlocked, as long as the device, system or component is so adapted, arranged, capable, configured, enabled, operable or operated. In addition, although the present disclosure describes or illustrates specific embodiments as providing specific advantages, specific embodiments may not provide these advantages, provide some advantages or provide all of these advantages.

Claims

1. A method implemented by a computer system, comprising: receiving a DC bus voltage condition of a plurality of AC-to-DC converters of an input-series-output-parallel (ISOP) power converter during a rectification phase for precharging a DC bus of the plurality of said AC-to-DC converters; detecting that (1) a peak voltage of each of the DC buses in the plurality of the AC to DC converters during the rectification phase has reached a first threshold voltage, and (2) a phase locked loop (PLL) signal indicates a locked state with an AC grid voltage; upon detecting that the PLL signal indicates the locked state with the AC grid voltage, enabling first voltage regulation to charge the AC to DC output of each of the plurality of AC to DC converters to a first reference voltage; determining an operating condition of an ISOP power converter, wherein the operating condition comprises (1) a load condition and an output voltage condition associated with a plurality of dual active bridge (DAB) converters, and (2) a monitored voltage condition of each of the plurality of AC to DC converters; based on the operating condition, enabling a second voltage regulation of each of the plurality of DAB converters to charge the DAB output to a second reference voltage within a current limit; and The second reference voltage is maintained for the output voltage condition.

2. The method according to claim 1, further comprising: generating control variables for the second voltage regulation based on the operating conditions, wherein the control variables include a first pulse width of a primary H-bridge output voltage of each of the DAB converters, a second pulse width of a secondary H-bridge output voltage of each of the DAB converters, and a phase shift angle between the primary H-bridge output voltage and the secondary H-bridge output voltage; and Based on the control variable, the second voltage regulation of each of the plurality of the DAB converters is enabled to reach the second reference voltage within the current limit.

3. The method according to claim 1, further comprising: pre-charging the DC buses of a plurality of the AC to DC converters using power connected to an output of the DAB converter; as well as Based on the control variable, reverse charging voltage regulation within the current limit is enabled for each of the plurality of AC to DC converters.

4. The method according to claim 1, wherein: The load condition includes a no-load condition and a partial-load condition.

5. The method according to claim 1, wherein: The output voltage condition includes a zero output voltage condition and a partial output voltage condition.

6. The method according to claim 5, further comprising: An initial voltage value associated with the portion of the output voltage condition is monitored.

7. The method according to claim 1, wherein: The monitored voltage condition of each of the plurality of AC to DC converters includes that the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the first reference voltage, and the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the peak voltage, while the PLL signal indicates the locked state with the AC grid voltage.

8. The method according to claim 7, further comprising: When it is detected that the monitored voltage condition of each of the plurality of the AC to DC converters has reached the first reference voltage, the second voltage regulation of each of the plurality of the DAB converters is simultaneously enabled to charge the DAB output to reach the second reference voltage.

9. The method according to claim 7, further comprising: When it is detected that the monitored voltage condition of each of the plurality of the AC to DC converters has reached the peak voltage while the PLL signal indicates the locked state with the AC grid voltage, the second voltage regulation of each of the plurality of the DAB converters is simultaneously enabled to charge the DAB output to reach the second reference voltage.

10. The method according to claim 1, wherein: Maintaining the second reference voltage for the output voltage condition includes at least one of enabling AC to DC voltage regulation and enabling DC to DC voltage regulation.

11. The method according to claim 1, wherein: The rectification phase for pre-charging the DC bus of the plurality of the AC to DC converters is enabled via a pre-charge switch system, wherein the pre-change switch system comprises a first switch and a resistor for reducing surge current, and a bypass second switch, the bypass second switch being operated when the peak voltage of each of the DC buses of the plurality of the AC to DC converters has reached the first threshold voltage during the rectification phase.

12. A system comprising: one or more processors; and a non-transitory memory coupled to the processor, the non-transitory memory comprising instructions executable by the processor, the processor, when executing the instructions, being operable to: receiving a DC bus voltage condition of a plurality of AC-to-DC converters of an input-series-output-parallel (ISOP) power converter during a rectification phase for precharging a DC bus of the plurality of said AC-to-DC converters; detecting that (1) a peak voltage of each of the DC buses in the plurality of the AC to DC converters during the rectification phase has reached a first threshold voltage, and (2) a phase locked loop (PLL) signal indicates a locked state with an AC grid voltage; upon detecting that the PLL signal indicates the locked state with the AC grid voltage, enabling first voltage regulation to charge the AC to DC output of each of the plurality of AC to DC converters to a first reference voltage; determining an operating condition of an ISOP power converter, wherein the operating condition comprises (1) a load condition and an output voltage condition associated with a plurality of dual active bridge (DAB) converters, and (2) a monitored voltage condition of each of the plurality of AC to DC converters; based on the operating condition, enabling a second voltage regulation of each of the plurality of DAB converters to charge the DAB output to a second reference voltage within a current limit; and The second reference voltage is maintained for the output voltage condition.

13. The system according to claim 12, wherein: The processor, when executing the instructions, is further operable to: generating control variables for the second voltage regulation based on the operating conditions, wherein the control variables include a first pulse width of a primary H-bridge output voltage of each of the DAB converters, a second pulse width of a secondary H-bridge output voltage of each of the DAB converters, and a phase shift angle between the primary H-bridge output voltage and the secondary H-bridge output voltage; and Based on the control variable, the second voltage regulation of each of the plurality of the DAB converters is enabled to reach the second reference voltage within the current limit.

14. The system according to claim 12, wherein: The processor, when executing the instructions, is further operable to: pre-charging the DC buses of a plurality of the AC to DC converters using power connected to an output of the DAB converter; as well as Based on the control variable, reverse charging voltage regulation within the current limit is enabled for each of the plurality of AC to DC converters.

15. The system of claim 12, wherein: The load condition includes a no-load condition and a partial-load condition.

16. The system of claim 12, wherein: The output voltage condition includes a zero output voltage condition and a partial output voltage condition.

17. The system of claim 12, wherein: The monitored voltage condition of each of the plurality of AC to DC converters includes that the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the first reference voltage, and the monitored voltage condition of the AC to DC output of each of the plurality of AC to DC converters has reached the peak voltage, while the PLL signal indicates the locked state with the AC grid voltage.

18. The system of claim 17, wherein: The processor, when executing the instructions, is further operable to: When it is detected that the monitored voltage condition of each of the plurality of the AC to DC converters has reached the first reference voltage, the second voltage regulation of each of the plurality of the DAB converters is simultaneously enabled to charge the DAB output to reach the second reference voltage.

19. The system of claim 17, wherein: The processor, when executing the instructions, is further operable to: When it is detected that the monitored voltage condition of each of the plurality of the AC to DC converters has reached the peak voltage while the PLL signal indicates the locked state with the AC grid voltage, the second voltage regulation of each of the plurality of the DAB converters is simultaneously enabled to charge the DAB output to reach the second reference voltage.

20. One or more computer-readable non-transitory storage media containing software that, when executed, is operable to: receiving a DC bus voltage condition of a plurality of AC-to-DC converters of an input-series-output-parallel (ISOP) power converter during a rectification phase for precharging a DC bus of the plurality of said AC-to-DC converters; detecting that (1) a peak voltage of each of the DC buses in the plurality of the AC to DC converters during the rectification phase has reached a first threshold voltage, and (2) a phase locked loop (PLL) signal indicates a locked state with an AC grid voltage; upon detecting that the PLL signal indicates the locked state with the AC grid voltage, enabling first voltage regulation to charge the AC to DC output of each of the plurality of AC to DC converters to a first reference voltage; determining an operating condition of an ISOP power converter, wherein the operating condition comprises (1) a load condition and an output voltage condition associated with a plurality of dual active bridge (DAB) converters, and (2) a monitored voltage condition of each of the plurality of AC to DC converters; based on the operating condition, enabling a second voltage regulation of each of the plurality of DAB converters to charge the DAB output to a second reference voltage within a current limit; and The second reference voltage is maintained for the output voltage condition.

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