ATE-based UIS and Rdson joint test circuit and test method

Abstract

The present invention provides an ATE-based combined UIS and Rdson test circuit and test method, relating to the technical field of integrated circuit testing. The ATE-based combined UIS and Rdson test circuit of the present invention comprises an ATE, a generating circuit, an amplifying circuit, and a comparing circuit; the power supplies in the generating circuit, the amplifying circuit, and the comparing circuit are provided by the ATE, and the generating circuit comprises a first high-speed switch group, a second high-speed switch group, an air-core inductor, a current-sense resistor, and a first diode. The present invention uses the current-sense resistor, the amplifying circuit, and the comparing circuit to replace and monitor the current waveform in the circuit, and writes relevant programs to control the power supply of the test circuit and collect relevant data and waveforms on an ATE machine, accurately obtaining the magnitude of avalanche energy and the Rdson test value, thereby reducing the number of test items to be written and the test time, improving test efficiency, and reducing test costs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to an ATE-based UIS and Rdson combined testing circuit and testing method. Background Art

[0002] With the continuous advancement of power electronics technology, especially as the frequency of modern power electronic circuits continues to increase, the operating environment faced by power switching devices has become increasingly complex and demanding. Under high-frequency operating conditions, power switching devices must withstand higher voltage and current rates of change, placing higher demands on device reliability and performance. In practical applications, loads often include significant inductive loads such as solenoids and motors, as well as additional stray inductance introduced by improper circuit design and complex system wiring. These factors can cause voltage overshoot or ringing during the switching process, causing the voltage across the device to momentarily exceed its rated operating voltage range, potentially damaging the device and ultimately leading to failure of the power electronics system.

[0003] To gain a deeper understanding of the performance of power switching devices in such complex operating environments, researchers have designed various testing methods, among which UIS (Unclamped Inductive Load Switching) testing is the most important. UIS testing can be used to assess the ability of power switching devices to withstand high voltage and current surges, particularly their energy handling capacity during avalanche breakdown. This test is not only crucial for evaluating device stability but also provides valuable data for device design, helping engineers optimize device performance and improve reliability in harsh operating environments. Furthermore, Rdson (on-resistance) testing of power switching devices is a key performance metric. Rdson refers to the resistance between the drain and source terminals of a device in the on state, which directly affects power loss. The conduction loss of a power switching device is often closely correlated with the Rdson value. The larger the on-resistance, the greater the power loss during device conduction, which affects overall system efficiency. Therefore, accurately measuring the avalanche breakdown energy Rdson value is crucial for the design and application of power switching devices.

[0004] Most existing test solutions focus on testing a single parameter, making it impossible to measure both parameters simultaneously during the same test. However, in practical applications, switching power devices often need to withstand high voltage surges and high on-resistance simultaneously, requiring simultaneous testing of both UIS and Rdson. Existing test solutions perform UIS and Rdson tests separately, resulting in low test efficiency. Summary of the Invention

[0005] (1) Technical problems solved

[0006] In view of the deficiencies of the prior art, the present invention provides an ATE-based UIS and Rdson combined test circuit and test method, which solves the technical problem of low test efficiency of the existing test scheme.

[0007] (2) Technical solution

[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0009] In a first aspect, the present invention provides an ATE-based UIS and Rdson combined test circuit, comprising: an ATE, a generating circuit, an amplifying circuit, and a comparing circuit; wherein the power supplies of the generating circuit, the amplifying circuit, and the comparing circuit are provided by the ATE;

[0010] The generating circuit includes a first high-speed switch group, a second high-speed switch group, an air-core inductor, a current-sense resistor and a first diode.

[0011] The first end of the first high-speed switch group is connected to the control end of the power switch device to be tested;

[0012] The first end of the power switch device to be tested is connected to the first end of the second high-speed switch group via an air-core inductor, and the second end of the second high-speed switch group is connected to the second end of the power switch device to be tested via a current-sense resistor;

[0013] The anode of the first diode is connected to the common end of the current-sense resistor and the second high-speed switch group, and the cathode is connected to the common end of the air-core inductor and the second high-speed switch group;

[0014] The two input terminals of the amplifier circuit are connected to the two ends of the current-sense resistor, the output terminal is connected to the first input terminal of the comparison circuit, the second input terminal of the comparison circuit is connected to the reference voltage; the output terminal of the comparison circuit is connected to the third terminal of the second high-speed switch group;

[0015] The second end of the first high-speed switch group is connected to the common end of the comparison circuit and the second high-speed switch group;

[0016] The amplification circuit is used to obtain the current waveform in the circuit and capture it through ATE-related resources to obtain the peak current during the entire avalanche process; the comparison circuit is used to detect the peak current in the circuit. When the peak current is reached, the comparison circuit outputs a negative voltage to control the disconnection of the high-speed switches in the first high-speed switch group and the second high-speed switch group, thereby stopping the voltage supply of the ATE resources, causing the power switch device to be tested to enter the off state. The air-core inductor causes the power switch device to be tested to enter the avalanche breakdown state through discharge. The entire process of avalanche breakdown obtains relevant test data and related waveforms through ATE resources.

[0017] Preferably, the first high-speed switch group includes a first switch tube, a second switch tube and a second resistor;

[0018] The first end of the first switch tube is the first end of the first high-speed switch group; the gate of the first switch tube is connected to the first end of the second switch tube, and the second end of the second switch tube is the second end of the first high-speed switch group; the two ends of the second resistor are respectively connected to the second end and the gate of the first switch tube;

[0019] The second end of the first switch tube is connected to the power supply provided by the ATE; the second end of the second switch tube is grounded or at a low voltage.

[0020] Preferably, the first switch tube is a PMOS, and the second switch tube is an NMOS, wherein the first end of the PMOS and the NMOS is a drain, and the second end is a source;

[0021] Alternatively, the first switch tube is a P-channel IGBT, and the second switch tube is an N-channel IGBT, wherein the first end of the P-channel IGBT and the N-channel IGBT is the collector, and the second end is the emitter.

[0022] Preferably, the second high-speed switch group includes a third switch tube, a fourth switch tube and a third resistor;

[0023] Wherein, the first end of the third switch tube is the first end of the second high-speed switch group;

[0024] The gate of the third switch tube is connected to the first end of the fourth switch tube, and the common end thereof is the second end of the second high-speed switch group;

[0025] The gate of the fourth switch tube is the third terminal of the first high-speed switch group;

[0026] Two ends of the third resistor are connected to the second end and the gate of the third switch tube respectively;

[0027] The second end of the third switch tube is connected to the power supply provided by the ATE; the second end of the fourth switch tube is grounded or at a low voltage.

[0028] Preferably, the third switch tube is a PMOS, and the fourth switch tube is an NMOS, wherein the first end of the PMOS and the NMOS is a drain, and the second end is a source;

[0029] Alternatively, the third switch tube is a P-channel IGBT, and the fourth switch tube is an N-channel IGBT, wherein the first end of the P-channel IGBT and the N-channel IGBT is the collector, and the second end is the emitter.

[0030] Preferably, a compensation circuit is further included, and the compensation circuit is used to compensate for the offset error in the amplifying circuit.

[0031] In a second aspect, the present invention provides an ATE-based UIS and Rdson joint testing method, wherein the UIS and Rdson joint testing method is used to control the UIS and Rdson joint testing circuit as described above to perform the following steps:

[0032] Use the ATE machine to provide the power required for the test circuit to turn on the device, and select the ATE test board resources according to the parameters of the power switching device to be tested;

[0033] Use a power supply to charge the air-core inductor to reach the peak current of the test;

[0034] Use a current-sense resistor and an amplifier circuit to monitor the current in the circuit;

[0035] Use a comparison circuit to monitor the peak current during the test;

[0036] When the comparator outputs a negative voltage, the power supply is stopped and the power switch device under test is controlled to be turned off;

[0037] Use an air-core inductor to discharge and put the power switch device under test into an avalanche state;

[0038] Use ATE equipment to collect test data and waveforms.

[0039] Preferably, when using a current-sense resistor and an amplifier circuit to monitor the current in the circuit, the UIS and Rdson combined testing method further comprises: performing real-time compensation on the amplifier circuit through a compensation circuit.

[0040] Preferably, when the comparator outputs a negative voltage, stopping the power supply and controlling the shutdown of the power switch device to be tested includes:

[0041] The output voltage of the comparator is detected. When the comparator outputs a negative voltage, the high-speed switch that controls the gate voltage of the device under test and the charging voltage of the air-core inductor is disconnected, the voltage supply stops, and the device under test enters the shutdown state.

[0042] Preferably, the ATE test board resources include the turn-on gate voltage required by the power switch device to be tested, the air-core inductor charging voltage, and the power supply voltages of the comparator and amplifier.

[0043] (3) Beneficial effects

[0044] The present invention provides an ATE-based UIS and Rdson combined test circuit and test method. Compared with the existing technology, it has the following advantages:

[0045] The present invention uses a current-sense resistor, an amplifier circuit, and a comparison circuit to replace and monitor the current waveform in the circuit, and writes relevant programs to control the power supply of the test circuit and collect relevant data and waveforms on an ATE machine, accurately obtaining the size of the avalanche energy and the Rdson test value, thereby reducing the number of test items to be written and the test time, improving test efficiency, and reducing test costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 This is a schematic diagram of an ATE-based UIS and Rdson combined test circuit in Example 1;

[0048] Figure 2 This is a circuit diagram of an ATE-based UIS and Rdson combined test circuit in Example 1;

[0049] Figure 3 This is a circuit diagram of an ATE-based UIS and Rdson combined test circuit including a compensation circuit in Example 1;

[0050] Figure 4 This is a block diagram of an ATE-based UIS and Rdson joint test in Example 2;

[0051] Figure 5 This is a specific flow chart of step S5 in Example 2. DETAILED DESCRIPTION

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention are clearly and completely described. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0053] The embodiments of the present application solve the technical problem of low test efficiency of existing test schemes by providing an ATE-based UIS and Rdson joint test circuit and test method, so that two key parameters, avalanche energy and Rdson, can be obtained simultaneously through one test process, ensuring accuracy while greatly improving test efficiency.

[0054] The technical solution in the embodiments of the present application is to solve the above technical problems, and the overall idea is as follows:

[0055] The UIS test and Rdson test of power switching devices are two important indicators for evaluating the performance of power switching devices. Although there are some mature solutions for measuring UIS and Rdson separately at home and abroad, most of the existing technologies are aimed at testing a single parameter and cannot obtain both parameters simultaneously during the same test process. In fact, in practical applications, switching power devices often need to withstand high voltage shocks and high on-resistance at the same time, so the testing requirements for UIS and Rdson are synchronized. If a test method can be designed to test UIS and Rdson simultaneously, it will be able to greatly improve test efficiency, save time and costs, and have important economic value, especially in large-scale production or product quality control. At the same time, it is of great significance to reduce the cost of integrated circuit testing and improve test efficiency.

[0056] In order to solve the above problems, the embodiment of the present invention provides an ATE-based UIS and Rdson combined test circuit and test method. First, the ATE machine resources are used to provide voltage to the gate of the power switch device under test and the air-core inductor, so that the power switch device under test is turned on. At the same time, the air-core inductor starts to charge, and the voltage across the drain and source of the power switch device under test also rises. Then, the current in the circuit is converted into voltage through a high-precision current-sense resistor and reasonably amplified by an amplifier. At the same time, the compensation amplifier supplements the amplification circuit. By setting the flip voltage of the comparator, when the set threshold is reached, the current in the circuit is converted into voltage. When the voltage is high, the amplifier output jumps from a positive voltage to a negative voltage. Due to the application of the negative voltage, the high-speed switch that controls the gate input voltage and the air-core inductor charging voltage is turned off, the power switching device under test enters the off state, and the charging of the air-core inductor is completed. Since the current in the air-core inductor cannot change suddenly, the air-core inductor will quickly discharge the current into the power switching device under test, causing the power switching device under test to enter an avalanche breakdown state. The voltage across the drain and source of the power switching device under test will be clamped to the breakdown voltage. When the current drops to zero, the avalanche breakdown ends, and the voltage across the drain and source of the power switching device under test will drop to zero.

[0057] During the on-state of the power switching device under test, when the current in the circuit reaches the Rdson test current condition, the voltage across the drain and source of the power switching device under test can be obtained by controlling the ATE, thereby obtaining the Rdson value of the power switching device under test. After the avalanche breakdown is completed, the ATE reads the relevant test parameters to obtain the avalanche energy during the avalanche process, and the results are printed on the ATE software interface, thus achieving simultaneous measurement of two parameters. This method can effectively shorten test time, reduce the number of test items to be written, and improve test efficiency.

[0058] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0059] Example 1:

[0060] This embodiment provides a UIS and Rdson joint test circuit based on ATE, such as Figure 1 As shown, it includes: ATE, a generating circuit, an amplifying circuit and a comparing circuit; wherein the power supply of the generating circuit, the amplifying circuit and the comparing circuit is provided by the relevant resources of the ATE;

[0061] The generating circuit includes a first high-speed switch group, a second high-speed switch group, an air-core inductor L, a current-sense resistor R1 and a first diode D1.

[0062] The first end of the first high-speed switch group is connected to the control end of the power switch device to be tested;

[0063] The first end of the power switch device to be tested is connected to the first end of the second high-speed switch group via the air-core inductor L, and the second end of the second high-speed switch group is connected to the second end of the power switch device to be tested via the current-sense resistor R1;

[0064] The anode of the first diode D1 is connected to the common end of the current-sense resistor R1 and the second high-speed switch group, and the cathode is connected to the common end of the air-core inductor and the second high-speed switch group;

[0065] The two input terminals of the amplifier circuit are connected to the two ends of the current-sense resistor, the output terminal is connected to the first input terminal of the comparison circuit, the second input terminal of the comparison circuit is connected to the reference voltage; the output terminal of the comparison circuit is connected to the third terminal of the second high-speed switch group;

[0066] The second end of the first high-speed switch group is connected to the common end of the comparison circuit and the second high-speed switch group;

[0067] The amplification circuit is used to obtain the current waveform in the circuit and capture it through ATE-related resources to obtain the peak current during the entire avalanche process; the comparison circuit is used to detect the peak current in the circuit. When the peak current is reached, the comparison circuit outputs a negative voltage to control the disconnection of the high-speed switches in the first high-speed switch group and the second high-speed switch group, thereby stopping the voltage supply of the ATE resources, causing the power switch device to be tested to enter the off state. The air-core inductor causes the power switch device to be tested to enter the avalanche breakdown state through discharge. The entire process of avalanche breakdown obtains relevant test data and related waveforms through ATE resources.

[0068] It should be noted that in Figure 1The power switch device under test is an NMOS device, with its first terminal being the drain, its second terminal being the source, and its control terminal being the gate. In specific implementations, the power switch device under test can also be a PMOS device, an N-channel IGBT, or a P-channel IGBT. For an IGBT, its first terminal is the collector, its second terminal is the emitter, and its control terminal is the gate. The connection method for both N-channel and P-channel IGBTs is the same.

[0069] It should be noted that during the implementation process, the current and test frequency in the combined test were relatively high. Ordinary inductors may saturate under high current conditions, resulting in changes in inductance value. Air-core inductors do not saturate and can maintain consistent inductance values ​​over a wider current range. Furthermore, ordinary inductors tend to concentrate magnetic fields and generate electromagnetic interference, while air-core inductors reduce the generation of electromagnetic interference and avoid magnetic saturation.

[0070] It should be noted that if Figure 1 In the embodiment, the amplifying circuit adopts an amplifier, and the comparing circuit adopts a comparator.

[0071] like Figure 2 As shown, both the first and second high-speed switch groups include PMOS, NMOS, and some resistors. Because they are high-side drivers, a PMOS is used at one end connected to the power switch device under test. Due to the high power supply voltage, to ensure the switching speed of the PMOS, an NMOS is required for level conversion to drive the PMOS on and off. During operation, when the amplifier output is high, the NMOS turns on, pulling the G-pole voltage of the PMOS down to 0. A voltage difference exists between the S-pole and G-pole terminals of the PMOS, causing the PMOS to turn on and the power switch device under test, allowing the power supply to charge the air-core inductor. When the amplifier output is low, the NMOS turns off, pulling the G-pole voltage of the PMOS up to the power supply voltage through the resistor. The S-pole voltage disappears, causing the PMOS to turn off and the power switch device under test to shut down, stopping the power supply from charging the air-core inductor. At this point, the current rapidly decreases and enters the power switch device under test, causing it to enter an avalanche breakdown state. In the specific implementation process, PMOS is changed to P-channel IGBT, NMOS is changed to N-channel IGBT, SG corresponds to EG, and the connection method is also to change the source to the emitter of IGBT, and the drain to the collector of IGBT.

[0072] like Figure 3As shown, in a specific implementation, to prevent detection errors caused by offset errors in the amplifiers within the amplification circuit, the combined UIS and Rdson test circuit also includes a compensation circuit. This compensation circuit comprises an amplifier (for ease of description, the amplifier within the amplification circuit is referred to as the first amplifier, and the amplifier within the compensation circuit is referred to as the second amplifier). The inverting input of the second amplifier is connected to the non-inverting input of the first amplifier. Two connection ports, A and B, are sequentially provided on the connection line between the output of the first amplifier and the inverting input of the comparator (i.e., A is closer to the first amplifier, and B is closer to the comparator). The output of the second amplifier is connected to the connection port A, and the inverting input of the second amplifier is connected to the connection port B.

[0073] Example 2:

[0074] This embodiment provides a UIS and Rdson joint test method based on ATE. The joint test method is used to control the UIS and Rdson joint test circuit described in Example 1 to perform the following steps: Figure 4 To complete the UIS and Rdson joint test, perform the following steps:

[0075] S1. Use the ATE machine to provide the power required for the test circuit to turn on the device, and select the ATE test board resources according to the parameters of the power switch device to be tested;

[0076] S2. Use a power supply to charge the air-core inductor to reach the peak current of the test;

[0077] S3. Use a current-sense resistor and an amplifier circuit to monitor the current in the circuit;

[0078] S4. Use a comparison circuit to monitor the peak current during the test;

[0079] S5. When the comparator outputs a negative voltage, the power supply is stopped and the power switch device under test is turned off;

[0080] S6. Use an air-core inductor to discharge, so that the power switch device under test enters an avalanche state;

[0081] S7. Use the ATE machine to collect test data and waveforms.

[0082] The following describes each step in detail:

[0083] In step S1, the ATE machine is used to provide the power required for the test circuit to turn on the device, and the ATE test board resources are selected according to the parameters of the power switch device to be tested. The specific implementation process is as follows:

[0084] First, select appropriate ATE test board resources based on the voltage provided by each part of the test circuit and the accuracy of the required test data, configure these boards on the ATE machine, and connect the ATE test resources to the circuit to be tested.

[0085] Then, software programming is used to control the power-on of different boards in the ATE machine, including the turn-on voltage of the gate of the power switching device under test, the charging voltage of the air-core inductor connected to the drain of the power switching device under test, and the power supply voltage of the amplifier and comparator.

[0086] Finally, software programming is used to control different boards of the ATE machine to obtain test circuit related data, including the output voltage of the amplifier and the voltage across the drain and source.

[0087] In step S2, the air-core inductor is charged using a power supply to reach the peak current of the test. The specific implementation process is as follows:

[0088] During the on-time period (the time period to be tested), the ATE equipment is connected to the air-core inductor and a voltage is applied. Current begins to flow through the inductor. This current does not change instantaneously because the air-core inductor has the characteristic of resisting current changes. Air-core inductors have a key physical property called self-inductance. When current begins to flow through the inductor, the change in current generates a magnetic field within the inductor. According to Faraday's law of electromagnetic induction, the change in magnetic field generates an opposing electromotive force (i.e., induced electromotive force), which resists the change in current. Due to the air-core inductor's resistance to current changes, the current does not immediately reach the maximum value of the power supply, but instead gradually increases until it reaches the peak current required for the test.

[0089] In step S3, a current sensing resistor and an amplifier circuit are used to monitor the current in the circuit. The specific implementation process is as follows:

[0090] It should be noted that, in a specific implementation process, in order to improve the detection accuracy, a compensation circuit is used to perform real-time compensation on the amplification circuit through negative feedback.

[0091] A high-precision current-sense resistor is connected to the source of the power switching device to be tested. Since the charging current of the air-core inductor will also flow through the high-precision current-sense resistor, the current in the circuit is converted into voltage through the high-precision current-sense resistor, which is convenient for observation and capture of the test. By setting a reasonable resistance size, the voltage across the current-sense resistor is amplified. A compensation amplifier with extremely small offset voltage is selected, and the amplifier circuit is compensated through negative feedback to make the output waveform more accurate. The current waveform is replaced by a voltage waveform and connected to the comparator circuit.

[0092] The ATE resource is connected to the amplifier output, and the amplifier waveform is obtained through programming, thereby obtaining the current waveform in the circuit. At the same time, the output of the amplifier is connected to the comparator, so that the comparator can compare the voltage in real time.

[0093] In step S4, a comparison circuit is used to monitor the peak current during the test. The specific implementation process is as follows:

[0094] The output of the amplifier is connected to the input of the comparator. When the output voltage of the amplifier does not reach the flip voltage set by the comparator, the amplifier outputs a positive voltage to close the high-speed switch that controls the gate voltage of the power switching device under test and the charging voltage of the air-core inductor. The voltage is provided normally. When the output voltage of the amplifier is equal to the flip voltage set by the amplifier, the comparator immediately outputs a negative voltage.

[0095] In step S5, when the comparator outputs a negative voltage, the power supply is stopped and the power switch device to be tested is controlled to be turned off. The specific implementation process is as follows:

[0096] When the comparator outputs a negative voltage, the high-speed switch that controls the gate voltage of the power switch device under test and the charging voltage of the air-core inductor is disconnected, the voltage stops supplying, and the power switch device under test enters the off state. The specific flow chart is as follows Figure 5 shown.

[0097] The high-speed switch consists of two MOS transistors: an NMOS connected to the amplifier output, and a PMOS connected to the NMOS and the air-core inductor charging voltage. The drain of the NMOS is connected to the gate of the PMOS via a resistor. When the amplifier output voltage is positive, the NMOS turns on, and through a resistor, the gate voltage of the PMOS is pulled down to a low voltage. This creates a voltage difference between the gate and source of the PMOS, turning the PMOS on and charging the air-core inductor. When the amplifier output voltage is negative, the NMOS turns off, and the voltage across the resistor approaches a high voltage, which pulls the gate voltage of the PMOS high. This eliminates the voltage difference between the gate and source of the PMOS, causing the PMOS to turn off and the ATE to stop charging the air-core inductor.

[0098] In step S6, an air-core inductor is used to discharge the power switch device to be tested so as to enter an avalanche state. The specific implementation process is as follows:

[0099] When the high-speed switch is disconnected, the air-core inductor stops charging, the magnetic field within it begins to collapse, and the current stored in the air-core inductor, unable to change suddenly, flows out of the inductor. The current in the air-core inductor gradually decreases according to the principle of energy conservation, and this discharge process typically exhibits exponential decay. Because the air-core inductor's discharge circuit contains a freewheeling diode, the current flows through the circuit path between the power switch under test and the freewheeling diode.

[0100] Since the power switching device under test cannot withstand the rapidly discharged current pulse, it will be forced to enter the avalanche breakdown state. At this time, the voltage across the drain and source of the power switching device under test will quickly rise to the breakdown voltage, and the current of the air-core inductor will drop rapidly. The duration of the avalanche breakdown is consistent with the current reduction time.

[0101] Connect ATE resources at both ends of the drain and source of the power switch device to be tested to obtain the waveform of the entire UIS test process, and obtain the duration of the avalanche process and the magnitude of the breakdown voltage through the program.

[0102] In step S7, the ATE machine is used to collect test data and waveforms. The specific implementation process is as follows:

[0103] Connecting ATE resources to the drain and source terminals of the power switch device under test captures waveforms from the entire UIS test process. By reading the test waveforms, the voltage across the drain and source terminals of the power switch device under test when the specified current is reached during the Rdson test can be determined, thereby obtaining the Rdson value. By reading the test waveforms and using the program to determine the duration of the avalanche process and the magnitude of the breakdown voltage, the avalanche energy experienced by the power switch device under test can be calculated, demonstrating the effectiveness of the embodiments of the present invention.

[0104] The present invention allows for flexible and appropriate parameter settings based on the specific power switching devices under test, enabling combined UIS and Rdson testing of different power switching devices. By comparing the avalanche energy and Rdson data obtained from separate UIS and Rdson measurements, the test accuracy of the avalanche energy and Rdson of different devices can be controlled within the error range.

[0105] In summary, compared with the existing technology, the present invention has the following beneficial effects:

[0106] The embodiment of the present invention uses a current-sense resistor, an amplifier circuit, and a comparison circuit to replace and monitor the current waveform in the circuit, and writes relevant programs to control the power supply of the test circuit and collect relevant data and waveforms on an ATE machine, accurately obtaining the size of the avalanche energy and the Rdson test value, thereby reducing the number of test items to be written and the test time, improving test efficiency, and reducing test costs.

[0107] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0108] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A UIS and Rdson joint test circuit based on ATE, characterized in that: include: ATE, a generating circuit, an amplifying circuit and a comparing circuit; wherein the power supply of the generating circuit, the amplifying circuit and the comparing circuit is provided by ATE; The generating circuit includes a first high-speed switch group, a second high-speed switch group, an air-core inductor, a current-sense resistor and a first diode. The first end of the first high-speed switch group is connected to the control end of the power switch device to be tested; The first end of the power switch device to be tested is connected to the first end of the second high-speed switch group via an air-core inductor, and the second end of the second high-speed switch group is connected to the second end of the power switch device to be tested via a current-sense resistor; The anode of the first diode is connected to the common end of the current-sense resistor and the second high-speed switch group, and the cathode is connected to the common end of the air-core inductor and the second high-speed switch group; The two input terminals of the amplifier circuit are connected to the two ends of the current-sense resistor, the output terminal is connected to the first input terminal of the comparison circuit, the second input terminal of the comparison circuit is connected to the reference voltage; the output terminal of the comparison circuit is connected to the third terminal of the second high-speed switch group; The second end of the first high-speed switch group is connected to the common end of the comparison circuit and the second high-speed switch group; The amplification circuit is used to obtain the current waveform in the circuit and capture it through ATE-related resources to obtain the peak current during the entire avalanche process; the comparison circuit is used to detect the peak current in the circuit. When the peak current is reached, the comparison circuit outputs a negative voltage to control the disconnection of the high-speed switches in the first high-speed switch group and the second high-speed switch group, thereby stopping the voltage supply of the ATE resources, causing the power switch device to be tested to enter the off state. The air-core inductor causes the power switch device to be tested to enter the avalanche breakdown state through discharge. The entire process of avalanche breakdown obtains relevant test data and related waveforms through ATE resources.

2. The ATE-based UIS and Rdson combined test circuit according to claim 1, wherein: The first high-speed switch group includes a first switch tube, a second switch tube and a second resistor; The first end of the first switch tube is the first end of the first high-speed switch group; the gate of the first switch tube is connected to the first end of the second switch tube, and the second end of the second switch tube is the second end of the first high-speed switch group; the two ends of the second resistor are respectively connected to the second end and the gate of the first switch tube; The second end of the first switch tube is connected to the power supply provided by the ATE; the second end of the second switch tube is grounded or at a low voltage.

3. The ATE-based UIS and Rdson combined test circuit according to claim 2, wherein: The first switch tube is a PMOS, and the second switch tube is an NMOS, wherein the first end of the PMOS and the NMOS is a drain, and the second end is a source; Alternatively, the first switch tube is a P-channel IGBT, and the second switch tube is an N-channel IGBT, wherein the first end of the P-channel IGBT and the N-channel IGBT is the collector, and the second end is the emitter.

4. The ATE-based UIS and Rdson combined test circuit according to claim 1, wherein: The second high-speed switch group includes a third switch tube, a fourth switch tube and a third resistor; Wherein, the first end of the third switch tube is the first end of the second high-speed switch group; The gate of the third switch tube is connected to the first end of the fourth switch tube, and the common end thereof is the second end of the second high-speed switch group; The gate of the fourth switch tube is the third terminal of the first high-speed switch group; Two ends of the third resistor are respectively connected to the second end and the gate of the third switch tube; The second end of the third switch tube is connected to the power supply provided by the ATE; the second end of the fourth switch tube is grounded or at a low voltage.

5. The ATE-based UIS and Rdson combined test circuit according to claim 4, characterized in that: The third switch tube is a PMOS, and the fourth switch tube is an NMOS, wherein the first end of the PMOS and the NMOS is a drain, and the second end is a source; Alternatively, the third switch tube is a P-channel IGBT, and the fourth switch tube is an N-channel IGBT, wherein the first end of the P-channel IGBT and the N-channel IGBT is the collector, and the second end is the emitter.

6. The ATE-based UIS and Rdson combined test circuit according to any one of claims 1 to 5, characterized in that: The invention also includes a compensation circuit, wherein the compensation circuit is used to compensate for offset errors in the amplification circuit.

7. A UIS and Rdson joint testing method based on ATE, characterized in that: The UIS and Rdson combined test method is used to control the UIS and Rdson combined test circuit according to any one of claims 1 to 6 to perform the following steps: Use the ATE machine to provide the power required for the test circuit to turn on the device, and select the ATE test board resources according to the parameters of the power switching device to be tested; Use a power supply to charge the air-core inductor to reach the peak current of the test; Use a current-sense resistor and an amplifier circuit to monitor the current in the circuit; Use a comparison circuit to monitor the peak current during the test; When the comparator outputs a negative voltage, the power supply is stopped and the power switch device under test is controlled to be turned off; Use an air-core inductor to discharge and put the power switch device under test into an avalanche state; Use ATE equipment to collect test data and waveforms.

8. The ATE-based UIS and Rdson joint testing method according to claim 7, wherein: When using a current-sense resistor and an amplifier circuit to monitor the current in the circuit, the UIS and Rdson combined testing method further includes: performing real-time compensation on the amplifier circuit through a compensation circuit.

9. The ATE-based UIS and Rdson joint testing method according to claim 7, wherein: When the comparator outputs a negative voltage, stopping the power supply and controlling the shutdown of the power switch device to be tested includes: The output voltage of the comparator is detected. When the comparator outputs a negative voltage, the high-speed switch that controls the gate voltage of the device under test and the charging voltage of the air-core inductor is disconnected, the voltage supply stops, and the device under test enters the shutdown state.

10. The ATE-based UIS and Rdson joint testing method according to claim 7, wherein: ATE test board resources include the turn-on gate voltage required by the power switching device to be tested, the air-core inductor charging voltage, and the power supply voltage of the comparator and amplifier.

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