Simulation circuit test excitation generation method based on heuristic greedy algorithm

Abstract

The invention discloses an analog circuit test excitation generation method based on a heuristic greedy algorithm, and the method comprises the steps: carrying out the defect modeling of a to-be-tested analog circuit, obtaining a defect simulation analog circuit, setting a search space according to an excitation source of the to-be-tested analog circuit, equally dividing the search space to obtain a plurality of sub-search spaces, and carrying out the detection of the to-be-tested analog circuit. The search point where the geometric center of each sub-search space is located is taken as an initial point, a search starting point is determined according to the number of detectable defects of each initial point, and then test excitation is searched from the search starting point based on a heuristic greedy algorithm, so that a test excitation set required by the analog circuit is obtained. According to the invention, the generation efficiency of simulation circuit test excitation can be effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog circuit testing, and more specifically, relates to an analog circuit test stimulus generation method based on a heuristic greedy algorithm. Background Art

[0002] As the integration of circuit boards and the complexity of components grow exponentially, the requirements for their controllability, testability, and observability are becoming increasingly higher, and the requirements for testing are becoming increasingly stringent, which has led to an increase in the difficulty and cost of chip fault testing. Under a specific stimulus, if the presence of a defect in a circuit affects the voltage of the circuit, and the degree of the impact is sufficient to distinguish it from a non-defective circuit, then the defect is considered to be detectable. Studies have found that the choice of test stimulus directly affects the cost and efficiency of circuit defect detection.

[0003] Test stimulus generation can be viewed as a search and optimization problem. The number of detectable defects is evaluated as a function of the DC excitation voltage value. However, since the excitation signal of the analog circuit is a continuous real value and can take any value within the allowable range, there are infinite possible excitation combinations. In addition, due to the complex behaviors such as signal fluctuations, distortion, and nonlinear response that may exist in the circuit, in general, the curve of the number of detectable defects in the circuit changing with the DC excitation is not continuous and differentiable, and it is difficult to obtain the optimal solution through mathematical optimization methods. However, most of the existing analog circuit test stimulus optimization methods have the disadvantages of time-consuming circuit simulation analysis, complex feature acquisition process, weak universality of decision function constraints, and poor scalability. The solution effect is not satisfactory, and it is necessary to seek new algorithms to obtain better solutions. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method for generating analog circuit test stimuli based on a heuristic greedy algorithm. The test stimuli are evaluated by the number of detectable defects, and then the heuristic greedy algorithm is used to gradually adjust the test stimuli to move in the direction of a large number of detectable defects. Finally, a set of test stimulus sets is generated in the shortest possible time, thereby effectively improving the generation efficiency of analog circuit test stimuli.

[0005] In order to achieve the above-mentioned object of the invention, the analog circuit test stimulus generation method based on the heuristic greedy algorithm of the present invention comprises the following steps:

[0006] S1: For the analog circuit to be tested, all components in the circuit netlist are identified, defect models are established for all components except the power supply, and a defect list is generated. Each defect model is equivalently compressed and injected into the analog circuit to be tested one by one to obtain a defect simulation circuit;

[0007] S2: According to the number N of stimulus sources of the analog circuit to be tested, an N-dimensional search space is established, and the search space is discretized according to the achievable accuracy of the test stimulus to obtain the coordinates of each search grid point;

[0008] S3: Divide the search space into D=2 N Thus, D sub-search spaces are obtained, and the search grid point where the geometric center of each sub-search space is located is taken as the initial point start d , d = 1, 2, ..., D, for each initial point start in the simulation circuit d Perform defect simulation and record each starting point start d The set of detectable defects Select the initial point with the largest number of detectable defects as the search starting point base;

[0009] S4: Search the test stimulus set based on the heuristic greedy algorithm. The specific method is:

[0010] S4.1: Initialize the cumulative detectable defect set Initialize the test stimulus set E = {start1, start2, ..., start D};

[0011] S4.2: Initialize the search step length L=L0, where L0 represents a preset initial value of the search step length;

[0012] S4.3: Sample K search grid points in the search space with a distance L from the search base point as the neighborhood search point p k , k = 1, 2, ..., K, K represents the preset number of sampling points;

[0013] S4.4: For each neighborhood search point p in the analog circuit k Perform defect simulation to obtain the corresponding detectable defect set f k , the neighborhood search point p k Add the test stimulus set E, and let the cumulative detectable defect set F′=F∪f1∪f2∪…∪f K ;

[0014] S4.5: Determine whether the search end condition is met, if yes, proceed to step S4.9, otherwise proceed to step S4.6;

[0015] S4.6: Determine whether |F′|>|F|, where || indicates the number of detectable defects in the set. If yes, proceed to step S4.7, otherwise proceed to step S4.8;

[0016] S4.7: Let the cumulative detectable defect set F = F′, and then search for point p from K neighborhoods kFilter the neighborhood search points with the largest number of detectable defects Update search base point Return to step S4.3;

[0017] S4.8: Let the search step size L = λ×L, λ represents the preset search step size scaling factor, λ∈(0,1), and return to step S4.3;

[0018] S4.9: Use the current test stimulus set E as the test stimulus set for the final analog circuit test.

[0019] The present invention is based on a method for generating test stimuli for analog circuits using a heuristic greedy algorithm. Defect modeling is performed on an analog circuit to be tested to obtain a defect simulation analog circuit. A search space is then set according to a stimulus source of the analog circuit to be tested. The search space is equally divided into a number of sub-search spaces. A search point where the geometric center of each sub-search space is located is taken as an initial point. A search starting point is determined according to the number of detectable defects at each initial point. A test stimulus is then searched from the search starting point based on a heuristic greedy algorithm, thereby obtaining a test stimulus set required for the analog circuit.

[0020] The present invention has the following effects:

[0021] 1) The present invention uses a greedy algorithm to always select the grid point that can maximize the heuristic function as the next search point, ensuring that each step of the algorithm is moving towards the stimulus direction that can trigger more defect exposure and improve defect coverage, prompting the algorithm to gradually approach the ideal test stimulus configuration, optimizing the search process, and enhancing the reliability verification efficiency and accuracy of the analog circuit;

[0022] 2) The present invention can quickly and automatically provide test engineers with a test strategy that is both widely applicable and robust without the need for prior knowledge of the circuit, especially when facing the challenge of generating test vectors for large-scale analog circuits, highlighting its rapid response and processing capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flowchart of a specific implementation method of the analog circuit test stimulus generation method based on the heuristic greedy algorithm of the present invention;

[0024] Figure 2 This is an example diagram of the component hard defect model specified by IEEE P2427;

[0025] Figure 3 It is a schematic diagram of a two-dimensional search space;

[0026] Figure 4 yes Figure 3 Schematic diagram of spatial partitioning of the search space shown;

[0027] Figure 5It is a flow chart of searching the test stimulus set by the heuristic greedy algorithm in the present invention;

[0028] Figure 6 is a flow chart of test stimulus optimization based on the Pareto genetic algorithm in this embodiment;

[0029] Figure 7 is a structural diagram of a bandgap reference circuit in this embodiment;

[0030] Figure 8 Schematic diagram of search space division in this embodiment;

[0031] Fig. 9 is a schematic diagram of the function values ​​of the individuals in the initial population of this embodiment with respect to the two optimization objective functions and the current Pareto optimal solution;

[0032] Fig.10 It is a schematic diagram of the function values ​​of the individuals in the final generation population of this embodiment with respect to the two optimization objective functions and the current Pareto optimal solution. DETAILED DESCRIPTION

[0033] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0034] In order to better illustrate the technical solution of the present invention, the technical principle of the present invention is first briefly described.

[0035] As a simple and direct optimization strategy, the heuristic greedy algorithm is widely used in various optimization problems. The core idea of ​​the algorithm is to select only the optimal decision in the current state in each iteration, incorporate it into the solution, update the state of the solved part of the problem, and make another selection on this basis until the preset termination condition is reached. Through the accumulation of continuous local optimal decisions, the greedy algorithm can provide a better solution for complex objective functions in a shorter time. By making local optimal decisions to achieve a global approximate optimal solution, it avoids the high computational complexity of directly exploring the global optimal solution.

[0036] 1) Design of heuristic function

[0037] Assume that there are K kinds of defects in the analog circuit to be tested, and there are T test points to evaluate whether the circuit defects can be detected. Under each set of specific stimuli, use simulation software to perform static analysis on the circuit to be tested, and compare the voltage differences at each test point when there are defects and when there are no defects. When the voltage difference at test point j exceeds the threshold of 0.01V under the action of defect k compared with the non-defective state, it can be determined that test point j can detect defect k through the current test stimulus, k = 1, 2, ..., K, j = 1, 2, ..., T. The following formula is used to quantify the detection capability of test point j for defect k, where the logical value 0 indicates that defect k can be detected at test point j, and 1 indicates that it cannot be detected:

[0038]

[0039] In the formula, represents the voltage value at the measuring point j under the condition of defect k, Represents the voltage value at measuring point j when there is no defect.

[0040] In order to comprehensively analyze the detection capability of all measurement points for defect k under a specific stimulus, the following formula is used to indicate whether defect k can be successfully detected by the measurement point set under the stimulus condition:

[0041]

[0042] Therefore, under the voltage excitation vector V, the number of detectable defects F(V) can be expressed by the following formula:

[0043]

[0044] The above formula is the heuristic function of the heuristic greedy algorithm of the present invention. Its numerical value directly reflects the number of detectable defects under the action of the excitation V. The larger the value, the more defects can be detected by the excitation and the better the excitation performance.

[0045] Based on the above principles, the present invention proposes a method for generating analog circuit test stimuli based on a heuristic greedy algorithm. Figure 1 FIG. 1 is a flowchart of a specific implementation of the method for generating analog circuit test stimulus based on a heuristic greedy algorithm of the present invention. Figure 1 As shown, the specific steps of the analog circuit test stimulus generation method based on the heuristic greedy algorithm of the present invention include:

[0046] S101: Component Defect Modeling and Injection:

[0047] For the analog circuit to be tested, all components in the circuit netlist are identified, defect models are established for all components except the power supply, and a defect list is generated. Each defect model is equivalently compressed and injected one by one into the analog circuit to be tested to obtain a defect simulation circuit.

[0048] In this way, defects that may occur due to various defect mechanisms (such as additional metal deposition) in the actual manufacturing process can be simulated. The defect model provided by the IEEE P2427 standard proposal is used in this embodiment. According to the definition of the IEEE P2427 draft standard, defects are considered to be unexpected permanent changes in circuit elements or component connections that are not within the scope of component manufacturing specifications. Defects that occur in integrated circuits are generally divided into two categories: parameter defects and hard defects. Hard defects are usually caused by problems in the silicon manufacturing process such as dust particles, insufficient etching, etc., which will cause the topology of the manufactured circuit to change. Defect-oriented tests (DOT) rely on the use of well-defined defect models to quantify defect coverage. Although defect modeling in analog circuits has not yet been standardized like digital circuits, the IEEE P2427 working group has proposed an emerging standard proposal that addresses the standardization of hard defect modeling in analog circuits and power electronics. Figure 2 It is the component hard defect model information table specified by IEEE P2427. Figure 2 As shown, two defect models of open circuit and short circuit are established for two-port components (resistors, capacitors, etc.), and for three-port components (MOS tubes, transistors, etc.), three ports are open circuited and two ports are short circuited, for a total of six defect models. The defect model can include open circuit defects and short circuit defects. In this embodiment, in order to improve simulation efficiency and avoid unnecessary calculation overhead, short circuit defects are not injected into components with the same ports.

[0049] The specific method of defect injection in this embodiment is: use Python script to generate .alter statements for each defect indicated in the defect list, with the goal of simulating each transistor-level defect one by one and capturing its impact on the circuit. .alter is a statement used in the spice language to modify parameters. In the .alter statement, an open model is connected in series with the component port to inject an open circuit defect, or a short model is connected in parallel with the component port to inject a short circuit defect. The generated .alter statement is then imported into the circuit netlist and simulated using HSPICE software, that is, circuits with various defects are simulated and circuit performance parameters are obtained. The response of the defective circuit is compared with the baseline response of the defect-free circuit to analyze and obtain the defect detection results.

[0050] S102: Establishing a search space:

[0051] According to the number N of excitation sources of the analog circuit to be tested, an N-dimensional search space is established, and the search space is discretized according to the achievable accuracy of the test excitation to obtain the coordinates of each search grid point.

[0052] Each dimension in the N-dimensional search space represents an independent stimulus source, and its value range defines the boundary of the dimension. The entire space contains all possible stimulus source combinations, that is, all possible test stimulus combinations. Furthermore, this N-dimensional search space can be divided into multiple fine grids, and each grid intersection represents a set of specific stimulus source values. Figure 3 is a schematic diagram of a two-dimensional search space. Figure 3 As shown, when the circuit to be tested contains two excitation sources, a two-dimensional search space is constructed, in which the x-axis and y-axis respectively map the value ranges of the two excitation sources. It is assumed that this space is evenly divided into several grids with a resolution of 0.1V, and each coordinate point on the grid is a specific test excitation combination. The gridding strategy of this discretized continuous space helps to systematically explore the excitation space, ensure the comprehensiveness of the test coverage, and make the heuristic greedy search algorithm easier to implement. By traversing or selecting these grid points as test excitations, it is possible to try to find a test excitation that can trigger as many potential defects as possible in the circuit. Considering that the resolution of the voltage source in practice is generally maintained at the level of 0.01V, 0.01V is used as the reference unit for grid division in this embodiment, thereby ensuring the precise alignment of the model with the actual test environment, while maintaining the accuracy of the analysis and the feasibility in practice.

[0053] S103: Determine the search starting point:

[0054] Since the specific DC excitation value ranges that can detect different defects are different, in order to ensure the comprehensiveness of the search process and effectively locate a set of excitations that can maximize the number of defect detections, the present invention adopts a balanced exploration initialization strategy. That is, before the formal search for excitations, the search space is divided into D = 2 N Thus, D sub-search spaces are obtained, and the search point where the geometric center of each sub-search space is located is taken as the initial point start d , d = 1, 2, ..., D, for each initial point start in the simulation circuit d Perform defect simulation and record each starting point start d The set of detectable defects The initial point with the largest number of detectable defects is selected as the search starting point base. In this way, while searching the stimulus space comprehensively, the process of approaching the local optimal solution can be accelerated, thereby improving the overall test efficiency and effect.

[0055] Figure 4 yes Figure 3 Schematic diagram of spatial partitioning of the search space. Figure 4As shown, when the circuit to be tested has two excitation sources, the search space is divided into four equal parts, the centers of the four subspaces are taken as the initial points, and then the detectable defect sets of the four initial points are simulated and recorded, and then the one with the largest number of detectable defects is selected as the starting point base for subsequent searches.

[0056] S104: Searching for test stimulus set based on heuristic greedy algorithm:

[0057] Next, the stimulus space is iteratively searched based on a heuristic greedy algorithm to obtain the test stimulus set. Figure 5 Flowchart of the heuristic greedy algorithm for searching the test stimulus set in the present invention. Figure 5 As shown, the specific steps of searching the test stimulus set by the heuristic greedy algorithm in the present invention include:

[0058] S501: Initialize the accumulated detectable defect set and the test stimulus set:

[0059] Initialize the cumulative detectable defect set Initialize the test stimulus set E = {start1, start2, ..., start D}.

[0060] S502: Initialize the search step length L=L0, where L0 represents a preset initial value of the search step length.

[0061] In this embodiment, the initial value L0 of the search step is set to half the distance between adjacent initial points. By systematically traversing all grid points with a Euclidean distance of L centered at the current point, the direction that can induce more defect exposure is actively sought.

[0062] S503: Obtaining neighborhood search points:

[0063] In the search space, K search grid points with a distance L from the search base point base are sampled as the neighborhood search point p k , k = 1, 2, ..., K, K represents the number of preset sampling points. In this embodiment, K = 2N.

[0064] S504: Defect simulation:

[0065] In the analog circuit, for each neighborhood search point p k Perform defect simulation to obtain the corresponding detectable defect set f k , the neighborhood search point p k Add the test stimulus set E, that is, let E = E∪{p1,p2,…,p K}, let the cumulative detectable defect set F′=F∪f1∪f2∪…∪f K .

[0066] S505: Determine whether the search end condition is met, if so, go to step S509, otherwise go to step S506.

[0067] The search end condition can be set according to actual needs. Generally, it can be used to determine whether the cumulative number of detectable defects is greater than a preset threshold. In this embodiment, the search end condition is whether || means to find the number of detectable defects in the set, Indicates the preset threshold value for the number of detected defects.

[0068] In addition, when the cumulative number of detectable defects converges and there is no neighboring search point in the neighborhood of the current search base point that exceeds the number of detectable defects of the previously evaluated search grid points, this indicates that the marginal benefit of continued exploration is diminishing, which can also be used as a criterion for stopping the current search cycle. This strategy ensures that the algorithm can focus on the most effective test stimulus exploration path while avoiding invalid searches, further improving the solution efficiency and practical application value.

[0069] S506: Determine whether |F′|>|F|, if so, proceed to step S507, otherwise proceed to step S508.

[0070] S507: Update the cumulative detectable defect set and search base point:

[0071] Let the cumulative detectable defect set F = F′, search for point p from K neighborhoods k The number of defects that can be detected in the screening is the largest, that is, |f k |The largest neighborhood search point Update search base point Return to step S503.

[0072] S508: Let the search step L = λ×L, λ represents the preset search step scaling factor, λ∈(0,1), and return to step S503.

[0073] It can be seen that in the present invention, if there is a point with a greater number of detectable defects than the current grid point at a distance of L, then this point will be used as the center point of the next search; on the contrary, if no better point is found, the search step length L will be shortened by a predetermined ratio. This process uses continuous range adjustment and iterative search, and each step is based on the consideration of maximizing the immediate detection benefits, thereby steadily promoting the overall test scheme to a higher defect coverage rate, which not only ensures execution efficiency, but also improves the performance excellence of the resulting test stimulus set, providing strong support for the reliability verification of analog circuits.

[0074] S509: Determine the test stimulus set:

[0075] The current test stimulus set E is used as the test stimulus set for the final simulation circuit test.

[0076] The test stimulus set obtained above covers all simulated stimuli in the search process. This approach ensures the comprehensiveness of the test, but it also inevitably introduces a large number of redundant test stimuli. In order to more effectively control the test cost and improve the test efficiency, after the defect coverage of the test stimulus set reaches the expected index, the test stimulus needs to be screened and optimized, aiming to achieve the highest possible defect detection rate with the most streamlined number of test stimuli. But in fact, the two goals of low test cost and high test performance are often conflicting, and it is difficult to find an absolute optimal solution that can satisfy both at the same time. At this time, the problem belongs to a multi-objective optimization problem. Multi-objective optimization problems are widely present in the field of engineering applications, and such problems usually contain multiple goals. Specifically, the various sub-objectives of multi-objective optimization problems often conflict with each other, that is, the performance improvement of one sub-objective may be at the expense of the performance degradation of another sub-objective. Therefore, in the traditional sense, there is no absolute optimal solution that can simultaneously make all sub-objective functions reach the optimal state. In this situation, the key to solving the problem is to seek a compromise and coordination solution to achieve the optimal balance between the various sub-objective functions as much as possible. In order to solve this problem, the concept of Pareto optimal solution is introduced into multi-objective optimization problems. Since multi-objective optimization problems usually have multiple Pareto optimal solutions, finding and determining the Pareto optimal solution set becomes the key to solving multi-objective problems.

[0077] The multi-objective problem can be described as follows: Given a decision vector x = [x1, x2, ..., x N ] T , satisfying Q inequality constraints g q (x)≤0,q=1,2…,Q, while making M competitive objective functions f m (x), m = 1, 2, ..., M simultaneously minimize (or maximize):

[0078]

[0079] Due to conflicts between objective functions, it is usually difficult to find a solution that can optimize all sub-objectives at the same time. On the contrary, a solution may perform better than another solution on some sub-objective functions, but perform worse on other sub-objective functions. Such solutions that are difficult to clearly determine their superiority in comparison are called non-dominated solutions, and their specific definition is as follows:

[0080] Definition 1 If individual x 1 With individual x 2 If the following conditions are met, then the individual x is called 1 Dominant individual x 2 , x 1 is a non-dominated solution, and x2 To control the solution.

[0081] a. For all sub-goals, x 1 The performance is no worse than x 2 ,Right now Satisfy f m (x 1 )≤f m (x 2 ).

[0082] b. There is at least one subgoal, x 1 Outperforms x 2 ,Right now Satisfy the inequality f k (x 1 )<f k (x 2 ).

[0083] Traverse all individuals and compare the dominance and non-dominance relationship between the current individual and other individuals. If no individual is superior to the current individual, mark the current individual as a non-dominated individual. Mark the dominance level of all non-dominated individuals as the first level. Ignore the individuals that have been marked as non-dominated (that is, these individuals will no longer participate in the next round of comparison), and repeat the above steps to obtain the second-level non-dominated layer individuals. And so on, until the entire population is stratified. This process is called fast non-dominated sorting. The first-level individuals obtained by fast non-dominated sorting are the Pareto optimal solutions required.

[0084] The core idea of ​​the multi-objective optimization algorithm is to continuously extract non-dominated solutions from each generation of populations during the iteration process, and then construct the non-dominated solution set of the current population. As the iteration steps continue to advance, the non-dominated solution set gradually approaches the desired optimal solution set, and finally approaches the global optimal solution and reaches the best state.

[0085] Genetic Algorithm (GA) is a biological evolution process that simulates the natural selection and genetics mechanism of Darwin's theory of biological evolution. It mainly realizes the evolution of species through selection and mutation. It is a meta-heuristic algorithm with natural evolution. It is suitable for solving complex optimization problems and is widely used in many fields such as optimization problems of data mining and rule extraction, mobile robot path planning problems, scheduling problems, task allocation problems, etc.

[0086] The genetic algorithm starts with a population representing the potential solution set of the problem, and a population is composed of a certain number of individuals encoded by genes. Each individual is actually an entity with characteristics of chromosomes. As the main carrier of genetic material, the chromosome is a collection of multiple genes. Its internal expression (i.e., genotype) is a certain combination of genes, which determines the external expression of the shape of the individual. For example, the characteristic of black hair is determined by a certain combination of genes in the chromosome that controls this characteristic. Therefore, it is necessary to achieve the mapping from phenotype to genotype, i.e., encoding, at the beginning. Since the work of imitating genetic encoding is very complicated, it is often simplified, such as binary encoding. After the first generation of population is generated, according to the principle of survival of the fittest and survival of the fittest, it evolves from generation to generation to produce better and better approximate solutions. In each generation, individuals are selected according to the fitness of individuals in the problem domain, and combined crossover and mutation are performed with the help of genetic operators of natural genetics to produce a population representing a new solution set. This process will lead to the population being more adapted to the environment than the previous generation, just like natural evolution. The best individuals in the last generation of population can be decoded and used as the approximate optimal solution to the problem.

[0087] Based on the above principles, in this embodiment, the Pareto genetic algorithm is used to further optimize the test stimulus set E obtained by the heuristic greedy algorithm search, in order to find a series of Pareto optimal solutions, thereby providing a diverse selection set, so that it can weigh cost and performance according to actual conditions and needs, and make more reasonable decisions. Figure 6 : is a flow chart of test stimulus optimization based on Pareto genetic algorithm in this embodiment. Figure 6 As shown, the specific steps of test stimulus optimization based on the Pareto genetic algorithm in this embodiment include:

[0088] S601: Determine optimization target:

[0089] Determine the optimization target of test stimulus selection according to actual needs, record the number of optimization targets as M, and set the optimization objective function g of the test stimulus selection scheme m (X), m = 1, 2, ..., M, the smaller the optimization objective function value, the better the test scheme. In this embodiment, there are two optimization objectives, including the number of test excitation vectors and the defect detection rate. The number of test excitation vectors is related to the test cost. Generally speaking, the larger the number of test excitation vectors, the higher the test cost, so it is necessary to minimize the number of test excitation vectors. The optimization objective function expression of the number of test excitation vectors is:

[0090]

[0091] Where X = [x1, x2, …, x D ] represents the test stimulus vector selection scheme, x d is a binary variable, xd = 0 means that the dth test stimulus vector is not selected in the test stimulus vector selection scheme corresponding to the individual, x d =1 indicates that the dth test stimulus vector is selected in the test scheme corresponding to the individual, d=1,2,…,D, and D indicates the number of test stimulus vectors in the test stimulus set E.

[0092] In terms of defect detection rate, the higher the defect detection rate, the better the test stimulus selection scheme. Therefore, the optimization objective function expression of defect detection rate is:

[0093] g2(X)=1-fdr(X)

[0094] Where fdr(X) represents the defect detection rate of the test stimulus vector selection scheme. Defect coverage is equal to the number of detectable defects divided by the total number of injected defects. all , and its calculation formula is as follows:

[0095]

[0096] Therefore, the multi-objective function expression in this embodiment is as follows:

[0097]

[0098] S602: Generate an initial population.

[0099] The generation of the initial population is the first step of the genetic algorithm, and its quality directly affects the effect of subsequent evolution. In practical applications, a random method is usually used to generate the initial population. In this embodiment, H individuals X are randomly generated. h =[x h,1 ,x h,2 ,…,x h,D ], h = 1, 2, ..., H, each individual represents a test stimulus vector selection scheme, x h,d = 0 means that the dth test stimulus vector is not selected in the test stimulus vector selection scheme corresponding to the individual, x h,d =1 indicates that the dth test stimulus vector is selected in the test scheme corresponding to the individual, d = 1, 2, ..., D, and D indicates the number of test stimulus vectors in the test stimulus set E. The H randomly generated individuals constitute the initial population P.

[0100] S603: Set the number of iterations t=1.

[0101] S604: Generate new population:

[0102] The individuals in population P are selected, crossed, and mutated to generate a new population Q.

[0103] Since each individual in this embodiment is a binary coded vector, the individual crossover adopts the classic single-point crossover method, and the individual mutation adopts the classic single-point mutation method.

[0104] S605: Merge populations:

[0105] Merge population P and population Q to obtain population S = P∪Q.

[0106] S606: Individual optimization based on Pareto optimality:

[0107] Calculate the M optimization objective function values ​​corresponding to each individual in the population S, determine the Pareto dominance relationship between any two individuals based on the optimization objective function value, count the number of times each individual is dominated, sort all individuals from small to large according to the number of times they are dominated, and select the top H individuals to form the optimal population P′.

[0108] S607: Determine whether the number of iterations t<t max , t max Indicates the preset maximum number of iterations. If yes, go to step S608, otherwise go to step S609.

[0109] S608: Set the number of iterations t=t+1, set the population P=P′, and return to step S604.

[0110] S109: Obtaining a test stimulus vector optimization scheme:

[0111] According to the Pareto dominance relationship, non-dominated individuals in the preferred population P' are selected, and the test stimulus vector selection scheme corresponding to these non-dominated individuals is selected as a preferred scheme. It can be seen that by selecting non-dominated individuals, the decision maker is provided with the information needed to balance between multiple objectives.

[0112] In order to better illustrate the technical solution of the present invention, a specific example is used to experimentally verify the present invention. In this embodiment, the bandgap benchmark circuit provided by the IEEE P2427 working group is used to verify the feasibility of the present invention. Figure 7 is a structural diagram of the bandgap reference circuit in this embodiment. Figure 7 As shown in Figure 1, the bandgap benchmark circuit contains a total of 102 components, including 43 3-terminal components and 59 2-terminal components. The test stimulus generation of the bandgap benchmark circuit is analyzed in detail using Python scripting language and Hspice simulation software.

[0113] Based on the defect simulation framework described in the IEEE standard proposal, defect models are built for all components in the bandgap benchmark circuit. The open circuit defect is simulated as a 1GΩ resistor in series with the defect terminal, while the short circuit defect is modeled as a 200Ω resistor in parallel between the defect terminals. There are 376 complete defects, and after redundant defect reduction, a total of 340 defects are generated for the bandgap circuit.

[0114] The IEE bandgap reference circuit has three excitation sources with a nominal value of 2.5 V, so the voltage value range is limited to the interval [0, 2.5]. In this embodiment, 12 MOS transistor gate nodes and 1 output node, a total of 13 nodes, are used as measurement points.

[0115] There are three voltage sources in the bandgap reference circuit, so a three-dimensional test stimulus search space is established. In this embodiment, the space is divided into two equal parts: 3 =8 portions. Figure 8 Schematic diagram of search space division in this embodiment. Figure 8 As shown, take the geometric center point of each sub-search space ( Figure 8 The black dot in the middle is the initial point. Table 8 is a table of the initial point coordinates and the corresponding number of detectable defects in this embodiment. The set detected_defect is used to save the defects detected each time. At this time, the cumulative number of detectable defects is 200. Table 1 is a comparison table of the number of detectable defects at the initial point in this embodiment.

[0116] Initial point coordinates Number of detectable defects (0.62,0.62,0.62) 29 (0.62,1.88,0.62) 29 (0.62,0.62,1.88) 29 (0.62,1.88,1.88) 29 (1.88,0.62,0.62) 188 (1.88,1.88,0.62) 188 (1.88,0.62,1.88) 36 (1.88,1.88,1.88) 36

[0117] Table 1

[0118] As shown in Table 1, (1.88, 0.62, 0.62) and (1.88, 1.88, 0.62) can detect the largest number of defects, so this embodiment uses (1.88, 0.62, 0.62) as the search starting point to iteratively search the search space of the test stimulus. The first round of search is performed with an initial step of 0.62V. Since this embodiment searches in three-dimensional space, six neighborhood search points above, below, left, right, front, and back of the search base point are sampled each time the search is performed. Table 2 is a list of search point coordinates and the corresponding number of detectable defects in the first round of search in this embodiment.

[0119] Neighborhood search point Number of detectable defects (1.25,0.62,0.62) 148 (1.88,0,0.62) 188 (1.88,0.62,0) 186 (1.88,0.62,1.25) 39 (1.88,1.25,0.62) 186 (2.5,0.62,0.62) 184

[0120] Table 2

[0121] After the first round of search, the cumulative number of detectable defects is 218. However, since there is no point with more detectable defects among the adjacent coordinate points of (1.88, 0.62, 0.62), the step size is reduced by half, that is, 0.31V is used as the step size, and the second round of search is continued for the adjacent coordinate points of (1.88, 0.62, 0.62). Table 3 is a list of search point coordinates and corresponding detectable defect numbers in the first round of search in this embodiment.

[0122] Neighborhood search point coordinates Number of detectable defects (1.57,0.62,0.62) 192 (1.88,0.31,0.62) 188 (1.88,0.62,0.31) 187 (1.88,0.62,0.93) 50 (1.88,0.93,0.62) 188 (2.19,0.62,0.62) 185

[0123] Table 3

[0124] After the second round of search, the cumulative number of detectable defects is 221. Among the adjacent coordinate points of (1.88, 0.62, 0.62), (1.57, 0.62, 0.62) has more detectable defects, so (1.57, 0.62, 0.62) is selected as the next search point, and the iterative search is continued with a step size of 0.31V until the search end condition is met.

[0125] Finally, after searching 55 sets of stimuli in 19 minutes, 339 defects were successfully detected, with a defect coverage rate of 99.71%. In fact, the algorithm achieved a defect coverage rate of 99.5% after searching 21 stimuli in 8 minutes. After that, it took almost twice as long to further increase the coverage rate by 0.21%. At the end of defect detection, the remaining small number of defects are often difficult to trigger by conventional means, and in-depth exploration of the huge stimulus space is required, which will undoubtedly greatly reduce the efficiency and cost-effectiveness of the test. Therefore, appropriately relaxing the threshold of defect coverage may be a more reasonable strategy to help save test generation time.

[0126] The 55 test stimuli generated inevitably contain redundant tests. In order to optimize the test process, reduce the test cost, and improve the overall test efficiency, the test stimuli are optimized based on the Pareto genetic algorithm.

[0127] In the specific implementation, binary encoding is adopted, where the length D of the individual gene is set to the total number of searched stimuli, that is, 55. The population size H is set to 100, and the maximum number of iterations t max Set to 50 generations, and the mutation probability is set to the inverse of the individual gene length, that is, 1 / 55. In the initialization stage of the algorithm, the rand function is used to randomly generate 50 01 arrays of size 1×55, each array is an individual, representing a test incentive selection scheme, and then the two optimization objective function values ​​of each individual are calculated. In order to compare before and after the incentive vector is optimized, all individuals in the initial population are first non-dominated sorted to obtain the function values ​​of the initial population individuals on the two optimization objective functions and the Pareto optimal solution of the current population. Fig. 9 : is a schematic diagram of the function values ​​of the individuals in the initial population of this embodiment with respect to the two optimization objective functions and the current Pareto optimal solution. Fig. 9 As shown in the figure, the horizontal axis represents the number of individual selected test vectors, and the vertical axis represents the defect coverage that can be achieved by using the selected test vectors in combination. From the Pareto optimal solution of the current population represented by the triangular points, it can be seen that in the current state, 18 stimuli can be used to achieve a defect coverage of 99.71%.

[0128] The population was then evolved using a genetic algorithm, and after 50 rounds of selection, crossover, and mutation operations, the final population was obtained. Fig.10 : is a schematic diagram of the function values ​​of the individuals in the final generation population of this embodiment with respect to the two optimization objective functions and the current Pareto optimal solution. Fig.10 As shown in the figure, the individuals in the final generation population have evolved to the Pareto optimal state, and finally three Pareto optimal solutions are obtained, which are to cover 314 defects with one test stimulus (V1_V2_V3=1.65_0.54_0.31) and to cover 339 defects with two test stimuli (V1_V2_V3=1.65_0.54_0.31, V1_V2_V3=1.65_0.54_0.39). These results provide test engineers with a variety of test schemes to choose from, and they can flexibly adjust the test strategy according to the actual test cost budget and expected test benefits.

[0129] After verifying the feasibility and effectiveness of the present invention, the present invention is compared with the traditional random method, full scan method, and particle swarm algorithm. The defect coverage achieved by the present invention and other comparative methods at the same time is compared using the control variable method. Table 4 is a comparison table of the experimental results of the present invention and the comparative method in this embodiment.

[0130] algorithm Simulation times Number of detectable defects Minimum incentive required The present invention 55 339 3 Random Generation Method 55 286 11 Full scan method (step size is 0.5V) 75 249 13 Particle Swarm Optimization 60 307 8

[0131] Table 4

[0132] As shown in Table 4, under the same test generation time, compared with the random generation method, the full scan method and the particle swarm algorithm, the defect coverage of the present invention is increased by 15.59%, 26.47% and 9.42%, respectively, which further verifies the superior performance of the present invention in optimizing the test process and improving the test quality.

[0133] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A method for generating analog circuit test stimulus based on a heuristic greedy algorithm, characterized in that: The following steps are involved: S1: For the analog circuit to be tested, all components in the circuit netlist are identified, defect models are established for all components except the power supply, and a defect list is generated. Each defect model is equivalently compressed and injected into the analog circuit to be tested one by one to obtain a defect simulation circuit; S2: According to the number N of stimulus sources of the analog circuit to be tested, an N-dimensional search space is established, and the search space is discretized according to the achievable accuracy of the test stimulus to obtain the coordinates of each search grid point; S3: Divide the search space into D=2 N Thus, D sub-search spaces are obtained, and the search grid point where the geometric center of each sub-search space is located is taken as the initial point start d , d = 1, 2, ..., D, for each initial point start in the simulation circuit d Perform defect simulation and record each starting point start d The set of detectable defects Select the initial point with the largest number of detectable defects as the search starting point base; S4: Search the test stimulus set based on the heuristic greedy algorithm. The specific method is: S4.1: Initialize the cumulative detectable defect set Initialize the test stimulus set E = {start1, start2, ..., start D }; S4.2: Initialize the search step length L=L0, where L0 represents a preset initial value of the search step length; S4.3: Sample K search grid points in the search space with a distance L from the search base point as the neighborhood search point p k , k = 1, 2, ..., K, K represents the preset number of sampling points; S4.4: For each neighborhood search point p in the analog circuit k Perform defect simulation to obtain the corresponding detectable defect set f k , the neighborhood search point p k Add the test stimulus set E, and let the cumulative detectable defect set F′=F∪f1∪f2∪…∪f K ; S4.5: Determine whether the search end condition is met, if yes, proceed to step S4.9, otherwise proceed to step S4.6; S4.6: Determine whether |F′|>|F|, where || represents the number of detectable defects in the set. If so, proceed to step S4.7, otherwise proceed to step S4.8; S4.7: Let the cumulative detectable defect set F = F′, and then search for point p from K neighborhoods k Filter the neighborhood search points with the largest number of detectable defects Update search base point Return to step S4.3; S4.8: Let the search step size L = λ×L, λ represents the preset search step size scaling factor, λ∈(0,1), and return to step S4.3; S4.9: Use the current test stimulus set E as the test stimulus set for the final analog circuit test.

2. The method for generating analog circuit test stimulus according to claim 1, characterized in that: The defect model in step S1 adopts the defect model provided by the IEEE P2427 standard proposal.

3. The method for generating analog circuit test stimulus according to claim 1, characterized in that: In step S4.2, the initial value L0 of the search step is set to half the distance between adjacent initial points.

4. The method for generating analog circuit test stimulus according to claim 1, characterized in that: In step S4.5, the number of sampling points K=2N.

5. The method for generating analog circuit test stimulus according to claim 1, characterized in that: The search end condition in step S4.5 is whether | | indicates the number of detectable defects in the set. Indicates the preset threshold value for the number of detected defects.

6. The method for generating analog circuit test stimulus according to claim 1, characterized in that: The search termination condition in step S4.5 is whether the cumulative number of detectable defects converges and there is no neighborhood search point in the neighborhood of the current search base point with a number of detectable defects exceeding the previously evaluated search grid points.

7. The method for generating analog circuit test stimulus according to claim 1, characterized in that: The step S4.9 also includes performing test stimulus optimization on the current test stimulus set E based on the Pareto genetic algorithm, and the specific method is as follows: S4.9.1: Determine the optimization target of test stimulus selection according to actual needs, record the number of optimization targets as M, and set the optimization objective function g of the test stimulus selection scheme m (X), m = 1, 2, ..., M, the smaller the optimization objective function value, the better the test solution; S4.9.2: Randomly generate H individuals X h =[x h,1 ,x h,2 ,…,x h,D ], h = 1, 2, ..., H, each individual represents a test stimulus vector selection scheme, x h,d = 0 means that the dth test stimulus vector is not selected in the test stimulus vector selection scheme corresponding to the individual, x h,d =1 indicates that the dth test stimulus vector is selected in the test scheme corresponding to the individual, d=1,2,…,D, D indicates the number of test stimulus vectors in the test stimulus set E; the randomly generated H individuals constitute the initial population P; S4.9.3: Set the number of iterations t = 1; S4.9.4: Perform selection, crossover, and mutation operations on individuals in population P to generate a new population Q; S4.9.5: Merge population P and population Q to obtain population S = P ∪ Q; S4.9.6: Calculate the M optimization objective function values ​​corresponding to each individual in the population S, determine the Pareto dominance relationship between any two individuals based on the optimization objective function values, count the number of times each individual is dominated, sort all individuals from small to large according to the number of times they are dominated, and select the first H individuals to form the optimal population P′; S4.9.7: Determine whether the number of iterations t < t max , t max Indicates the preset maximum number of iterations. If yes, proceed to step S4.9.8, otherwise proceed to step S4.9.9; S4.9.8: Let the number of iterations t = t + 1, let the population P = P′, and return to step S4.9.4; S4.9.9: According to the Pareto dominance relationship, select the non-dominated individuals in the preferred population P′, and use the test excitation vector selection scheme corresponding to these non-dominated individuals as a preferred scheme.

8. The method for generating analog circuit test stimulus according to claim 7, characterized in that: The optimization objective function in step S4.9.1 includes the optimization objective function of the number of test excitation vectors and the optimization objective function of the defect detection rate, wherein the optimization objective function expression of the number of test excitation vectors is: Where X = [x1, x2, …, x D ] represents the test stimulus vector selection scheme, x d is a binary variable, x d = 0 means that the dth test stimulus vector is not selected in the test stimulus vector selection scheme corresponding to the individual, x d =1 indicates that the dth test stimulus vector is selected in the test scheme corresponding to the individual, d=1,2,…,D, D indicates the number of test stimulus vectors in the test stimulus set E; The optimization objective function expression of defect detection rate is: g2(X)=1-fdr(X) Where fdr(X) represents the defect detection rate of the test stimulus vector selection scheme.

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