Data storage method, controller and control device

Abstract

The application discloses a data storage method, a controller and a control device, and relates to the technical field of storage. The controller acquires first data to be stored, and generates corresponding ECC according to the first data. The generated ECC is used for error correction of the first data, and the ECC comprises a first part ECC and a second part ECC. The error correction capability of the complete ECC for the first data is higher than that of the first part ECC for the first data. Therefore, the controller writes the first data and the first part ECC into a first storage space, and writes the second part ECC into a second storage space. Since the data amount of the ECC is usually smaller than that of the first data, the storage resources required for storing the first data can be effectively reduced. Moreover, the complete ECC has higher error correction capability than the first part ECC, which can effectively guarantee the reliability of the stored first data. Thus, the reliability of data storage can be guaranteed while the data storage cost is reduced.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data storage method, controller, and control device. Background Technology

[0002] Data mirroring refers to storing the same data in multiple storage spaces, with each space also storing the corresponding error correcting code (ECC). When data needs to be read, the controller can retrieve the data and its corresponding ECC from one of the storage spaces. If the ECC read from that storage space indicates the data is error-free or that any existing errors are correctable, the controller can directly return the correct data. If the ECC read from that storage space indicates an uncorrectable error, the controller can read the correct data from another storage space and return it. By storing the same data in multiple storage spaces, data storage reliability can be guaranteed.

[0003] However, storing the same data in multiple storage spaces will consume a lot of storage resources, which will lead to higher data storage costs and limit the total amount of data that can be stored in those multiple storage spaces. Summary of the Invention

[0004] This application provides a data storage method to reduce data storage costs and increase the total amount of data that can be stored across multiple storage spaces while ensuring data storage reliability. Furthermore, this application also provides a corresponding controller, control device, computer-readable storage medium, and computer program product.

[0005] Firstly, this application provides a data storage method, which can be executed by a corresponding controller, such as a memory controller or a controller in a hard disk. During the data storage process, the controller acquires the first data to be stored and generates a corresponding ECC (Error Correction Code) based on the first data. The generated ECC is used to correct errors in the first data. The ECC includes a first part of ECC and a second part of ECC. The complete ECC (i.e., the first part of ECC + the second part of ECC) has a higher error correction capability for the first data than the first part of ECC. Thus, the controller writes the first data and the first part of ECC into a first storage space and writes the second part of ECC into a second storage space.

[0006] Because the first data can be stored solely in the first storage space during storage, and the amount of ECC data stored in both the first and second storage spaces is typically less than the amount of data to be stored, this effectively reduces the storage resources required to store the first data. Furthermore, not only can the first part of the ECC correct errors in the first data, but the complete ECC can also correct errors based on its enhanced error correction capabilities, effectively ensuring the reliability of the stored first data. Thus, the controller, while ensuring data storage reliability, can reduce data storage costs and increase the total amount of data that can be stored across multiple storage spaces.

[0007] In addition, this data storage method does not require the processor to perform data access granularity. Therefore, it can support the processor to perform data read and write at a smaller data access granularity (such as 64 bytes), which can enable the data read and write performance in the first storage space to reach a high level.

[0008] In one possible implementation, the controller can also respond to a read instruction sent by the processor by reading a first portion of the ECC and first data from the first storage space, and analyze the read first data based on the first portion of the ECC to obtain an analysis result. When the analysis result indicates that the read first data contains uncorrectable errors, the controller reads a second portion of the ECC from the second storage space, and corrects the read first data based on the first and second portions of the ECC to obtain the first target data. Finally, the controller feeds back the first target data to the processor. Thus, when the first portion of the ECC cannot correct the read first data, the controller uses the complete ECC with higher error correction capabilities to correct the read first data. This ensures that the processor can ultimately obtain the correct first data, thereby guaranteeing the reliability of the first data storage.

[0009] Optionally, when the analysis results indicate that the first data read contains correctable errors, the controller can use the first part of ECC to correct the errors in the first data read, obtain the second target data, and feed the second target data back to the processor. In this way, the processor can ultimately obtain the correct data, improving the reliability of data storage.

[0010] In one possible implementation, when the controller writes the first data and the first portion of the ECC to the first storage space, it may first determine the amount of data in the first portion of the ECC based on the amount of the first data, such as a ratio of 4:1 between the amount of the first data and the amount of data in the first portion of the ECC. Then, based on the amount of data in the first portion of the ECC, the controller determines the first portion of the ECC from the complete ECC. The controller then writes the first data and the determined first portion of the ECC to the first storage space. In this way, the controller can write a portion of the ECC and the first data to the same storage space, so that when reading the first data later, if there are a few errors in the first data, the first portion of the ECC can be used to verify whether errors have occurred in the first data.

[0011] In one possible implementation, when the controller determines the first part of the ECC from the complete ECC based on the amount of data in the first part of the ECC, it may specifically select a series of consecutive symbols from the complete ECC based on the amount of data, wherein each symbol includes a preset number of bits of data, and the selected symbols can serve as the first part of the ECC. In this way, the controller can obtain the first part of the ECC, which is stored in the same storage space as the first data, by consecutively selecting multiple symbols.

[0012] Alternatively, the controller may select multiple non-contiguous symbols from the complete ECC, without limitation.

[0013] In one possible implementation, the first and second storage spaces are located on a storage medium, which also includes a third storage space (and more storage spaces). This allows the controller to acquire the second data to be stored and generate an ECC (Extended Code Correction) corresponding to the second data. When the second data does not meet reliable storage conditions (e.g., the second data has low reliability requirements), the controller can write the second data and its corresponding ECC into the third storage space. Thus, for data with high data storage reliability requirements, the first and second storage spaces can be flexibly allocated according to address space for storage. For data with low reliability requirements, it is not necessary to allocate multiple storage spaces, thereby improving data storage flexibility.

[0014] In one possible implementation, the storage medium used in the first storage space is the same as that used in the second storage space, such as both storage spaces using dynamic random access memory (DRAM), and the data storage method in the first storage space matches the data storage method in the second storage space.

[0015] Optionally, the storage medium used in the first storage space may be different from that used in the second storage space, or the data storage methods in the first storage space and the data storage methods in the second storage space may not be compatible.

[0016] In one possible implementation, the storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels or columns. Thus, by using storage particles from different channels or columns to implement the first and second storage spaces, the probability of simultaneous failure of the storage particles corresponding to the two storage spaces can be effectively reduced.

[0017] In one possible implementation, the first storage space and the second storage space are in-memory storage spaces; alternatively, the first storage space and the second storage space are used for persistent storage of the first data. Thus, in both in-memory data storage and persistent data storage scenarios, the above method can be used to ensure the reliability of data storage while reducing data storage costs.

[0018] In one possible implementation, when the controller generates an error correction code (ECC) based on the first data, it may first obtain an encoding matrix, and then use the encoding matrix to encode the first data to obtain the ECC corresponding to the first data. The amount of data in the ECC corresponding to the first data is greater than or equal to a threshold, and this threshold is determined based on the amount of the first data; for example, the larger the amount of the first data, the higher the threshold. In this way, the controller uses the encoding matrix to generate the ECC corresponding to the first data.

[0019] In a second aspect, this application provides a controller comprising modules for executing the data storage method in the first aspect or any possible implementation thereof.

[0020] Thirdly, this application provides a controller including a power supply circuit and a processing circuit. The power supply circuit supplies power to the processing circuit, which is used to execute the data storage method in the first aspect or any possible implementation of the first aspect.

[0021] Fourthly, this application provides a controller including a processor and a memory. The processor and the memory communicate with each other. The processor executes instructions stored in the memory to cause the controller to execute a data storage method as described in the first aspect or any implementation thereof. It should be noted that the memory can be integrated into the processor or can be independent of the processor. The computing device may also include a bus. The processor is connected to the memory via the bus. The memory may include readable storage and random access memory.

[0022] Fifthly, this application provides a control device comprising a controller as described in any of the second to fourth aspects above, the controller being configured to execute the operational steps of the data storage method described in the first aspect or any of the implementations of the first aspect above.

[0023] In a sixth aspect, this application provides a computer-readable storage medium storing instructions that, when executed on a control device, cause the control device to perform the operation steps of the data storage method described in the first aspect or any implementation thereof.

[0024] In a seventh aspect, this application provides a computer program product containing instructions that, when run on a control device, causes the control device to perform the operational steps of the data storage method described in the first aspect or any implementation thereof.

[0025] Based on the implementation methods provided in the above aspects, this application can be further combined to provide more implementation methods. Attached Figure Description

[0026] Figure 1 A schematic diagram of the structure of an exemplary data storage system provided in this application;

[0027] Figure 2 A flowchart illustrating a data storage method provided in this application;

[0028] Figure 3 This is a schematic diagram illustrating the encoding of data using an encoding matrix.

[0029] Figure 4 A schematic diagram illustrating the use of the first storage space and the second storage space to store the first data and ECC;

[0030] Figure 5 This is a schematic diagram of two different storage spaces on storage medium 103;

[0031] Figure 6 This is a schematic diagram of encoding the first data using the (100, 64)RS8 encoding method;

[0032] Figure 7 A schematic diagram of the structure of a controller provided in this application;

[0033] Figure 8 A schematic diagram of another controller provided in this application;

[0034] Figure 9 A schematic diagram of another controller provided in this application. Detailed Implementation

[0035] To reduce data storage costs and increase the amount of data that can be stored in multiple storage spaces, this application provides a data storage method. By storing the data and its corresponding ECC in one storage space, and storing the other part of the ECC in another storage space, the reliability of data storage is guaranteed while reducing the storage resources required for data storage. This reduces the cost of data storage and allows for the storage of more data in the same storage space.

[0036] To facilitate understanding of the technical solution of this application, the relevant technical terms involved in this application will be explained below.

[0037] Error correction codes are codes used to detect whether data has errors and to correct erroneous data. In this application, when the controller writes data into the storage space, it also writes the corresponding error correction code for that data. This error correction code is used to determine whether there are errors in the data written into the storage space. Furthermore, when it is determined that there are errors in the data in the storage space, the error correction code is used to correct the erroneous data to obtain the correct data content.

[0038] Reed-Solomon (RS) encoding is a method that uses a polynomial over a finite field to represent data and redundant data. This redundant data can be constructed using polynomial operations for error detection and correction. During encoding, processing is typically done on a symbol-by-symbol basis. Each symbol can include m (where m is a positive integer, such as 8 bits) bits of data. The resulting encoding can contain n (where n is a positive integer) symbols, generated from k (where k is a positive integer less than n) data symbols to be transmitted / stored according to a certain association. The remaining (nk) symbols can be used as error correction codes for error detection and correction of the data symbols. The form of the RS encoding can be represented by (n, k).

[0039] In this application, the encoding matrix refers to the matrix used to encode data to generate error-correcting codes.

[0040] A memory chip, also known as a storage particle, is the basic unit for storing data. Each chip can transmit 4 or 8 bits of data at a time, that is, the bit width is 4 bits or 8 bits.

[0041] In this application, a rank refers to a set of particles. The number of particles in each rank can be determined based on the controller's data access granularity to the storage space and the bit width of each particle. For example, if the controller's data access granularity is 64 bits and the bit width of each particle is 8 bits, then a rank can include 8 (i.e., 64 / 8) particles.

[0042] In this application, a channel refers to the pathway through which the controller reads and writes data to the storage space. Each channel may include one or more ranks. Generally, the more channels there are, the faster the controller can read and write data to the storage space.

[0043] See Figure 1 The diagram illustrates the structure of a data storage system provided in this application. Figure 1 As shown, the data storage system 100 may include a processor 101, a controller 102, and a storage medium 103. The processor 101, the controller 102, and the storage medium 103 may be connected by a bus, such as a double data rate (DDR) bus or an inter-integrated circuit (I2C) bus.

[0044] The processor 101 is configured to provide data to be stored to the controller 102 and instruct the controller 102 to write the data into the storage medium 103. Furthermore, the processor 101 can also instruct the controller 102 to read data from the storage medium 103. Exemplarily, the processor 101 can be a central processing unit (CPU), or any combination of processors such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a system-on-chip (SoC), a software-defined infrastructure (SDI) chip, an artificial intelligence (AI) chip, and a data processing unit (DPU).

[0045] The controller 102 is responsible for reading and writing data to the storage medium 103, including writing new data provided by the processor 101 into the storage medium 103, and reading data stored in the storage medium 103 and feeding that data back to the processor 101. For example, the controller 102 may be hardware such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a complex programmable logic device (CPLD), or a field-programmable gate array (FPGA).

[0046] Storage medium 103 is used to store data provided by processor 101 and supports the reading of stored data by controller 102. Storage medium 103 can be a memory storage medium, such as Dynamic Random Access Memory (DRAM), Dual-Inline-Memory Modules (DIMM), or Storage Class Memory (SCM). In this case, storage medium 103 can be used for temporary data storage, and controller 102 can specifically be a memory controller. Alternatively, storage medium 103 can be a storage medium for persistent data storage, such as a solid-state drive (SSD) or hard disk drive (HDD).

[0047] When the controller 102 writes new data to the storage medium 103, if it backs up the data in multiple storage spaces within the storage medium 103 (i.e., storing the same data in multiple storage spaces so that if an error occurs in one storage space, the controller 102 can retrieve the correct data from the others), this data storage method will result in the data occupying a large amount of storage resources in the storage medium 103, leading to higher data storage costs and limiting the total amount of data that the storage medium 103 can store. For example, a 2GB storage space can only store a maximum of 1GB of data.

[0048] Based on this, the controller 102 provided in this application, during the process of writing new data to the storage medium 103, first obtains the data to be stored, which may be data provided by the processor 101, and generates an ECC (Error Correction Code) based on the first data. This ECC is used to correct errors in the data to be written (when there are errors in the written data, the ECC is used for error correction). Typically, error correction includes error detection and error correction. Error detection refers to detecting whether there are errors in the written data, and error correction refers to correcting the erroneous data in the written data to correct data. The generated ECC includes a first part of ECC and a second part of ECC. The first part of ECC also has the ability to correct errors in the data, and the error correction capability of the complete ECC for the data is higher than that of the first part of ECC. Then, the controller 102 writes the data and the first part of ECC into the first storage space in the storage medium 103, and writes the second part of ECC into the second storage space in the storage medium 103.

[0049] Because data can be stored in only one storage space of storage medium 103 during the data storage process, and the amount of ECC data stored in the first and second storage spaces is usually less than the amount of data to be stored, this effectively reduces the storage resources required for data storage. Furthermore, not only can the first part of the ECC correct the data, but the complete ECC can also correct the data based on a higher level of error correction capability, which effectively ensures the reliability of data storage. Thus, while ensuring the reliability of data storage, controller 102 can reduce data storage costs and increase the total amount of data that storage medium 103 can store.

[0050] Furthermore, this data storage method does not impose requirements on the data access granularity of the processor 101. Therefore, it can support the processor 101 to perform data read and write operations at a smaller data access granularity (such as 64 bytes), which allows for a high level of performance in reading and writing data in the first storage space. Moreover, in the storage medium 103, for data with high data storage reliability requirements, the corresponding first and second storage spaces can be flexibly allocated according to the address space for storage. For data with lower data storage reliability requirements, it is not necessary to allocate multiple storage spaces to store the data, thereby improving the flexibility of data storage.

[0051] In practical applications, the data storage system 100 can be used in centralized or distributed storage scenarios. In a centralized storage scenario, the processor 101, controller 102, and storage medium 103 in the data storage system 100 can adopt a disk-controller separation architecture or a disk-controller integrated architecture. In a distributed storage scenario, the processor 101, controller 102, and storage medium 103 in the data storage system 100 can adopt a storage-compute integrated architecture or a storage-compute separation structure. That is, the processor 101, controller 102, and storage medium 103 can reside in the same hardware entity, such as in the same server; or, the processor 101, controller 102, and storage medium 103 can reside in different hardware entities, such as the processor 101 in a server, and the controller 102 and storage medium 103 in a hard disk, and the server and hard disk can be connected via a peripheral component interconnect express (PCIe) bus.

[0052] It is worth noting that the above Figure 1The data storage system 100 shown is merely an example. In other possible data storage systems, there may be multiple processors, which may be the same or different types of processors, and all of these processors may instruct the controller 102 to read and write data to the storage medium 103. Alternatively, other possible data storage systems may include even more numbers or more types of storage media, for example, in... Figure 1 Based on the data storage system 100 shown, it may further include storage medium A. Storage medium 103 serves as memory for temporary data storage, while storage medium A serves as a hard disk for persistent data storage. Alternatively, other possible data storage systems may include other types of devices, such as network interface cards (NICs). This application does not limit the specific architecture of the data storage system.

[0053] Next, the data storage method provided in this application will be described with reference to the accompanying drawings.

[0054] See Figure 2 , Figure 2 This application provides a flowchart illustrating a data storage method that can be applied to... Figure 1 The data storage system 100 shown can be applied to other suitable data storage systems. For ease of illustration, this method is applied to... Figure 1 The data storage system 100 shown is used as an example for illustration.

[0055] in, Figure 2 The data storage method shown may specifically include:

[0056] S201: The processor 101 provides the first data to be stored to the controller 102.

[0057] In this embodiment, the processor 101 can process business operations during operation, such as data merging and data calculation. Furthermore, the processor 101 can generate corresponding business data during the business processing. For ease of distinction and description, the business data generated by the processor 101 will be referred to as first data. This first data can be temporarily stored or persistently stored in the file storage system 100.

[0058] In practical applications, the processor 101 can also obtain user input data, and thus the processor 101 can provide the user input data as the first data to the controller 102, so as to instruct the controller 102 to cache or persistently store the first data.

[0059] S202: The controller 102 generates an ECC based on the first data, and the ECC includes a first part of the ECC and a second part of the ECC, wherein the generated ECC is used to correct errors in the first data, and the error correction capability of the ECC for the first data is higher than that of the first part of the ECC for the first data.

[0060] In one possible implementation, the controller 102 can acquire a predefined encoding matrix, for example, the encoding matrix can be pre-configured in the controller 102. In this way, the controller 102 can use the encoding matrix to encode the first data, and the resulting encoding includes the first data and the ECC, thereby allowing the ECC to be extracted from the encoding result.

[0061] Generally, the larger the amount of ECC data generated, the stronger the error correction capability of the ECC for the first data. The error correction capability described in this embodiment includes error detection and error correction. Here, error detection refers to the controller 102's ability to detect whether errors have occurred in the data stored in the storage medium 103 based on the ECC; error correction refers to the controller 102's ability to correct the erroneous data stored in the storage medium 103 based on the ECC to obtain correct data.

[0062] Therefore, the amount of ECC data generated by controller 102 can be greater than or equal to a threshold, which is determined based on the amount of the first data. Typically, the amount of ECC data generated will be less than the amount of the first data. For example, if the first data is 256 bits, then the amount of ECC data generated can be 144 bits (or more than 144 bits, etc.). Correspondingly, the number of rows in the encoding matrix used to generate the ECC can be determined based on the amount of data written to the storage space by controller 102 in a single data write operation and the amount of ECC data corresponding to that data. Furthermore, the encoding matrix has the characteristic that any submatrix is ​​invertible.

[0063] For example, such as Figure 3 As shown, assuming the controller 102 writes (n×m) bits of data to the storage space in one write operation, the data to be written can be arranged into n data blocks, each data block can include m bits, where n and m are both positive integers greater than 1, and the data in each data block can constitute a data symbol. Therefore, the controller 102 can use the following... Figure 3 The encoding matrix shown comprises (n×(n+k)) data blocks. The values ​​of the data blocks in each of the first n rows of the encoding matrix are as follows: Figure 3As shown, the values ​​of the data blocks in each row from row (n+1) to row (n+k) of the encoding matrix can be predefined according to the encoding algorithm. Then, the controller 102 can perform a multiplication operation between the encoding matrix and the matrix composed of n data blocks to obtain the following... Figure 3 The encoding result shown includes (n+k) data blocks. The first n data blocks contain the data to be written, and the (n+1)th to (n+k)th data blocks are the corresponding ECCs. Thus, during a single write operation, the controller 102 can generate (k×m) bits of ECC, allowing the subsequent storage of (n×m) bits of data and (k×m) bits of ECC in the storage medium 103.

[0064] In practical applications, the amount of the first data to be stored can be greater than (n×m) bits. Therefore, the controller 102 can perform multiple write operations on the first data, generating a corresponding ECC (Extended Code Classification) during each write operation. For example, assuming n is 64, m is 8, and k is 36, the controller 102 writes 512 bits of data to the storage space in one write operation. Each time the controller 102 writes 512 bits, it also writes the corresponding 288-bit ECC. When the first data is 256 bytes (2048 bits), the controller 102 can perform four write operations. Each time a write operation is performed, a 288-bit ECC is generated for the 512 bits written. The total ECC for the first data is 1152 bits (288 bits × 4), or 144 bytes.

[0065] In this embodiment, the controller 102 can divide the ECC generated for the first data into two parts, which will be referred to as the first part ECC and the second part ECC, respectively. Each part of the ECC has error correction capability for the first data, and the error correction capability of the complete ECC (i.e., the first part ECC + the second part ECC) is higher than that of any part of the ECC.

[0066] As an implementation example, the number of bits in the first ECC portion can be determined based on the amount of the first data. Specifically, the controller 102 can determine the data size of the first ECC portion based on the amount of the first data, and determine the first ECC portion from the generated complete ECC portion based on the data size of the first ECC portion. For example, when the first data includes 512 bits, the controller 102 can generate a complete ECC portion of 288 bits, and further determine that the data size of the first ECC portion is 128 bits. In this case, the ratio between the amount of the first data and the data size of the first ECC portion can be 4:1.

[0067] Furthermore, the complete ECC generated by controller 102 may include multiple symbols, such as Figure 3 The diagram shows K symbols (i.e., symbols C1 to Ck). Each symbol includes a predetermined number of bits of data, such as 8 bits.

[0068] In one example, during the process of determining the first part of the ECC from the complete ECC, the controller 102 can select multiple consecutive symbols from the complete ECC based on the amount of data in the first part of the ECC. For example, it can select symbols C1, C2, ..., Cx consecutively as the first part of the ECC (including x symbols), and the remaining symbols Cx+1 to Ck can be used as the second part of the ECC (including kx symbols).

[0069] In another example, controller 102 can select multiple discontinuous symbols from the complete ECC based on the amount of data in the first part of ECC, such as selecting symbols C1, C2, C3, C4, and symbols C9, C10, ..., Cx+4, as the first part of ECC (including x symbols). The remaining symbols C5, C6, C7, C8, Cx+5 to Ck can be used as the second part of ECC (including kx symbols).

[0070] It should be noted that the above-described implementation of determining the first part of ECC is only an example. In other embodiments, the controller 102 may also select the first part of ECC from the complete ECC in other ways, and this is not limited.

[0071] The data size of the first part of the ECC can be different from that of the second part. For example, assuming that the total data size of the ECC generated by the controller 102 is 144 bytes, the data size of the first part of the ECC can be 64 bytes, while the data size of the second part of the ECC can be 80 bytes. Alternatively, the data size of the first part of the ECC can be the same as that of the second part of the ECC.

[0072] Furthermore, the first part of the ECC can be any part of the complete ECC. For example, the first part of the ECC could be... Figure 3 The (n+1)th to (n+x)th data blocks are given, where x is a positive integer less than k, and the second part has ECC. Figure 3 The (n+x+1)th to (n+k)th data blocks in the middle. For example, the first part, ECC, could be... Figure 3 The (n+5)th to (n+8)th data blocks, and the first part of the ECC is Figure 3 The (n+1)th to (n+4)th data blocks and the (n+8)th to (n+k)th data blocks.

[0073] S203: The controller 102 writes the first data and the first part of ECC into the first storage space in the storage medium 103.

[0074] S204: Controller 102 writes the second part of ECC into the second storage space in storage medium 103.

[0075] In this embodiment, the controller 102 can divide the first data into two storage spaces in the storage medium 103, namely the first storage space and the second storage space, and these two storage spaces are used to store the first data to be stored and the ECC.

[0076] When storing data, the controller 102 writes all the first data into one storage space, and writes different parts of the complete ECC into different storage spaces. Specifically, the controller 102 writes the first data and the first part of the ECC into the first storage space, and writes the second part of the ECC into the second storage space.

[0077] The following sections describe the process of the controller 102 writing the first data to the storage space and the implementation of ECC, based on different implementation methods of the storage space.

[0078] In the first implementation, the first storage space and the second storage space are two different storage spaces on the same storage medium; or, the first storage space and the second storage space are storage spaces of the same type but on different storage media. In this case, the data storage method in the first storage space matches the data storage method in the second storage space.

[0079] For example, the first storage space can be divided into regions in a 4:1 ratio, including, for example... Figure 4The data storage area and ECC storage area are shown, wherein the size of the data storage area is four times the size of the ECC storage area. When controller 102 writes the first data and the first part of ECC into the first storage space, the amount of data in the first part of ECC is one-quarter of the amount of the first data. Assuming the amount of the first data is 256 bytes and the amount of data in the first part of ECC is 64 bytes, then controller 102 can write 256 bytes of the first data into the data storage area of ​​the first storage space and write 64 bytes of the first part of ECC into the ECC storage area of ​​the first storage space. Figure 4 As shown.

[0080] Similarly, the second storage space can also be divided into regions in a 4:1 ratio, such as... Figure 4 The diagram shows regions 1 and 2, where region 1 is four times the size of region 2. When writing the second part of the ECC to the second storage space, controller 102 can further divide the second part of the ECC into a first subset and a second subset in a 4:1 ratio, where the data size of the first subset is four times that of the second subset. Assuming the second part of the ECC contains 80 bytes of data, the first subset contains 64 bytes, and the second subset contains 16 bytes. Therefore, controller 102 can write the 64 bytes of the first subset from the second part of the ECC to region 1, and the 16 bytes of the second subset from the second part of the ECC to region 2. Figure 4 As shown.

[0081] At this point, the size of the first storage space can be different from that of the second storage space. For example, the size of the second storage space can be one-quarter of the size of the first storage space, which can effectively save the storage resources required for data storage.

[0082] Furthermore, when the first storage space and the second storage space are different storage spaces on the same storage medium, the first storage space can be implemented using a first portion of the storage particles on the storage medium, and the second storage space can be implemented using a second portion of the storage particles on the storage medium. Moreover, the storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels; in this case, the first storage space and the second storage space can correspond to different channels on the storage medium 103. Alternatively, the storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different columns; in this case, the first storage space and the second storage space can correspond to different columns on the storage medium 103. Thus, the storage particles corresponding to the two storage spaces are independent of each other.

[0083] For example, such as Figure 5As shown, the storage medium 103 may have two channels, namely channel 0 and channel 1, wherein each channel may include one or more columns. Figure 5 This example uses a channel consisting of four columns. Each column can include multiple storage particles. Figure 5 Taking an example where each column includes 8 storage channels, the first storage space and the second storage space can be storage space A in channel 0 and storage space B in channel 1, respectively; or, the first storage space and the second storage space can be storage space A in column 0 included in channel 0 and storage space C in column 3 included in channel 0, respectively.

[0084] Therefore, by using storage particles on different channels or columns to implement the first and second storage spaces, the probability of simultaneous failure of the storage particles corresponding to the two storage spaces can be effectively reduced. In practical applications, the probability of simultaneous failure of storage particles on different channels or columns is close to 0. Furthermore, simulation tests based on the standard test set SPECint2017 show that the reliability of storing the first data using two storage spaces is similar to the reliability of mirroring the first data.

[0085] In the second implementation, the first and second storage spaces are storage spaces on different types of storage media, such as the first storage space located on a DIMM and the second storage space located on an SCM. In this case, the data storage method in the first storage space can differ from the data storage method in the second storage space. For example, the first storage space can be divided into regions in a 4:1 ratio, and the way the controller 102 writes the first data and the first part of ECC into the first storage space can be the same as described above. Figure 4 The method shown is the same; however, since there is no need to divide the second storage space into regions, when the controller 102 writes the second part of ECC into the second storage space, it can directly write the second part of ECC into a continuous address region in the second storage space, without having to store the second part of ECC in a 4:1 ratio.

[0086] In practical applications, after completing the writing of the first data and ECC, the controller 102 can also return a notification of successful data writing to the processor 101.

[0087] Because the first piece of data can be stored in only one storage space during the data storage process, while the amount of ECC data stored in multiple different storage spaces is usually smaller than the amount of the first piece of data, this can effectively reduce the storage resources required for data storage. Furthermore, not only can the first part of the ECC correct errors in the first piece of data, but the complete ECC (i.e., the first part of the ECC + the second part of the ECC) can also correct errors in the first piece of data based on a higher level of error correction capability, which can effectively ensure the reliability of the first piece of data storage.

[0088] To further understand how the different portions of ECC stored in the two storage spaces can guarantee the reliability of the first data storage, the following section further describes the process by which the controller 102 uses both the first and second portions of ECC to correct errors in the read first data. Furthermore, Figure 2 The method shown may also include the following steps.

[0089] S205: The processor 101 sends a read command to the controller 102 to read the first data.

[0090] Normally, the controller 102 can execute the operation of reading data from the storage medium 103 under the read command of the processor 101. The read command may include information such as the storage address and data size of the first data, so that the controller 102 can determine the first data to be read according to the read command.

[0091] S206: Controller 102 reads the first data and the first part of ECC from the first storage space.

[0092] S207: Controller 102 analyzes the first data according to the first part of ECC and obtains the analysis results.

[0093] In this embodiment, the controller 102 can determine whether there is an uncorrected error (UCE) in the first data read based on the first part of ECC.

[0094] The first part of the ECC has error correction capabilities for the first data, and the level of its error correction capability is related to the amount of data in the first ECC. Generally, the higher the amount of data in the first part of the ECC, the higher its error correction capability for the first data.

[0095] Because the voltage of some storage cells may change unexpectedly when the first data is stored on storage medium 103, causing storage errors in the data stored using those cells, the first data read by controller 102 may contain some errors. Therefore, after reading the first part of the ECC and the first data, controller 102 can use the first ECC to analyze the first data and obtain corresponding analysis results. These analysis results can be used to indicate whether there are errors in the read first data.

[0096] If the controller 102 determines that there is no error in the first data based on the analysis results, the controller 102 can directly return the first data to the processor 101, such as by feeding the first data back to the processor 101 through the DDR bus.

[0097] If the controller 102 determines that an error has occurred in the first data based on the analysis results, but the error is a correctable error (CE) based on the first part of ECC, then the controller 102 can use the first part of ECC to correct the error in the first data to obtain the correct data, hereinafter referred to as target data 2. Then, the controller 102 feeds the target data 2 back to the memory 101 so that the processor 101 can obtain the correct first data (i.e., target data 2).

[0098] Among them, the controller 102 uses ECC to correct data errors. This has already been applied in real-world scenarios, and the specific implementation of the error correction process will not be elaborated here.

[0099] If it is determined that an error has occurred in the first data, and the error is an uncorrectable error based on the first part of ECC (i.e., it exceeds the error correction capability of the first part of ECC), then the controller 102 can continue to execute subsequent steps to correct the error in the first data read.

[0100] S208: When the analysis result indicates that there is an uncorrectable error in the first data read, the controller 102 reads the second part of the ECC in the second storage space.

[0101] S209: The controller 102 corrects the first data read based on the first part of ECC and the second part of ECC to obtain target data 1.

[0102] It is understandable that since the error correction capability of the complete ECC is higher than that of the first part of the ECC, when the controller 102 cannot correct the errors in the read first data based solely on the first part of the ECC, the controller 102 can read the second part of the ECC from the second storage space. In this way, the controller 102 can combine the first part of the ECC and the second part of the ECC to obtain the complete ECC, and thus use the complete ECC with higher error correction capability to correct the first data to obtain the correct data, hereinafter referred to as target data 1.

[0103] Taking RS encoding of the first data by controller 102 as an example, assuming the first data is 512 bits, controller 102 can encode the first data in an (100, 64)RS8 encoding format. That is, controller 102 can generate a data symbol in units of 8 bits, thus generating 64 data symbols based on the first data. Furthermore, controller 102 will also generate 36 ECC symbols for error correction of the first data for this 512-bit data, such as... Figure 6 As shown, the total number of symbols is 100 (64+36). The first part of the ECC can include 16 ECC symbols, stored in the first storage space; the second part of the ECC can include 20 ECC symbols, stored in the second storage space, as shown below. Figure 6 As shown.

[0104] When the controller 102 uses the first part of ECC to correct errors in 64 data symbols (i.e., the first data), it can correct a maximum of 8 (i.e., 16 / 2) data symbols that have erroneous errors. That is, the number of data symbols that the first part of ECC can correct is half the number of symbols corresponding to the first part of ECC.

[0105] When the number of erroneous data symbols is greater than 8, the controller 102 can use 36 data symbols (including the first part of ECC and the second part of ECC) to correct 64 data symbols, and can correct up to 18 (i.e. 36 / 2) erroneous data symbols.

[0106] Therefore, when the number of erroneous data symbols is no more than 8, the controller 102 can directly use the 16 ECC symbols in the first storage space to complete data error correction and feed back the correct first data to the processor 101. When the number of erroneous data symbols is more than 8 but no more than 18, the controller 102 can use all 36 ECC symbols to complete data error correction and feed back the correct first data to the processor 101. When the number of erroneous data symbols is more than 18, the controller 102 can feed back notification information such as data storage error or data read failure to the processor 102.

[0107] S210: The controller 102 feeds back the target data 1 to the processor 101 so that the processor 101 can obtain the correct first data (i.e., target data 1).

[0108] In this embodiment, since the first part of ECC also has error correction capability for ECC, in most scenarios of reading the first data, the controller 102 can complete the error correction of the read first data using only the first part of ECC, without having to read the second part of ECC from the second storage space. This can ensure that the processor 101 achieves a high level of performance in reading the first data.

[0109] Furthermore, when the first part of the ECC fails to correct errors, the controller 102 can use the complete ECC with higher error correction capability to correct the read first data. This ensures that the processor 101 can obtain the correct first data, thereby ensuring the reliability of the first data stored in the storage medium 103.

[0110] It is worth noting that the above description uses the controller 102 storing and retrieving the first data as an example. For other data provided by the processor 102, the controller 102 can use a similar method to store and retrieve that other data to improve data storage reliability. Alternatively, the controller 102 can use different read / write methods to store and retrieve other data provided by the processor 101. The following description uses the controller 102 reading and writing the second data in other ways as an example.

[0111] In a first possible implementation, after receiving the second data provided by the processor 101, the controller 102 can detect whether the second data meets the reliability storage conditions. For example, detecting whether the second data meets the reliability storage conditions could involve detecting whether the importance level issued by the processor 101 for the second data indicates that the second data should be stored reliably.

[0112] For example, processor 101 can not only provide second data to controller 102, but also provide controller 102 with the importance level corresponding to the second data. The importance level of the data can be indicated, for example, using a corresponding flag bit. When the flag bit is set to "1", it indicates a high importance level of the data, meaning the second data meets the reliability storage conditions. In this case, controller 102 can store the data using the same process as storing the first data. When the flag bit is set to "0", it indicates a low importance level of the data, meaning the second data does not meet the reliability storage conditions. In this case, controller 102 can use other storage methods to store the data.

[0113] In this embodiment, assuming the second data does not meet the reliable storage conditions, the controller 102 can encode the second data using a new encoding matrix to obtain the ECC corresponding to the second data. Where the quantity of the first data and the second data are the same, the amount of ECC data generated by the controller 102 for the second data is less than the amount of ECC data generated for the first data.

[0114] Then, the controller 102 can partition a third storage space in the storage medium 103, which does not overlap with the first storage space or the second storage space. Furthermore, the controller 102 can write the second data and the corresponding ECC into the third storage space (i.e., it is not necessary to use multiple storage spaces to store the ECC corresponding to the second data).

[0115] Accordingly, when the processor 101 instructs the controller 102 to read the second data, the controller 102 can read the second data and the corresponding ECC (Error Correction Code) at the same time, and use the ECC to detect whether there are any errors in the read second data. When no error occurs, the controller 102 can directly feed back the read second data to the processor 101; when an error occurs, the controller 102 uses the ECC to correct the read second data, obtains the correct second data, and feeds back the corrected second data to the processor 101.

[0116] In a second possible implementation, after receiving the second data provided by the processor 101, the controller 102 can detect whether it has received an indication from the processor 101 regarding the reliable storage of the second data. This indication could be, for example, a reliability storage tag. If the indication is received, the controller 102 can determine that the second data meets the reliability storage conditions and store the first data according to the storage method described above for the first data. If the controller 102 does not receive the indication, it can determine that the second data does not meet the reliability storage conditions. In this case, the controller 102 can directly write the second data into the third storage space already created in the storage medium 103, i.e., there is no need to generate and store ECC for the second data.

[0117] Accordingly, when the processor 101 requests the controller 102 to read the second data, the controller 102 can directly feed back the read second data to the processor 101 without performing error detection and error correction on the read second data.

[0118] It is understood that the above implementation examples are only for illustrative purposes. In actual applications, the controller 102 may also use other methods to store and retrieve the second data, and there is no limitation on this.

[0119] Thus, in the storage medium 103, for data with high data storage reliability requirements (such as the first data), the controller 102 can flexibly divide the data into multiple corresponding storage spaces and storage spaces according to the address space to store the data and its corresponding ECC. For data with low data storage reliability requirements, it is not necessary to divide the data into multiple storage spaces to store the data and its corresponding ECC, or it is not necessary to store the data ECC, etc. This can support multiple data storage methods and improve the flexibility of data storage.

[0120] It is worth noting that other reasonable combinations of steps that can be conceived by those skilled in the art based on the above description also fall within the scope of protection of this application. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0121] The above combination Figures 1 to 6 The data storage method provided in the embodiments of this application will be introduced, and the controller provided in the embodiments of this application will be introduced next with reference to the accompanying drawings.

[0122] See Figure 7 A schematic diagram of a controller structure is shown. Figure 7 As shown, the controller 700 includes:

[0123] The acquisition module 701 is used to acquire the first data to be stored;

[0124] The generation module 702 is used to generate an error correction code (ECC) based on the first data. The ECC includes a first part of ECC and a second part of ECC. The ECC is used to correct errors in the first data. The error correction capability of the ECC for the first data is higher than that of the first part of ECC for the first data.

[0125] The writing module 703 is used to write the first data and the first part of ECC into the first storage space; and to write the second part of ECC into the second storage space.

[0126] In one possible implementation, the controller 700 further includes:

[0127] The read module 704 is configured to read the first portion of ECC and the first data in the first storage space in response to a read instruction sent by the processor.

[0128] Analysis module 705 is used to analyze the first data based on the first part of ECC and obtain analysis results;

[0129] The reading module 704 is further configured to read the second portion of ECC in the second storage space when the analysis result indicates that the first data read contains an uncorrectable error;

[0130] The error correction module 706 is used to correct the read first data according to the first part of ECC and the second part of ECC to obtain the first target data;

[0131] Feedback module 707 is used to feed back the first target data to the processor.

[0132] In one possible implementation, the writing module 703 is configured to:

[0133] Based on the quantity of the first data, determine the amount of data in the first part of ECC;

[0134] Based on the amount of data, the first portion of the ECC is determined from the ECC;

[0135] Write the first data and the first part of ECC into the first storage space.

[0136] In one possible implementation, the writing module 703 is configured to:

[0137] Based on the data volume, a plurality of consecutive symbols are selected from the ECC, each of the plurality of symbols including a preset number of bits of data, and the first part of the ECC is the plurality of symbols.

[0138] In one possible implementation, the first storage space and the second storage space are located in a storage medium, and the storage medium further includes a third storage space;

[0139] The acquisition module 701 is used to acquire the second data to be stored;

[0140] The generation module 702 is used to generate the ECC corresponding to the second data;

[0141] The writing module 703 is used to write the second data and the corresponding ECC to the third storage space when the second data does not meet the reliable storage conditions.

[0142] In one possible implementation, the storage medium used in the first storage space is the same as that used in the second storage space, and the data storage method in the first storage space matches the data storage method in the second storage space.

[0143] In one possible implementation, the storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels or columns.

[0144] In one possible implementation, the first storage space and the second storage space are storage spaces in memory;

[0145] Alternatively, the first storage space and the second storage space may be used to persistently store the first data.

[0146] In one possible implementation, the generation module 702 is configured to:

[0147] Obtain the encoding matrix;

[0148] The first data is encoded using the encoding matrix to obtain the ECC corresponding to the first data. The amount of data in the ECC corresponding to the first data is greater than or equal to a threshold, which is determined based on the amount of the first data.

[0149] because Figure 7 The controller 700 shown corresponds to Figure 2 The controller 102 in the method shown, therefore Figure 7 The specific implementation of the controller 700 and its technical effects can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0150] Figure 8 This application provides a schematic diagram of the hardware structure of a controller 800, which, for example, can implement the above-described... Figure 2 The controller 102 in the illustrated embodiment, etc.

[0151] like Figure 8 As shown, the controller 800 includes a processor 801, a memory 802, and a communication interface 803. The processor 801, memory 802, and communication interface 803 communicate via a bus 804, or via wireless transmission or other means. The memory 802 stores instructions, and the processor 801 executes the instructions stored in the memory 802. Further, the controller 800 may also include a memory unit 805, which is connected to the processor 801, the storage medium 802, and the communication interface 803 via the bus 804. The memory 802 stores program code, and the processor 801 can call the program code stored in the memory 802 to perform the following operations:

[0152] Retrieve the first data to be stored;

[0153] An error correction code (ECC) is generated based on the first data. The ECC includes a first part of ECC and a second part of ECC. The ECC is used to correct errors in the first data. The error correction capability of the ECC for the first data is higher than that of the first part of ECC for the first data.

[0154] Write the first data and the first part of ECC into the first storage space;

[0155] Write the second part of ECC into the second storage space.

[0156] It should be understood that in the embodiments of this application, the processor 801 may be a CPU, or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete device assemblies, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0157] The memory 802 may include read-only memory and random access memory, and provides instructions and data to the processor 801. The memory 802 may also include non-volatile random access memory.

[0158] The memory 802 can be volatile memory or non-volatile memory, or it can include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0159] The communication interface 803 is used to communicate with other devices connected to the controller 800, such as the processor. The bus 804 may include a data bus, as well as a power bus, control bus, and status signal bus. However, for clarity, all buses are labeled as bus 804 in the figure.

[0160] It should be understood that the controller 800 according to the embodiments of this application may correspond to the controller 102 in the embodiments of this application, and may correspond to the execution of the controller according to the embodiments of this application. Figure 2 The method executed by controller 102 in the illustrated method, and the above and other operations and / or functions implemented by controller 800, are respectively for the purpose of implementing... Figure 2 The process of the corresponding methods in [the document] will not be elaborated here for the sake of brevity.

[0161] Figure 9 This application provides a schematic diagram of the hardware structure of a controller 900, which, for example, can implement the above-described... Figure 2 The controller 102 in the illustrated embodiment, etc. Figure 9As shown, the controller 900 includes a power supply circuit 901 and a processing circuit 902. The power supply circuit 901 supplies power to the processing circuit 902, and the processing circuit 902 performs the following operations:

[0162] Retrieve the first data to be stored;

[0163] An error correction code (ECC) is generated based on the first data. The ECC includes a first part of ECC and a second part of ECC. The ECC is used to correct errors in the first data. The error correction capability of the ECC for the first data is higher than that of the first part of ECC for the first data.

[0164] Write the first data and the first part of ECC into the first storage space;

[0165] Write the second part of ECC into the second storage space.

[0166] It should be understood that the controller 900 according to the embodiments of this application may correspond to the controller 102 in the embodiments of this application, and may correspond to the controller executing the embodiments of this application. Figure 2 The methods executed by controller 102 in the illustrated method, and the above and other operations and / or functions implemented by controller 900, are respectively for the purpose of implementing... Figure 2 The process of the corresponding methods in [the document] will not be elaborated here for the sake of brevity.

[0167] This application also provides a control device, which includes the controller described in the above embodiments. The control device is capable of implementing the methods or functions executed by the controller in the above embodiments.

[0168] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a control device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the control device to execute the above-described data storage method.

[0169] This application also provides a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a control device, all or part of the processes or functions described in this application are generated.

[0170] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0171] The computer program product can be a software installation package. If any of the aforementioned data storage methods are required, the computer program product can be downloaded and executed on a computing device.

[0172] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0173] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data storage method, characterized by, The method includes: Retrieve the first data to be stored; An error correction code (ECC) is generated based on the first data. The ECC includes a first part ECC and a second part ECC. The ECC is used to correct errors in the first data. The error correction capability of the ECC for the first data is higher than that of the first part ECC for the first data. The first part ECC is used to correct the first data when there are correctable errors based on the first part ECC. The second part ECC is used to correct the first data in combination with the first part ECC when there are uncorrectable errors based on the first part ECC. Write the first data and the first part of ECC into the first storage space; Write the second part of ECC into the second storage space.

2. The method of claim 1, wherein, The method further includes: In response to a read command sent by the processor, the first portion of the ECC and the first data in the first storage space are read; The first data is analyzed based on the first part of ECC to obtain the analysis results; When the analysis result indicates that the first data read contains an uncorrectable error, the second portion of ECC in the second storage space is read; Based on the first part of ECC and the second part of ECC, the first data read is corrected to obtain the first target data; The first target data is fed back to the processor.

3. The method of claim 1, wherein, The step of writing the first data and the first portion of ECC into the first storage space includes: Based on the quantity of the first data, determine the amount of data in the first part of ECC; Based on the amount of data, the first portion of the ECC is determined from the ECC; Write the first data and the first part of ECC into the first storage space.

4. The method of claim 3, wherein, Determining the first portion of ECC from the ECC based on the data volume includes: Based on the data volume, a plurality of consecutive symbols are selected from the ECC, each of the plurality of symbols including a preset number of bits of data, and the first part of the ECC is the plurality of symbols.

5. The method of claim 1, wherein, The first storage space and the second storage space are located in a storage medium, and the storage medium further includes a third storage space; The method further includes: Retrieve the second data to be stored; Generate the ECC corresponding to the second data; When the second data does not meet the reliability storage conditions, the second data and the corresponding ECC are written to the third storage space.

6. The method of claim 1, wherein, The storage medium used in the first storage space is the same as that used in the second storage space, and the data storage method in the first storage space matches the data storage method in the second storage space.

7. The method of claim 1, wherein, The storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels or columns.

8. The method of claim 1, wherein, The first storage space and the second storage space are storage spaces in memory; Alternatively, the first storage space and the second storage space may be used to persistently store the first data.

9. The method according to any one of claims 1 to 8, characterized in that, The step of generating error correction codes (ECCs) based on the first data includes: Obtain the encoding matrix; The first data is encoded using the encoding matrix to obtain the ECC corresponding to the first data. The amount of data in the ECC corresponding to the first data is greater than or equal to a threshold, which is determined based on the amount of the first data.

10. A controller characterized by comprising: The controller includes: The acquisition module is used to acquire the first data to be stored; A generation module is used to generate an error correction code (ECC) based on the first data. The ECC includes a first part of ECC and a second part of ECC. The ECC is used to correct errors in the first data. The error correction capability of the ECC for the first data is higher than that of the first part of ECC for the first data. The first part of ECC is used to correct errors in the first data when there are correctable errors based on the first part of ECC. The second part of ECC is used to correct errors in the first data in combination with the first part of ECC when there are uncorrectable errors in the first data based on the first part of ECC. The writing module is used to write the first data and the first part of ECC into the first storage space; and to write the second part of ECC into the second storage space.

11. The controller of claim 10, wherein, The controller also includes: The read module is configured to read the first portion of ECC and the first data in the first storage space in response to a read instruction sent by the processor. The analysis module is used to analyze the first data based on the first part of ECC and obtain the analysis results; The reading module is further configured to read the second portion of ECC in the second storage space when the analysis result indicates that the first data being read contains an uncorrectable error; The error correction module is used to correct the read first data according to the first part of ECC and the second part of ECC to obtain the first target data; The feedback module is used to feed back the first target data to the processor.

12. The controller of claim 10, wherein, The writing module is used for: Based on the quantity of the first data, determine the amount of data in the first part of ECC; Based on the amount of data, the first portion of the ECC is determined from the ECC; Write the first data and the first part of ECC into the first storage space.

13. The controller according to claim 12, characterized in that, The writing module is used for: Based on the data volume, a plurality of consecutive symbols are selected from the ECC, each of the plurality of symbols including a preset number of bits of data, and the first part of the ECC is the plurality of symbols.

14. The controller of claim 10, wherein, The first storage space and the second storage space are located in a storage medium, and the storage medium further includes a third storage space; The acquisition module is used to acquire the second data to be stored; The generation module is used to generate the ECC corresponding to the second data; The writing module is used to write the second data and the corresponding ECC to the third storage space when the second data does not meet the reliable storage conditions.

15. The controller of claim 10, wherein, The storage medium used in the first storage space is the same as that used in the second storage space, and the data storage method in the first storage space matches the data storage method in the second storage space.

16. The controller of claim 10, wherein, The storage particles corresponding to the first storage space and the storage particles corresponding to the second storage space belong to different channels or columns.

17. The controller of claim 10, wherein, The first storage space and the second storage space are storage spaces in memory; Alternatively, the first storage space and the second storage space may be used to persistently store the first data.

18. The controller of any one of claims 10 to 17, wherein, The generation module is used for: Obtain the encoding matrix; The first data is encoded using the encoding matrix to obtain the ECC corresponding to the first data. The amount of data in the ECC corresponding to the first data is greater than or equal to a threshold, which is determined based on the amount of the first data.

19. A controller characterized by comprising: It includes a power supply circuit and a processing circuit, wherein the power supply circuit is used to supply power to the processing circuit, and the processing circuit is used to perform the method according to any one of claims 1 to 9.

20. A controller characterized by comprising: Including processor and memory; The processor is configured to execute instructions stored in the memory to cause the controller to perform the steps of the method as described in any one of claims 1 to 9.

21. A control device, characterized by The control device includes the controller according to any one of claims 10 to 20.

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