Universal serial bus power transfer (USB-PD) system and method of operating USB-PD power converter

Abstract

The invention relates to a universal serial bus power transfer (USB-PD) system and a method of operating a USB-PD power converter. The method includes, in response to detecting an absence of a load device, sending a low power mode signal from a secondary side controller coupled to control a secondary side of the USB-PD power converter to a primary side controller coupled to control a primary side of the USB-PD power converter, and transitioning the secondary side controller from a secondary side active mode to a secondary side low power mode; transitioning the primary side controller from the primary side active mode to a primary side low power mode in response to receiving the low power mode signal; in response to detecting the connection of the load device, sending an active mode signal from the secondary-side controller to the primary-side controller, and transitioning the secondary-side controller from a secondary-side low-power mode to a secondary-side active mode; and transitioning the primary side controller from the primary side low power mode to the primary side active mode.

Description

Technical Field

[0001] The present invention relates to a Universal Serial Bus Power Delivery (USB-PD) system and a method for operating a USB-PD power converter. Background Art

[0002] Various electronic devices (e.g., such as smartphones, tablets, notebooks, laptops, hubs, chargers, adapters, etc.) are configured to transfer power through a USB connector according to the USB power delivery protocol defined in various revisions of the Universal Serial Bus (USB) Power Delivery (USB-PD) specification. An alternating current to direct current (AC-DC) converter converts power from an alternating current (AC) source to a direct current (DC) source at a specified voltage level. Summary of the invention

[0003] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0004] In an embodiment of the technology presented herein, a universal serial bus power delivery (USB-PD) system includes: a transformer including a primary side and a secondary side, the primary side being coupled to receive a rectified alternating current (AC) input voltage at an input port, and the secondary side being connected to provide a direct current (DC) output voltage at an output port; a first power switch connected to a primary side controller; a primary side controller coupled to the first power switch to control operation of the transformer, wherein the primary side controller is configured to: transition from a primary side active mode to a primary side low power mode in response to receiving a low power mode signal, and transition from the primary side low power mode to a primary side active mode in response to receiving an active mode signal, and a secondary side controller coupled to the output port, wherein the secondary side controller is configured to: send a low power mode signal to the primary side controller and transition from the secondary side active mode to the secondary side low power mode in response to detecting that a load device is not present on the output port; and transition from the secondary side low power mode to the secondary side active mode in response to detecting connection of a load device to the output port, and send an active mode signal to the primary side controller.

[0005] In an embodiment of the technology presented herein, a system for operating a universal serial bus power delivery (USB-PD) power converter includes: a device for sending a low power mode signal from a secondary side controller coupled to control the secondary side of the USB-PD power converter to a primary side controller coupled to control the primary side of the USB-PD power converter, and transitioning the secondary side controller from a secondary side active mode to a secondary side low power mode in response to detecting that a load device is not present on an output port of the USB-PD power converter; a device for transitioning the primary side controller from a primary side active mode to a primary side low power mode in response to receiving the low power mode signal; a device for sending an active mode signal from the secondary side controller to the primary side controller in response to detecting connection of a load device to the output port, and transitioning the secondary side controller from a secondary side low power mode to a secondary side active mode; and a device for transitioning the primary side controller from a primary side low power mode to a primary side active mode in response to receiving the active mode signal.

[0006] In an embodiment of the technology presented herein, a method of operating a universal serial bus power delivery (USB-PD) power converter includes: in response to detecting that a load device is not present on an output port of the USB-PD power converter, sending a low power mode signal from a secondary side controller coupled to control the secondary side of the USB-PD power converter to a primary side controller coupled to control the primary side of the USB-PD power converter, and transitioning the secondary side controller from a secondary side active mode to a secondary side low power mode; in response to receiving the low power mode signal, transitioning the primary side controller from the primary side active mode to the primary side low power mode; in response to detecting connection of a load device to the output port, sending an active mode signal from the secondary side controller to the primary side controller, and transitioning the secondary side controller from the secondary side low power mode to the secondary side active mode; and in response to receiving the active mode signal, transitioning the primary side controller from the primary side low power mode to the primary side active mode.

[0007] In an embodiment of the technology presented herein, a universal serial bus power delivery (USB-PD) system includes: a transformer including a primary side and a secondary side, the primary side being coupled to receive a rectified alternating current (AC) input voltage at an input port, the secondary side being connected to provide a direct current (DC) output voltage at an output port; a first power switch connected between the input port and the primary side; a second power switch connected between the output port and the secondary side; a primary side controller coupled to the first power switch; and a secondary side controller coupled to the second power switch, wherein the secondary side controller is configured to: in response to detecting that no load device is present on the output port, send a low power mode signal to the primary side controller and transition from a secondary side active mode to a secondary side low power mode, the primary side controller is configured to transition from the primary side active mode to the primary side low power mode in response to receiving the low power mode signal, and wherein the power consumption of the transformer, the primary side controller in the primary side low power mode, and the secondary side controller in the secondary side low power mode is less than 5 mW.

[0008] In order to achieve the aforementioned and related purposes, the following description and the accompanying drawings set forth some illustrative aspects and implementations. These illustrative aspects and implementations merely indicate some of the various ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of the present disclosure will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and Figure 1B A schematic block diagram of a power converter according to some embodiments is provided.

[0010] Figure 2 is a block diagram of a secondary side controller according to some embodiments.

[0011] FIG. 3A to FIG. 3C A flow chart of a method for power mode control according to some embodiments is shown.

[0012] Figure 4 is a timing diagram illustrating power mode control according to some embodiments.

[0013] Figure 5 is a timing diagram illustrating cross-line capacitor (X-cap) discharge control according to some embodiments.

[0014] Figure 6 An exemplary implementation of a system for a USB device in accordance with some implementations is shown. DETAILED DESCRIPTION

[0015] The claimed subject matter is now described with reference to the accompanying drawings, wherein the same reference numerals are used to refer to the same elements throughout the text. In the following description, for the purpose of illustration, a large number of specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it is apparent that the claimed subject matter can be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form to facilitate description of the claimed subject matter.

[0016] It should be understood that the following description of the embodiments should not be understood as limiting. The scope of the present disclosure is not intended to be limited by the embodiments or drawings described below, which are considered to be illustrative only. The drawings are considered to be schematic representations, and the elements shown in the drawings are not necessarily shown to scale. On the contrary, the various elements are represented so that their functions and general purposes become apparent to those skilled in the art.

[0017] All numerical values ​​in the detailed description and claims herein are indicated values ​​modified by "about" or "approximately", and take into account experimental errors and variations that would be expected by a person of ordinary skill in the art.

[0018] The power converter provides current and power during various operating environments of the power converter, including normal conditions, load transient conditions, and output fault conditions. There is a time period when the power converter is coupled to an external power source (e.g., an AC source) but no load device is coupled to the power converter. During such a no-load state, the power converter transitions to a low-power mode. In some embodiments, the power converter includes a primary side coupled to the external power source and a secondary side connected to the load device. The primary side is controlled by a primary side controller, and the secondary side is controlled by a secondary side controller. In response to the secondary side controller detecting a no-load state, the secondary side controller notifies the primary side controller with a signal to enter a low-power mode. When both the primary side controller and the secondary side controller enter a low-power mode, the power consumption of the power converter can be reduced to less than 5mW.

[0019] Figure 1A and Figure 1B A schematic block diagram of a power converter 100 according to some embodiments is provided. In some embodiments, the power converter 100 is an AC-DC power converter operating in a discontinuous conduction mode (DCM). The power converter 100 includes a primary side controller 102 and a secondary side controller 104 for controlling a flyback transformer 106 having a primary side controller 102 and a secondary side controller 104 electrically coupled to an AC input (AC IN ) of the first winding (N P1 ) and connected to the DC output (DC OUT ) of the secondary winding (NS ). The AC input is connected to a first terminal of the flyback transformer 106 through an across-line capacitor (X-cap) 111, an electromagnetic interference (EMI) filter 112, a bridge rectifier 113, and one or more input filters 114. In some embodiments, the AC input is a sinusoidal signal with an amplitude between about 85V and 285V. A power switch 117, such as a primary field effect transistor (PRFET), has a first node or drain node connected to a second terminal of the flyback transformer 106, a gate node connected to the primary side controller 102, and a third node or source node connected to the primary side controller 102 through a current sensing element 118 connected to ground to sense the primary side current flowing through the primary winding when the power switch 117 is closed or turned on. A low-side (LS) gate driver 119 in the primary side controller 102 controls the power switch 117. A current sensing unit 120 in the primary side controller 102 monitors the current from the current sensing element 118. In some embodiments, the primary side 108 includes an active clamp flyback (ACF) circuit 121. The ACF circuit 121 includes an ACF switch 121S controlled by an ACF gate driver 121D. A high-side (HS) driver 123 in the primary side controller 102 controls the ACF gate driver 121D to drive the ACF switch 121S and provide the ACF function. In some embodiments, the ACF circuit 121 is omitted and the power converter 100 operates in a quasi-resonant mode.

[0020] On the secondary side 110, the power converter 100 includes a filter capacitor 124 connected between a third terminal of the flyback transformer 106 and an electrical ground or ground terminal, and an output capacitor 126 connected between the third terminal and the electrical ground, the output capacitor 126 providing a DC output voltage to an output interface such as an output connector 128. In some embodiments, the capacitance of the filter capacitor 124 is between about 500 μF and 1000 μF, such as about 680 μF. Typically, as in the embodiment shown, the output connector 128 is also connected to the secondary side controller 104 via a plurality of communication channels 130 to support various charging protocols. Suitable output connectors 128 may include connectors that are compatible with and support the following standard and proprietary charging protocols, including Universal Serial Bus Power Delivery USB PD2.0 and USB PD3 ​​with Programmable Power Supply (PPS), Quick Charge, AFC and Charging Protocol. For example, output connector 128 may include a Universal Serial Bus C (USB-C) compatible connector, wherein power converter 100 complies with the USB protocol to provide a DC output voltage of about 3.3 VDC to about 21.5 VDC (or higher in the case of an extended power range (EPR)) at a current of up to substantially 5 amperes (A).

[0021] In some embodiments, the power converter 100 includes a synchronous rectifier (SR) field effect transistor 132 (SRFET) on the secondary side 110, which is connected between the flyback transformer 106 and the current sensing resistor 134 (RSENSE) and is connected to the negative terminal of the DC output through the current sensing resistor 134 (RSENSE). The SRFET 132 includes a drain node 132A, a gate node 132B, and a source node 132C. The drain node 132A is connected to the fourth terminal of the flyback transformer 106 and is connected to the SR sense pin (SR_SEN) of the secondary side controller 104 through a resistor 136 to sense the voltage on the drain node 132A of the SRFET 132; the gate node 132B is connected to the SR gate drive pin (SR_DRV) of the secondary side controller 104 to drive or control the SRFET 132; and the source node 132C is connected to the negative DC output and connected to the secondary side controller 104 through the SR-Vss ground voltage level pin (SR-Vss). The first node of the RSENSE resistor 134 is connected to the current sense negative pin (CSN) of the secondary side controller 104, and the second node is connected to the negative terminal of the DC output and the current sense positive pin (CSP) so that the secondary side controller 104 can sense the output current I from the power converter 100. OUT In some implementations, the resistance of RSENSE resistor 134 is between about 3 Mohm and 10 Mohm, such as 5 Mohm.

[0022] Optionally, as in the illustrated embodiment, the secondary side 110 includes an additional or secondary provider switch (PS) 148, such as an NFET, connected between the flyback transformer 106 and the positive terminal of the DC output to enable the secondary side controller 104 to shut down the DC output to prevent overvoltage and / or undervoltage conditions. The PS switch 148 includes a voltage_bus_in pin (V BUS_IN ) source node 148A, connected to the voltage bus control pin (V BUS_CTRL ) to drive or control the gate node 148B of the PS switch 148 and the voltage bus output pin (V BUS_OUT ) and a drain node 148C connected to the positive terminal of the DC output.

[0023] The flyback transformer 106 in the power converter 100 provides an isolation circuit or barrier to electrically isolate the secondary side 110 from the high AC input voltage present on the primary side 108. Figure 1A to Figure 1B In an example embodiment of the present invention, the isolation barrier further includes an auxiliary winding of the flyback transformer 106, which is used as a flyback buck transformer 106A to provide power to the primary side controller 102. The flyback buck transformer 106A is coupled to the boost pin (BSW) of the primary side controller 102 through the rectifier 155 and to the VCC pin of the primary side controller 102 through the rectifier 156. The boost ground pin (BGND) of the primary side controller 102 is grounded. The boost unit 159 in the primary side controller 102 is used as a boost circuit to provide VCC to the primary side controller 102. The resistor divider 158 connected to the overvoltage protection (OVP_AUX) pin of the primary side controller 102 is used to sense V on the secondary side 110 via the flyback buck transformer 106A. BUS_IN (ie, the reflected voltage of the secondary side input voltage). If an overvoltage condition is detected, the OVP unit 171 in the primary side controller 102 disables the power switch 117.

[0024] In addition, as in Figure 1A to Figure 1B In an example embodiment of the invention, the power converter 100 uses a pulse width modulation (PWM) signal provided from a PWM drive pin on the secondary side controller 104 to the primary side controller 102, and the isolation barrier may also include a pulse transformer 174 connected between the PWM drive pin and the PULSEIN pin and the soft start (SS) pin of the primary side controller 102. The SS pin may be grounded through a capacitor 180. The secondary side controller 104 controls the width of the PWM signal based on the power required on the DC output, which turns on the power switch 117 to start the switching cycle, thereby optimizing or increasing the efficiency of the power converter 100. The pulse detector 181 in the primary side controller 102 detects the signal transmitted by the secondary side controller 104 through the pulse transformer 174.

[0025] In some embodiments, the primary side controller 102 includes a high voltage startup unit 182 and an X-cap discharge unit 183. The high voltage startup unit 182 monitors the voltage on the X-cap 111. The X-cap discharge unit 183 generates an AC INThe X-cap 111 is discharged when the signal is removed (for example, by unplugging the power converter 100). In some embodiments, the X-cap 111 is omitted. The power-on reset (POR) and undervoltage lockout unit (OLU) 184 provide reset and undervoltage protection functions. The low dropout regulator 185 generates the internal voltage for the primary side controller 102. The control unit 186 receives signals from the boost unit 159, the CS unit 120, the OVP unit 171 and the pulse detector 181. The bias generator and oscillator 187 provides a clock signal to the control unit 186, which is used to create a PWM signal for controlling the power switch 117 and the ACF gate driver 121D.

[0026] In some embodiments, the power converter 100 is configured for DCM operation. In DCM, during each switching cycle, the secondary winding (N S ) decreases to zero before the primary side 108 is turned on. When the primary side is turned on, the magnetic flux established in the transformer core causes current to flow through the secondary winding (N) of the flyback transformer 106 once the primary side power switch 117 is turned off. S When the current flowing through the secondary winding of the flyback transformer 106 (N S ) decreases to zero, the secondary side controller 104 (eg, via the pulse transformer 174) sends a signal to the primary side controller 102 to start a new switching cycle.

[0027] Figure 2is a block diagram of the secondary side controller 104 according to some embodiments. The secondary side controller 104 also typically includes an SR sensing unit 202 and an SR gate driver 204, which is coupled to the gate node of the SRFET 132 through the SR_GDRV pin. The SR sensing unit 202 is coupled to the drain node of the SRFET 132 through the SR-SNS pin and to the source node of the SRFET 132 through the SR-Vss pin. The SR sensing unit 202 typically includes a zero crossing detector (ZCD) block, a negative sense (NSN) block, a peak detector (PKD) block, and a line feed forward (LFF) block for sensing the voltage on the drain of the SRFET 132 to sense or detect zero crossing, negative voltage, peak (positive) voltage, and feed forward operation. One or more outputs of the SR sensing unit 202 are coupled to the SR gate driver 204 to control the SRFET 132, and are coupled to the pulse width modulation (PWM) circuit 206 to provide a signal to the primary side controller 102 through the PWM drive pin PWM_DRV to control the power switch 117. The PWM circuit 206 includes: a ramp generator and a pulse width modulator (PWM) for generating a signal with a modulated pulse width, a PWM driver for boosting the voltage of the signal to a voltage required to drive the primary side controller 102 or the power switch 117, and an ACF for controlling the PWM driver during active clamp flyback operation.

[0028] The secondary side controller 104 also includes a secondary side provider FET (SSPF) circuit 208. The SSPF circuit 208 includes a provider FET switch (PS) gate driver for driving the PS switch 148 to detect V BUS_IN and V BUS_OUT OV-UV circuit or block for overvoltage (OV) and undervoltage (UV) conditions on the BUS_IN and V BUS_OUT A discharge circuit or block for discharging the CC pin during power delivery mode and a VCONN block for reusing the CC pin to power the electronics in the USB Type-C cable during low power mode and a VCONN block for BUS_IN Adjusts the hysteresis level within the hysteresis comparator (HYS C) block.

[0029] The interface circuit 210 includes circuits or blocks for communicating with a device powered or charged by the secondary side controller 104 to support various charging protocols. These circuits or blocks may include: a bi-phase mark code (BMC) and physical layer (PHY) for communicating with a device using certain charging protocols; a charger detection block; and a deep sleep reference block for providing a minimum output voltage reference and current during low power mode operation.

[0030] The secondary side controller 104 includes a microcontroller unit (MCU) subsystem 212, which includes: logic and a microprocessor or controller for executing programs stored in a memory in the MCU subsystem; an analog-to-digital converter (ADC); a multi-purpose timer counter pulse width modulator (TCPWM) that is capable of performing a variety of functions required for MCU operation; and a plurality of general purpose input / outputs (GPIOs), only one of which is shown. The secondary side controller 104 includes a feedback circuit 214 that is coupled to a feedback pin to provide error correction to the PWM circuit 206, and in certain embodiments of the isolation barrier, to provide a feedback signal to the primary side controller 102. In some embodiments, the feedback circuit 214 includes a constant voltage (CV) reference, a constant current (CC) reference, one or more error amplifiers and current DACs (digital-to-analog converters) (IDACs), a low-side current sense amplifier (LSCSA), and a short circuit protection (SCP) block.

[0031] FIG. 3A to FIG. 3C FIG. 1 is a flow chart of a method 300 for power mode control according to some embodiments. Figure 3A At 304, for example, when the power converter 100 is coupled to an external power source to receive AC IN , AC power is enabled for the power converter 100. At 306, the power converter 100 is in active mode. In active mode, power is transmitted to the load device connected to the output connector 128. The secondary side controller 104 generates a PWM signal for the primary side controller 102 to control the power converter 100 to transmit power according to the voltage and current specified by the protocol determined for the load device. At 308, the secondary side controller 104 detects that there is no load device on the output connector 128. For example, a previously connected load device may be disconnected from the output connector 128. In response to the no load condition at 308, the secondary side controller 104 stops sending the PWM signal at 310 because output power is not required. At 312, the secondary side controller 104 sends a low power mode signal to the primary side controller 102 via the pulse transformer 174. At transition A, the method 300 Figure 3B Continue.

[0032] Reference Figure 3B, the method 300 enters from transition A. At 314, the primary side controller 102 enters a low power mode. In the low power mode, the ACF circuit 121, the HS driver 123, and the OVP unit 171 are turned off (specified by the dot-dash pattern). The pulse detector 181 and the X-cap discharge unit 183 operate in a low current mode (specified by the long dash-short dash pattern). In the active mode, the control block 186 pulls down the gate of the enable transistor 121E (p-type) to provide VCC to the ACF gate driver 121D. In the low power mode, the control block 186 disables the pull-down on the node 121V, which results in disabling the transistor 121E via the resistor between VCC and the node 121V. Providing VCC on the gate of the enable transistor 121E maintains the off state of the ACF gate driver 121D. The filter 121F connected between the gate and the drain of the ACF switch 121S maintains the off state of the ACF switch 121S. In some implementations, in the low power mode of the primary side controller 102 , the current consumption is less than about 30 μA.

[0033] At 316, the secondary side controller 104 enters a low power mode. In the low power mode, the secondary side controller 104 turns off the SR sensing unit 202, the PWM and ramp generator in the PWM circuit 206, the PS gate driver in the SSPF circuit 208, the OV-UV unit, the VBUS_IN discharge unit and the VBUS_OUT discharge unit and the VCONN unit, the charger detection unit in the interface circuit 210, the MCU subsystem 212, and the feedback circuit 214 (designated by a dot-dash pattern). The SR gate driver 204, the PWM driver in the PWM circuit 206, the LDO and HV regulators in the SSPF circuit 208, the deep sleep reference and BMC PHY in the interface circuit 210, and the wake-up timer 212W operate in a low current mode (designated by a long dash-short dash pattern). In some embodiments, in the low power mode of the secondary side controller 104, the current consumption is less than about 170 μA.

[0034] At 318, the power converter 100 is in the low power mode. In some implementations, the power converter 100 consumes less than about 5 mW, such as less than 3 mW, in the low power mode.

[0035] In some embodiments, the secondary side controller 104 uses a periodic timer (such as the wake-up timer 212W in the MCU subsystem 212) to trigger a wake-up interrupt. The primary side controller 102 implements functions such as load detection or output voltage maintenance during the wake-up interrupt. In some embodiments, the primary side controller 102 implements input voltage monitoring during the wake-up interrupt to IN The X-cap 111 is allowed to discharge when the signal is removed.

[0036] At 320, the output connector 128 is monitored for connection to a load device. If a load is detected at 320, the method 300 transitions back to C. Figure 3A At 322, the secondary side controller 104 enters the active mode and sends an active mode signal to the primary side controller 102. The power converter 100 resumes active mode operation at 306. If no load is detected at 320, the secondary side controller 104 monitors the input voltage V BUS_IN The secondary side controller 104 may monitor V in response to a wake-up interrupt. BUS_IN Voltage.

[0037] During low power mode, the HYS comparator block with the reference from the Deep Sleep Reference block is used to pull V BUS_IN The voltage is maintained at a predetermined voltage V1, such as approximately 4V. If at 324 V BUS_IN If the voltage is not less than V1 during the wake-up interrupt, then at 318, the power converter 100 remains in the low power mode. If at 324 V BUS_IN The voltage is less than V1 during the wake-up interrupt, then at 326, the secondary side controller 104 enters the wake-up mode and sends a wake-up signal to the primary side controller 102. In some implementations, V1 is defined using a deep sleep reference unit in the interface circuit 210.

[0038] In wake-up mode, the method changes to Figure 3C At 328, the primary side controller 102 wakes up and powers up the control unit 186, the boost unit 159, the LS gate driver 119, the current sensing unit 120, and the bias generator and oscillator 187 (designated by the dash-dot-dot-dash pattern). The control unit 186, the boost unit 159, the LS gate driver 119, the current sensing unit 120, and the bias generator and oscillator 187 are otherwise powered down during the low power mode. At 330, the secondary side controller 104 sends PWM pulses to the primary side controller 102 via the pulse transformer 174 to power the VBUS output and thereby increase the output voltage.

[0039] At 332, the primary side controller 102 determines whether a load device is connected to the output connector 128. If a load device is detected at 332, the method 300 transitions to C. Figure 3A , and the secondary side controller 104 enters the active mode and sends an active mode signal to the primary side controller 102. The power converter 100 resumes active mode operation at 306.

[0040] If no load device is detected at 332 , the secondary side controller 104 determines VBUS_IN The voltage is greater than V2, such as about 4.1 V. In some embodiments, V2 is defined using a deep sleep reference unit in the interface circuit 210. If V BUS_IN If the voltage is greater than V2, method 300 transitions to Figure 3A , wherein the secondary side controller 104 stops sending PWM signals at 310 and sends a low power mode signal to the primary side controller 102 at 312. If the output voltage is not greater than V2 at 334, the secondary side controller 104 determines whether a power-on reset condition (POR) is triggered. If the POR is triggered at 336, the method 300 terminates at 338. If the POR is not triggered at 336, the secondary side controller 104 continues to send PWM pulses at 330 to increase the output voltage.

[0041] Figure 4 4 is a timing diagram 400 illustrating power mode control according to some embodiments. In some embodiments, the secondary side controller 104 communicates with the primary side controller 102 using a PWM driver in the PWM circuit 206. The PWM output signal is transmitted to the primary side controller 102 through the pulse transformer 174. The pulse detector 181 in the primary side controller 102 detects the PWM output signal. During the active mode, the secondary side controller 104 sends a signal indicating the switching interval of the primary side controller 102 to provide power to the output connector 128. In some embodiments, the secondary side controller 104 also uses the PWM signal to signal the power mode to the primary side controller 102.

[0042] During active mode, the pulse detector 181 uses a differential configuration that compares the PWM output signal to a high threshold VSENSE_P and a low threshold VSENSE_N. If the PWM output signal exceeds VSENSE_P, the pulse detector 181 detects a positive pulse, and if the PWM output signal is below VSENSE_N, the pulse detector 181 detects a negative pulse. The differential configuration requires two sets of comparators and a reference generator. In low power mode and wake-up mode, the pulse detector 181 implements a single-ended configuration where only negative pulses are used for communication. In some embodiments, the pulse detector 181 uses a ground reference instead of VSENSE_N to detect negative pulses, allowing the use of a single comparator without a separate reference generator, which reduces the power consumption of the pulse detector 181.

[0043] In active mode, the secondary side controller 104 sends pulses to alternate between an active high side (ACF circuit 121 active and power switch 117 inactive) and an active low side interval (ACF circuit 121 inactive and power switch 117 active). In some embodiments, the primary side controller 102 generates a low power mode signal by sending three consecutive negative pulses at 402. Since the primary side controller 102 is in active mode, the pulse detector 181 can use a differential configuration. In some embodiments, the transition between active mode and low power mode takes about 30 μs (T1). At 404, the secondary side controller 104 sends a wake-up signal, such as a single negative pulse below the ground reference, and the primary side controller 102 wakes up. In some embodiments, the wake-up timer 212W generates a wake-up signal after about 200ms (T2). In some embodiments, the secondary side controller 104 sends PWM pulses during the wake-up interval to maintain the output voltage. After the output voltage is maintained, the secondary side controller 104 sends a low power mode signal at 406, and the cycle repeats.

[0044] Figure 5 is a timing diagram 500 illustrating X-cap discharge control according to some embodiments. X-cap discharge control is implemented to discharge the X-cap 111 so that the voltage present on the X-cap 111 will not shock the user in the event that the power converter 100 is unplugged from the external power source. The X-cap voltage (HV) is compared to an under-voltage threshold. During the low power mode, the high voltage startup unit 182 remains active to detect an under-voltage (UV) condition. In some embodiments, the high voltage startup unit 182 is configured to signal a UV continuation signal if the UV condition persists for N checks, such as 3 checks. Referring to Figure 5 , the high voltage startup unit 182 detects the UV condition at 502, 504, 506 and asserts the UV persistence signal at 508. In some embodiments, the X-cap discharge unit 183 operates in a low current mode during the low power mode and only checks for line UV faults once during the wake-up cycle, such as at 510. If the UV persistence signal is present, the X-cap discharge unit 183 turns off the X-cap discharge. At 512, when the AC input plug is disconnected and 3 checks of line UV do not occur at wake-up 512, the X-cap discharge unit 183 determines that the UV persistence signal is not present and enables X-cap discharge.

[0045] Example embodiments may include a computer-readable medium (e.g., such as firmware, flash memory, etc.) storing instructions that are executed by a device (e.g., such as Figure 1A , Figure 1B and Figure 2The secondary side controller 104 in the embodiment is configured to execute FIG. 3A to FIG. 3C At least a portion of the method described in . For example, one or more embodiments may include a non-transitory computer-readable medium storing a set of processor-executable instructions that, when executed by a semiconductor device controller that includes at least a processor (e.g., a CPU or another core processor) and a memory, are configured to facilitate operation according to the techniques described herein. In some embodiments, the processor-executable instructions, when executed, are configured to facilitate execution of a method, such as at least some of the aforementioned methods. In some embodiments, the processor-executable instructions, when executed, are configured to facilitate implementation of a system, such as at least some of one or more of the aforementioned systems. A person of ordinary skill in the art can design many such computer-readable media that are configured to operate according to the techniques presented herein.

[0046] Figure 6 6 is a block diagram illustrating a system 600 for a USB device according to some embodiments. The system 600 may include a peripheral subsystem 602 including multiple components for USB power transmission (USB-PD). The peripheral subsystem 602 may include a peripheral interconnect 604 including a peripheral clock module (PCLK) 606 for providing clock signals to various components of the peripheral subsystem 602. The peripheral interconnect 604 may be a peripheral bus, such as a single-stage or multi-stage advanced high-performance bus (AHB), and may provide a data and control interface between the peripheral subsystem 602, the CPU subsystem 608, and the system resources 610. The peripheral interconnect 604 may include a controller circuit system such as a direct memory access (DMA) controller, which may be programmed to transfer data between peripheral blocks without input from the CPU subsystem 608, without control of the CPU subsystem 608, or without imposing the same transfer.

[0047] Peripheral interconnect 604 may be used to couple peripheral subsystem 602 components to other components of system 600. A plurality of general purpose input / outputs (GPIOs) 612 may be coupled to peripheral interconnect 604 for sending and receiving signals. GPIO 612 may include circuitry configured to implement various functions such as pull-ups, pull-downs, input threshold selection, input and output buffer enable / disable, single multiplexing, and the like. Other functions may also be implemented by GPIO 612. One or more timer / counter / pulse width modulators (TCPWMs) 614 may also be coupled to peripheral interconnect and may include circuitry implementing timing circuits (timers), counters, pulse width modulators (PWMs), decoders, and other digital functions associated with I / O signal operation and may provide digital signals to system components of system 600. The peripheral subsystem 602 may also include one or more serial communication blocks (SCBs) 616 for implementing serial communication interfaces, such as I2C, serial peripheral interface (SPI), universal asynchronous receiver / transmitter (UART), controller area network (CAN), CXPI (clock extension peripheral interface), etc.

[0048] For USB power delivery applications, peripheral subsystem 602 may include USB power delivery subsystem 618 coupled to peripheral interconnect 604, and USB power delivery subsystem 618 includes a set of USB PD modules 620 for USB power delivery. USB PD modules 620 may be coupled to peripheral interconnect 604 via USB-PD interconnect 622. The USB PD module 620 may include: an analog-to-digital converter (ADC) module for converting various analog signals into digital signals; an error amplifier (AMP) for regulating the output voltage on the VBUS line through the PD protocol; a high voltage (HV) regulator for converting the power supply voltage into a precise voltage (such as 3.5V to 5V) to power the system 600; a low-side current sensing amplifier (LSCSA) for accurately measuring the load current; an overvoltage protection (OVP) module and an overcurrent protection (OCP) module for providing overcurrent and overvoltage protection on the VBUS line with configurable thresholds and response times; one or more gate drivers for external power field effect transistors (FETs) for USB power transmission in provider and consumer configurations; and a communication channel PHY (CC-BB-PHY) module for supporting communication on the Type-C communication channel (CC) line. The USB PD module 620 may also include a charger detection module to determine whether the charging circuit system is present and coupled to the system 600, and a VBUS discharge module to control the voltage discharge on the VBUS. The VBUS discharge module can be configured to couple to a power node on the VBUS line or an output (power dissipater) node on the VBUS line and regulate the voltage on the VBUS line to a desired voltage level (i.e., a voltage level specified in the voltage level negotiated by the PD protocol). The USB power delivery subsystem 618 may also include an electrostatic discharge (ESD) suppression circuit system 626 that may be required on a pad 624 and a Type-C port for external connections. The USB PD module 620 may also include a communication module for retrieving and transmitting information (such as control signals) such as from the secondary side controller 104 to the primary side controller 102.

[0049] The GPIO 612, TCPWM 614, and SCB 616 may be coupled to an input / output (I / O) subsystem 628, which may include a high-speed (HS) I / O matrix 630 connected to a plurality of GPIOs 632. The GPIO 612, TCPWM 614, and SCB 616 may be coupled to the GPIO 632 via the HS-I / O matrix 630.

[0050] The central processing unit (CPU) subsystem 608 is used to process instructions, store program information and data. The CPU subsystem 608 may include one or more processing units 634 for executing instructions and reading and writing memory locations from multiple memories. The processing unit 634 may be a processor suitable for operating in an integrated circuit (IC) or a system on chip (SOC) device. In some embodiments, the processing unit 634 may be optimized for low-power operation using a large number of clock gating. In this embodiment, different internal control circuits may be implemented for the operation of the processing unit in different power states. For example, the processing unit 634 may include a single-wire debug (SWD) module, a terminal count (TC) module, a wake-up interrupt controller (WIC) configured to wake up the processing unit from a sleep state (which can turn off the power when the IC or SOC is in a sleep state), a fast multiplier, a nested vector interrupt controller (NVIC) and an interrupt multiplexer (IRQMUX). The CPU subsystem 608 may include one or more memories, including a flash memory 636, a static random access memory (SRAM) 638 and a read-only memory (ROM) 640. Flash memory 636 may be a non-volatile memory (NAND flash memory, NOR flash memory, etc.) configured to store data, programs, and / or other firmware instructions. Flash memory 636 may include a system performance controller interface (SPCIF) register and a read accelerator, and improves access times by being integrated into the CPU subsystem 608. SRAM 638 may be a volatile memory configured to store data and firmware instructions accessible by the processing unit 634. ROM 640 may be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during operation of the system 600. SRAM 638 and ROM 640 may have associated control circuitry. Processing unit 634 and memory modules 636, 638, 640 may be coupled to a system interconnect 642 to route signals to various components of the CPU subsystem 608 and to route signals from various components of the CPU subsystem 608 to other blocks or modules of the system 600. System interconnect 642 may be implemented as a system bus, such as a single-stage or multi-stage AHB. System interconnect 642 may be configured as an interface to couple together various components of CPU subsystem 608. System interconnect 642 may be coupled to peripheral interconnect 604 to provide a signal path between CPU subsystem 608 and components of peripheral subsystem 602.

[0051] System resources 610 may include a power module 644, a clock module 646, a reset module 648, and a test module 650. The power module 644 may include a sleep control module, a wake-up interrupt control (WIC) module, a power-on reset (POR) module, multiple voltage references (REF), and a PWRSYS module. In some embodiments, the power module 644 may include a circuit system that enables the system 600 to draw power from an external source and / or provide power to an external source at different voltage levels and / or current levels, and control operations in different power states such as active, low power, or sleep. In various embodiments, more power states may be achieved as the system 600 throttles to achieve desired power consumption or power output. For example, the secondary side controller 104 may access secondary electrical parameters on the secondary side. The clock module 646 may include a clock control module, a watchdog timer (WDT), an internal low speed oscillator (ILO), and an internal main oscillator (IMO). The reset module 648 may include a reset control module and an external reset module (XRES module). The test module 650 may include a module for controlling and entering a test mode, and a test control module for analog functions and digital functions (digital test and analog DFT).

[0052] System 600 can be implemented in a monolithic (e.g., single) semiconductor die. In other embodiments, different portions or modules of system 600 can be implemented on different semiconductor dies. For example, memory modules 636, 638, 640 of CPU subsystem 608 can be on-chip or off-chip. In other embodiments, circuit systems with separate dies can be packaged in a single "chip", or remain separate and arranged as separate components on a circuit board (or in a USB cable connector).

[0053] System 600 can be implemented in multiple application environments to provide USB PD functionality. In any application environment, an electronic device (e.g., a USB-enabled device) can have an IC controller or SOC implementation implemented by system 600, which is arranged and configured to perform operations according to the techniques described herein. In one embodiment, system 600 can be arranged and configured in a personal computer (PC) power adapter for a laptop computer, a notebook computer, etc. In another embodiment, system 600 can be housed in a power adapter (e.g., a wall charger) for a mobile electronic device (e.g., a smartphone, a tablet computer, etc.). In another embodiment, system 600 can be set and configured in a wall socket, which is configured to provide power via a USB type A port and / or a USB type C port. In another embodiment, system 600 can be arranged and configured in a car charger, which is configured to provide power via a USB type A port and / or a USB type C port. In yet another embodiment, the system 600 can be arranged and configured in a power pack that can be charged via a USB Type A port and / or a USB Type C port and then power another electronic device. In other embodiments, a system such as the system 600 can be configured with the power switch gate control circuitry described herein and can be incorporated into various other USB-enabled electronic devices or electromechanical devices.

[0054] It should be understood that a system implemented on or as an IC controller (such as system 600) can be placed in a variety of applications that vary depending on the type of power source used and the direction of power supply. For example, in the case of a car charger, the power source is an on-board battery that provides DC power, while in the case of a mobile power adapter, the power source is an AC wall outlet. In addition, in the case of a PC power adapter, the flow of power input is from the provider device to the consumer device, while in the case of a power pack, the flow of power input can be in either direction, depending on whether the power pack is operating as a power provider (e.g., powering another device) or as a power consumer (e.g., allowing itself to be charged). For these reasons, the various applications of system 600 should be viewed in an illustrative rather than a restrictive sense.

[0055] Providing a low power mode for the power converter by powering down various components of the primary side controller 102 and the secondary side controller 104 results in an average power consumption of less than 5 mW or even less than 3 mW. The periodic wake-up interval enables maintaining the output voltage and implementing protection functions such as X-cap discharge.

[0056] In an embodiment of the technology presented herein, a universal serial bus power delivery (USB-PD) system includes: a transformer including a primary side and a secondary side, the primary side being coupled to receive a rectified alternating current (AC) input voltage at an input port, and the secondary side being connected to provide a direct current (DC) output voltage at an output port; a first power switch connected to the primary side; a primary side controller coupled to the first power switch to control operation of the transformer, wherein the primary side controller is configured to: transition from a primary side active mode to a primary side low power mode in response to receiving a low power mode signal, and transition from the primary side low power mode to a primary side active mode in response to receiving an active mode signal; and a secondary side controller coupled to the output port, wherein the secondary side controller is configured to: send a low power mode signal to the primary side controller and transition from the secondary side active mode to the secondary side low power mode in response to detecting that a load device is not present on the output port; and transition from the secondary side low power mode to the secondary side active mode in response to detecting connection of a load device to the output port, and send an active mode signal to the primary side controller.

[0057] In an embodiment of the technology presented herein, the primary side controller includes a detector communicatively coupled to the secondary side controller, the detector being configured in a differential configuration to detect a low power mode signal in the primary side active mode, and the detector being configured in a single-ended configuration to detect an active mode signal in the primary side low power mode.

[0058] In an implementation of the techniques presented herein, the detector uses a positive reference signal and a negative reference signal in a differential configuration to detect a low power mode signal, and the detector uses a ground reference signal in a single ended configuration to detect an active mode signal.

[0059] In an implementation of the technology presented herein, a USB-PD system includes a pulse transformer coupled between a secondary side controller and a detector of a primary side controller.

[0060] In an embodiment of the technology presented herein, a USB-PD system includes a second power switch connected between an input port and a primary side, and a gate driver connected between the second power switch and a primary side controller, wherein the primary side controller is configured to power off the gate driver in a primary side low power mode.

[0061] In an embodiment of the technology presented herein, a USB-PD system includes a pull-up transistor connected between a power voltage source and a power terminal of a gate driver, wherein a primary side controller includes a pull-down transistor connected between a gate terminal of the pull-up transistor and a reference voltage source, the primary side controller is configured to assert an enable signal at the gate terminal of the pull-down transistor in a primary side active mode, and the primary side controller is configured to remove the enable signal in a primary side low power mode.

[0062] In an implementation of the technology presented herein, a USB-PD system includes a filter connected between a gate terminal of a second power switch and a source terminal of the second power switch.

[0063] In an embodiment of the technology presented in this article, the secondary side controller is configured to: transition to a secondary side wake-up mode; in the secondary side wake-up mode, in response to the voltage on the output port being less than a first threshold, send a wake-up signal to the primary side controller and send a drive signal to the primary side controller; and in response to the voltage on the output port being greater than a second threshold, send a low power mode signal to the primary side controller and return to the secondary side low power mode, and the primary side controller is configured to: in response to receiving the wake-up signal, transition to the primary side wake-up mode and control the first power switch based on the drive signal; and return to the primary side low power mode in response to receiving the low power mode signal.

[0064] In an embodiment of the technology presented herein, a USB-PD system includes a cross-line capacitor (X-cap) coupled between an input port and a primary side, wherein a secondary side controller is configured to: periodically transition from a secondary side low power mode to a secondary side wake-up mode; and for each transition, send a wake-up signal to the primary side controller in the secondary side wake-up mode, and the primary side controller is configured to: transition to the primary side wake-up mode in response to receiving the wake-up signal; detect a low voltage condition at the input port in the primary side wake-up mode; and discharge the X-cap in response to detecting a predetermined number of low voltage conditions.

[0065] In an embodiment of the technology presented herein, a method of operating a universal serial bus power delivery (USB-PD) power converter includes: in response to detecting that no load device is present on an output port of the USB-PD power converter, sending a low power mode signal from a secondary side controller coupled to control the secondary side of the USB-PD power converter to a primary side controller coupled to control the primary side of the USB-PD power converter, and transitioning the secondary side controller from a secondary side active mode to a secondary side low power mode; in response to receiving the low power mode signal, transitioning the primary side controller from the primary side active mode to the primary side low power mode; in response to detecting connection of a load device to the output port, sending an active mode signal from the secondary side controller to the primary side controller, and transitioning the secondary side controller from the secondary side low power mode to the secondary side active mode; and in response to receiving the active mode signal, transitioning the primary side controller from the primary side low power mode to the primary side active mode.

[0066] In an embodiment of the technology presented herein, the method includes configuring a detector in a primary side controller in a differential configuration to detect a low power mode signal in a primary side active mode, and configuring the detector in a single-ended configuration to detect an active mode signal in a primary side low power mode.

[0067] In embodiments of the techniques presented herein, detecting a low power mode signal includes detecting the low power mode signal using a positive reference signal and a negative reference signal in a differential configuration, and detecting an active mode signal includes detecting the active mode signal using a ground reference signal in a single-ended configuration.

[0068] In an implementation of the technology presented herein, the method includes transmitting an active mode signal and a low power mode signal using a pulse transformer coupled between a secondary side controller and a detector of a primary side controller.

[0069] In an implementation of the technology presented herein, the method includes controlling an active clamp flyback (ACF) circuit coupled to the primary side using a gate driver coupled to a primary side controller in a primary side active mode, and powering off the gate driver in a primary side low power mode.

[0070] In an embodiment of the technology presented herein, the method includes: in a primary side active mode, asserting an enable signal at a gate terminal of a pull-down transistor connected between a gate terminal of the pull-up transistor and a reference voltage source, wherein the pull-up transistor is connected between a power voltage source and a power terminal of a gate driver; and removing the enable signal in a primary side low power mode.

[0071] In an implementation of the technology presented herein, the method includes maintaining an off state of the ACF circuit in a primary-side low power mode.

[0072] In an embodiment of the technology presented in this article, the method includes: transitioning the secondary side controller to a secondary side wake-up mode; in the secondary side wake-up mode, in response to a voltage on an output port being less than a first threshold, sending a wake-up signal to the primary side controller and sending a drive signal to the primary side controller; in response to receiving the wake-up signal, transitioning the primary side controller to the primary side wake-up mode; in the primary side wake-up mode, the primary side controller controls the operation of the transformer of the USB-PD power converter based on the drive signal; in response to the voltage on the output port being greater than a second threshold, sending a low power mode signal to the primary side controller and returning the secondary side controller to the secondary side low power mode; and in response to receiving the low power mode signal, returning the primary side controller to the primary side low power mode.

[0073] In an embodiment of the technology presented in this article, the method includes: periodically transitioning from a secondary side low power mode to a secondary side wake-up mode; for each transition to the secondary side wake-up mode, sending a wake-up signal to a primary side controller in the secondary side wake-up mode; in response to receiving the wake-up signal, transitioning the primary side controller to the primary side wake-up mode; in the primary side wake-up mode, detecting a low voltage condition at an input port of a USB-PD power converter; and in response to detecting a predetermined number of low voltage conditions, discharging a cross-line capacitor (X-cap) coupled between the input port and the primary side of the transformer.

[0074] In an embodiment of the technology presented herein, a universal serial bus power transmission (USB-PD) system includes: a transformer including a primary side and a secondary side, the primary side being coupled to receive a rectified alternating current (AC) input voltage at an input port, the secondary side being connected to provide a direct current (DC) output voltage at an output port; a first power switch connected between the input port and the primary side; a second power switch connected between the output port and the secondary side; a primary side controller coupled to the first power switch; and a secondary side controller coupled to the second power switch, wherein the secondary side controller is configured to: in response to detecting that no load device is present on the output port, send a low power mode signal to the primary side controller and transition from a secondary side active mode to a secondary side low power mode, the primary side controller is configured to transition from the primary side active mode to the primary side low power mode in response to receiving the low power mode signal, and wherein the power consumption of the transformer, the primary side controller in the primary side low power mode, and the secondary side controller in the secondary side low power mode is less than 5 mW.

[0075] In an embodiment of the technology presented in this article, the secondary side controller is configured to: in response to detecting the connection of a load device to the output port, transition from the secondary side low power mode to the secondary side active mode, and send an active mode signal to the primary side controller, and the primary side controller is configured to transition from the primary side low power mode to the primary side active mode in response to receiving the active mode signal.

[0076] Various operations of the embodiments are provided herein. In one embodiment, one or more of the operations described may constitute computer-readable instructions stored on one or more computer-readable media, which, if executed by a computing device, will cause the computing device to perform the described operations. The order of describing some or all of the operations in the operation should not be interpreted as implying that these operations are necessarily sequence-dependent. Those skilled in the art who benefit from this specification will understand the alternative order. In addition, it should be understood that not all operations must be present in each embodiment provided herein. In addition, it should be understood that not all operations are required in some embodiments.

[0077] Furthermore, unless otherwise stated, "first," "second," etc. are not intended to imply a temporal aspect, a spatial aspect, a sequence, etc. Instead, these terms are merely used as identifiers, names, etc. of features, elements, items, etc. For example, a first object and a second object generally correspond to object A and object B or two different or two identical objects or the same object.

[0078] In addition, "exemplary" etc. are used in this article to represent that it is used as an example, instance, explanation, etc., and it is not necessarily advantageous. As used in this article, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, "a" and "an" used in this application can generally be interpreted as referring to "one or more", unless otherwise specified or clear for the singular form according to the context. In addition, at least one of A and B and / or the like usually means A or B and / or both A and B. In addition, to the extent that "including", "having", "has", "with" and / or its variants are used in the specific embodiments or claims, such terms are intended to be inclusive in a manner similar to the term "including".

[0079] In addition, although the present disclosure has been shown and described with respect to one or more implementations, those skilled in the art will think of equivalent changes and modifications based on reading and understanding of this specification and the accompanying drawings. The present disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such components are intended to correspond to any component that performs the specified function (e.g., functionally equivalent) of the described components, even if it is not structurally equivalent to the disclosed structure. In addition, although the specific features of the present disclosure may be disclosed only for one implementation in several implementations, such features can be combined with one or more other features of other implementations as can be expected and advantageous for any given or specific application.

Claims

1. A universal serial bus power transmission USB-PD system, comprising: a transformer including a primary side coupled to receive a rectified alternating current (AC) input voltage at an input port and a secondary side connected to provide a direct current (DC) output voltage at an output port; a first power switch connected to the primary side; a primary side controller coupled to the first power switch to control the operation of the transformer, wherein the primary side controller is configured to: transitioning from the primary side active mode to the primary side low power mode in response to receiving the low power mode signal; and transitioning from the primary side low power mode to the primary side active mode in response to receiving an active mode signal; and a secondary-side controller coupled to the output port, wherein the secondary-side controller is configured to: In response to detecting that no load device is present at the output port, sending the low power mode signal to the primary side controller and transitioning from a secondary side active mode to a secondary side low power mode; and In response to detecting connection of the load device to the output port, transitioning from the secondary side low power mode to the secondary side active mode and sending the active mode signal to the primary side controller.

2. The USB-PD system according to claim 1, wherein: The primary side controller includes a detector communicatively coupled to the secondary side controller; the detector being configured in a differential configuration in the primary side active mode to detect the low power mode signal; as well as The detector is configured in a single-ended configuration in the primary-side low power mode to detect the active mode signal.

3. The USB-PD system according to claim 2, wherein: the detector detecting the low power mode signal using a positive reference signal and a negative reference signal in the differential configuration; and The detector detects the active mode signal using a ground reference signal in the single-ended configuration.

4. The USB-PD system according to claim 2, comprising: A pulse transformer is coupled between the secondary side controller and the detector of the primary side controller.

5. The USB-PD system according to claim 1, comprising: a second power switch connected between the input port and the primary side; as well as a gate driver connected between the second power switch and the primary-side controller, wherein: The primary side controller is configured to de-energize the gate driver in the primary side low power mode.

6. The USB-PD system according to claim 5, comprising: a pull-up transistor connected between a power voltage source and a power terminal of the gate driver, wherein: The primary side controller includes a pull-down transistor connected between a gate terminal of the pull-up transistor and a reference voltage source; The primary side controller is configured to assert an enable signal at a gate terminal of the pull-down transistor in the primary side active mode; and The primary side controller is configured to remove the enable signal in the primary side low power mode.

7. The USB-PD system according to claim 5, comprising: A filter is connected between the gate terminal of the second power switch and the source terminal of the second power switch.

8. The USB-PD system according to claim 1, wherein: The secondary side controller is configured to: Transition to secondary side wake-up mode; In the secondary side wake-up mode, in response to the voltage on the output port being less than a first threshold, sending a wake-up signal to the primary side controller and sending a drive signal to the primary side controller; as well as In response to the voltage on the output port being greater than a second threshold, sending the low power mode signal to the primary side controller and returning to the secondary side low power mode; and The primary side controller is configured to: In response to receiving the wake-up signal, transitioning to a primary-side wake-up mode and controlling the first power switch based on the drive signal; and In response to receiving the low power mode signal, returning to the primary side low power mode.

9. The USB-PD system according to claim 1, comprising: A cross-line capacitor X-cap is coupled between the input port and the primary side, wherein: The secondary side controller is configured to: periodically transitioning from the secondary-side low power mode to a secondary-side wake-up mode; and For each transition, sending a wake-up signal to the primary side controller in the secondary side wake-up mode, and The primary side controller is configured to: In response to receiving the wake-up signal, transitioning to a primary-side wake-up mode; In the primary side wake-up mode, detecting a low voltage condition at the input port; and The X-cap is discharged in response to detecting a predetermined number of low voltage conditions.

10. A method of operating a Universal Serial Bus Power Delivery (USB-PD) power converter, comprising: In response to detecting that no load device is present at the output port of the USB-PD power converter: sending a low power mode signal from a secondary side controller coupled to control a secondary side of the USB-PD power converter to a primary side controller coupled to control a primary side of the USB-PD power converter; as well as transitioning the secondary-side controller from a secondary-side active mode to a secondary-side low-power mode; in response to receiving the low power mode signal, transitioning the primary side controller from a primary side active mode to a primary side low power mode; In response to detecting connection of the load device to the output port: sending an active mode signal from the secondary side controller to the primary side controller; as well as transitioning the secondary side controller from the secondary side low power mode to the secondary side active mode; as well as In response to receiving the active mode signal, the primary side controller is transitioned from the primary side low power mode to the primary side active mode.

11. The method according to claim 10, comprising: configuring a detector in the primary side controller in a differential configuration to detect the low power mode signal in the primary side active mode; as well as The detector is configured in a single-ended configuration to detect the active mode signal in the primary side low power mode.

12. The method according to claim 11, wherein: Detecting the low power mode signal comprises detecting the low power mode signal using a positive reference signal and a negative reference signal in the differential configuration; and Detecting the active mode signal includes detecting the active mode signal using a ground reference signal in the single-ended configuration.

13. The method according to claim 11, comprising: The active mode signal and the low power mode signal are transmitted using a pulse transformer coupled between the secondary side controller and the detector of the primary side controller.

14. The method according to claim 10, comprising: In the primary side active mode, using a gate driver coupled to the primary side controller to control an active clamp flyback ACF circuit coupled to the primary side; as well as The gate driver is powered down in the primary side low power mode.

15. The method according to claim 14, comprising: in the primary side active mode, asserting an enable signal at a gate terminal of a pull-down transistor connected between a gate terminal of a pull-up transistor and a reference voltage source, wherein the pull-up transistor is connected between a power voltage source and a power terminal of the gate driver; and The enable signal is removed in the primary side low power mode.

16. The method according to claim 14, comprising: The ACF circuit is maintained in an off state in the primary-side low power mode.

17. The method according to claim 10, comprising: transitioning the secondary side controller to a secondary side wake-up mode; In the secondary side wake-up mode, in response to the voltage on the output port being less than a first threshold, sending a wake-up signal to the primary side controller and sending a drive signal to the primary side controller; In response to receiving the wake-up signal, transitioning the primary-side controller to a primary-side wake-up mode; In the primary-side wake-up mode, the primary-side controller controls the operation of the transformer of the USB-PD power converter based on the drive signal; sending the low power mode signal to the primary side controller and returning the secondary side controller to the secondary side low power mode in response to the voltage on the output port being greater than a second threshold; as well as In response to receiving the low power mode signal, returning the primary side controller to the primary side low power mode.

18. The method according to claim 10, comprising: periodically transitioning from the secondary side low power mode to a secondary side wake-up mode; for each transition to the secondary side wake-up mode, sending a wake-up signal to the primary side controller in the secondary side wake-up mode; In response to receiving the wake-up signal, transitioning the primary-side controller to a primary-side wake-up mode; In the primary side wake-up mode, detecting a low voltage condition at an input port of the USB-PD power converter; as well as In response to detecting a predetermined number of low voltage conditions, a cross-line capacitor X-cap coupled between the input port and the primary side of the USB-PD power converter is discharged.

19. A universal serial bus power transmission USB-PD system, comprising: a transformer including a primary side coupled to receive a rectified alternating current (AC) input voltage at an input port and a secondary side connected to provide a direct current (DC) output voltage at an output port; a first power switch connected between the input port and the primary side; a second power switch connected between the output port and the secondary side; a primary-side controller coupled to the first power switch; as well as A secondary side controller is coupled to the second power switch, wherein: The secondary side controller is configured to: in response to detecting that no load device is present at the output port, send a low power mode signal to the primary side controller and transition from a secondary side active mode to a secondary side low power mode; The primary side controller is configured to: transition from a primary side active mode to a primary side low power mode in response to receiving the low power mode signal; and The power consumption of the transformer, the primary-side controller in the primary-side low-power mode, and the secondary-side controller in the secondary-side low-power mode is less than 5 mW.

20. The system of claim 19, wherein: The secondary-side controller is configured to: in response to detecting connection of the load device to the output port, transition from the secondary-side low power mode to the secondary-side active mode and send an active mode signal to the primary-side controller; as well as The primary side controller is configured to transition from the primary side low power mode to the primary side active mode in response to receiving the active mode signal.

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