FPGA Architecture File-Based Chip Circuit Automatic Generator and Method

Abstract

The present invention relates to the technical field of chip circuit layout, a chip circuit automatic generator and method based on an FPGA architecture file. The chip circuit automatic generator includes an input module, a placement and routing module, a verification module, and an output module. The input module is used to parse the FPGA architecture file input by the user by using the architecture file parser. The placement and routing module is used to arrange and connect each column unit circuit model in the demand column unit circuit model set, and arrange and connect each row unit circuit in the row unit circuit set. The verification module is used to perform a verification operation on the row unit circuit set based on a preset error type set, and perform a verification operation on the top-level circuit diagram based on the error type set. The output module is used to format and output the top-level circuit diagram. The present invention can improve the efficiency and accuracy of chip circuit connection.

Description

Technical Field

[0001] The present invention relates to the technical field of chip circuit layout, and particularly to a chip circuit automatic generator and method based on an FPGA architecture file. Background Art

[0002] The circuit design process of an FPGA chip is a complex and delicate process. It follows the top-down design principle and is sequentially divided into three key levels: the top-level circuit, the row unit circuit, and the column unit circuit. The column unit circuit, as the basic building block in this hierarchical structure, is particularly important due to its high reusability. When constructing larger-scale and more complex chip circuits, designers usually need to combine multiple column unit circuits into row unit circuits, and then integrate multiple row unit circuits into the top-level circuit to form a complete and powerful FPGA chip.

[0003] However, in this combination process, the challenges are also huge. Due to the extremely large number of signals and interfaces involved, often reaching the level of tens of thousands or even hundreds of thousands, the traditional manual splicing method is not only time-consuming and laborious, but also extremely prone to connection errors due to human negligence or mistakes, thus affecting the performance and stability of the entire chip. Summary of the Invention

[0004] The present invention provides a chip circuit automatic generator and method based on an FPGA architecture file, and its main purpose is to improve the efficiency and accuracy of chip circuit connection.

[0005] To achieve the above object, a chip circuit automatic generator based on an FPGA architecture file provided by the present invention is characterized in that the chip circuit automatic generator includes an input module, a placement and routing module, a verification module, and an output module;

[0006] The input module includes an architecture file parser and a basic column unit circuit library;

[0007] The input module is used to use the architecture file parser to parse the FPGA architecture file input by the user to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a set of required column unit circuit models;

[0008] The placement and routing module is used to arrange and connect each column unit circuit model in the set of required column unit circuit models according to the circuit design information to obtain a set of row unit circuits;

[0009] The placement and routing module is further used to arrange and connect each row unit circuit in the set of row unit circuits according to the row unit circuit verification result sent by the verification module and the circuit design information to obtain a top-level circuit diagram;

[0010] The verification module is used to perform a verification operation on the set of row unit circuits based on a preset set of error types to obtain a row unit circuit verification result;

[0011] The verification module is also used to perform a verification operation on the top-level circuit diagram based on the set of error types to obtain a top-level circuit verification result;

[0012] The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

[0013] In addition, in the chip circuit automatic generator, there is also an FPGA top-level circuit automatic generation program;

[0014] The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parse architecture service;

[0015] The FPGA top-level circuit automatic generation program is used to configure the data formats of the input module and the placement and routing module;

[0016] Among them, the read architecture service is used to read the FPGA architecture file by using the openpyxl library in Python to obtain the circuit design information;

[0017] Among them, the parse architecture service is used to configure the data types of the circuit design information by using a pre-built.map text format to obtain the circuit design information in the.map text format.

[0018] In addition, the.map text format consists of keywords of structure, index, direction, associated proximity relationship, and instance information.

[0019] In addition, the basic column unit circuit library includes a preset number of column unit circuit models:

[0020] The column unit circuit model is obtained by standardizing and storing a pre-built column unit circuit;

[0021] The column unit circuit model is used to provide retrieval information for the input module so that each column unit circuit can be independently called by the input module;

[0022] Among them, the column unit circuit is obtained by arranging pre-built logic unit circuits in the column direction.

[0023] In addition, the configuration process of the standardized storage includes keeping the heights of the column unit circuits consistent by using dbCreateRect in dbAccess of the Cadence skill according to the preset y - coordinate setting.

[0024] Use the sort in the Cadence skill to arrange the IO ports in each column unit circuit in ascending ASCII code order.

[0025] In addition, the preset error type set in the verification module includes at least open - circuit, short - circuit, and floating.

[0026] In addition, the chip circuit automatic generator includes:

[0027] The FPGA architecture file supports xlsx and XML formats;

[0028] The target - form FPGA circuit supports text format and physical diagram format.

[0029] In addition, the verification results of the row unit circuits and the top - level circuit are divided into qualified and unqualified;

[0030] When the verification result of the row unit circuit or the top - level circuit is unqualified, generate an unqualified log file and use warning in the Cadence skill for visual display.

[0031] To achieve the above object, the present invention also provides a method for automatically generating a chip circuit based on an FPGA architecture file, characterized in that the method includes:

[0032] Obtain pre - constructed input module, placement and routing module, verification module, and output module;

[0033] Among them, the input module includes an architecture file parser and a basic column unit circuit library;

[0034] Use the input module to call the architecture file parser to parse the user - input FPGA architecture file to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a set of required column unit circuit models;

[0035] Use the placement and routing module to arrange and connect each column unit circuit model in the set of required column unit circuit models according to the circuit design information to obtain a set of row unit circuits;

[0036] Use the verification module to perform a verification operation on the set of row unit circuits based on the preset error type set to obtain the verification result of the row unit circuits;

[0037] Using the layout and routing module, arrange and connect each row unit circuit in the row unit circuit set according to the row unit circuit verification result sent by the verification module and the circuit design information to obtain a top-level circuit diagram;

[0038] Using the verification module, perform a verification operation on the top-level circuit diagram based on the error type set to obtain a top-level circuit verification result;

[0039] Using the output module, format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

[0040] In addition, the method further includes:

[0041] Obtain a pre-built FPGA top-level circuit automatic generation program;

[0042] Among them, the FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parse architecture service;

[0043] Using the FPGA top-level circuit automatic generation program, configure the data formats of the input module and the layout and routing module. The process of data format configuration is as follows:

[0044] Using the read architecture service, call the openpyxl library in Python to read the FPGA architecture file to obtain the circuit design information;

[0045] Using the parse architecture service, configure the data types of the circuit design information using a pre-built.map text format to obtain the circuit design information in.map text format.

[0046] To solve the problems described in the background art, the present invention constructs a chip circuit automatic generator. By using the input module and the placement and routing module in the chip circuit automatic generator, the FPGA architecture file input by the user is transformed into a target-form FPGA circuit, and the placement and routing process is monitored through a pre-constructed verification module, which can initially realize the automatic connection of the chip circuit. Since the Cadence skill is used in the placement and routing module to execute the placement and routing process, and the Cadence skill does not support the format of the FPGA architecture file, the present invention reads it through Python and uses a pre-configured.map text format to transform the FPGA architecture file into circuit design information that can be read by the Cadence skill, thereby realizing the automatic connection of the chip circuit. Therefore, the present invention can improve the efficiency and accuracy of chip circuit connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 FIG. is a flowchart of a chip circuit automatic generator based on an FPGA architecture file provided by an embodiment of the present invention;

[0048] Figure 2 FIG. is a schematic diagram of an FPGA architecture in a chip circuit automatic generator based on an FPGA architecture file provided by an embodiment of the present invention;

[0049] Figure 3 FIG. is a schematic diagram of an input FPGA architecture file in a chip circuit automatic generator based on an FPGA architecture file provided by an embodiment of the present invention;

[0050] Figure 4 FIG. is a schematic diagram of circuit design information in a.map text format in a chip circuit automatic generator based on an FPGA architecture file provided by an embodiment of the present invention;

[0051] Figure 5 FIG. is a schematic flowchart of a chip circuit automatic generation method based on an FPGA architecture file provided by an embodiment of the present invention.

[0052] The realization, functional features and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] In order to make the objectives, technical solutions and advantages of the present application more apparent, exemplary embodiments according to the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. It should be understood that the present application is not limited by the exemplary embodiments described herein.

[0054] One embodiment of the present application relates to a chip circuit automatic generator based on an FPGA architecture file, as Figure 1 shown, mainly including an input module, a placement and routing module, a verification module, and an output module;

[0055] The input module includes an architecture file parser and a basic column unit circuit library;

[0056] The input module is used to use the architecture file parser to parse the FPGA architecture file input by the user to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a set of required column unit circuit models;

[0057] The placement and routing module is used to arrange and connect each column unit circuit model in the set of required column unit circuit models according to the circuit design information to obtain a set of row unit circuits;

[0058] The placement and routing module is further used to arrange and connect each row unit circuit in the set of row unit circuits according to the row unit circuit verification result sent by the verification module and the circuit design information to obtain a top-level circuit diagram;

[0059] The verification module is used to perform a verification operation on the set of row unit circuits based on a preset set of error types to obtain a row unit circuit verification result;

[0060] The verification module is further used to perform a verification operation on the top-level circuit diagram based on the set of error types to obtain a top-level circuit verification result;

[0061] The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain an FPGA circuit in a target form.

[0062] Among them, the FPGA refers to a field programmable gate array.

[0063] Among them, the FPGA architecture file is a configuration file used to describe the hardware logic structure, resource distribution, and connection relationship of the FPGA.

[0064] Among them, the architecture file parser is a service used to parse the content in the FPGA architecture file.

[0065] Among them, the basic column unit circuit library is a database used to store column unit circuits.

[0066] Among them, the set of row unit circuits and the top-level circuit diagram are structures at different levels in the chip, as Figure 2 shown.

[0067] Among them, the operation of parsing the FPGA architecture file input by the user refers to: referring to Figure 3 the format of the FPGA architecture file shown, extracting the values of each keyword in the FPGA architecture file, and obtaining a set of key-value pairs.

[0068] Among them, the verification results of the row unit circuit and the top-level circuit include two types: qualified and unqualified.

[0069] Among them, the preset error type set refers to a data set collected by R & D personnel according to common error types in the target scenario.

[0070] Among them, the formatted output refers to the process of selecting a suitable output interface according to specific circumstances and outputting the top-level circuit diagram, such as text or image.

[0071] Specifically, in the embodiment of the present invention, due to the characteristic of the FPGA chip with distinct rows and columns, taking the row unit circuit as an example, the row unit circuit is composed of several column unit circuits. The data after parsing the architecture file details the column unit circuit types (covering various types such as CLELL, DSP, ERAM, etc.) of each column inside the row unit circuit, as well as their precise position information inside the chip. As Figure 3 shown, in the 24th column of the row unit named TOP1, the column unit circuit is CLELM, and the 25th column is CLELL.

[0072] Specifically, in the embodiment of the present invention, by parsing the FPGA architecture file, circuit design information is obtained, where the circuit design information includes information such as the number of row units in the chip, the number of each row unit, and necessary IO interface information, etc.

[0073] In the embodiment of the present invention, the basic column unit circuit library is called, and the column unit circuit models corresponding to the circuit design information are extracted to obtain a set of required column unit circuit models. For example, the set of required column unit circuit models [column unit circuit 001, column unit circuit 003, column unit circuit 008...].

[0074] Among them, the steps of arranging and connecting each column unit circuit model are as follows:

[0075] Specifically, in the embodiment of the present invention, the arrangement and connection of the layout and routing module are based on the data (circuit design information) parsed by the input module, and the layout and routing module is responsible for automatically completing the layout and routing of the circuit.

[0076] First, according to the rules preset by technicians, the row unit circuit diagrams are automatically generated, and the column unit devices are intelligently placed, and the automatic wiring between them is completed. Further, according to higher-level rules, the top-level circuit diagram is automatically created, the row unit devices are intelligently placed, and the complex wiring between them is completed.

[0077] Further, in order to ensure the correctness of the circuit design, the verification module is responsible for comprehensively verifying the generated circuit. It focuses on checking whether there are common error phenomena such as open circuits, short circuits, and floating in the circuit to ensure the stability and reliability of the circuit.

[0078] Specifically, in the embodiments of the present invention, the layout and wiring module and the verification module are alternately executed, and the process is as follows:

[0079] After all devices are initialized, the program starts to gradually construct the circuit in a bottom-up manner.

[0080] 1) First, the program starts to generate the internal circuits of each row unit. In this stage, the program follows the principle of layout first and then wiring.

[0081] 2) In the layout stage, the program will place the column unit circuits inside the row unit circuits column by column according to the layout information read from the circuit design information, and construct detailed information records for each column unit device.

[0082] 3) Subsequently, the wiring module will solidify the information of these column unit devices and accurately complete the connection wiring between the column units.

[0083] 4) When the circuit layout and wiring work is completed, the program will intelligently generate the pins required by the circuit in the four directions of up, down, left, and right of the column unit.

[0084] 5) At this step, the verification module will conduct a preliminary check on the pins of the column unit and the interconnections between different column units to check for any floating phenomena. If there are floating pins, a warning will be issued, recorded in the log file, and displayed on the schematic diagram through the built-in warning of Cadence for the user to determine whether the floating is retained.

[0085] 6) Finally, the program will encapsulate these column units with interface information into a row unit rectangular black box for subsequent top-level circuit calls.

[0086] Further, the operations of the layout and wiring module and the verification module for the top-level circuit layout are as follows:

[0087] 1) After all the row unit circuits read from the architecture file are generated, the program will start the layout work of the top-level circuit. In this process, the program will intelligently place the row units according to the layout information of the architecture file and construct the connection information between the row units.

[0088] 2) Subsequently, the program will automatically complete the wiring work in the top-level circuit according to these connection information, ensuring correct and efficient communication between each row unit.

[0089] 3) Finally, the program will generate a complete top-level circuit, which includes all necessary row unit circuits and connection information. Through the built-in function interface of the EDA tool, such as schCheck in Cadence skill, error verification such as floating pins is performed and recorded in the log file. The user determines whether the floating phenomenon is retained. Here, some ports are actually floating, and some special connections are left for the user to connect manually. Usually, only a small number of floating phenomena are left.

[0090] Furthermore, in the embodiment of the present invention, the execution process of the output module is as follows:

[0091] After the verification module checks whether the circuit is short-circuited or open-circuited, if the result is correct, the user can decide to save the final file as a cellview that supports EDA tool interaction, that is, the data format of openAccess, to obtain the target form FPGA circuit. Among them, the data format of openAccess can facilitate interaction with other EDA tools and other engineers; or it is a netlist format in SPICE syntax, which is convenient for direct simulation.

[0092] Specifically, in the embodiment of the present invention, in the chip circuit automatic generator, there is also an FPGA top-level circuit automatic generation program;

[0093] The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill. The FPGA top-level circuit automatic generation program includes a read architecture service and a parse architecture service;

[0094] The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the placement and routing module;

[0095] Among them, the read architecture service is used to read the FPGA architecture file using the openpyxl library in Python to obtain the circuit design information;

[0096] Among them, the parse architecture service is used to configure the data type of the circuit design information using the pre-built.map text format to obtain the circuit design information in.map text format.

[0097] Among them, Python and Cadence skill are two programming languages / tools in different fields, serving the general software development and electronic design automation (EDA) fields respectively.

[0098] Among them, the FPGA top-level circuit automatic generation program is not only used to configure the data formats of the input module and the placement and routing module, but also used to control the subsequent verification module and output module.

[0099] Among them, the openpyxl library is a third-party library in Python specifically used to read and write Excel 2010+ format files, and is suitable for the format of the FPGA architecture file in the embodiments of the present invention.

[0100] Among them, the.map text format is a text format configured by the present invention. Refer to Figure 4 As shown, each data segment in the.map text format starts with BEGIN COL and ends with END COL. This is a structured data, and then each data segment contains an index (INDEX), such as X24, X25, X26, etc. In addition, it also contains direction (DIRECTION) information, such as R (right), etc.

[0101] Among them, a part of the circuit design information in the.map text format is Figure 4 the content in

[0102] Specifically, in the embodiments of the present invention, the.map text format consists of keywords of structure, index, direction, associated proximity relationship, and instance information.

[0103] Specifically, refer to Figure 3 As shown, each data segment also contains information on association (RELATED_VBRK) and adjacent (PRE_COL and NEXT_COL) relationships, such as R1, X23, X25, etc. These information may be used to describe the associated proximity relationship. And there is also an instance (INSTANCE) part inside each data segment, which contains the instance name (INST_NAME) and the master identifier (MASTER). Among them, the content in parentheses such as RELATED_VBRK, PRE_COL, and NEXT_COL represents keywords.

[0104] Specifically, in the embodiments of the present invention, the basic column unit circuit library includes a preset number of column unit circuit models:

[0105] The column unit circuit model is obtained by standardizing and storing the pre-constructed column unit circuit;

[0106] The column unit circuit model is used to provide retrieval information for the input module, so that each column unit circuit can be independently called by the input module;

[0107] Among them, the column unit circuits are obtained by arranging pre-constructed logic unit circuits in the column direction.

[0108] Specifically, in the embodiment of the present invention, the configuration process of the standardized storage includes, according to the preset y-coordinate setting, using dbCreateRect of dbAccess in the Cadence skill to keep the heights of each column unit circuit consistent;

[0109] Using sort in the Cadence skill to arrange the IO ports in each column unit circuit in ascending order of ASCII code.

[0110] Among them, the y-coordinate is used to determine the layout position of each circuit unit in the vertical direction in the integrated circuit layout design.

[0111] Among them, the dbAccess is a set of interfaces in the Cadence skill programming language for accessing and operating the Design Database.

[0112] Among them, the dbCreateRect refers to a function for creating a rectangle in the layout database.

[0113] Among them, the sort refers to a function that can rearrange the elements in a list according to a specified rule (such as numerical value, string order).

[0114] Among them, the IO port is an interface in the integrated circuit for signal input (Input) and output (Output) with external circuits or devices.

[0115] Among them, the ASCII code is a character encoding standard based on the Latin alphabet, representing 128 characters with 7-bit binary numbers.

[0116] Specifically, in the embodiment of the present invention, when using Cadence or other EDA tools to construct the basic unit circuit library, we strictly follow the following principles to ensure the consistency and compatibility of the column units: First, the heights of all column units can be kept consistent by using dbCreateRect of dbAccess in the Cadence skill, just set the y-coordinate to the same height. This helps to avoid misalignment in the vertical direction during the layout process; Second, the IO ports of the column units are arranged in ascending order of ASCII code through the sort method of cadenceskill. Such standardized sorting not only improves the layout efficiency but also effectively prevents connection errors or layout chaos caused by inconsistent port orders. By following these principles, we ensure the stability and accuracy of the column units after layout.

[0117] Specifically, in the embodiments of the present invention, the preset error type set in the verification module includes at least open circuit, short circuit, and floating.

[0118] Among them, the open circuit means that the current path is disconnected due to reasons such as wire breakage, solder joint detachment, or switch not closed somewhere in the circuit, and the current cannot flow normally.

[0119] Among them, the short circuit means that two nodes that should not be directly connected in the circuit (such as the positive and negative poles of the power supply, the signal line and the ground) are connected by a low-resistance path due to reasons such as wire contact or component damage.

[0120] Among them, the floating means that a certain node in the circuit is not connected to a definite reference point (such as the power supply, the ground, or the load), is in a high-impedance state, and the potential is unstable due to environmental noise or parasitic capacitance.

[0121] In the embodiments of the present invention, the open circuit, short circuit, and floating are the most common error types.

[0122] Specifically, in the embodiments of the present invention, the chip circuit automatic generator includes:

[0123] The FPGA architecture file supports xlsx and XML formats;

[0124] The target form FPGA circuit supports text format and physical diagram format.

[0125] Specifically, in the embodiments of the present invention, the architecture file supports xlsx or XML format, specifically depending on the editing tool used by the user.

[0126] The target form FPGA circuit supports text format and physical diagram format, depending on the user's intention. If it is decided to save the target form FPGA circuit as a physical diagram format that supports EDA tool interaction, this data format can facilitate interaction with other EDA tools and other engineers, while choosing the text format, such as the netlist format of SPICE syntax, is convenient for direct simulation.

[0127] Specifically, in the embodiments of the present invention, the verification results of the row unit circuit and the top-level circuit are divided into qualified and unqualified;

[0128] When the verification result of the row unit circuit or the top-level circuit is unqualified, an unqualified log file is generated, and visualization is realized by using the warning in the Cadence skill.

[0129] Among them, the log file refers to a record file automatically generated during the operation of a computer system, software, or device, which is used to store key data such as operation events, status changes, error messages, and user behaviors in detail.

[0130] Among them, the warning is a prompt message generated during the execution of a script or the design operation, indicating that there are potential problems in the code or operation, but it will not immediately cause the program to terminate or design errors.

[0131] Specifically, in the verification module, a preliminary check will be performed on the pins of the column unit circuit model and the interconnections between different column unit circuits to check for any floating phenomenon. If there are floating pins, a warning will be issued, recorded in the log file, and displayed on the schematic diagram through the built-in warning of Cadence for the user to determine whether the floating is to be retained.

[0132] To solve the problems described in the background art, the present invention constructs a chip circuit automatic generator. By using the input module and the layout and routing module in the chip circuit automatic generator, the FPGA architecture file input by the user is transformed into a target form FPGA circuit, and the layout and routing process is monitored through a pre-built verification module, which can initially realize the automatic connection of the chip circuit; since the Cadence skill is used in the layout and routing module to execute the layout and routing process, and the Cadence skill does not support the format of the FPGA architecture file, the present invention reads it through Python and uses a pre-configured.map text format to transform the FPGA architecture file into circuit design information that can be read by the Cadence skill, thereby realizing the automatic connection of the chip circuit. Therefore, the present invention can improve the efficiency and accuracy of chip circuit connection.

[0133] Further, referring to Figure 5 as shown, the embodiment of the present invention also provides a control method executed by using Figure 1 the chip circuit automatic generator based on the FPGA architecture file as shown, including:

[0134] S1. Obtain a pre-built input module, layout and routing module, verification module, and output module. Among them, the input module includes an architecture file parser and a basic column unit circuit library.

[0135] S2. Use the input module to call the architecture file parser to parse the FPGA architecture file input by the user to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a set of required column unit circuit models;

[0136] S3. Use the layout and routing module to arrange and connect each column unit circuit model in the set of column unit circuit models according to the circuit design information to obtain a set of row unit circuits;

[0137] S4. Use the verification module to perform a verification operation on the set of row unit circuits based on a preset set of error types to obtain a row unit circuit verification result;

[0138] S5. Use the layout and routing module to arrange and connect each row unit circuit in the set of row unit circuits according to the row unit circuit verification result sent by the verification module and the circuit design information to obtain a top-level circuit diagram;

[0139] S6. Use the verification module to perform a verification operation on the top-level circuit diagram based on the set of error types to obtain a top-level circuit verification result;

[0140] S7. Use the output module to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

[0141] Among them, the FPGA refers to a field programmable gate array.

[0142] Among them, the FPGA architecture file is a configuration file used to describe the hardware logic structure, resource distribution, and connection relationship of the FPGA.

[0143] Among them, the architecture file parser is a service used to parse the content in the FPGA architecture file.

[0144] Among them, the basic column unit circuit library is a database used to store column unit circuits.

[0145] Among them, the set of row unit circuits and the top-level circuit diagram are structures at different levels in the chip, as Figure 2 shown.

[0146] Among them, the operation of parsing the user-input FPGA architecture file refers to: referring to the Figure 3 format of the FPGA architecture file shown, extracting the numerical values of each keyword in the FPGA architecture file to obtain a set of key-value pairs.

[0147] Among them, the row unit circuit verification result and the top-level circuit verification result include two types: qualified and unqualified.

[0148] Among them, the preset set of error types is a data set collected by R & D personnel according to common error types in the target scenario.

[0149] Among them, the formatted output refers to the process of selecting an appropriate output interface according to specific circumstances and outputting the top-level circuit diagram, such as text or image.

[0150] Specifically, in the embodiments of the present invention, due to the characteristic of the FPGA chip with distinct rows and columns, taking the row unit circuit as an example, the row unit circuit is composed of several column unit circuits. The data after parsing the architecture file details the types of column unit circuits (covering various types such as CLELL, DSP, ERAM, etc.) of each column inside the row unit circuit, as well as their precise position information inside the chip. As Figure 3 shown, in the 24th column of the row unit named TOP1, the column unit circuit is CLELM, and the 25th column is CLELL.

[0151] Specifically, in the embodiments of the present invention, by parsing the FPGA architecture file, circuit design information is obtained, where the circuit design information includes information such as the number of row units in the chip, the number of each row unit, and the necessary IO interface information, etc.

[0152] In the embodiments of the present invention, the basic column unit circuit library is called, and the column unit circuit models corresponding to the circuit design information are extracted to obtain a set of required column unit circuit models. For example, the set of required column unit circuit models [column unit circuit 001, column unit circuit 003, column unit circuit 008...].

[0153] Among them, the steps of arranging and connecting the various column unit circuit models are as follows:

[0154] Specifically, in the embodiments of the present invention, the arrangement and connection of the layout and routing module are based on the data (circuit design information) parsed by the input module, and the layout and routing module is responsible for automatically completing the layout and routing of the circuit.

[0155] First, according to the rules preset by technicians, a row unit circuit diagram is automatically generated, and column unit devices are intelligently placed to complete the automatic wiring between them. Further, according to higher-level rules, a top-level circuit diagram is automatically created, row unit devices are intelligently placed, and complex wiring between them is completed.

[0156] Furthermore, in order to ensure the correctness of the circuit design, the verification module is responsible for comprehensively verifying the generated circuit. It focuses on checking whether there are common error phenomena such as open circuits, short circuits, and floating in the circuit to ensure the stability and reliability of the circuit.

[0157] Specifically, in the embodiments of the present invention, the layout and routing module and the verification module execute alternately, and the process is as follows:

[0158] After all devices are initialized, the program starts to gradually build the circuit in a bottom-up manner.

[0159] 1) First, the program starts to generate the internal circuits of each row unit. In this stage, the program follows the principle of layout first and then routing.

[0160] 2) In the layout stage, the program will place the column unit circuits inside the row unit circuits column by column according to the layout information read from the circuit design information, and build detailed information records for each column unit device.

[0161] 3) Subsequently, the routing module will solidify the information of these column unit devices and accurately complete the connection routing between column units.

[0162] 4) When the circuit layout and routing work is completed, the program will intelligently generate the pins required by the circuit in the four directions of up, down, left, and right of the column units.

[0163] 5) At this step, the verification module will conduct a preliminary check on the pins of the column units and the interconnections between different column units to check for any floating phenomena. If there are floating pins, a warning will be issued, recorded in the log file, and displayed on the schematic diagram through the built-in warning of Cadence for the user to determine whether to retain the floating.

[0164] 6) Finally, the program will package these column units with interface information into a row unit rectangular black box for subsequent top-level circuit calls.

[0165] Furthermore, the operations of the layout and routing module and the verification module for the top-level circuit layout are as follows:

[0166] 1) After generating all the row unit circuits read from the architecture file, the program will start the layout work of the top-level circuit. During this process, the program will intelligently place the row units according to the layout information of the architecture file and construct the connection information between the row units.

[0167] 2) Subsequently, the program will automatically complete the wiring work in the top-level circuit according to this connection information to ensure correct and efficient communication between each row unit.

[0168] 3) Finally, the program will generate a complete top-level circuit, which contains all the necessary row unit circuits and connection information. Through the built-in function interface of the EDA tool such as schCheck in Cadence skill, error verification such as pin floating is performed, recorded in the log file, and the user determines whether to retain the floating phenomenon. Here, some ports are actually floating, and some special connections are retained for the user to connect manually. Usually, only a few floating phenomena are left.

[0169] Further, in the embodiment of the present invention, the execution process of the output module is as follows:

[0170] After the verification module checks whether the circuit is short-circuited or open-circuited, if the result is correct, the user can decide to save the final file as a cellview that supports EDA tool interaction, that is, the data format of openAccess, to obtain the target form FPGA circuit. Among them, the data format of openAccess can facilitate interaction with other EDA tools and other engineers; or it is a netlist format in SPICE syntax, which is convenient for direct simulation.

[0171] Specifically, in the embodiment of the present invention, the method further includes:

[0172] Obtain a pre-built FPGA top-level circuit automatic generation program;

[0173] Among them, the FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parse architecture service;

[0174] Use the FPGA top-level circuit automatic generation program to configure the data format of the input module and the placement and routing module. Among them, the process of data format configuration is as follows:

[0175] Use the read architecture service to call the openpyxl library in Python to read the FPGA architecture file and obtain the circuit design information;

[0176] Use the parse architecture service to configure the data type of the circuit design information in the pre-built.map text format to obtain the circuit design information in the.map text format.

[0177] Among them, Python and Cadence skill are two programming languages / tools in different fields, serving the general software development and electronic design automation (EDA) fields respectively.

[0178] Among them, the FPGA top-level circuit automatic generation program is not only used to configure the data format of the input module and the placement and routing module, but also used to control the subsequent verification module and output module.

[0179] Among them, the openpyxl library is a third-party library in Python specifically used to read and write Excel 2010+ format files, which is suitable for the format of the FPGA architecture file in the embodiment of the present invention.

[0180] Among them, the.map text format is a text format configured by the present invention. Refer to Figure 4 As shown, each data segment in the.map text format starts with BEGIN COL and ends with END COL. This is a structured data. Then each data segment contains an index (INDEX), such as X24, X25, X26, etc. In addition, it also contains direction (DIRECTION) information, such as R (right), etc.

[0181] Among them, a part of the circuit design information in the.map text format is Figure 4 the content in

[0182] Specifically, in the embodiments of the present invention, the.map text format is composed of keywords of structure, index, direction, associated adjacent relationship, and instance information.

[0183] Specifically, refer to Figure 3 As shown, each data segment also contains information on the associated (RELATED_VBRK) and adjacent (PRE_COL and NEXT_COL) relationships, such as R1, X23, X25, etc. These information may be used to describe the associated adjacent relationship. And there is an instance (INSTANCE) part inside each data segment, which contains the instance name (INST_NAME) and the master identifier (MASTER). Among them, the content in parentheses such as the above RELATED_VBRK, PRE_COL, and NEXT_COL represents keywords.

[0184] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms.

[0185] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A chip circuit automatic generator based on FPGA architecture file, characterized in that: The chip circuit automatic generator includes an input module, a layout and routing module, a verification module and an output module; The chip circuit automatic generator also includes an FPGA top-level circuit automatic generation program; The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parsing architecture service; The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the layout and routing module; The architecture reading service is used to use the openpyxl library in Python to read the FPGA architecture file and obtain circuit design information; The parsing architecture service is used to configure the data type of the circuit design information using a pre-built .map text format to obtain the circuit design information in a .map text format; The .map text format consists of keywords of structure, index, direction, associated neighbor relationship and instance information; The input module includes an architecture file parser and a basic column unit circuit library; The basic column unit circuit library includes a preset number of column unit circuit models: The column unit circuit model is obtained by standardizing and storing the pre-built column unit circuit; The column unit circuit model is used to provide retrieval information for the input module so that each column unit circuit can be independently called by the input module; Wherein, the column unit circuit is obtained by arranging the pre-built logic unit circuit in the column direction; The configuration process of the standardized storage includes maintaining the height of each column unit circuit consistent according to the preset y coordinate setting by using dbCreateRect of dbAccess in the Cadenceskill; Using the sort in the Cadence skill, the IO ports in each column unit circuit are arranged in the order of ASCII codes; The input module is used to parse the FPGA architecture file input by the user using the architecture file parser to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a required column unit circuit model set; The layout and routing module is used to arrange and connect each column unit circuit model in the required column unit circuit model set according to the circuit design information to obtain a row unit circuit set; The layout and routing module is further used to arrange and connect each row unit circuit in the row unit circuit set according to the row unit circuit verification result sent by the verification module and the circuit design information to obtain a top-level circuit diagram; The verification module is used to perform a verification operation on the row unit circuit set based on a preset error type set to obtain a row unit circuit verification result; The verification module is further used to perform a verification operation on the top-level circuit diagram based on the error type set to obtain a top-level circuit verification result; The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

2. The chip circuit automatic generator based on the FPGA architecture file as claimed in claim 1, characterized in that: The preset error type set in the verification module at least includes open circuit, short circuit and floating.

3. The chip circuit automatic generator based on FPGA architecture file as claimed in claim 2, characterized in that: The chip circuit automatic generator includes: The FPGA architecture file supports xlsx and XML formats; The target form FPGA circuit supports text format and physical diagram format.

4. The chip circuit automatic generator based on FPGA architecture file as claimed in claim 3, characterized in that: The row unit circuit verification results and the top-level circuit verification results are divided into qualified and unqualified; When the row unit circuit verification result or the top-level circuit verification result is unqualified, an unqualified log file is generated and visualized using a warning in the Cadence skill.

5. A method for automatically generating a chip circuit based on an FPGA architecture file, implemented based on the automatic chip circuit generator based on an FPGA architecture file according to claim 1, characterized in that: The method comprises: Get pre-built input modules, layout and routing modules, verification modules, and output modules; Wherein, the input module includes an architecture file parser and a basic column unit circuit library; Using the input module, calling the architecture file parser, parsing the FPGA architecture file input by the user to obtain circuit design information, and querying the basic column unit circuit library according to the circuit design information to obtain a required column unit circuit model set; Using the layout and routing module, according to the circuit design information, arrange and connect each column unit circuit model in the required column unit circuit model set to obtain a row unit circuit set; Using the verification module, performing a verification operation based on a preset error type set on the row unit circuit set to obtain a row unit circuit verification result; Using the layout and routing module, according to the row unit circuit verification result sent by the verification module and the circuit design information, each row unit circuit in the row unit circuit set is arranged and connected to obtain a top-level circuit diagram; Using the verification module, performing a verification operation based on the error type set on the top-level circuit diagram to obtain a top-level circuit verification result; The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

6. The method for automatically generating chip circuits based on FPGA architecture files according to claim 5, characterized in that: The method further comprises: Get pre-built FPGA top-level circuit automatic generation program; The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parsing architecture service; The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the layout and routing module, wherein the process of data format configuration is as follows: Using the read architecture service, calling the openpyxl library in Python, reading the FPGA architecture file, and obtaining the circuit design information; The analysis architecture service is used to configure the data type of the circuit design information using the pre-built .map text format to obtain the circuit design information in the .map text format.

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