Ising electromechanical circuit based on alcu model and adaptive amv

Abstract

The application discloses an Ising machine circuit based on an ALCU model and an adaptive AMV, and belongs to the technical field of electronic circuits. The Ising machine circuit has a plurality of spin units connected with each other, each spin unit comprising an SRAM for storing a spin state, an SRAM array for storing interaction coefficients and external magnetic field coefficients of corresponding interconnected spin units, an adaptive AMV circuit and a spin update circuit based on an ALCU model; the AMV has a symmetric sampling circuit and a sensitive amplifier SA, and the positive term and the negative term of a spin update factor are sampled to output voltages V CT and V CB , and F0 is output by comparing the two voltages, and is used for controlling spin update. According to the number of interconnected spin units and the size of the coefficients, the application can stably output a voltage difference, support more interconnected spin units and a higher coefficient bit width, improve the convergence precision of Ising, and reduce hardware overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and particularly relates to an Ising machine circuit based on an ALCU model and adaptive AMV. BACKGROUND

[0002] Combination optimization problems exist widely in various application fields, such as image processing in computer vision, path planning in automatic driving, layout and routing in integrated circuit (IC) design, etc. Therefore, an efficient method for solving combination optimization problems can promote the rapid development of related technologies. Some natural computing paradigms, such as Ising computing, ant colony algorithm, genetic algorithm, etc., are proposed to efficiently solve combination optimization problems by simulating the spontaneous convergence of physical models in nature. The Ising model describes the characteristics of magnetic spins in a magnetic field. Each spin in the model has two spin states: spin up (+1) and spin down (-1). The spin state changes due to the effect of an external magnetic field and the interaction between interconnected spins. Therefore, the system energy of the Ising model naturally approaches the ground state, which corresponds to the optimal solution of the Quadratic Unconstrained Binary Optimization (QUBO) model. Therefore, by mapping the combination optimization problem to the QUBO model, the Ising model can efficiently solve such combination optimization problems.

[0003] For traditional processors based on the von Neumann architecture, it is difficult to simulate the behavior of spins in parallel. Therefore, a special processor with the Ising model is needed to effectively solve combination optimization problems. Ising computing processors have been implemented through different processes. For example, quantum annealing systems and Ising chips based on CMOS technology. Quantum annealing systems are limited by the working conditions of superconducting devices, requiring extremely high energy consumption to maintain ultra-low temperature, which poses a serious challenge to practical applications. In contrast, COMS-type Ising chips are a better choice for implementing Ising computing accelerator processors, as they can work at room temperature and the process conditions are mature and easy to expand.

[0004] However, the ability of COMS-type Ising chip to solve complex combinatorial optimization problems is limited by the number of interacting spins, the coefficient precision and the random update model of spin state. The Ising machine based on digital adder has an advantage in coefficient precision, but the large adder limits its scalability. On the contrary, the analog majority vote circuit (AMV) can realize spin update with minimal hardware overhead. However, its application is limited by the small number of interacting spins and the coefficient precision. In addition, the energy of the Ising model has local minimum, so it is necessary to disturb the spin state by the simulated annealing algorithm to make the energy get rid of the local minimum. However, the implementation of complex simulated annealing algorithm is not feasible in hardware. Therefore, the simulated annealing technique is simplified to manage the flip of the spin by a random signal, but the convergence accuracy of the model is reduced. SUMMARY

[0005] In view of the above, the present application proposes an Ising machine circuit based on ALCU model and adaptive AMV, which aims to calculate the optimal state of combinatorial optimization problem and realize low hardware overhead and high solution accuracy.

[0006] To achieve the above object, the technical scheme adopted by the present application is as follows:

[0007] An Ising machine circuit based on ALCU model and adaptive AMV, the Ising machine circuit has a plurality of interconnected spin units, each spin unit includes an SRAM for storing spin state, an SRAM array for storing corresponding interaction coefficients and external magnetic field coefficients of interconnected spin units, an adaptive AMV circuit and a spin update circuit based on ALCU model;

[0008] The SRAM array for storing corresponding interaction coefficients of interconnected spin units includes XNOR and XOR logic units, which are used to complete the same or different sign judgment of spin state and interaction coefficient of interconnected spin units; the adaptive AMV circuit has a pair of symmetric sampling circuits and a sensitive amplifier, a pair of sampling circuits sample the same sign coefficient corresponding to the positive term of spin update factor, the positive external magnetic field coefficient and the different sign coefficient corresponding to the negative term of spin update factor, the negative external magnetic field coefficient, and the sensitive amplifier compares the size of the positive term and the negative term of the spin update factor to generate a spin update control signal, the adaptive AMV circuit can compensate the equivalent resistance of the pull-up network in the sampling circuit; after obtaining the spin update control signal, the spin update circuit based on ALCU model controls the state update of the spin unit.

[0009] Preferably, the SRAM array storing the corresponding interconnection spin cell interaction coefficient and external magnetic field coefficient comprises a plurality of N-bit coefficient SRAM cells, and the XNOR and XOR logical operations of the interconnection spin state value and the corresponding interaction coefficient sign bit are completed inside the SRAM storage cell storing the interaction coefficient sign bit, if the results of the logical operations are the same, output the opposite sign determination signal EN=1, and the same sign determination signal if the results of the logical operations are different, output the determination signal EN=0, For the external magnetic field coefficient, EN is the sign bit signal of the external magnetic field coefficient, is the inverse signal of the sign bit of the external magnetic field coefficient, and EN and are both low active in the sampling circuit; the determination signal and the interaction coefficient and the external magnetic field coefficient except the sign bit are output to the adaptive AMV circuit.

[0010] Preferably, the adaptive AMV circuit comprises left and right symmetrical left sampling circuit, right sampling circuit and a sensitive amplifier, the left sampling circuit is used for sampling the same sign coefficient and the positive external magnetic field coefficient except the sign bit, corresponding to the positive term of F i , the output voltage is V CT ; the right sampling circuit is used for sampling the opposite sign coefficient and the negative external magnetic field coefficient except the sign bit, corresponding to the negative term of F i , the output voltage is V CB . The sensitive amplifier is used for comparing the size of V CT and V CB and generating the spin update control signal F0; the same sign coefficient refers to the interaction coefficient with the same sign of the coefficient sign bit and the interconnection spin state value, and the opposite sign coefficient refers to the interaction coefficient with the opposite sign of the coefficient sign bit and the interconnection spin state value. In operation, after sampling is completed in the high level stage of the clock, the SA compares the size of V CT and V CB in the low level stage of the clock, and generates the spin update control signal F0.

[0011] Preferably, the left sampling circuit and the right sampling circuit comprise a plurality of same sampling units, each sampling unit is composed of a PNCA circuit and a pull-down unit circuit; the pull-down unit circuit comprises a circuit for sampling each bit except the sign bit;

[0012] The pull-down unit circuit corresponding to the left sampling circuit is in the determination signal The left sampling circuit corresponding to the pull-down unit circuit transmits the rest of the bits except the sign bit of the same sign coefficient and the positive external magnetic field coefficient to the corresponding discharge NMOS tube under the control of the judgment signal EN; the right sampling circuit corresponding to the pull-down unit circuit transmits the rest of the bits except the sign bit of the opposite sign coefficient and the negative external magnetic field coefficient to the corresponding discharge tube under the control of the judgment signal EN; and the PNCA circuit opens the pull-up compensation PMOS under the control of the highest bit of the coefficient except the sign bit, so as to balance the equivalent impedance of the overall pull-up and pull-down network. When the bit width of the coefficient increases or the number of interconnected spins increases, the sampling output circuit will not be too close to 0 potential and cannot be detected by the SA due to the impedance balancing of the PNCA circuit.

[0013] The discharge function part of the pull-down unit circuit has different pull-down strengths for different bits of the coefficient. For the lowest bit of the coefficient, a single NMOS is used for discharge; for the second bit of the coefficient, two NMOSs are used for discharge. For the nth bit of the coefficient, 2 n-1 n pull-down tubes are needed for discharge.

[0014] The PNCA circuit opens the pull-up compensation PMOS under the control of the highest bit of the coefficient except the sign bit, so as to balance the equivalent impedance of the overall pull-up and pull-down network. When the bit width of the coefficient increases or the number of interconnected spins increases, the sampling output circuit will not be too close to 0 potential and cannot be detected by the SA due to the impedance balancing of the PNCA circuit.

[0015] The ALCU model of the application is first obtained from the first-order approximation of the Glauber probability model that the spin is updated to +1, that the spin is updated to +1 when F0&R0 is true, and that the spin is updated to +1 when F0|R0 is true. The two kinds of control logic are matched with the update direction of the spin in the local steady state, and the complement of the asymmetric update trend of the spin is formed. When F0&R0 is true, the spin is updated to +1, but only when R0=0, the spin will be updated to -1. When F i =0, F0 is coded as 1, and the trend of updating the spin to +1 is increased. When the control logic of F0|R0 being true is used, only when R0=1, the spin will be updated to +1; therefore, when F i =0, F0 is coded as 0, and the trend of updating the spin to -1 is increased. The two kinds of control algorithms are named as AF1 and OF0, respectively. Through the logical complement of the asymmetric trend of the spin update, the two algorithms can achieve higher convergence accuracy. At the same time, the two algorithms only need simple AND gates and OR gates at the circuit level, and have extremely low hardware overhead.

[0016] Compared with the prior art, the application has the following beneficial effects:

[0017] The application greatly simplifies the sampling circuit of the AMV by integrating the XNOR, XOR logic calculation unit in the coefficient storage SRAM. Through the dynamic adjustment of the equivalent resistance of the pull-up network by the PNCA circuit, the adaptive AMV can support more interconnected spins and larger interaction coefficient / external magnetic field coefficient than the original AMV. The spin update circuit of the Ising machine designed by using the ALCU model has extremely low hardware overhead and high convergence accuracy. Therefore, the application has superiority in hardware overhead and convergence accuracy over the existing Ising machine. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is the Ising machine schematic diagram provided by the adaptive AMV circuit and the ALCU spin update circuit according to the application;

[0019] Figure 2 is the schematic diagram of the interaction coefficient, external magnetic field coefficient storage SRAM and the internally integrated XNOR and XOR logic calculation unit according to the application;

[0020] Figure 3 is the schematic diagram of the adaptive AMV circuit according to the application;

[0021] Figure 4 is the circuit schematic diagram corresponding to the two algorithms (AF1 and OF0) based on the ALCU model according to the application;

[0022] Figure 5 is the row and column random number common schematic diagram according to the application; DETAILED DESCRIPTION

[0023] The application will be further described and illustrated in conjunction with the specific embodiments. The embodiments are only exemplary and do not limit the scope of the disclosure. The technical features of each embodiment in the application can be combined accordingly without conflict.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the application belongs. The terms used herein are only for the purpose of describing the application and are not intended to limit the application.

[0025] The application will be further described and illustrated in conjunction with the specific embodiments.

[0026] An Ising machine circuit based on the ALCU model and adaptive AMV, the Ising machine circuit has a plurality of interconnected spin units, each spin unit includes an SRAM for storing spin state, an SRAM array for storing the interaction coefficient and external magnetic field coefficient of the corresponding interconnected spin unit, an adaptive AMV circuit and a spin update circuit based on the ALCU model.

[0027] The XNOR and XOR logic units included in the SRAM array corresponding to the interaction coefficient of the interconnected spin cell are used to complete the same sign or different sign judgment of the spin state of the interconnected spin cell and the interaction coefficient; the adaptive AMV circuit has a symmetric sampling circuit and a sensitive amplifier, a pair of sampling circuits sample the same sign coefficient corresponding to the positive term of the spin update factor and the positive external magnetic field coefficient and the different sign coefficient corresponding to the negative term of the spin update factor and the negative external magnetic field coefficient, and the sensitive amplifier compares the size of the positive term and the negative term of the spin update factor to generate a spin update control signal, and the adaptive AMV circuit can compensate the equivalent resistance of the pull-up network in the sampling circuit; after obtaining the spin update control signal, the state update of the spin cell is controlled by the spin update circuit based on the ALCU model.

[0028] As shown in Figure 1 , in an optional embodiment of the present application, the Ising machine of the present application has 100 interconnected spin cells, and all the spin cells are connected to each other through an 8-neighbor interconnected topology. Among them, according to the characteristics of the interconnected topology, every four adjacent spin cells are combined into a spin update group, and the four spin cells in each spin update group will be updated in turn within four clock cycles; therefore, the update of all spin cells will be completed within four clock cycles, and the spin states of two spin cells with an interconnected relationship will not be updated at the same time to cause update errors, and the specific update process is as follows:

[0029] 1) A single spin cell stores 8 3-bit interaction coefficients and a 3-bit external magnetic field coefficient; wherein each interaction coefficient corresponds to the interaction force between an interconnected adjacent spin cell and the spin cell; when the spin cell is updated, the 8 adjacent spin cells output the spin state value to the SRAM array of the spin cell; the SRAM array outputs the determination signal EN, and the remaining bits of the 8 interaction coefficients and the external magnetic field coefficient except the sign bit to the adaptive AMV circuit;

[0030] 2) The adaptive AMV circuit compares the differential sampling voltages to determine the positive and negative of the spin update factor F i , and updates the local spin cell state through the spin update circuit;

[0031] 3) After the local spin cell state is updated, the state update of the adjacent 8 interconnected spin cells is performed in the next period, and all the spin cells will complete a round of update within four periods, and the spin states of two spin cells with an interconnected relationship will not be updated at the same time.

[0032] As shown in Figure 2As shown, in an optional embodiment of the present invention, a single spin unit includes nine sets of 3-bit coefficient SRAM storage units (hereinafter referred to as coefficient SRAM), one spin state SRAM storage unit with an output port (hereinafter referred to as spin state SRAM), one adaptive AMV circuit, and one ALCU spin update circuit.

[0033] In the coefficient SRAM, the SRAM storing the sign bit integrates XNOR and XOR logic calculation units to perform calculations on the corresponding neighboring spin value (σ). aj The sign bit of the interaction coefficient between the two spins (J) S The XNOR and XOR operations are performed. When the results of both operations are the same, EN = 1. EN = 0 when the results of the two operations are different. For the external magnetic field coefficient, EN is the sign bit signal of the external magnetic field coefficient. The inverted signal of the sign bit of the external magnetic field coefficient is EN in the sampling circuit. All are active low; the coefficients (J0 and J1) and EN bits, except for the sign bit, are active low. The data is transmitted to the corresponding sampling circuit in the adaptive AMV circuit via the output port. The writing of coefficients is controlled by the word line (WL) and bit lines (BL and BLB). The ALCU spin update circuit operates on the spin update control signal F0 and the random number R... V and R H The spin state is updated under control. The spin state includes +1 and -1, where +1 represents spin up and -1 represents spin down.

[0034] like Figure 3 As shown, in an optional embodiment of the present invention, the adaptive AMV circuit has two symmetrically arranged sampling circuits and a sense amplifier (SA). The left sampling circuit... Under the control of EN, the sampling circuit samples coefficients with the same sign and positive external magnetic field coefficients, while the sampling circuit on the right samples coefficients with opposite signs and negative external magnetic field coefficients. Each sampling circuit has nine identical sampling units, each containing multiple pull-down unit circuits for different bits of the coefficients and a pull-up network compensation adjustment (PNCA) circuit (hereinafter referred to as PNCA circuit). One sampling unit is used to sample the external magnetic field coefficients, and the other eight sampling units sample the interaction coefficients of the eight interconnected spins respectively through their respective pull-down unit circuits.

[0035] The two groups of sampling circuits in the adaptive AMV circuit are defined as left sampling circuit and right sampling circuit respectively. The pull-down unit circuit in the sampling unit of the left sampling circuit is defined as left pull-down unit circuit. Similarly, the pull-down unit circuit in the sampling unit of the right sampling circuit is defined as right pull-down unit circuit. The left pull-down unit circuit is used to sample the coefficients with the same sign as the corresponding interconnection spin, and the positive term of the corresponding spin update factor F i , and the output voltage is V CT . The right pull-down unit circuit is used to sample the coefficients with the opposite sign as the corresponding interconnection spin, and the negative term of the corresponding spin update factor F i , and the output voltage is V CB .

[0036] The adaptive AMV circuit has two working stages of sampling and amplification. In the high level stage of the clock, the pull-up network of the two sampling circuits charges the output nodes CT and CB respectively, and the pull-down network discharges the output nodes CT and CB under the control of the corresponding coefficients. The stable differential sampling voltage is amplified by SA in the low level stage of the clock. The discharge function part of the pull-down unit circuit has different pull-down strengths for different bits of the coefficients. For the lowest bit of the coefficient, a separate pull-down NMOS tube is used for discharge; for the second bit of the coefficient, two pull-down NMOS tubes are used for discharge. For the n-th bit of the coefficient, 2 n-1 pull-down NMOS tubes are needed for discharge.

[0037] When the adaptive AMV circuit works, in the high level stage of the clock, the sampling circuit completes the sampling of the coefficients and outputs V CT and V CB , and the sizes of V CT and V CB respectively represent the sizes of the positive term and the negative term in the spin update factor F i . In the low level stage of the clock, SA compares the sizes of V CT and V CB , and outputs the spin update control signal F0. In this embodiment, when V CT >V CB , the spin update control signal F0=1; when V CT <V CB , the spin update control signal F0=0; when V CT =V CB , the spin is in a local steady state, and the spin update control signal F0=0 or F0=1.

[0038] In a specific embodiment of the present application, the sampling unit circuit has two groups of sampling unit circuits for sampling the first bit (J i0 ) and the second bit (J i1The sampling circuit. Among them, for J... i0 The sampling circuit is as follows Figure 3 As shown in (b), PMOS transistor M1 is in EN or J under control i0 The signal is transmitted to NMOS transistor M3 when M1 is turned on and J... i0 When the value is 1, M3 is turned on, discharging the sampling output bit line CT / CB. Specifically, the circuit for sampling the least significant bit of the coefficient includes PMOS transistor M1, NMOS transistor M2, and NMOS transistor M3; the substrate of M1 is connected to the power supply VDD, the substrates of M2 and M3 are grounded, the source terminal of M1 is connected to the least significant bit signal of the coefficient, the drain terminals of M1 and M2 are connected to the gate terminal of M3, the source terminal of M2 is connected to the source terminal of M3 and grounded, the drain terminal of M3 is connected to the input terminal of SA, and the gate terminal of M1 is connected to the gate terminal of M2 and connected to the determination signal EN or the output of the coefficient SRAM cell.

[0039] For J i1 The sampling circuit is as follows Figure 3 As shown in (c), different from Figure 3 (b) The sampling circuit for the second digit of the coefficient has two discharge NMOS transistors, M6 and M7. Different pull-down strengths of the NMOS transistors correspond to different bit weights of the coefficient. If it is to be extended to a 4-bit coefficient, then for the third digit of the coefficient, four pull-down NMOS transistors are needed. Specifically, the circuit for sampling the second digit of the coefficient includes PMOS transistor M4, NMOS transistor M5, NMOS transistor M6, and NMOS transistor M7; the substrate of M4 is connected to the power supply VDD, the substrates of M5, M6, and M7 are grounded, the source terminal of M4 is connected to the second digit signal of the coefficient, the drain terminals of M4, M5, and M6 are connected to the gate terminal of M7, the source terminals of M5, M6, and M7 are connected to and grounded, the drain terminal of M6 is connected to the drain terminal of M7 and connected to the input terminal of SA, and the gate terminal of M4 is connected to the gate terminal of M5 and connected to the judgment signal EN or the output of the coefficient SRAM cell.

[0040] In one specific embodiment of the present invention, the PNCA circuit is as follows: Figure 3As shown in (d), PNCA uses NMOS transistor M9 to transmit a clock signal to control PMOS transistor M8 to charge the output bit line CT / CB. The control signal of M9 is the second most significant bit of the coefficient. When the second most significant bit of the coefficient is 1, it means that many discharge transistors are turned on in the pull-down network composed of multiple pull-down sampling unit circuits. At this time, the equivalent impedance of the pull-down network is low. If the second most significant bits of multiple coefficients are 1 at the same time, the overall impedance of the pull-down network is significantly reduced. At this time, PNCA can effectively balance the equivalent impedance of the pull-up network, so that the voltage difference on the output bit line CT / CB is not too small to be detected by SA. At the same time, this compensation is equal for the sampling circuits on both sides, so it will not cause detection errors. Specifically, the PNCA circuit includes a PMOS transistor M8, an NMOS transistor M9, and a PMOS transistor M10. The source terminal of M8, the substrate of M8, and the source terminal of M10 are connected to the substrate of M10 and connected to the power supply VDD. The gate terminal of M8, the drain terminal of M9, and the drain terminal of M10 are connected to each other. The gate terminal of M9 is connected to the gate terminal of M10 and connected to the second-highest bit signal of the coefficient. The substrate of M9 is grounded. The source terminal of M9 is connected to the clock control signal. The drain terminal of M8 is the output terminal and is connected to the input terminal of the sensitive amplifier. The symmetrical sampling circuit samples the coefficients when the clock control signal is high, generating V. CT and V CB When the clock control signal is low, the sensitive amplifier compares V. CT and V CB The size of the signal is determined and a spin update control signal F0 is generated.

[0041] In this invention, the ALCU model is derived from the Glauber probability model: The simplified result is obtained; where ΔE i This represents the local energy change during a spin state flip, where T is the equivalent temperature of the simulated annealing. Updating the spin state to +1 includes two cases:

[0042] 1) The current spin state is -1, and a random flip occurs. At this time, the local variable ΔE caused by the node spin flip is... i =-Δσ i F i -2F i ;therefore,

[0043] 2) The current spin state is +1, and no random flips occur. The local variable caused by node spin flips is 2F. i ;therefore,

[0044] Among them, P Glauber (-2F i ) = 1 - P Glauber (2F i), so the probability of spin state updating to +1 is Since in 0≤P Glauber ≤1, the first-order linear approximation has a good fitting effect, which is simplified as: By introducing a random number r to control the random inversion of the spin, when F i +(1-2r)T>0, the spin updates to +1; in order to simplify the circuit implementation scheme, the sign bit F0 of F i and the 0, 1 random number R0 containing the probability changing over time are used to simplify the model, and when F0+R0>1, the spin state updates to +1; but since the original continuous variable is discretized, the definition of the spin state update for F0+R0=1 will cause the asymmetric trend of spin update. Therefore, the ALCU model is designed by using the coding mode of F0 when F i =0 to complement the logic.

[0045] Through the above analysis, the spin update logic of the ALCU spin update circuit is any one of the following:

[0046] The spin state updates to +1 when F0&R0 is true, otherwise it updates to -1;

[0047] The spin state updates to +1 when F0|R0 is true, otherwise it updates to -1;

[0048] Wherein R0 is an external injected random signal containing 0 and 1, for the spin update logic F0&R0: the probability of R0 being 0 gradually decreases by 0, for the spin update logic F0|R0: the probability of R0 being 1 gradually decreases by 0, and F0 is a spin update control signal.

[0049] The ALCU model matches the two spin update logics simplified based on the Glauber probability model with the update direction when the spin is in a local steady state, and designs two approximate logic complementary spin update algorithms (OF0 algorithm and AF1 algorithm) and corresponding circuits. The spin update circuit is selected from any one of the following:

[0050] The spin update circuit based on the OF1 algorithm: including an AND gate composed of a NAND gate and an inverter in series, an NOR gate and an inverter; wherein the input signal of the AND gate is two external input random numbers, the output end of the AND gate is connected to one input end of the NOR gate, the other input end of the NOR gate is connected to the output end of the adaptive AMV circuit to access the spin update control signal F0, the output end of the NOR gate is connected to an inverter, and the output end of the NOR gate and the output end of the inverter are respectively connected to two bit lines of the SRAM storing the spin state, for writing the updated spin state into the SRAM storing the spin state;

[0051] The spin update circuit based on the AF0 algorithm comprises two NAND gates and an inverter, the input signal of the first NAND gate is two external input random numbers, the output end of the first NAND gate is connected to one input end of the second NAND gate, the other input end of the second NAND gate is connected to the output end of the adaptive AMV circuit to access the spin update control signal F0, the output end of the second NAND gate is connected to an inverter, and the output end of the second NAND gate and the output end of the inverter are respectively connected to two bit lines of the SRAM for storing the spin state, and are used for writing the updated spin state into the SRAM for storing the spin state.

[0052] The AF1 algorithm adopts F0&R0 as true to update the spin to +1, but as long as R0=0, the spin will be updated to -1. When the update logic is adopted, when F i =0, F0 is coded as 1, and the trend of updating the spin to +1 is increased. When the control logic of the OF0 algorithm adopts F0|R0 as true to update the spin to +1, as long as R0=1, the spin will be updated to +1; therefore, when F i =0, F0 is coded as 0, and the trend of updating the spin to -1 is increased.

[0053] As shown in Figure 4 (a), the circuit implementation of the OF0 algorithm adopts an or logic-based scheme, when F0|R0=1, the state of the spin is updated to +1, otherwise, it is updated to -1. In order to meet the annealing convergence process, the probability that R H and R V are 1 gradually decreases from 0.5 to 0, R0 is obtained by performing an and logic operation on R H and R V , and in the termination stage of annealing, R0 remains 0 and no longer randomly flips the state of the spin. As shown in Figure 4 (b), the circuit implementation of the AF1 algorithm adopts an and logic-based scheme, when F0&R0=1, the state of the spin is updated to +1, otherwise, it is updated to -1. Similarly, in order to meet the annealing convergence process, the probability that R H and R V are 1 gradually decreases from 0.5 to 0, R0 is obtained by performing an NAND logic operation on R H and R V , and in the termination stage of annealing, R0 remains 1 and no longer randomly flips the state of the spin.

[0054] As shown in Figure 5 , in one specific embodiment of the present application, each node respectively obtains two random numbers R H and R VThe two random numbers are then logically operated to obtain a random flipping control random number R0, wherein each row shares the same row random number R H Each column now shares the same column random number R V This scheme can make spins in different rows and columns obtain different random number combinations. For an N x N array, the required random number can be reduced from N 2 to 2N, thus effectively reducing the required external random number source.

[0055] The foregoing description of the disclosed embodiments enables any person skilled in the art to make or use the present application. Modifications to examples will be readily apparent to those of ordinary skill in the art, and the general principles defined herein can be applied to other embodiments without departing from the spirit and scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An Ising machine circuit based on the ALCU model and adaptive AMV, characterized in that, The Ising machine circuit has multiple interconnected spin units. Each spin unit includes an SRAM for storing spin states, an SRAM array for storing the interaction coefficients and external magnetic field coefficients of the corresponding interconnected spin units, an adaptive AMV circuit, and a spin update circuit based on the ALCU model. The SRAM array storing the interaction coefficients of the corresponding interconnected spin units includes XNOR and XOR logic cells to determine whether the spin states of the interconnected spin units and the interaction coefficients have the same or opposite signs. The SRAM array storing the interaction coefficients and external magnetic field coefficients of the corresponding interconnected spin units contains several N-bit coefficient SRAM cells. Within the SRAM storage cells storing the sign bits of the interaction coefficients, XNOR and XOR logic operations are performed between the interconnected spin state values ​​and the corresponding sign bits of the interaction coefficients. If the results of the logic operations are the same, an opposite sign determination signal is output. Same sign determination signal ; If the results of the logical operation are different, an opposite sign determination signal will be output. Same sign determination signal For the external magnetic field coefficient, This is the sign bit signal for the external magnetic field coefficient. The sign bit of the external magnetic field coefficient is inverted; the determination signal and the interaction coefficients and external magnetic field coefficients of the remaining bits except the sign bit are output to the adaptive AMV circuit. The adaptive AMV circuit has a symmetrical sampling circuit and a sensitive amplifier. The pair of sampling circuits respectively sample the same-sign coefficients and positive external magnetic field coefficients corresponding to the positive term of the spin update factor, and the opposite-sign coefficients and negative external magnetic field coefficients corresponding to the negative term of the spin update factor. In the sampling circuit... and All are active low; the sensitive amplifier compares the magnitudes of the positive and negative terms of the spin update factor to generate a spin update control signal, and the adaptive AMV circuit can compensate for the equivalent resistance of the pull-up network in the sampling circuit. After obtaining the spin update control signal, the spin unit state update is controlled by the spin update circuit based on the ALCU model.

2. The Ising machine circuit based on the ALCU model and adaptive AMV according to claim 1, characterized in that, The SRAM for storing spin states is used to store the spin states of local spin units. The spin states include +1 and -1, where +1 represents spin up and -1 represents spin down.

3. The Ising machine circuit based on the ALCU model and adaptive AMV according to claim 1, characterized in that, The adaptive AMV circuit includes a symmetrical left sampling circuit, a right sampling circuit, and a sensitive amplifier. The left sampling circuit samples the same-sign coefficients and the positive external magnetic field coefficients, excluding the sign bit, and outputs a sampling voltage V. CT The sampling circuit on the right is used to sample the remaining bits (excluding the sign bit) of the opposite-sign coefficients and the negative external magnetic field coefficients, and outputs a sampling voltage V. CB Sensitive amplifier is used to compare V CT and V CB The size and generate spin update control signal The same-sign coefficient refers to the interaction coefficient where the sign bit of the coefficient is the same as the spin state value of the interconnection, and the opposite-sign coefficient refers to the interaction coefficient where the sign bit of the coefficient is opposite to the spin state value of the interconnection.

4. The Ising machine circuit based on the ALCU model and adaptive AMV according to claim 3, characterized in that, When V CT > V CB At that time, the spin update control signal When V CT < V CB At that time, the spin update control signal When V CT = V CB At this time, the spin is in a local steady state, and the spin update control signal is activated. or .

5. The Ising machine circuit based on the ALCU model and adaptive AMV according to claim 3, characterized in that, The left and right sampling circuits contain multiple identical sampling units, each consisting of a PNCA circuit and a pull-down unit circuit; the pull-down unit circuit contains a circuit that samples each bit except for the sign bit. The pull-down unit circuit corresponding to the sampling circuit on the left side determines the signal with the same sign. Under the control of , the remaining bits of the same sign coefficient and the positive external magnetic field coefficient, excluding the sign bit, are transmitted to the corresponding discharge NMOS transistor; The pull-down unit circuit corresponding to the sampling circuit on the right side determines the signal with different signs. Under the control of the circuit, the remaining bits of the coefficients with opposite signs and the negative external magnetic field coefficients, excluding the sign bit, are transmitted to the corresponding discharge transistors. The PNCA circuit turns on the pull-up compensation PMOS transistor under the control of the highest bit of the coefficients, excluding the sign bit, so as to balance the equivalent resistance of the pull-up network composed of multiple PNCA circuits and the charging PMOS transistors of the sensitive amplifier and the pull-down network composed of multiple pull-down unit circuits after the bit width of the coefficients increases or the number of interconnected spin units increases.

6. The Ising machine circuit based on the ALCU model and adaptive AMV according to claim 5, characterized in that, The circuit for sampling the least significant bit of the coefficient includes PMOS transistor M1, NMOS transistor M2, and NMOS transistor M3. The substrate of M1 is connected to power supply VDD, the substrates of M2 and M3 are grounded, the source terminal of M1 is connected to the least significant bit signal of the coefficient, the drain terminals of M1 and M2 are connected to the gate terminal of M3, the source terminals of M2 and M3 are connected to the source terminal and grounded, the drain terminal of M3 is connected to the input terminal of a sensitive amplifier, and the gate terminals of M1 and M2 are connected to the decision signal EN output from the coefficient SRAM cell. ; The circuit for sampling the second lowest bit of the coefficient includes PMOS transistors M4, M5, M6, and M7. The substrate of M4 is connected to power supply VDD; the substrates of M5, M6, and M7 are grounded; the source terminal of M4 is connected to the second bit signal of the coefficient; the drain terminals of M4, M5, and M6 are connected to the gate terminal of M7; the source terminals of M5, M6, and M7 are connected to and grounded; the drain terminal of M6 is connected to the drain terminal of M7 and connected to the input terminal of the sensitive amplifier; the gate terminal of M4 is connected to the gate terminal of M5 and connected to the decision signal EN output from the coefficient SRAM cell. ; The PNCA circuit includes a PMOS transistor M8, an NMOS transistor M9, and a PMOS transistor M10. The source terminal of M8, the substrate of M8, and the source terminal of M10 are connected to the substrate of M10 and connected to the power supply VDD. The gate terminal of M8, the drain terminal of M9, and the drain terminal of M10 are connected to each other. The gate terminal of M9 is connected to the gate terminal of M10 and connected to the second-highest bit signal of the coefficient. The substrate of M9 is grounded. The source terminal of M9 is connected to the clock control signal. The drain terminal of M8 is the output terminal and connected to the input terminal of the sensitive amplifier. The symmetrical sampling circuit samples the coefficients when the clock control signal is high, generating V. CT and V CB When the clock control signal is low, the sensitive amplifier compares V. CT and V CB The size and generate spin update control signal .

7. The Ising machine circuit based on the ALCU model and adaptive AMV according to claim 3, characterized in that, The spin update logic of the spin update circuit based on the ALCU model is any one of the following: If true, the spin state is updated to +1; otherwise, it is updated to -1. If true, the spin state is updated to +1; otherwise, it is updated to -1. in, For externally injected random signals containing 0s and 1s, the spin update logic... : The probability of being 0 gradually decreases to 0 for spin update logic. : The probability of being 1 gradually decreases to 0. This is the spin update control signal.

8. The Ising machine circuit based on the ALCU model and adaptive AMV according to claim 7, characterized in that, The spin renewal circuit is selected from any of the following: The spin update circuit based on the OF1 algorithm includes an AND gate (composed of a NAND gate and an inverter connected in series), a NOR gate, and an inverter. The AND gate's input signals are two external random numbers. The AND gate's output is connected to one input of the NOR gate, and the other input of the NOR gate is connected to the output of an adaptive AMV circuit to receive the spin update control signal. The output of the NOR gate is connected to an inverter, and the output of the NOR gate and the output of the inverter are respectively connected to two bit lines of the SRAM storing the spin state, which is used to write the updated spin state into the SRAM storing the spin state. The spin update circuit based on the AF0 algorithm consists of two NAND gates and an inverter. The input signals of the first NAND gate are two external random numbers. The output of the first NAND gate is connected to one input of the second NAND gate, and the other input of the second NAND gate is connected to the output of the adaptive AMV circuit to receive the spin update control signal. The output of the second NAND gate is connected to an inverter, and the output of the second NAND gate and the output of the inverter are respectively connected to two bit lines of the SRAM storing the spin state, which is used to write the updated spin state into the SRAM storing the spin state.

9. A method for calculating the Ising machine circuit based on the ALCU model and adaptive AMV as described in any one of claims 1-8, wherein the Ising machine comprises 100 interconnected spin units, and the spin units are interconnected in an adjacent 8-unit interconnection topology; characterized in that, The calculation method includes the following steps: 1) A single spin unit stores eight 3-bit interaction coefficients and one 3-bit external magnetic field coefficient; each interaction coefficient corresponds to the interaction force between an interconnected neighboring spin unit and the current spin unit; the external magnetic field coefficient corresponds to the force exerted by an external magnetic field on the spin unit; when a spin unit is updated, the eight neighboring spin units output their spin state values ​​to the SRAM array of that spin unit; the SRAM array outputs a decision signal. , The remaining bits of the eight interaction coefficients and the external magnetic field coefficient, excluding the sign bit, are fed into the adaptive AMV circuit. 2) The adaptive AMV circuit determines the spin update factor by comparing the differentially sampled voltages. The positive and negative signs are determined, and the local spin unit state is updated through the spin update circuit in any of the following ways; Method 1: For spin update circuits based on the OF1 algorithm, when At that time, the spin update control signal ;when At that time, the spin update control signal ;exist If true, update the spin state to +1; otherwise, update the spin state to -1. in, A random signal containing 0s and 1s is injected from the outside, and The probability of the spin unit gradually decreases, and in the later stage of system convergence, the spin unit no longer randomly flips its state. Method 2: For spin update circuits based on the AF0 algorithm, when At that time, the spin update control signal ;when At that time, the spin update control signal ;exist If true, update the spin state to +1; otherwise, update the spin state to -1. in, A random signal containing 0s and 1s is injected from the outside, and The probability of the spin unit gradually decreases, and in the later stage of system convergence, the spin unit no longer randomly flips its state. 3) After the local spin unit state is updated, the state of the 8 adjacent interconnected spin units will be updated in the next cycle. All spin units will complete one round of updates within four cycles, and the spin states of two interconnected spin units will not be updated at the same time.

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