Memory structure

Abstract

The invention relates to a memory structure which comprises a memory array. The memory array is a block including six sub-blocks. The memory array includes a plurality of string selection line portions and a plurality of ground selection line portions. The plurality of string selection line portions are arranged in a first direction. Each string selection line portion is located in a corresponding sub-block. The plurality of ground selection line portions are arranged in a first direction. And each grounding selection line part is only shared by two corresponding sub-blocks. The memory structure can be a 3D NAND flash memory with high capacity and high performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and in particular to a memory structure. Background Art

[0002] Since non-volatile memory elements (eg, flash memory) have the advantage that stored data will not disappear even after power is turned off, they have become a type of memory element widely used in personal computers and other electronic devices.

[0003] The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory (such as read interference). Summary of the invention

[0004] The present invention provides a memory structure, which can effectively reduce read disturb.

[0005] The present invention provides a memory structure, including a memory array. The memory array is a block including six sub-blocks. The memory array includes a plurality of string select line sections and a plurality of ground select line sections. The plurality of string select line sections are arranged along a first direction. Each string select line section is located in a corresponding sub-block. The plurality of ground select line sections are arranged along the first direction. Each ground select line section is shared by only two corresponding sub-blocks.

[0006] According to an embodiment of the present invention, in the above memory structure, each string selection line section may include at least one string selection line.

[0007] According to an embodiment of the present invention, in the above memory structure, each ground selection line section may include at least one ground selection line.

[0008] According to an embodiment of the present invention, in the above memory structure, the memory array may include a substrate and a stacking structure. The stacking structure is located on the substrate. The stacking structure includes a plurality of insulating layers and a plurality of conductive layers stacked alternately.

[0009] According to an embodiment of the present invention, in the memory structure, a plurality of ground selection line portions may be located between a plurality of string selection line portions and a substrate.

[0010] According to an embodiment of the present invention, in the above memory structure, each string selection line portion may include at least one conductive layer in the upper portion of the stacked structure. Multiple conductive layers in the middle portion of the stacked structure may serve as multiple word lines. Each ground selection line portion may include at least one conductive layer in the lower portion of the stacked structure.

[0011] According to an embodiment of the present invention, in the above memory structure, the memory array may further include a plurality of channel pillars. The plurality of channel pillars are located in a stacked structure.

[0012] According to an embodiment of the present invention, in the above memory structure, the memory array may further include a plurality of charge storage structures, and the plurality of charge storage structures are located between the plurality of channel pillars and the plurality of word lines.

[0013] According to an embodiment of the present invention, in the above memory structure, the memory array may further include a first source line slit, a second source line slit, and a third source line slit. The first source line slit, the second source line slit, and the third source line slit may be arranged in sequence along a first direction and may extend along a second direction. The first direction may intersect the second direction.

[0014] According to an embodiment of the present invention, in the above memory structure, the six sub-blocks may include a first sub-block, a second sub-block, a third sub-block, a fourth sub-block, a fifth sub-block and a sixth sub-block arranged in sequence along a first direction. The first sub-block, the second sub-block and the third sub-block may be located between the first source line wall and the second source line wall. The fourth sub-block, the fifth sub-block and the sixth sub-block may be located between the second source line wall and the third source line wall.

[0015] According to an embodiment of the present invention, in the above-mentioned memory structure, the plurality of ground selection line portions may include a first ground selection line portion, a second ground selection line portion, and a third ground selection line portion sequentially arranged along a first direction. The first ground selection line portion may be shared by the first sub-block and the second sub-block. The second ground selection line portion may be shared by the third sub-block and the fourth sub-block. The third ground selection line portion may be shared by the fifth sub-block and the sixth sub-block.

[0016] According to an embodiment of the present invention, in the above memory structure, the memory array may further include a first isolation slit and a second isolation slit. The first isolation slit and the second isolation slit may be arranged in sequence along the first direction and may extend along the second direction. The first isolation slit may be located between the first source line slit and the second source line slit. The second isolation slit may be located between the second source line slit and the third source line slit.

[0017] According to an embodiment of the present invention, in the above memory structure, the first ground selection line portion may be located between the first source line wall and the first isolation wall. The second ground selection line portion may be located between the first isolation wall and the second isolation wall. The third ground selection line portion may be located between the second isolation wall and the third source line wall.

[0018] According to an embodiment of the present invention, in the above-mentioned memory structure, the memory array may further include a third isolation wall, a fourth isolation wall, a fifth isolation wall and a sixth isolation wall. The third isolation wall, the fourth isolation wall, the fifth isolation wall and the sixth isolation wall may be arranged in sequence along the first direction and may extend along the second direction. The first sub-block may be located between the first source line wall and the third isolation wall. The second sub-block may be located between the third isolation wall and the fourth isolation wall. The third sub-block may be located between the fourth isolation wall and the second source line wall. The fourth sub-block may be located between the second source line wall and the fifth isolation wall. The fifth sub-block may be located between the fifth isolation wall and the sixth isolation wall. The sixth sub-block may be located between the sixth isolation wall and the third source line wall.

[0019] According to an embodiment of the present invention, in the above memory structure, the third isolation wall, the fourth isolation wall, the fifth isolation wall and the sixth isolation wall may be located above the first isolation wall and the second isolation wall. The fourth isolation wall may be aligned with the first isolation wall. The fifth isolation wall may be aligned with the second isolation wall.

[0020] According to an embodiment of the present invention, in the memory structure, the second source line wall may have an opening.

[0021] According to an embodiment of the present invention, in the memory structure, the ground selection lines in the first ground selection line section can be integrally formed. The ground selection lines in the second ground selection line section can be integrally formed. The ground selection lines in the third ground selection line section can be integrally formed.

[0022] According to an embodiment of the present invention, in the above memory structure, the memory array may further include a seventh isolation wall. The seventh isolation wall may extend along the second direction. The seventh isolation wall may be located between the fourth isolation wall and the fifth isolation wall. The seventh isolation wall may be aligned with the second source line wall and the opening.

[0023] According to an embodiment of the present invention, in the above-mentioned memory structure, the ground selection line in the first ground selection line section may be integrally formed. The ground selection line in the third ground selection line section may be integrally formed. The ground selection line in the second ground selection line section may include a first conductive layer and a second conductive layer. The first conductive layer and the second conductive layer may be separated by a second source line wall. The first conductive layer and the second conductive layer may be electrically connected to each other.

[0024] According to an embodiment of the present invention, in the above memory structure, the first conductive layer may be located in the third sub-block, and the second conductive layer may be located in the fourth sub-block.

[0025] Based on the above, in the memory structure proposed by the present invention, the memory array is a block including six sub-blocks, and each ground selection line portion is only shared by two corresponding sub-blocks. Thus, when performing a read operation on the memory structure, read disturbance can be reduced.

[0026] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 FIG. 1 is a top view of a memory structure according to some embodiments of the present invention.

[0028] Figure 2 For along Figure 1 Sectional view along section line I-I'.

[0029] Figure 3 1 is a top view of a memory structure according to some other embodiments of the present invention.

[0030] Description of the accompanying drawings

[0031] 10, 20: Memory structure

[0032] 100: Base

[0033] 102: Stacked structure

[0034] 104: Insulation layer

[0035] 106, 106a, 106b: conductive layer

[0036] 106s: string selection line

[0037] 106g: Ground selection line

[0038] 108: Channel Column

[0039] 110: Channel layer

[0040] 112: Insulation column

[0041] 114: Conductive plug

[0042] 116: Charge storage structure

[0043] 118: Source column

[0044] 120: Dielectric layer

[0045] B: Block

[0046] BS, BS1, BS2, BS3, BS4, BS5, BS6: sub-blocks

[0047] D1, D2: Direction

[0048] GSL, GSL1, GSL2, GSL3: Ground selection line

[0049] IS1, IS2, IS3, IS4, IS5, IS6, IS7: The Wall

[0050] MA: Memory Array

[0051] OP: Opening

[0052] R: Repeating unit

[0053] SLIT1, SLIT2, SLIT3: Source line wall

[0054] SSL, SSL1, SSL2, SSL3, SSL4, SSL5, SSL6: string selection line

[0055] WL: Word Line DETAILED DESCRIPTION

[0056] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. For ease of understanding, the same components will be described with the same symbols in the following description. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. In fact, the size of various features may be increased or decreased arbitrarily for the sake of clarity.

[0057] Figure 1 FIG. 1 is a top view of a memory structure according to some embodiments of the present invention. Figure 2 For along Figure 1 In addition, Figure 1 In the top view, omit Figure 2 Some components in the cross-section diagram to clearly describe Figure 1 The configuration relationship between the components in.

[0058] Please refer to Figure 1 and Figure 2, the memory structure 10 includes a memory array MA. In some embodiments, the memory structure 10 may be a non-volatile memory structure, such as a three-dimensional NAND flash memory structure. The memory array MA is a block B including six sub-blocks BS. In some embodiments, the six sub-blocks BS may include sub-blocks BS1, sub-blocks BS2, sub-blocks BS3, sub-blocks BS4, sub-blocks BS5, and sub-blocks BS6 arranged in sequence along a direction D1. In addition, the number of memory arrays MA is not limited to the number in the figure. As long as the number of memory arrays MA is more than one, it falls within the scope of the present invention.

[0059] The memory array MA includes a plurality of string selection line portions SSL and a plurality of ground selection line portions GSL. The plurality of string selection line portions SSL are arranged along a direction D1. In some embodiments, the plurality of string selection line portions SSL may extend along a direction D2. The direction D1 may intersect with the direction D2. In some embodiments, the number of the string selection line portions SSL may be six. In some embodiments, the string selection line portion SSL may include a string selection line portion SSL1, a string selection line portion SSL2, a string selection line portion SSL3, a string selection line portion SSL4, a string selection line portion SSL5, and a string selection line portion SSL6 arranged in sequence along the direction D1.

[0060] Each string selection line section SSL is located in a corresponding sub-block BS. In some embodiments, the string selection line section SSL1 is located in the sub-block BS1. In some embodiments, the string selection line section SSL2 is located in the sub-block BS2. In some embodiments, the string selection line section SSL3 is located in the sub-block BS3. In some embodiments, the string selection line section SSL4 is located in the sub-block BS4. In some embodiments, the string selection line section SSL5 is located in the sub-block BS5. In some embodiments, the string selection line section SSL6 is located in the sub-block BS6.

[0061] The plurality of ground selection line portions GSL are arranged along the direction D1. In some embodiments, the plurality of ground selection line portions GSL may extend along the direction D2. In some embodiments, the number of the ground selection line portions GSL may be three. In some embodiments, the plurality of ground selection line portions GSL may include a ground selection line portion GSL1, a ground selection line portion GSL2, and a ground selection line portion GSL3 sequentially arranged along the direction D1.

[0062] Each ground selection line portion GSL is shared by only two corresponding sub-blocks BS. Thus, when performing a read operation on the memory structure 10, read interference can be reduced. In some embodiments, the ground selection line portion GSL1 can be shared by sub-block BS1 and sub-block BS2. In some embodiments, the ground selection line portion GSL2 can be shared by sub-block BS3 and sub-block BS4. In some embodiments, the ground selection line portion GSL3 can be shared by sub-block BS5 and sub-block BS6.

[0063] The memory array MA may include a substrate 100 and a stacked structure 102. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, although not shown in the figure, the memory array MA may also include a component layer (including at least one active component and / or at least one passive component, etc.) and an internal connection structure layer (including at least one internal connection structure and at least one dielectric layer, etc.) located between the substrate 100 and the stacked structure 102, and the description thereof is omitted here. In some embodiments, a plurality of ground selection line portions GSL may be located between a plurality of string selection line portions SSL and the substrate 100.

[0064] The stacked structure 102 is located on the substrate 100. The stacked structure 102 includes a plurality of insulating layers 104 and a plurality of conductive layers 106 that are alternately stacked. In some embodiments, the material of the insulating layer 104 may include silicon oxide. In some embodiments, the conductive layer 106 may include a barrier layer and a metal layer. In some embodiments, the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. In some embodiments, the material of the metal layer may include tungsten (W).

[0065] In some embodiments, each string selection line portion SSL may include at least one conductive layer 106 in the upper portion of the stack structure 102. That is, the conductive layer 106 in the upper portion of the stack structure 102 may be used as a string selection line 106s. Each string selection line portion SSL may include at least one string selection line 106s. For example, Figure 2 As shown, each string selection line section SSL may include two string selection lines 106s, but the present invention is not limited thereto. In some embodiments, the string selection lines 106s in each string selection line section SSL may be integrally formed. In some embodiments, the plurality of string selection lines 106s in each string selection line section SSL may be formed separately.

[0066] In some embodiments, the plurality of conductive layers 106 in the middle of the stack structure 102 may serve as a plurality of word lines WL. In addition, the number of word lines WL is not limited to the number shown in the figure.

[0067] Each ground selection line portion GSL may include at least one conductive layer 106 in the lower portion of the stack structure 102. That is, the conductive layer 106 in the lower portion of the stack structure 102 may be used as a ground selection line 106g. Each ground selection line portion GSL may include at least one ground selection line 106g. For example, Figure 2As shown, each ground selection line section GSL may include three ground selection lines 106g, but the present invention is not limited thereto. In some embodiments, the ground selection line 106g in the ground selection line section GSL1 may be integrally formed. In some embodiments, the multiple ground selection lines 106g in the ground selection line section GSL1 may be formed separately. In some embodiments, the ground selection line 106g in the ground selection line section GSL3 may be integrally formed. In some embodiments, the multiple ground selection lines 106g in the ground selection line section GSL3 may be formed separately. In addition, the multiple conductive layers 106 may include a conductive layer 106a and a conductive layer 106b. The ground selection line 106g in the ground selection line section GSL2 may include a conductive layer 106a and a conductive layer 106b. The conductive layer 106a and the conductive layer 106b may be separated from each other. For example, the conductive layer 106a and the conductive layer 106b may be separated by the source line wall SLIT2. The conductive layer 106a may be located in the sub-block BS3. The conductive layer 106b may be located in the sub-block BS4. The conductive layer 106a and the conductive layer 106b may be electrically connected to each other. In some embodiments, the conductive layer 106a and the conductive layer 106b may be electrically connected to each other through an interconnect structure (not shown). In some embodiments, the plurality of ground selection lines 106g in the ground selection line portion GSL2 may be formed separately.

[0068] The memory array MA may also include a plurality of channel pillars 108. The plurality of channel pillars 108 are located in the stacked structure 102. In some embodiments, the channel pillars 108 may include a channel layer 110, an insulating pillar 112, and a conductive plug 114. In some embodiments, the plurality of channel pillars 108 are arranged using 14 staggered channel pillars 108 as a repeating unit R, but the present invention is not limited thereto. In some embodiments, the material of the channel layer 110 may include polysilicon. The insulating pillar 112 is located in the channel layer 110. In some embodiments, the material of the insulating pillar 112 may include silicon oxide. The conductive plug 114 is located on the channel layer 110 and the insulating pillar 112. The material of the conductive plug 114 may include doped polysilicon.

[0069] The memory array MA may further include a plurality of charge storage structures 116. The plurality of charge storage structures 116 are located between the plurality of channel pillars 108 and the plurality of word lines WL. The plurality of charge storage structures 116 may also be located between the plurality of channel pillars 108 and the plurality of insulating layers 104. In some embodiments, the charge storage structures 116 may surround the channel pillars 108. In some embodiments, the charge storage structures 116 may be oxide / nitride / oxide (ONO) composite layers.

[0070] The memory array MA may further include a source line wall SLIT1, a source line wall SLIT2, and a source line wall SLIT3. The source line wall SLIT1, the source line wall SLIT2, and the source line wall SLIT3 may be arranged in sequence along the direction D1, and may extend along the direction D2. The source line wall SLIT1, the source line wall SLIT2, and the source line wall SLIT3 may include a source column 118 and a dielectric layer 120. In some embodiments, the material of the source column 118 may include doped polysilicon. The dielectric layer 120 is located between the source column 118 and the plurality of conductive layers 106, so that the source column 118 may be electrically insulated from the plurality of conductive layers 106. The dielectric layer 120 may also be located between the source column 118 and the plurality of insulating layers 104. In some embodiments, the material of the dielectric layer 120 may include silicon oxide.

[0071] In some embodiments, sub-blocks BS1, BS2 and BS3 may be located between source line walls SLIT1 and SLIT2. In some embodiments, sub-blocks BS4, BS5 and BS6 may be located between source line walls SLIT2 and SLIT3.

[0072] The memory array MA may further include an isolation wall IS1 and an isolation wall IS2. The isolation wall IS1 and the isolation wall IS2 may be located in the stacked structure 102. The isolation wall IS1 and the isolation wall IS2 may be arranged in sequence along the direction D1 and may extend along the direction D2. The isolation wall IS1 may be located between the source line wall SLIT1 and the source line wall SLIT2. The isolation wall IS2 may be located between the source line wall SLIT2 and the source line wall SLIT3. In some embodiments, the material of the isolation wall IS1 and the isolation wall IS2 may include an insulating material, such as silicon oxide.

[0073] In some embodiments, the ground selection line portion GSL1 and the ground selection line portion GSL2 may be separated from each other by an isolation wall IS1. In some embodiments, the ground selection line portion GSL2 and the ground selection line portion GSL3 may be separated from each other by an isolation wall IS2. In some embodiments, the ground selection line portion GSL1 may be located between the source line wall SLIT1 and the isolation wall IS1. The ground selection line portion GSL2 may be located between the isolation wall IS1 and the isolation wall IS2. The ground selection line portion GSL3 may be located between the isolation wall IS2 and the source line wall SLIT3.

[0074] The memory array MA may further include an isolation wall IS3, an isolation wall IS4, an isolation wall IS5, and an isolation wall IS6. The isolation wall IS3, the isolation wall IS4, the isolation wall IS5, and the isolation wall IS6 may be located in the stacked structure 102. The isolation wall IS3, the isolation wall IS4, the isolation wall IS5, and the isolation wall IS6 may be arranged in sequence along the direction D1, and may extend along the direction D2. In some embodiments, the isolation wall IS3, the isolation wall IS4, the isolation wall IS5, and the isolation wall IS6 may be located above the isolation wall IS1 and the isolation wall IS2. In some embodiments, the isolation wall IS4 may be aligned with the isolation wall IS1. In some embodiments, the isolation wall IS5 may be aligned with the isolation wall IS2. In some embodiments, the material of the isolation wall IS3, the isolation wall IS4, the isolation wall IS5, and the isolation wall IS6 may include an insulating material, such as silicon oxide.

[0075] In some embodiments, the string selection line portion SSL1 and the string selection line portion SSL2 may be separated from each other by an isolation wall IS3. In some embodiments, the string selection line portion SSL2 and the string selection line portion SSL3 may be separated from each other by an isolation wall IS4. In some embodiments, the string selection line portion SSL3 and the string selection line portion SSL4 may be separated from each other by a source line wall SLIT2. In some embodiments, the string selection line portion SSL4 and the string selection line portion SSL5 may be separated from each other by an isolation wall IS5. In some embodiments, the string selection line portion SSL5 and the string selection line portion SSL6 may be separated from each other by an isolation wall IS6.

[0076] In some embodiments, the string selection line portion SSL1 may be located between the source line wall SLIT1 and the isolation wall IS3. In some embodiments, the string selection line portion SSL2 may be located between the isolation wall IS3 and the isolation wall IS4. In some embodiments, the string selection line portion SSL3 may be located between the isolation wall IS4 and the source line wall SLIT2. The string selection line portion SSL4 may be located between the source line wall SLIT2 and the isolation wall IS5. The string selection line portion SSL5 may be located between the isolation wall IS5 and the isolation wall IS6. The string selection line portion SSL6 may be located between the isolation wall IS6 and the source line wall SLIT3.

[0077] In some embodiments, sub-block BS1 may be located between source line wall SLIT1 and isolation wall IS3. In some embodiments, sub-block BS2 may be located between isolation wall IS3 and isolation wall IS4. In some embodiments, sub-block BS3 may be located between isolation wall IS4 and source line wall SLIT2. Sub-block BS4 may be located between source line wall SLIT2 and isolation wall IS5. Sub-block BS5 may be located between isolation wall IS5 and isolation wall IS6. Sub-block BS6 may be located between isolation wall IS6 and source line wall SLIT3.

[0078] In some embodiments, the memory structure 10 may further include other required components (eg, an internal connection structure (not shown) located on the stack structure 102), and the description thereof is omitted here.

[0079] Based on the above embodiments, in the memory structure 10, the memory array MA is a block B including six sub-blocks BS, and each ground selection line portion GSL is only shared by two corresponding sub-blocks BS. Therefore, when performing a read operation on the memory structure 10, read disturbance can be reduced.

[0080] Figure 3 1 is a top view of a memory structure according to some other embodiments of the present invention.

[0081] Please refer to Figure 1 and Figure 3 , Figure 3 The memory structure 20 and Figure 1 The differences of the memory structure 10 are as follows. In the memory structure 20, the source line wall SLIT2 may have an opening OP. In the memory structure 20, the ground selection line 106g in the ground selection line portion GSL2 may be integrally formed. In the memory structure 20, the memory array MA may also include an isolation wall IS7. The isolation wall IS7 may extend along the direction D2. The isolation wall IS7 may be located between the isolation wall IS4 and the isolation wall IS5. The isolation wall IS7 may be aligned with the source line wall SLIT2 and the opening OP. In the memory structure 20, the string selection line portion SSL3 and the string selection line portion SSL4 may be separated from each other by the isolation wall IS7 and the source line wall SLIT2. In some embodiments, the material of the isolation wall IS7 may include an insulating material, such as silicon oxide.

[0082] In addition, in the memory structure 10 and the memory structure 20, the same or similar components are represented by the same symbols, and their description is omitted.

[0083] Based on the above embodiment, in the memory structure 20, the memory array MA is a block B including six sub-blocks BS, and each ground selection line portion GSL is only shared by two corresponding sub-blocks BS. Therefore, when performing a read operation on the memory structure 20, read disturbance can be reduced.

[0084] In summary, in the memory structure of the above embodiment, since each ground selection line portion is only shared by two corresponding sub-blocks, read disturbance can be reduced when performing a read operation on the memory structure.

[0085] Although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.

Claims

1. A memory structure, characterized in that: include: A memory array, wherein the memory array is a block including six sub-blocks, and comprises: a plurality of string selection line portions arranged along a first direction, wherein each of the string selection line portions is located in a corresponding sub-block; and A plurality of ground selection line portions are arranged along the first direction, wherein Each of the ground selection line portions is shared by only the corresponding two sub-blocks. Each of the string selection line sections includes at least one string selection line, Each of the ground selection line sections includes at least one ground selection line, and The memory array comprises: substrate; and The stacked structure is located on the substrate and includes a plurality of insulating layers and a plurality of conductive layers stacked alternately, wherein The plurality of ground selection line portions are located between the plurality of string selection line portions and the substrate.

2. The memory structure according to claim 1, wherein Each of the string selection line parts includes at least one of the conductive layers in the upper portion of the stack structure, The plurality of conductive layers in the middle portion of the stacked structure serve as a plurality of word lines, and Each of the ground selection line portions includes at least one of the conductive layers in a lower portion of the stack structure.

3. The memory structure of claim 1 , wherein the memory array further comprises: The first source line wall, the second source line wall and the third source line wall are arranged in sequence along the first direction and extend along the second direction, wherein The first direction intersects the second direction, The six sub-blocks include a first sub-block, a second sub-block, a third sub-block, a fourth sub-block, a fifth sub-block and a sixth sub-block which are sequentially arranged along the first direction. The first sub-block, the second sub-block and the third sub-block are located between the first source line wall and the second source line wall, and The fourth sub-block, the fifth sub-block, and the sixth sub-block are located between the second source line wall and the third source line wall.

4. The memory structure according to claim 3, wherein The plurality of ground selection line portions include a first ground selection line portion, a second ground selection line portion, and a third ground selection line portion which are sequentially arranged along the first direction. The first ground selection line portion is shared by the first sub-block and the second sub-block, The second ground selection line portion is shared by the third sub-block and the fourth sub-block, and The third ground selection line portion is shared by the fifth sub-block and the sixth sub-block.

5. The memory structure of claim 4, wherein the memory array further comprises: The first isolation wall and the second isolation wall are arranged in sequence along the first direction and extend along the second direction, wherein The first isolation wall is located between the first source line wall and the second source line wall, and The second isolation wall is located between the second source line wall and the third source line wall.

6. The memory structure according to claim 5, wherein The first ground selection line portion is located between the first source line wall and the first isolation wall. The second ground selection line portion is located between the first isolation wall and the second isolation wall, and The third ground selection line portion is located between the second isolation wall and the third source line wall.

7. The memory structure of claim 5, wherein the memory array further comprises: The third isolation wall, the fourth isolation wall, the fifth isolation wall and the sixth isolation wall are arranged in sequence along the first direction and extend along the second direction, wherein The first sub-block is located between the first source line wall and the third isolation wall. The second sub-block is located between the third isolation wall and the fourth isolation wall, The third sub-block is located between the fourth isolation wall and the second source line wall. The fourth sub-block is located between the second source line wall and the fifth isolation wall, The fifth sub-block is located between the fifth isolation wall and the sixth isolation wall, and The sixth sub-block is located between the sixth isolation wall and the third source line wall.

8. The memory structure of claim 7, wherein The third isolation wall, the fourth isolation wall, the fifth isolation wall and the sixth isolation wall are located above the first isolation wall and the second isolation wall. The fourth isolation wall is aligned with the first isolation wall, and The fifth isolation wall is aligned with the second isolation wall.

9. The memory structure according to claim 7, wherein the second source line wall has an opening.

10. The memory structure of claim 9, wherein the memory array further comprises: A seventh isolation wall extends along the second direction, wherein the seventh isolation wall is located between the fourth isolation wall and the fifth isolation wall and is aligned with the second source line wall and the opening.

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