Semiconductor device and power control unit

Abstract

A semiconductor device and a power control unit are provided. A semiconductor device is provided with: a semiconductor substrate (41) provided with an active region (411) and an outer peripheral region (412) in which a withstand voltage structure (413) is formed; and a temperature sensor (91) that detects the temperature of the semiconductor substrate in the outer peripheral region. The semiconductor device is electrically connected to a control device that detects whether or not there is an abnormality in the cooling system (140) on the basis of the temperature detected by the temperature sensor. The semiconductor device further includes a conductive spacer (70) on the semiconductor substrate active region. The temperature sensor does not overlap the conductive spacer in the plate thickness direction, and is disposed closer to the center side of the semiconductor substrate than the withstand voltage structure in the orthogonal direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a power control unit. Background Art

[0002] Patent document 1 describes a semiconductor device having a semiconductor substrate, a surface electrode, a field plate electrode, and a temperature sensor. The semiconductor substrate has an element portion having a functional structure and a peripheral portion having a terminal withstand voltage structure. The surface electrode is provided on the element portion. The field plate electrode is connected to the surface electrode and provided on the terminal withstand voltage structure. The temperature sensor is provided on the field plate electrode. The Joule heat generated by the element portion is conducted to the temperature sensor via the surface electrode and the field plate electrode.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 6872933 Summary of the invention

[0006] When a temperature sensor is placed on the terminal withstand voltage structure, a special structure such as a field plate electrode needs to be provided between the terminal withstand voltage structure and the temperature sensor to prevent the sensor from being affected by the electric field of the peripheral portion. It is difficult to increase the area of ​​the element portion while placing the temperature sensor on the peripheral portion without providing a special structure.

[0007] An object of the present disclosure is to provide a semiconductor device and a power control unit that can arrange a temperature sensor in a peripheral region without providing a special structure for preventing the influence of an electric field in the peripheral region and can increase the area of ​​an active region.

[0008] A semiconductor device of a technical solution disclosed in the present invention comprises: a semiconductor substrate having an active area as a formation area of ​​an element and a peripheral area surrounding the active area and forming a pressure-resistant structure when viewed in a plane in the direction of the plate thickness; and a temperature sensor for detecting the temperature of the semiconductor substrate in the peripheral area; the semiconductor device is electrically connected to a control device, and the control device detects whether there is an abnormality in a cooling system for cooling the semiconductor substrate based on the temperature detected by the temperature sensor; and further comprises a conductive spacer arranged on the active area on one side of the semiconductor substrate; the temperature sensor does not overlap with the conductive spacer in the direction of the plate thickness, and the temperature sensor is arranged closer to the center side of the semiconductor substrate than the pressure-resistant structure in an orthogonal direction orthogonal to the plate thickness direction.

[0009] Since the function required of the temperature sensor is not the maximum temperature detection of the semiconductor substrate but the abnormality detection of the cooling system, the configuration of the temperature sensor is not easily restricted. Since the temperature sensor is arranged on the center side of the semiconductor substrate closer to the pressure-resistant structure, there is no need to set a special structure to prevent the influence of the electric field caused by the pressure-resistant structure. Furthermore, since there is no overlap with the conductive spacer in the thickness direction of the plate, there is no need to set a gap in the active area for setting the temperature sensor. The temperature sensor can be arranged in the peripheral area without setting a special structure to prevent the influence of the electric field caused by the pressure-resistant structure, and the area of ​​the active area can be expanded.

[0010] A power control unit of another technical solution disclosed in the present invention comprises: a semiconductor substrate having an active area as an element formation area, and a peripheral area surrounding the active area and forming a pressure-resistant structure when observed in a plane in the direction of the plate thickness; a conductive spacer arranged on the active area on one side of the semiconductor substrate; a temperature sensor for detecting the temperature of the semiconductor substrate in the peripheral area; and a control device for detecting whether there is an abnormality in a cooling system for cooling the semiconductor substrate based on the detected temperature detected by the temperature sensor; the temperature sensor does not overlap with the conductive spacer in the direction of the plate thickness, and the temperature sensor is arranged closer to the center side of the semiconductor substrate than the pressure-resistant structure in an orthogonal direction orthogonal to the plate thickness direction.

[0011] In the power control unit as well, the temperature sensor can be arranged in the peripheral region without providing a special structure for preventing the influence of the electric field caused by the withstand voltage structure, and the area of ​​the active region can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a diagram showing a schematic configuration of a drive system of a vehicle to which the semiconductor device according to the first embodiment is applied.

[0013] Figure 2 It is a plan view showing the semiconductor device according to the first embodiment.

[0014] Figure 3 It is along Figure 2 A cross-sectional view of a semiconductor device along line III-III.

[0015] Figure 4 is a cross-sectional view of the power control unit.

[0016] Figure 5 This is a plan view of a semiconductor package substrate.

[0017] Figure 6 It is along Figure 5 Cross-sectional view of line VI-VI.

[0018] Figure 7It is along Figure 5 Cross-sectional view along line VII-VII.

[0019] Figure 8 It is a flow chart of abnormality detection of cooling system.

[0020] Fig. 9 It is a plan view showing a semiconductor substrate according to the second embodiment.

[0021] Fig.10 It is a plan view showing a semiconductor substrate according to the third embodiment.

[0022] Fig.11 It is a plan view showing a semiconductor substrate according to a fourth embodiment.

[0023] Fig.12 It is a plan view showing a semiconductor substrate according to the fifth embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, a plurality of modes for implementing the present disclosure will be described with reference to the drawings.

[0025] In each embodiment, the same reference numerals are given to the parts corresponding to the matters described in the previous embodiment, and the repeated description may be omitted. When only a part of the structure is described in each embodiment, the other embodiments described previously can be applied to the other parts of the structure.

[0026] Furthermore, not only are combinations of parts that can be combined in each embodiment explicitly described, but embodiments, embodiments and modifications, and modifications can also be partially combined even without explicit description, unless there is any particular obstacle in the combination.

[0027] (First embodiment)

[0028] The semiconductor device 20 of this embodiment is applied to, for example, a power control unit 4 of a mobile body that uses a rotating electric machine as a driving source. The mobile body is, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vertical take-off and landing machine or an unmanned aerial vehicle, a ship, a construction machine, or an agricultural machine. The following describes an example of application to a vehicle.

[0029] <Vehicle drive system>

[0030] First, based on Figure 1 A schematic configuration of a vehicle drive system 1 will be described. The vehicle drive system 1 includes a DC power supply 2 , a motor generator 3 , and a power control unit 4 .

[0031] The DC power supply 2 is a DC voltage source composed of a secondary battery that can be charged and discharged. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a driving source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power control unit 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0032] <Power Control Unit>

[0033] Next, the circuit structure of the power control unit 4 is described. The power control unit 4 includes a power conversion circuit and a control device 13. Figure 1 As shown, the power control unit 4 includes a smoothing capacitor 5 and an inverter 6 as a power conversion circuit.

[0034] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7 which is a power line on the high potential side and an N line 8 which is a power line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel with the DC power supply 2.

[0035] The inverter 6 is a DC-AC conversion circuit. The inverter 6 has a semiconductor device 20. The semiconductor device 20 of the present embodiment includes a MOSFET as a switching element. The inverter 6 converts the DC voltage into a three-phase AC voltage according to the switching control performed by the control device 13, and outputs it to the motor generator 3. As a result, the motor generator 3 is driven to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 under the rotational force from the wheels into a DC voltage according to the switching control performed by the control device 13, and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0036] The control device 13 has a control circuit that controls the on and off of the MOSFET 11. The control circuit controls the on (on) or off (off) of the plurality of MOSFETs 11. As a result, the power control unit 4 can supply three-phase AC currents with different cycles to the motor generator 3. In addition, the control device 13 may also include a drive circuit that drives the MOSFET in addition to the control circuit. The drive circuit supplies a drive current to the gate of the MOSFET 11 of the corresponding arm based on the drive instruction of the control circuit.

[0037] The control device 13 outputs a PWM signal as a drive instruction, for example. The control device 13 is composed of, for example, a processor and a memory. ECU is the abbreviation of Electronic Control Unit. PWM is the abbreviation of Pulse Width Modulation. The drive circuit drives the corresponding MOSFET 11 by applying a drive current, that is, turns on the drive or turns off the drive. There are cases where the drive circuit is called a driver.

[0038] In addition, the control device 13 and the method thereof described in the present disclosure may also be implemented by a special-purpose computer that is composed of a processor that is programmed to execute one or more functions embodied by a computer program. Alternatively, the device and the method thereof described in the present disclosure may also be implemented by a special-purpose hardware logic circuit. Alternatively, the device and the method thereof described in the present disclosure may also be implemented by one or more special-purpose computers composed of a combination of a processor that executes a computer program and one or more hardware logic circuits. In addition, the computer program may also be stored as an instruction executed by a computer in a non-movable tangible recording medium that can be read by a computer.

[0039] The inverter 6 is configured with upper and lower arm circuits 9 of three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 have an upper arm 9H and a lower arm 9L, respectively. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H being the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase of the motor generator 3 via the output line 10. The inverter 6 has six arms. At least a portion of each of the P line 7, the N line 8, and the output line 10 is composed of a conductive member such as a bus bar.

[0040] In this embodiment, an n-channel MOSFET 11 is used as a switching element constituting each arm. MOSFET is an abbreviation of Metal Oxide Semiconductor Field Effect Transistor. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other.

[0041] A freewheeling diode 12 is connected in anti-parallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11 or may be provided independently of the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0042] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation of Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in anti-parallel.

[0043] The power control unit 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the upper and lower arm circuits 9 described above. According to this structure, voltage can be increased or decreased. The power control unit 4 may also include a filter capacitor that removes power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0044] The power control unit 4 has a cooler 110 in addition to the structure described so far. The cooler 110 is a device for cooling a plurality of semiconductor devices 20. The cooler 110 is included in a cooling system 140 having a refrigerant pump 130 and the like that circulates the refrigerant in the cooler 110. The power module 120 is composed of a plurality of semiconductor devices 20 and the cooler 110. The cooler 110 is connected to a pump and the like, and the cooler 110 has a stacked cooling structure stacked in the Z direction. The cooler 110 has a supply pipe, a discharge pipe, and a plurality of relay pipes 111. The plurality of relay pipes 111 are arranged in a ladder shape between the supply pipe and the discharge pipe. The supply pipe and the discharge pipe are connected via the relay pipe 111 in a form in which the refrigerant can flow. In addition, the semiconductor devices 20 are independently accommodated between adjacent relay pipes 111. The semiconductor device 20 is clamped between adjacent relay pipes 111. The semiconductor device 20 is cooled on both sides by the cooler 110.

[0045] <Semiconductor Device>

[0046] Next, based on Figure 2 to Figure 7 The schematic structure of the semiconductor device 20 will be described. Figure 2 It is a plan view showing the semiconductor device 20 according to the first embodiment. Figure 3 It is along Figure 2 Cross-sectional view along line III-III. Figure 4 is a cross-sectional view of the power control unit 4 . Figure 5 is a plan view of the semiconductor substrate 41 . Figure 6 It is along Figure 5 Cross-sectional view of line VI-VI. Figure 7 It is along Figure 5 Cross-sectional view along line VII-VII.

[0047] In the following, the thickness direction of the semiconductor element (semiconductor substrate) is set as the Z direction. The direction orthogonal to the Z direction is set as the orthogonal direction. The first direction among the orthogonal directions is set as the Y direction. The second direction different from the first direction among the orthogonal directions is set as the X direction. Unless otherwise stated, the shape observed in a plane from the Z direction, in other words, the shape along the XY plane defined by the X direction and the Y direction is set as the plane shape. In addition, there is a case where the plane observation from the Z direction is simply expressed as a plane observation.

[0048] like Figure 2 to Figure 7 As shown, the semiconductor device 20 includes a sealing body 30, a semiconductor element 40, wiring members 50, 60, a conductive spacer 70, and an external connection terminal 80. The semiconductor device 20 also includes a bonding wire 90 and a bonding member 100. The semiconductor device 20 constitutes one of the above-mentioned arms. That is, two semiconductor devices 20 constitute the upper and lower arm circuits 9 of one phase.

[0049] The sealing body 30 seals a part of other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed outside the sealing body 30. The sealing body 30 is made of, for example, resin. An example of a resin is an epoxy resin. The sealing body 30 is made of resin and is formed, for example, by transfer molding. Such a sealing body 30 may be referred to as a sealing resin body, a molding resin, a resin molded body, etc. The sealing body 30 may also be formed using, for example, a gel. The gel is, for example, arranged in the opposing regions of a pair of wiring components 50, 60.

[0050] like Figure 2 or Figure 3 As shown, the planar shape of the sealing body 30 is roughly rectangular. In the sealing body 30, there is a surface 30a as a surface forming an outer contour and a back surface 30b which is opposite to the surface 30a in the Z direction. The surface 30a and the back surface 30b are, for example, roughly flat surfaces. In addition, there are side surfaces 30c, 30d, 30e, and 30f connected to the surface 30a and the back surface 30b. The side surface 30c is a surface from which the main terminals 81 and 82 of the external connection terminal 80 protrude. The side surface 30d is a surface opposite to the side surface 30c in the Y direction. The side surface 30d is a surface from which the signal terminal 83 protrudes. The side surfaces 30e and 30f are surfaces from which the external connection terminal 80 does not protrude. The side surface 30e is a surface opposite to the side surface 30f in the X direction.

[0051] The semiconductor element 40 includes a semiconductor substrate 41, a source electrode 42, a drain electrode 43 and a pad 44. In addition, a gate electrode (not shown) is also formed on the semiconductor substrate 41. As an example, the gate electrode has a groove structure. The gate electrode may not have a groove structure. The gate electrode may also have a planar structure. The semiconductor element 40 is sometimes referred to as a semiconductor chip. The semiconductor substrate 41 is formed into a vertical element using silicon (Si), a wide bandgap semiconductor having a wider bandgap than silicon, etc. as a material. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond.

[0052] The vertical element is configured so that the main current flows in the thickness direction of the semiconductor substrate 41. The semiconductor element 40 is arranged so that the thickness direction is substantially parallel to the Z direction. The semiconductor element 40 has main electrodes on both sides in the thickness direction. On the semiconductor substrate 41 made of SiC, an n-channel MOSFET 11 is formed as a vertical element to obtain the semiconductor substrate 41 of this embodiment. Figure 3 As shown, the semiconductor substrate 41 has a source electrode 42 as a main electrode on a surface 41 a facing the wiring member 50 , and has a drain electrode 43 on a back surface 41 b opposite to the surface 41 a .

[0053] When the MOSFET 11 is turned on, a current (main current) flows between the main electrodes, that is, between the drain electrode 43 and the source electrode 42. When the diode 12 is a parasitic diode, the source electrode 42 also serves as an anode electrode, and the drain electrode 43 also serves as a cathode electrode. The diode 12 may also be formed in a chip independent of the MOSFET 11. The drain electrode 43 is a main electrode on the high potential side, and the source electrode 42 is a main electrode on the low potential side. The drain electrode 43 is formed on substantially the entire area of ​​the lower surface. The source electrode 42 is formed on a portion of the upper surface.

[0054] The pad 44 is a signal electrode. The pad 44 is formed in a region different from the region where the source electrode 42 is formed on one side 41a of the semiconductor substrate 41. Figure 5 As shown, the semiconductor substrate 41 has five pads 44. Specifically, it has a gate pad 44G, a Kelvin source pad 44KS, a cathode potential detection pad 44K of the temperature sensor 91, an anode potential detection pad 44A of the temperature sensor 91, and a current sensor pad 44SS.

[0055] The five pads 44 are arranged along the X direction. From the side surface 30f toward the side surface 30e, the five pads 44 are arranged in the order of Kelvin source pad 44KS, current sensor pad 44SS, gate pad 44G, anode potential detection pad 44A, and cathode potential detection pad 44K. Each pad 44 is electrically connected to the corresponding signal terminal 83 via a bonding wire 90. Two adjacent pads 44 are separated to a degree that can ensure the insulation of the bonding wire 90. In addition, the number and arrangement order of the pads 44 are not limited to this.

[0056] The wiring member 50 is electrically connected to the source electrode 42 and provides a wiring function. Similarly, the wiring member 60 is electrically connected to the drain electrode 43 and provides a wiring function. The wiring members 50 and 60 are arranged in a manner to sandwich the semiconductor element 40 in the Z direction. The wiring members 50 and 60 are arranged in a manner to face each other at least partially in the Z direction. The wiring members 50 and 60 cover the semiconductor element 40 in a planar view.

[0057] The wiring components 50 and 60 provide a heat dissipation function for dissipating the heat generated by the semiconductor element 40. The wiring components 50 and 60 may be referred to as heat sinks, heat sinks, etc. The wiring components 50 and 60 of the present embodiment are metal plates made of metals with good conductivity such as Cu and Cu alloys. The metal plate is provided as a part of a lead frame, for example. Instead of the metal plate, a substrate having a metal body arranged on both sides of an insulating substrate may be used. The wiring components 50 and 60 may also have a plated film of Ni, Au, etc. on the metal surface.

[0058] The wiring component 50 has an opposing surface 50a on the side of the semiconductor element 40 and a back surface 50b opposite to the opposing surface 50a. Similarly, the wiring component 60 also has an opposing surface 60a and a back surface 60b. The wiring components 50, 60 are, for example, roughly rectangular in plan view. The back surfaces 50b, 60b of the wiring components 50, 60 are respectively exposed from the sealing body 30. There are cases where the back surfaces 50b, 60b are referred to as heat dissipation surfaces, exposed surfaces, etc. The back surface 50b of the wiring component 50 is roughly coplanar with one surface 30a of the sealing body 30. The back surface 60b of the wiring component 60 is roughly coplanar with the back surface 30b of the sealing body 30.

[0059] The conductive spacer 70 is interposed between the semiconductor element 40 and the wiring member 50. The conductive spacer 70 provides a spacer function of ensuring a predetermined distance between the semiconductor element 40 and the wiring member 50. When the corresponding signal terminal 83 is connected to the pad 44 of the semiconductor element 40 by the bonding wire 90, the conductive spacer 70 ensures the protrusion height of the bonding wire 90. The conductive spacer 70 is located in the middle of the conductive and thermal conductive path between the source electrode 42 of the semiconductor element 40 and the wiring member 50, and provides a wiring function and a heat dissipation function.

[0060] The conductive spacer 70 contains a metal material with good electrical and thermal conductivity such as Cu (copper). The conductive spacer 70 may also have a plated film on the surface. The conductive spacer 70 may be called a terminal, a metal block, etc. The semiconductor device 20 has the same number of conductive spacers 70 as the semiconductor element 40. The conductive spacer 70 is connected to the semiconductor element 40 separately. The conductive spacer 70 is, for example, a columnar body.

[0061] The external connection terminal 80 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 80 is formed of a metal material with good conductivity such as copper. The external connection terminal 80 is, for example, a plate. There are cases where the external connection terminal 80 is called a lead. The external connection terminal 80 includes main terminals 81, 82 and a signal terminal 83. The main terminals 81, 82 are external connection terminals 80 electrically connected to the main electrodes of the semiconductor element 40.

[0062] The main terminal 81 is electrically connected to the source electrode 42. The main terminal 81 may be referred to as a source terminal. The main terminal 81 is connected to the source electrode 42 via the wiring member 50. The main terminal 81 is connected to one end of the wiring member 50 in the Y direction. The thickness of the main terminal 81 is thinner than that of the wiring member 50. The main terminal 81 is connected to the wiring member 50 in a manner that is substantially coplanar with the opposing surface 50a, for example. The main terminal 81 may be connected to the wiring member 50 by being continuously and integrally provided, or may be provided as a separate component and connected by bonding.

[0063] The main terminal 81 of this embodiment is provided integrally with the wiring member 50 as a part of the lead frame. The main terminal 81 extends from the wiring member 50 in the Y direction and protrudes to the outside from the side surface 30c of the sealing body 30. The main terminal 81 has a bent portion in the middle of the portion covered by the sealing body 30 and protrudes from the side surface 30c near the center in the Z direction.

[0064] The main terminal 82 is electrically connected to the drain electrode 43. The main terminal 82 may be referred to as a drain terminal. The main terminal 82 is connected to the drain electrode 43 via the wiring member 60. The main terminal 82 is connected to one end of the wiring member 60 in the Y direction. The thickness of the main terminal 82 is thinner than that of the wiring member 60. The main terminal 82 is connected to the wiring member 60 in a manner that is substantially coplanar with the opposing surface 60a, for example. The main terminal 82 may be connected to the wiring member 60 by being continuously and integrally provided, or may be provided as a separate component and connected by bonding.

[0065] The main terminal 82 of this embodiment is provided integrally with the wiring member 60 as a part of a lead frame different from the main terminal 81. The main terminal 82 extends from the wiring member 60 in the Y direction and protrudes to the outside from the same side surface 30c as the main terminal 81. The main terminal 82 also has a bent portion in the middle of the portion covered by the sealing body 30, and protrudes from the side surface 30c near the center in the Z direction. The two main terminals 81 and 82 are arranged in the X direction so that the side surfaces face each other.

[0066] The signal terminal 83 is electrically connected to the corresponding pad 44 of the semiconductor element 40. The signal terminal 83 is electrically connected to the pad 44 via the bonding wire 90. The signal terminal 83 extends in the Y direction and protrudes from the side surface 30d of the sealing body 30 to the outside. The semiconductor device 20 of this embodiment has five signal terminals 83 corresponding to the pad 44. The five signal terminals 83 are arranged in the X direction. The signal terminal 83 is provided, for example, on a lead frame common to the wiring member 60 and the main terminal 82. The plurality of signal terminals 83 are electrically separated from each other by cutting a tie bar (not shown).

[0067] The bonding material 100 is interposed between the elements constituting the semiconductor device 20 to bond the elements to each other. The bonding material 100 is, for example, solder. The semiconductor device 20 includes a plurality of bonding materials 100. One of the bonding materials 100 is interposed between the source electrode 42 and the conductive spacer 70 to bond the source electrode 42 to the conductive spacer 70. Another of the bonding materials 100 is interposed between the conductive spacer 70 and the wiring component 50 to bond the conductive spacer 70 to the wiring component 50. Another of the bonding materials 100 is interposed between the drain electrode 43 of the semiconductor element 40 and the wiring component 60 to bond the drain electrode 43 to the wiring component 60.

[0068] The semiconductor element 40 is arranged between the wiring components 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched by the wiring components 50 and 60 arranged opposite to each other. As a result, the heat of the semiconductor element 40 can be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the wiring component 50 is roughly coplanar with the one surface 30a of the sealing body 30. The back surface 60b of the wiring component 60 is roughly coplanar with the back surface 30b of the sealing body 30. Since the back surfaces 50b and 60b are exposed surfaces, the heat dissipation can be improved.

[0069] <Semiconductor substrate>

[0070] The planar shape of the semiconductor substrate 41 is approximately rectangular. Figure 5As shown, the semiconductor substrate 41 includes an active region 411 and a peripheral region 412. The active region 411 is a region where vertical elements are formed. The active region 411 is sometimes referred to as a main region, a cell region, etc. In the figure, in order to distinguish the active region 411 from the peripheral region 412, the active region 411 is hatched in a plan view.

[0071] The active region 411 includes a central active region 411a, a right end active region 411b, and a left end active region 411c. The planar shape of the central active region 411a is substantially rectangular. The central active region 411a and the pad 44 are arranged in the Y direction. The central active region 411a covers the conductive spacer 70 in a planar view. Figure 5 The conductive spacer 70 is indicated by a two-dot chain line. In addition, the central active region 411a is sometimes referred to as a main region. The right end active region 411b and the left end active region 411c are sometimes referred to as extension regions.

[0072] The right end active region 411b is connected to the right end of the end on the side of the pad 44 in the central active region 411a. The right end is the end on the side of the side 30e. The left end active region 411c is connected to the left end on the side of the pad 44 in the central active region 411a. The left end is the end on the side of the side 30f. The active region 411 is roughly U-shaped when viewed from a plane. A plurality of cells (unit structure) are provided in the active region 411. The plurality of cells are connected in parallel to each other to form a MOSFET.

[0073] The peripheral region 412 surrounds the active region 411 in plan view. Figure 6 The double-dashed line shown indicates the boundary between the active region 411 and the peripheral region 412. The peripheral region 412 includes a first peripheral region 412a and a second peripheral region 412b. The first peripheral region 412a corresponds to an annular region surrounding the active region 411 and the first peripheral region 412a along the periphery of the semiconductor substrate 41. The second peripheral region 412b corresponds to a region of the peripheral region 412 adjacent to the central active region 411a, the right end active region 411b, and the left end active region 411c. The second peripheral region 412b can also be said to be a region surrounded by the central active region 411a, the right end active region 411b, and the left end active region 411c.

[0074] A voltage-resistant structure 413 is formed in the first peripheral region 412a. As an example, in the present embodiment, a guard ring is formed as the voltage-resistant structure 413. The voltage-resistant structure 413 is configured in a ring shape along the periphery of the semiconductor substrate 41. In addition, an insulating film 414 is provided on one side 41a of the semiconductor substrate 41 corresponding to the peripheral region 412. In addition, although not shown in the figure, a gate insulating film is formed on the wall surface of the groove (groove). A gate electrode is formed on the surface of the gate insulating film to fill the groove. In addition, although not shown in the figure, an insulating film 414 is provided in a manner to cover the gate electrode.

[0075] The semiconductor element 40 further includes a protective film 45 disposed on the insulating film 414. The protective film 45 is provided on the insulating film 414 so as to cover the peripheral portion of the source electrode 42. As a material of the protective film 45, for example, polyimide, silicon nitride film, or the like can be used.

[0076] The protective film 45 has a first opening 451a and a second opening 451b. The first opening 451a defines a bonding area between the source electrode 42 and the bonding member 100. The first opening 451a and the second opening 451b are through holes that penetrate the protective film 45 in the Z direction. The first opening 451a is arranged so as to overlap with the source electrode 42 when viewed from above. The first opening 451a is substantially consistent with the active area 411 when viewed from above. The second opening 451b is arranged so as to overlap with the pad 44 when viewed from above. The second opening 451b is provided in five pieces corresponding to each pad. The second opening 451b will be described later.

[0077] The source electrode 42 has a first exposed portion 421a exposed from the first opening 451a of the protection film 45 and providing a bonding region with the conductive spacer 70. The first exposed portion 421a is disposed on the active region 411 of the semiconductor substrate 41. The source electrode 42 has a multilayer structure. The source electrode 42 has a base electrode 422 and a connection electrode 423.

[0078] The base electrode 422 is a metal layer disposed on the semiconductor substrate 41 side in the multilayer source electrode 42. As an example, the base electrode 422 is formed of a material having Al (aluminum) as a main component. The base electrode 422 of this embodiment is formed of an Al alloy such as AlSi, AlSiCu, etc. The base electrode 422 may be referred to as a wiring electrode, a base layer, a first metal layer, etc.

[0079] The base electrode 422 covers the active region 411 in a planar view and extends to the peripheral region 412. The base electrode 422 is connected to the source and anode of the vertical element. The base electrode 422 is connected to the insulating film 414 in an orthogonal direction. The protective film 45 is arranged on the insulating film 414 so as to cover the peripheral portion of the base electrode 422.

[0080] The connecting electrode 423 is stacked on the base electrode 422. The connecting electrode 423 is also called an upper electrode, an upper electrode, an upper layer, an upper layer, or a second metal layer. The connecting electrode 423 contains at least a metal in order to be welded to the conductive spacer 70. The connecting electrode 423 may contain a non-metal together with the metal. The connecting electrode 423 is stacked on the base electrode 422 in the first opening 451a of the protective film 45. The outer peripheral end of the connecting electrode 423 is in contact with the inner peripheral surface of the protective film 45 defining the first opening 451a. A first exposed portion 421a is provided on the outer surface of the connecting electrode 423.

[0081] The pad 44 also has the same structure as the source electrode 42. The base electrode 422 of the pad 44 is arranged on the semiconductor substrate 41 side in the source electrode 42 of the multilayer structure. The connection electrode 423 of the pad 44 is stacked and arranged on the base electrode 422 of the pad 44. The source electrode 42 of the pad 44 has a second exposed portion 421b exposed from the second opening 451b of the protective film 45 and providing a bonding area between the bonding wire 90. The outer peripheral end of the connection electrode 423 of the pad 44 is in contact with the inner peripheral surface of the protective film 45 defining the second opening 451b. The second exposed portion 421b is provided on the outer surface of the connection electrode 423 of the pad 44.

[0082] In addition, the semiconductor element 40 includes a gate wiring 46 as a wiring portion. The gate wiring 46 is arranged at a position that does not overlap with the source electrode 42 and the pad 44 in a planar view, and is covered by a protective film 45. The gate wiring 46 electrically connects the gate electrode of the MOSFET 11 formed on the semiconductor substrate 41 to the gate pad 44G. The gate wiring 46 is, for example, a metal wiring formed of a material having Al (aluminum) as a main component. The gate wiring 46 is electrically connected to the gate electrode via a wiring not shown in the figure.

[0083] As an example, the gate wiring 46 of the present embodiment is arranged in its entirety on the first peripheral region 412a. The gate wiring 46 is arranged in a ring shape so as to surround the active region 411 and the second peripheral region 412b. The voltage-resistant structure 413 is formed in a ring shape along the periphery of the semiconductor substrate 41 so as to surround the gate wiring 46. In plan view, the gate wiring 46 is arranged closer to the active region 411 and the second peripheral region 412b than the voltage-resistant structure 413. In plan view, the voltage-resistant structure 413 is arranged away from the active region 411 and the second peripheral region 412b to the outside to the extent that the gate wiring 46 can be arranged.

[0084] <Temperature Sensor>

[0085] The semiconductor device 20 has a temperature sensor 91. The temperature sensor 91 has a P-type anode region 92 and an N-type cathode region 93. The anode region 92 and the cathode region 93 constitute a PN diode. The anode region 92 and the cathode region 93 are formed by doping impurities into polysilicon arranged on the semiconductor substrate 41. The temperature sensor 91 is provided in an inactive region. The anode region 92 and the cathode region 93 are covered by an insulating film 414. The anode region 92 is electrically connected to the anode potential detection pad 44A, and the cathode region 93 is electrically connected to the cathode potential detection pad 44K via a portion of the polysilicon wiring covered by the insulating film 414, namely, the wiring 415. The anode potential detection pad 44A and the cathode potential detection pad 44K are electrically connected to the control device 13 via the bonding wire 90 and the signal terminal 83.

[0086] The control device 13 applies a positive voltage to the anode region 92 relative to the cathode region 93, and controls so that a certain current flows between the anode region 92 and the cathode region 93. When the semiconductor device 20 is in the on mode, since the current flows in the active region 411, Joule heat is generated in the active region 411. As a result, the temperature of the semiconductor substrate 41 rises. Then, the forward voltage of the PN diode of the temperature sensor 91 changes depending on the temperature of the semiconductor substrate 41. The control device 13 measures the forward voltage of the PN diode of the temperature sensor 91, and detects the temperature based on the measured value.

[0087] Generally, it is known that in the semiconductor substrate 41, the temperature increases as it is closer to the center of the active region 411. When the temperature sensor 91 is used for the purpose of overheat protection of the semiconductor substrate 41, the temperature sensor 91 is often arranged near the center where the temperature is the highest. Thus, the temperature sensor 91 can detect the maximum temperature of the semiconductor substrate 41. By detecting the maximum temperature with the temperature sensor 91, overheating of the semiconductor substrate 41 can be suppressed in a timely manner.

[0088] In the present embodiment, the temperature sensor 91 is not provided at the center of the active area 411. In the present embodiment, the temperature sensor 91 is provided in the second peripheral area 412b. The temperature sensor 91 of the present embodiment does not detect the maximum temperature but detects the temperature of the second peripheral area 412b. In the present embodiment, the temperature sensor 91 is used for the purpose of detecting an abnormality of the cooling system 140. The abnormality detection of the cooling system 140 will be described later.

[0089] The configuration of the temperature sensor 91 is further described below. As described above, in planar observation, the conductive spacer 70 is enclosed by the central active region 411a. The second peripheral region 412b is a region surrounded by the central active region 411a, the right end active region 411b, and the left end active region 411c. In addition, the second peripheral region 412b is surrounded in a ring shape by the first peripheral region 412a provided with a pressure-resistant structure 413. Thus, the temperature sensor 91 does not overlap with the conductive spacer 70 in planar observation, and can also be said to be arranged on the center side of the semiconductor substrate 41 closer to the pressure-resistant structure 413 in the orthogonal direction. More specifically, the temperature sensor 91 is arranged in the gap between the anode potential detection pad 44A and the cathode potential detection pad 44K in the second peripheral region 412b. In addition, the configuration of the temperature sensor 91 is not limited to this.

[0090] As described above, the semiconductor device 20 is cooled by the cooler 110. Since the heat of the semiconductor substrate 41 is dissipated by the cooler 110, the temperature of the semiconductor substrate 41 decreases compared to the case where the semiconductor device 20 is not cooled by the cooler 110. The temperature sensor 91 detects the actual temperature of the second peripheral region 412b in a state where the heat of the semiconductor substrate 41 is dissipated by the cooler 110. The actual temperature detected by the temperature sensor 91 may be referred to as the detected temperature.

[0091] The temperature sensor 91 is electrically connected to the control device 13. The control device 13 has a first control unit 14 and a second control unit 15. The first control unit 14 has the above-mentioned drive circuit and control circuit. When the actual temperature of the detection object area in the semiconductor substrate 41 is outside the assumed temperature range described later, the second control unit 15 detects that an abnormality has occurred in the cooling system 140. In addition, as an example, the detection object area is the second peripheral area 412b. In this embodiment, as an example, an example of applying the second control unit 15 to a personal computer is adopted. In the figure, the first control unit 14 is abbreviated as "1CTR". The second control unit 15 is abbreviated as "2CTR".

[0092] The second control unit 15 includes a computing unit 16 such as a CPU, a storage unit 17 including a volatile memory such as a RAM and a non-volatile memory such as a ROM, and an input / output interface (not shown). The computing unit 16 of the second control unit 15 executes a program stored in the storage unit 17. The computing unit 16 performs various computing processes by executing the program. The computing unit 16 executes a predetermined formula when performing various computing processes. In addition, the computing unit 16 performs computing processes using various signals input to the interface.

[0093] The storage unit 17 stores the assumed temperature of the detection target area. The assumed temperature is the temperature of the second outer peripheral area 412b having a predetermined temperature range detected by the temperature sensor 91 when it is assumed that there is no blockage in the cooling system 140 and the refrigerant flows normally. The calculation unit 16 includes a temperature acquisition unit 16A, a temperature comparison unit 16B, and an abnormality detection unit 16C as functional blocks. The second control unit 15 can detect whether an abnormality has occurred in the cooling system 140 by executing each functional block.

[0094] Figure 8 This is a flowchart of abnormality detection of the cooler 110 performed by the second control unit 15. In step S10, the temperature acquisition unit 16A acquires the actual temperature of the detection target area in the semiconductor substrate 41. In step S20, the temperature comparison unit 16B compares the actual temperature of the detection target area with the assumed temperature. In step S30, when the actual temperature is outside the assumed temperature range, if the abnormality detection unit 16C detects that the cooling system 140 has an abnormality in step S40, the process proceeds to "end". Then, the control device 13 performs a protection action to protect the inverter 6. In addition, the protection action may be performed by the second control unit 15 or not. The protection action only needs to be performed by the control device 13. It is sufficient as long as the control device 13 includes a protection unit that performs the protection action of the inverter 6. In addition, in step S30, when the actual temperature is within the assumed temperature range, if the abnormality detection unit 16C detects that the cooling system 140 has no abnormality in step S50, the process returns to "start". When the actual temperature is within the assumed temperature range in step S30 , the process is repeated until an abnormality in the cooling system 140 is detected.

[0095] In the figure, the calculation unit 16 is abbreviated as “ALU”. The temperature acquisition unit 16A is abbreviated as “TAS”. The temperature comparison unit 16B is abbreviated as “TCS”. The abnormality detection unit 16C is abbreviated as “ADS”. The storage unit 17 is abbreviated as “STU”.

[0096] <Current Sensor>

[0097] The semiconductor device 20 further includes a current sensor 94. The current sensor 94 has a function of detecting an overcurrent flowing through the vertical element. The current sensor 94 includes a smaller number of unit cells than the main semiconductor element 11, and has the same structure as the vertical element.

[0098] The current sensor 94 has an active region with a smaller surface area in the semiconductor substrate 41 than the main vertical element. In the current sensor 94 with a small surface area, the leakage current of the gate insulating film caused by static electricity generated during the manufacturing process becomes higher. Therefore, compared with the main vertical element, the ESD tolerance of the current sensor 94 is reduced, and the insulation breakdown is easy. In this embodiment, as described above, a gap with a predetermined distance that can maintain the insulation of the adjacent bonding wires 90 is provided between two adjacent pads 44. The width of the gap between the two pads 44 is shorter than the length of the pad 44 in the Y direction. The current sensor 94 of this embodiment is provided in the gap between the gate pad 44G and the current sensor pad 44SS in the X direction.

[0099] The length of the current sensor 94 in the X direction is equivalent to the width of the gap in the X direction. The length of the current sensor 94 in the Y direction is equivalent to the length of the pad 44 in the Y direction. The length of the current sensor 94 in the X direction is longer than the length of the current sensor 94 in the Y direction. In the present embodiment, since the width of the gap between the two pads 44 is specified by the design conditions, the surface area of ​​the current sensor 94 is increased by making the length of the current sensor 94 in the Y direction longer than the length of the current sensor 94 in the X direction. As a result, it is easy to suppress the reduction of ESD tolerance.

[0100] <Effects>

[0101] The semiconductor device 20 includes a semiconductor substrate 41 and a temperature sensor 91. The semiconductor substrate 41 includes an active region 411 and a peripheral region 412. The active region 411 is a region where a vertical element is formed. The peripheral region 412 surrounds the active region 411 in a plan view and is formed with a pressure-resistant structure 413. The temperature sensor 91 detects the temperature of the semiconductor substrate 41. The semiconductor device 20 is electrically connected to the control device 13. The control device 13 has a function of detecting whether a cooling system 140 that cools the semiconductor substrate 41 has an abnormality based on the detected temperature detected by the temperature sensor 91.

[0102] The semiconductor device 20 further includes a source electrode 42, a drain electrode 43, and a conductive spacer 70. The source electrode 42 is disposed on the active region 411 on one side 41a of the semiconductor substrate 41 and is electrically connected to the vertical element. The drain electrode 43 is disposed on the back surface and is electrically connected to the vertical element. The conductive spacer 70 is provided on the source electrode 42 and is connected to the source electrode 42. A temperature sensor 91 is disposed in a manner that does not overlap with the conductive spacer 70 in the Z direction and is closer to the center of the semiconductor substrate 41 than the withstand voltage structure 413 in the orthogonal direction.

[0103] When the function of the temperature sensor 91 is to detect the maximum temperature of the semiconductor substrate 41, it is required to be arranged near the center in the orthogonal direction of the semiconductor substrate 41 with the highest temperature as described above. However, in the present embodiment, the function of the temperature sensor 91 is to detect an abnormality in the cooling system 140. Therefore, it is not necessary to arrange the temperature sensor 91 near the center in the orthogonal direction of the semiconductor substrate 41. It is not easy to impose restrictions on the arrangement of the temperature sensor 91.

[0104] When the temperature sensor 91 is disposed on the withstand voltage structure 413, a special structure such as a field plate electrode needs to be provided in order to prevent the temperature sensor 91 from being affected by the electric field of the withstand voltage structure 413. However, in the present embodiment, the temperature sensor 91 is provided in a region closer to the center of the semiconductor substrate 41 than the peripheral region 412. Therefore, it is not necessary to provide a special structure such as a field plate electrode to prevent the temperature sensor 91 from being affected by the electric field of the withstand voltage structure 413. The electric field can be suppressed from being concentrated on the temperature sensor 91.

[0105] In addition, when the temperature sensor 91 and the conductive spacer 70 overlap in the Z direction, the active region 411 is reduced according to the area of ​​the temperature sensor 91. However, in the present embodiment, the temperature sensor 91 and the conductive spacer 70 do not overlap in the Z direction. Therefore, it is possible to suppress the reduction of the active region 411 in the area of ​​the temperature sensor 91. That is, the temperature sensor 91 can be arranged in the peripheral region 412 without providing a special structure for preventing the influence of the electric field of the withstand voltage structure 413, and the area of ​​the active region 411 can be expanded.

[0106] The semiconductor device 20 has a plurality of pads 44 disposed on the peripheral region 412. The plurality of pads 44 are disposed away from the conductive spacer 70 in the Y direction. The plurality of pads 44 are disposed with gaps in the X direction. A temperature sensor 91 is disposed between two adjacent pads 44. The active region 411 can be expanded to a region adjacent to the pads 44.

[0107] The active region 411 includes a central active region 411a, a right end active region 411b, and a left end active region 411c. The central active region 411a and a plurality of pads 44 are arranged in the Y direction. The right end active region 411b is connected to the right end of the end portion on the pad 44 side in the central active region 411a. The left end active region 411c is connected to the left end of the end portion on the pad 44 side in the right end active region 411b. The active region 411 can be expanded into the central active region 411a, the right end active region 411b, and the left end active region 411c. The active region 411 can be expanded.

[0108] The power control unit 4 includes the semiconductor device 20 and the control unit 13 described above. The control unit 13 detects whether there is an abnormality in the cooling system 140 that cools the semiconductor substrate 41 based on the detected temperature detected by the temperature sensor 91. The power control unit 4 also achieves the same effect.

[0109] The control device 13 includes a storage unit 17, a temperature acquisition unit 16A, a temperature comparison unit 16B, and an abnormality detection unit 16C. The storage unit 17 stores an assumed temperature having a predetermined temperature range, which is detected by the temperature sensor 91 assuming that the refrigerant normally flows in the cooling system 140. The temperature acquisition unit 16A acquires the actual temperature of the semiconductor substrate 41 detected by the temperature sensor 91, that is, the actual temperature. The temperature comparison unit 16B compares the actual temperature of the semiconductor substrate 41 with the assumed temperature. The abnormality detection unit 16C detects that the cooling system 140 has an abnormality when the actual temperature is outside the assumed range. The abnormality of the cooling system 140 can be detected based on the temperature detected by the temperature sensor 91.

[0110] (Second embodiment)

[0111] The specific forms of the second to fifth embodiments are described below. Figures 9 to 12 The description of the voltage-resistant structure 413 and the gate wiring 46 in the semiconductor substrate 41 is omitted. Fig. 9 1 is a plan view of a semiconductor substrate 41 according to the second embodiment. In the second embodiment, the active region 411 does not include the right end active region 411b and the left end active region 411c, but only includes the central active region 411a. Thus, the same effect as that of the first embodiment is achieved. In addition, the semiconductor device 20 may not include the current sensor 94.

[0112] (Third embodiment)

[0113] Fig.10: is a plan view showing a semiconductor substrate 41 of the third embodiment. The third embodiment changes the configuration of the temperature sensor 91 from the structure of the second embodiment. In the third embodiment, the temperature sensor 91 is provided in a form adjacent to the right side in the X direction of one of the five pads 44 located at the end in the X direction. As an example, the temperature sensor 91 is provided adjacent to the cathode potential detection pad 44K. As another example, the temperature sensor 91 may be provided adjacent to the Kelvin source pad 44KS. Thus, the same effect as the first embodiment is achieved.

[0114] (Fourth embodiment)

[0115] Fig.11 FIG. 4 is a plan view showing a semiconductor substrate 41 according to the fourth embodiment. Fig.11 In the embodiment, five pads 44 are provided near the end in the X direction. As an example, when five pads 44 are provided near the left end, the active region 411 has a central active region 411a and a right end active region 411b. The temperature sensor 91 is provided between two pads 44, or is provided adjacent to the end of the five pads 44 in the X direction. In particular, if the temperature sensor 91 is provided between two pads 44, the range of the right end active region 411b will not be narrowed. The active region 411 can be expanded.

[0116] (Fifth embodiment)

[0117] Fig.12 1 is a plan view showing a semiconductor substrate 41 according to the fifth embodiment. In the fifth embodiment, four pads 44 are provided. The number of pads 44 is not limited to 5. This also provides the same effects as those of the first embodiment.

[0118] The present disclosure is described based on the embodiments, but it should be understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also includes various deformation forms and deformations within the equivalent range. In addition, various combinations and forms are shown in the present disclosure, but other combinations and forms that only contain one element, more or less elements, also fall within the scope and scope of the present disclosure.

Claims

1. A semiconductor device, have: A semiconductor substrate having an active region as a region for forming an element and a peripheral region surrounding the active region in a planar view in a thickness direction and having a pressure-resistant structure; and a temperature sensor for detecting a temperature of the semiconductor substrate in the peripheral region; The semiconductor device is electrically connected to a control device, and the control device detects whether a cooling system for cooling the semiconductor substrate has an abnormality based on the temperature detected by the temperature sensor. The semiconductor device is characterized in that A conductive spacer is further provided on one side of the semiconductor substrate and is disposed on the active region. The temperature sensor does not overlap with the conductive spacer in the plate thickness direction, and is arranged closer to the center of the semiconductor substrate than the withstand voltage structure in a direction orthogonal to the plate thickness direction.

2. The semiconductor device according to claim 1, wherein A plurality of pads are provided, which are electrodes for signals and are arranged on the outer peripheral area on the one surface. In a first direction which is one of the orthogonal directions, the plurality of pads are arranged apart from the conductive spacer. In a second direction different from the first direction among the orthogonal directions, the plurality of pads are arranged with gaps therebetween. The temperature sensor is disposed between two of the pads, or is disposed adjacent to the pad at the end in the second direction.

3. The semiconductor device according to claim 2, wherein: The above active area has: A main area arranged with the plurality of pads in the first direction; and The extended region is a region having an area smaller than that of the main region when viewed in the planar view, is connected to an end portion of the main region located on the pad side, and is arranged in parallel with the pad in the second direction.

4. A power control unit, characterized in that: have: A semiconductor substrate having an active region as a region for forming an element and a peripheral region surrounding the active region in a planar view in a thickness direction and having a pressure-resistant structure; A conductive spacer is disposed on the active area in one surface of the semiconductor substrate; a temperature sensor for detecting a temperature of the semiconductor substrate in the peripheral region; as well as The control device detects whether there is an abnormality in a cooling system for cooling the semiconductor substrate based on the detected temperature detected by the temperature sensor. The temperature sensor does not overlap with the conductive spacer in the plate thickness direction, and is arranged closer to the center of the semiconductor substrate than the withstand voltage structure in a direction orthogonal to the plate thickness direction.

5. The power control unit according to claim 4, characterized in that: The control device has: a storage unit storing an assumed temperature of the semiconductor substrate having a predetermined temperature range detected by the temperature sensor assuming that a refrigerant normally flows in the cooling system; a temperature acquisition unit that acquires the actual temperature of the semiconductor substrate detected by the temperature sensor; a temperature comparison unit, which compares the actual temperature with the assumed temperature; as well as The abnormality detection unit detects that an abnormality occurs in the cooling system when the actual temperature is outside the assumed temperature range.

Images