Cooling profiles across multiple substrates or dies

Abstract

The invention relates to a cooling distribution across multiple substrates or dies. Novel tools and techniques for implementing semiconductor packages or chip packages are provided, and more particularly, methods, systems, and apparatus for implementing semiconductor packages or chip packages are provided, the semiconductor package or chip package includes a substrate including a first channel, a first die coupled to the first substrate and including at least a first portion of a second channel, and a first opening extending from the first channel to the second channel.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 63 / 586,133 filed by Jeremy Theil on September 28, 2023, entitled “Structure and Methods to Distribute Cooling Across Multiple Dies” (“the '133 Application”), the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0003] Copyright Notice

[0004] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0005] The present disclosure generally relates to methods, systems, and apparatus for implementing a semiconductor device including a channel. Background Art

[0006] For high power density semiconductor devices, it may be advantageous to extract the generated heat from the front side or back side of the semiconductor device, substrate, die, etc. In some examples, to extract the heat, one or more fluids may be used for heat transfer. To deliver the fluid to the front side or back side of the semiconductor device, substrate, die, etc., a channel may be placed near one or more active areas of the semiconductor device, substrate, die, etc. By providing a channel near one or more active areas of the semiconductor device, substrate, die, etc., the thermal resistance between the heat source and the cooling fluid may be minimized and cooling may be provided to the one or more active areas.

[0007] In a multi-die or multi-substrate module, it may be difficult to deliver cooling liquid between two or more dies, between two or more substrates, between a substrate and a die, between a substrate and another component, between a die and another component, and so on.

[0008] Therefore, there is a need for more robust and scalable solutions for implementing semiconductor packages and chip packages with channels. Therefore, methods, systems and apparatus for implementing semiconductor packages or chip packages are provided, wherein the semiconductor packages or chip packages include one or more channels extending across or between multiple components of a semiconductor device. Summary of the invention

[0009] In one aspect, the present disclosure relates to a semiconductor device comprising: a substrate comprising a first channel; a first die coupled to the substrate and comprising at least a first portion of a second channel; and a first opening extending from the first channel to the second channel and fluidically coupling the first channel to the second channel.

[0010] On the other hand, the present disclosure relates to a method of manufacturing a semiconductor device, the method comprising: forming a substrate, comprising: forming a first channel in the substrate; and forming a first layer on the substrate and forming a first opening extending from the first channel through the first layer; wherein the first layer includes an interface configured to be directly coupled to a surface of a die including at least a first portion of a second channel.

[0011] On the other hand, the present disclosure relates to a semiconductor device, comprising: a substrate including a first channel; a die coupled to the substrate and including at least a first portion of a second channel; a first opening extending from the first channel to the second channel; and a fluid contained within the first channel and the second channel and configured to flow between the first channel and the second channel through the first opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The nature and advantages of certain embodiments may be further understood by reference to the remainder of the specification and drawings, wherein the same reference numerals are used to denote similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When a reference numeral is referenced without specifying the existing sub-label, it is intended to refer to all such multiple similar components.

[0013] Figure 1 is a schematic top view of a semiconductor device according to various embodiments;

[0014] Figure 2 According to various embodiments Figure 1 A top view of a semiconductor device showing one or more channels in the dashed shaded area between a substrate and one or more dies of the semiconductor device;

[0015] Figure 3A and 3B According to various embodiments Figure 2 A cross-sectional view of a semiconductor device along line AA;

[0016] Figure 4 another cross-sectional view showing another embodiment of a semiconductor device according to various embodiments;

[0017] Figure 5 another cross-sectional view showing another embodiment of a semiconductor device according to various embodiments;

[0018] Figure 6 According to various embodiments Figure 2 A cross-sectional view of a semiconductor device along line BB;

[0019] Figure 7 another cross-sectional view showing another embodiment of a semiconductor device according to various embodiments;

[0020] Figure 8 another cross-sectional view showing another embodiment of a semiconductor device according to various embodiments;

[0021] Fig. 9 another cross-sectional view showing another embodiment of a semiconductor device according to various embodiments;

[0022] Fig.10 another cross-sectional view showing another embodiment of a semiconductor device according to various embodiments; and

[0023] Fig.11 is a flow chart of a method of manufacturing a semiconductor device according to various embodiments. DETAILED DESCRIPTION

[0024] Various embodiments provide tools and techniques for implementing a semiconductor package or chip package that includes one or more channels described herein.

[0025] In a first aspect, a semiconductor device may include a substrate including a first channel; a first die coupled to the substrate and including at least a first portion of a second channel; and a first opening extending from the first channel to the second channel and fluidically coupling the first channel to the second channel.

[0026] In some embodiments, at least one of the substrates further comprises a first layer or the first die comprises a second layer, and the first opening may extend from the first channel to the second channel through at least one of the first layer or the second layer. In various cases, at least one of the first layer or the second layer comprises a dielectric layer. In some examples, at least one of the first surfaces of the first layer is directly coupled to the second surface of the first die or the second layer, or the third surface of the second layer is directly coupled to the fourth surface of the substrate or the first layer.

[0027] In various examples, the semiconductor device further includes an interface between the substrate and the first die. The interface can directly couple the first surface of the substrate to the second surface of the first die and the first opening extending from the first channel to at least the first portion of the second channel can extend through the interface. In various cases, the interface can be formed using at least one of surface activated bonding or hybrid bonding. In some examples, the interface is configured to form a seal around the first opening extending from the first channel to at least the first portion of the second channel. The semiconductor device can also include a fluid contained within the first channel and the second channel, and the fluid can be configured to flow from the first channel to the second channel via the first opening.

[0028] In some cases, the opening is approximately the same size as a bottom surface of the second channel.

[0029] In various embodiments, the second channel is formed in the first die and a bottom surface of the second channel is a top surface of the substrate.

[0030] In some examples, the second portion of the second channel is formed at least partially within the substrate, and the second portion of the second channel is in fluid communication with at least the first portion of the second channel.

[0031] In various cases, the second channel is completely contained within the first die and the first die forms a bottom surface of the second channel. In some examples, the substrate further includes another first channel and the semiconductor device further includes a second opening. The first opening may extend from the first channel to the second channel at a first location, and the second opening may extend from the another first channel to the second channel at a second location. The second channel may bridge the first channel and the another first channel.

[0032] In some embodiments, the substrate further includes another first channel and the semiconductor device further includes a second opening. The first opening may extend from the first channel to the second channel at a first position, and the second opening may extend from the another first channel to the second channel at a second position. The second channel may bridge the first channel and the another first channel.

[0033] In various examples, the semiconductor device may further include: a second die coupled to the first die and including at least a portion of a third channel. The first die may be between the substrate and the second die. In some embodiments, a third opening may extend from the first channel to the third channel or from the second channel to the third channel through the first die. The semiconductor device may further include a fourth opening extending from the third channel to at least a portion of a fourth channel contained within the first die or another first die.

[0034] In some cases, the semiconductor device further includes a port coupled to the first channel. The port can be configured to allow fluid to flow into or out of the first channel.

[0035] In another aspect, a method of manufacturing a semiconductor device may include forming a substrate, comprising: forming a first channel in the substrate; and forming a first layer on the substrate and forming a first opening extending from the first channel through the first layer. The first layer may include an interface configured to directly couple to a surface of a die including at least a first portion of a second channel.

[0036] In some embodiments, the method may further include forming the die, comprising: forming at least the first portion of the second channel in the die; and coupling the substrate to the surface of the die via the interface. In some examples, the first opening extends from the first channel to the second channel and fluidically couples the first channel to the second channel.

[0037] On the other hand, a semiconductor device may include: a substrate comprising a first channel; a die coupled to the substrate and comprising at least a first portion of a second channel; a first opening extending from the first channel to the second channel; and a fluid contained within the first channel and the second channel and configured to flow between the first channel and the second channel through the first opening.

[0038] In the following description, for purposes of explanation, numerous details are set forth to provide a comprehensive understanding of the described embodiments. However, it will be apparent to those skilled in the art that other embodiments may be implemented without these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be incorporated into other embodiments. However, by the same token, a single feature or multiple features of any described embodiment should not be considered essential to every embodiment of the invention, as other embodiments of the invention may omit such features.

[0039] When an element is referred to herein as being "connected," "coupled," or "attached" to another element, it is understood that the element may be directly connected or coupled to another element, or that there may be an intermediate element between the elements. Conversely, when an element is referred to as being "directly connected," "directly coupled," or "directly attached" to another element, it is understood that there are no intermediate elements in the "direct" connection or coupling between the elements. However, the presence of a direct connection or coupling does not exclude other connections or couplings in which there may be intermediate elements. As used throughout this disclosure, "connected," "connected," etc. may refer to a connection (e.g., an electrical connection) between one or more elements, while "coupled," "coupled," etc. may refer to a connection (e.g., a mechanical or physical connection, link, or combination) between one or more elements.

[0040] When an element is referred to herein as being "positioned" or "located" in some manner relative to another element (e.g., positioned on, between, below, adjacent, or in some other relative manner), it is understood that the element may be directly positioned or located relative to another element (e.g., directly on another element) or that there may be intervening elements between the elements. Conversely, when an element is referred to as being "directly positioned" or "directly located" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct positioning does not exclude other instances where there may be intervening elements.

[0041] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a variety of different conductive materials, multiple layers of different conductive materials, dielectric materials, etc., and a dielectric layer may include a variety of dielectric materials, multiple layers of dielectric materials, conductive materials, etc. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intermediate elements that exist between the coupled or connected layers. Conversely, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intermediate elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections where intermediate elements may exist.

[0042] Furthermore, the terms left, right, front, back, top, bottom, forward, backward, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, they are used only to indicate the relative position and / or direction between the various parts of an object and / or component. In addition, terms such as first, second, and third are used only to distinguish elements or components from each other and are not intended to imply an order, sequence, or amount unless otherwise expressly stated.

[0043] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless otherwise indicated by the context, intermediate processes may occur before and / or after any portion of the described process, and various additional procedures may be reordered, added, and / or omitted according to various embodiments.

[0044] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, and the like should be understood to be modified in all instances by the term "about." As used herein, the term "substantially" or "approximately" refers to a variation of ±20% or less (e.g., ±20%, 10%, ±5%, etc.) relative to a reference value or ratio, including the endpoints of the range.

[0045] In this application, the use of the singular includes the plural unless otherwise stated, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "including" and "having" and other forms, such as "includes", "included", "has", "have" and "had", should be considered non-exclusive. In addition, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit, unless specifically stated otherwise.

[0046] As used herein, the phrase "at least one" preceding a series of items (with the terms "and" or "or" separating any items) modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any one item and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In examples where selection of "at least one of each of A, B, and C," or alternatively, "at least one of A, at least one of B, and at least one of C," is intended, it is explicitly described as such.

[0047] In existing semiconductor or chip packages, one or more channels, cavities or voids are usually formed to deliver cooling fluid to one or more active areas of a substrate, die or other component of a semiconductor device. However, these channels are usually limited to one die or other component of the semiconductor device. In a semiconductor device including multiple substrates, multiple dies or multiple other components, it is impossible to have channels, cavities or voids that can deliver cooling fluid within or between each of the multiple substrates, multiple dies or multiple other components.

[0048] The subject technology includes a semiconductor or chip device (e.g., an integrated circuit (IC), a chip or other semiconductor device or module) or an interposer (e.g., an interface with one or more electrical connections arranged between at least two layers or the like) that provides one or more channels (e.g., channels, cavities, gaps, openings, etc.). The semiconductor device may include one or more channels configured to provide a single path between multiple substrates, multiple dies, or multiple other components. For example, one or more openings or ports may be configured between one or more first channels of a first substrate and one or more second channels of a die or a second substrate. One or more direct bonding interfaces or layers or zero-gap bonding interfaces or layers may be used to at least partially, substantially or completely seal one or more openings or channels and prevent fluid from leaking between the first substrate and the die or the second substrate. Providing one or more fluidly connected channels between the substrate and the die or the second substrate provides the advantage of delivering cooling fluid to the die when the die is attached to the substrate as a separate part. In addition, the cooling fluid can flow between multiple dies attached to the substrate. Furthermore, providing one or more second channels within the die or second substrate provides the advantage of being able to tailor the one or more channels to maximize heat transfer or heat flow.

[0049] Figure 1 is a schematic top view of an embodiment of a semiconductor device 100 a according to various embodiments.

[0050] The semiconductor device 100a may include a substrate 200. The substrate 200 may be a supporting material (e.g., silicon, glass, ceramic, metal, conductive material, and / or any other semiconductor material or combination of materials) on which or within which elements or components (e.g., connectors, circuits, integrated circuits, passive devices, active devices, etc.) are fabricated or coupled. The one or more passive devices may be one or more circuit components (e.g., conductors, resistors, capacitors, inductors, etc.) that are capable of transmitting, absorbing, and / or dissipating power. The one or more active devices may be one or more circuit components (e.g., transistors, etc.) that are capable of controlling power flow. In various cases, the substrate 200 may be formed of one or more layers. The one or more layers may include, but are not limited to, one or more dielectric layers, one or more device layers, one or more conductive layers, one or more insulating layers, one or more redistribution layers, and / or the like.

[0051] In some cases, substrate 200 may be a package substrate, an interposer between two other substrates or semiconductor components, a circuit board (e.g., a printed circuit board), or another substrate configured to provide supporting material on or within which elements or components of a semiconductor device are fabricated or coupled.

[0052] The semiconductor device 100a may further include a first row or stack 302 of one or more dies 300 (e.g., one or more first dies 300). The one or more dies 300 may be coupled to the top surface 202 of the substrate 200. In some cases, instead of the one or more dies 300, there may be another substrate similar to the substrate 200. The other substrate may have many similar features described below with respect to the one or more dies 300.

[0053] The one or more dies 300 may include, but are not limited to, one or more electronic dies, one or more electronic circuits, one or more electronic integrated circuits (EICs), one or more photonic dies, one or more photonic circuits, one or more photonic integrated circuits (PICs), one or more active devices, one or more passive devices, one or more dummy dies (e.g., dies used to take up space, provide support, etc.), or other components, etc. The one or more dies 300 may include one or more layers (not shown). The one or more layers may include, but are not limited to, one or more dielectric layers, one or more device or circuit layers, one or more conductive layers, one or more insulating layers, one or more redistribution layers, other layers, and / or the like. The layers may further include one or more layers configured to provide component interconnection. In some embodiments, one or more dies 300 may include, but are not limited to, processing circuits (e.g., central processing units, microprocessors, etc.), switching circuits (e.g., switch application specific integrated circuits (ASICs), etc.), input / output circuits, memory circuits, circuits configured to receive one or more optical signals, voltage regulators, capacitors, passive wires, etc. Figure 1 There are ten dies 300 shown in FIG. 1 , however, there may be more or fewer dies depending on the semiconductor device, and semiconductor device 100 a is not intended to be limited to only the dies shown.

[0054] In various cases, Figure 1 A mold compound 304 indicated by the gray shaded area of ​​​​the ​​may be included between the one or more dies 300. The mold compound can be an epoxy or other material or combination of materials that is configured to insulate the one or more dies 300 from each other. The mold compound 304 can be configured to insulate the one or more dies 300 from each other or to couple the one or more dies 300 to the top surface 102 of the substrate. However, in some cases, such as Figure 2 As shown in , the mold compound 304 may not be included between the one or more dies 300 or may be included only at selected locations between the one or more dies 300.

[0055] Go to Figure 2 , Figure 2 yes Figure 1FIG. 1 is a top view of a semiconductor device 100 a showing one or more channels in a dashed shaded area between a substrate 200 and one or more dies 300 of the semiconductor device 100 a .

[0056] In various cases, the substrate 200 or the one or more dies 300 may include an interface 204 between the substrate 200 and the one or more dies 300. In some cases, the interface 204 may be located on the top surface 202 of the substrate or the bottom surface 306 of the one or more dies 300. In other cases, the interface 204 may be located on the top surface 202 of the substrate 200 and the bottom surface 306 of the one or more dies 300. The interface 204 may be formed by the one or more first layers 206 or the one or more second layers 308, which are formed at the interface 204. Figure 3A Although Figures 3B to 11 The one or more first layers 206 or the one or more second layers 308 are not shown in FIG. 1 , but may also be present in those embodiments of the semiconductor device.

[0057] The interface 204, the one or more first layers 206, or the one or more second layers 308 may include a bonding surface having direct bonding or coupling to another different bonding surface (e.g., a surface of the interface 204, the one or more first layers 206, or the one or more second layers 308, etc.). In some cases, the one or more bonding surfaces may include one or more zero-gap bonding surfaces (e.g., the top surface 202 and the bottom surface 306, etc.) or substantially zero-gap bonding surfaces, such as one or more hybrid bonding surfaces, one or more direct bonding surfaces, one or more surface-activated bonding surfaces, etc. In some cases, two or more zero-gap bonding surfaces may be directly bonded together using one or more hybrid bonding surfaces, one or more direct bonding surfaces, one or more surface-activated bonding surfaces, etc. The one or more hybrid bonding surfaces may include directly bonding two or more surfaces having more than one material (e.g., an insulator or a combination of a dielectric material and a conductive material, etc.). The one or more direct bonding surfaces may include directly bonding two surfaces together without an intermediate layer between the two surfaces. One or more surface activated bonding surfaces may include bonding (eg, directly bonding, etc.) two or more surfaces that have been chemically treated or treated with a plasma process to enhance bonding energy between the one or more surfaces.

[0058] It is important to note that the bonding surfaces, "zero gap" bonding surfaces, or substantially zero gap bonding surfaces described above may include situations where there is no gap or substantially no gap between the two bonding surfaces or where there is some gap between the two bonding surfaces. In other words, in each of these bonding situations, zero gap bonding situations, or substantially zero gap bonding situations, the bonding surface, zero gap bonding surface, or substantially zero gap bonding surface may be directly coupled to another bonding surface and there may be no bumps between the bonding surfaces. As described herein, "no bumps" means that there are no solder bumps, microbumps, etc. between the bonding surfaces. By coupling the bump-free bonding surfaces directly together, this allows the top surface 202 of the substrate 200 and the bottom surface 306 of the one or more dies 300 to be substantially or completely flush (e.g., there is no gap or substantially no gap between the top surface 202 and the bottom surface 306) against each other or on top of each other. Thus, the top surface 202 of the substrate 200 and the bottom surface 306 of the one or more dies 300 may be directly bonded together without a gap or substantially without a gap and there may be no bumps between the top surface 202 and the bottom surface 306 .

[0059] The height or plane of the top surface 202 of the substrate 200 may be substantially uniform or substantially flat (e.g., there are no bumps and no gaps or substantially no gaps between the top surface 202 and the bottom surface 306) to ensure that the top surface 202 of the substrate can be bonded (e.g., directly bonded, zero-gap bonded, etc.) to the bottom surface 306 of one or more dies 300.

[0060] In some examples, the substrate 200 may further include one or more first channels 208, and the one or more dies 300 may include at least a first portion 310 of one or more second channels 312. The one or more first channels 208 or the second channels 312 are formed by Figure 2 The one or more first channels 208 or the one or more second channels 312 may be located between the bottom surface 210 of the substrate 200 and the top surface 314 of the one or more dies 300 .

[0061] The one or more first channels 208 or the second channels 312 may contain or be configured to contain a fluid 216 indicated by the dashed shaded area of ​​FIGS. 3 to 10 . The fluid 216 may be water or other cooling fluid configured to cool one or more active regions of the substrate 200 or the one or more dies 300 (e.g., regions of the substrate 200 or the one or more dies 300 that include one or more active devices, etc.) or active devices. The fluid 216 may also be used to cool other areas of the semiconductor device 100 (e.g., one or more areas where there are thermal issues, etc.) and should not be limited to cooling only one or more active regions or active devices of the substrate 200 or the one or more dies 300. The one or more first channels 208 or the one or more second channels 312 may further include one or more ridges, one or more fins, one or more pillars, or other features or components to control the flow of the fluid within the one or more first channels 208 or the second channels 312 and enhance heat transfer between the active regions, active devices, or other components of the semiconductor device and the fluid.

[0062] In various cases, by directly bonding or coupling the substrate 200 to the one or more dies 300, e.g., by using one or more zero-gap bonding surfaces between the substrate 200 and the one or more dies 300, the bonding surface between the substrate 200 and the one or more dies 300 or the zero-gap bonding surface between the substrate 200 and the one or more dies 300 may be used to directly or indirectly create at least a partial, substantial, or complete seal between the top surface 202 of the substrate 200 and the bottom surface 306 of the one or more dies 300. The seal may be used to prevent the fluid 216 contained within the one or more first channels 208 or the one or more second channels 312 from leaking to other areas of the substrate 200 or the die 300. For example, the seal may prevent the fluid from contacting one or more interconnects or other metal features (not shown) between the substrate 200 and the one or more dies 300.

[0063] In various cases, the substrate 200 may also include one or more openings 212. Figure 2. The one or more openings 212 may be configured to extend at least partially through the substrate 200. The one or more openings 212 may be configured to fluidically couple the one or more first channels 208 and the one or more second channels 312 and allow a fluid (e.g., a cooling fluid, a heating fluid, or other types of fluids, etc.) to move or flow between the one or more first channels 208 and the one or more second channels 312. As used herein, fluid coupling or fluid connection means that a fluid is able to flow from one component to another. For example, a fluid is able to flow between the one or more first channels 208 and the one or more second channels 312 via the one or more openings 212. In this way, the fluid contained in the one or more first channels 208, the one or more second channels 312, and the one or more openings 212 can be advantageously transported to portions of the substrate 200 or the one or more dies 300 that require cooling, heating, etc. In various cases, the one or more openings 212 may be various shapes, such as circular, elliptical, square, rectangular, polygonal, irregular polygonal, or other shapes. In some cases, there can be multiple openings 212 extending from the first channel 208 to the second channel 312. Alternatively, there can be only one opening extending from the first channel 208 to the second channel 312. In some cases, one or more openings 212 can be substantially smaller than the one or more second channels 312 or the bottom surface of the one or more dies 300. In some cases, one or more openings 212 can be approximately the same size as the one or more second channels 312 or the bottom surface of the one or more dies 300.

[0064] In various cases, the substrate 200 may also include one or more ports 214 coupled to the one or more first channels 208. In some cases, the one or more ports 214 may be included on one or more dies 300 (not shown) and coupled to the one or more second channels 312. The one or more ports 214 may be configured to extend at least partially through the substrate 200 or the one or more dies 300. The one or more ports 214 may be configured to allow cooling fluid to move or flow into or out of the one or more first channels 208 or the one or more second channels 312. In various cases, the one or more ports 214 may be various shapes, such as circular, oval, square, rectangular, polygonal, irregular polygonal, or other shapes. In some cases, there may be multiple ports 214. Alternatively, there may be only one port 214.

[0065] Go to Figure 3A and 3B , Figure 3A and 3B yes Figure 2 A cross-sectional view taken along line AA. Figure 3A Various configurations of the one or more first channels 208 and the one or more second channels 312 arranged within the substrate 200 and the one or more dies 300 are shown. Figure 3B3, but without the one or more first layers 206 or the one or more second layers 308. However, as described above, Figure 3B The cross-section of may or may not include one or more first layers 206 or one or more second layers 308 .

[0066] Go to Figure 3A and 3B 2, Example A shows a first channel 208a configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208a can be configured to extend across the substrate 200 and fluidically coupled to a second channel 312a of the die 300a via an opening 212a. In this case, the opening 212a is substantially smaller than a bottom surface 316a of the second channel. In various cases, as shown in Example A, the second channel 312a can be completely contained within the die 300a. In various cases, as shown in Example A, one or more first layers 206, the top surface 202 of the substrate 200, or the top surface 202 of the first layer 206 can be the bottom surface 316a of the second channel 312a. In some cases, the top surface 202 of the substrate 200 or the first layer 206 or the bottom surface 306a of the die 300a or the second layer 308 may include one or more bonding surfaces (e.g., zero-gap bonding surfaces, substantially zero-gap bonding surfaces, direct bonding surfaces, etc.), which, as discussed above, may be configured to seal the first channel 208a, the second channel 312a, and the opening 212a and prevent the fluid 216 from leaking to other portions of the semiconductor device 100a.

[0067] Go to Figure 3A and 3B Example B of Example B shows that the first channel 208a is fluidly coupled to the second channel 312b of the die 300b via the opening 212b. In this example, the opening 212b is approximately the same size as the second channel 312b, or is approximately the same size or substantially the same as the bottom surface 306b of the die 300b. In various cases, as shown in Example B, the second channel 312b may extend between the substrate 200 and the die 300b so that only the first portion 310b of the second channel 312b is contained within the die 300b. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306b of the die 300b may include one or more bonding surfaces, as discussed above, which may be configured to seal the first channel 208a, the second channel 312b, and the opening 212b and prevent fluid from leaking to other parts of the semiconductor device 100a.

[0068] Go to Figure 3A and 3BExample C of the embodiment of the present invention shows the first channel 208a flowing under the die 300c. In this example, there is no second channel and the first channel can be used to cool the bottom surface 306c of the die 300c. In some cases, the die 300c may not need any cooling at all, and in this case, the first channel 208 can be arranged around the die 300c.

[0069] Figure 4 Another cross-sectional view of another embodiment of a semiconductor device 100b is shown. The semiconductor device 100b may be similar to the semiconductor device 100a. However, the arrangement of the one or more first channels 208 and the one or more second channels 312 may be different. Figure 4 The one or more first layers 206 or the one or more second layers 308 are not shown. However, as described above, Figure 4 The cross-section of may or may not include one or more first layers 206 or one or more second layers 308 .

[0070] Go to Figure 4 Example D shows a first channel 208d configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208d can be configured to extend across the substrate 200 and fluidically coupled to a second channel 312d of the die 300d via an opening 212d. The opening 212d can extend from the first channel 208 to the second channel 312d through the substrate 200 and the die 300d. In this case, the opening 212d is substantially smaller than a bottom surface 316d of the second channel 312d. In various cases, as shown in Example D, the second channel 312d can be completely contained within the die 300d. In various cases, a portion of the die 300d can be the bottom surface 316d of the second channel 312d. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306d of the die 300a may include one or more bonding surfaces, which, as discussed above, may be configured to seal the first channel 208d, the second channel 312d, and the opening 212d and prevent fluid leakage to other portions of the semiconductor device 100b.

[0071] Go to Figure 4 Example E of the embodiment of the present invention shows a first channel 208d flowing under the die 300e. In this example, there is no second channel and the first channel can be used to cool the bottom surface 306e of the die 300e. In addition, in Example E, the bottom surface 308e of the die 300e is configured or the one or more second layers 308 are configured as the top surface 318e of the first channel 208d. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306e of the die 300e may include one or more bonding surfaces, as discussed above, which can be configured to seal the first channel 208d and prevent fluid from leaking to other parts of the semiconductor device 100b.

[0072] Figure 5 Another cross-sectional view of another embodiment of a semiconductor device 100c is shown. The semiconductor device 100c may be similar to the semiconductor device 100a. However, the arrangement of the one or more first channels 208 and the one or more second channels 312 may be different. Figure 5 Not shown are the one or more first layers 206 or the one or more second layers 308. However, as described above, Figure 5 The cross-section of may or may not include one or more first layers 206 or one or more second layers 308 .

[0073] Go to Figure 5 Example F of Example F shows a first channel 208f configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208f can be configured to extend across the substrate 200 and fluidically coupled to a second channel 312f of the die 300f via an opening 212f. The opening 212f can extend from the first channel 208 to the second channel 312f through the substrate 200. In various cases, as shown in Example F, the second channel 312f can extend between the substrate 200 and the die 300f so that only a portion 310f of the second channel 312f is contained within the die 300f. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306f of the die 300f can include one or more bonding surfaces, as discussed above, which can be configured to seal the first channel 208f, the second channel 312f, and the opening 212f and prevent fluid from leaking to other portions of the semiconductor device 100c.

[0074] Go to Figure 5 Example G of Example G shows a first channel 208f fluidly coupled to a second channel 312g of a die 300g via an opening 212g. In this example, the opening size of the opening 212g and the second channel 312g are substantially the same. In various cases, as shown in Example G, the second channel 312g can be completely contained within the die 300g and the top surface 202 of the substrate 200 can be the bottom surface 316g of the second channel 312g. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306g of the die 300g can include one or more bonding surfaces, as discussed above, which can be configured to seal the first channel 208f, the second channel 312g, and the opening 212g and prevent fluid from leaking to other parts of the semiconductor device 100c.

[0075] Figure 6 exhibit Figure 2 Another cross-sectional view of an embodiment of a semiconductor device 100 a taken along line BB. Figure 5 Not shown are the one or more first layers 206 or the one or more second layers 308. However, as described above, Figure 5 The cross-section of may or may not include one or more first layers 206 or one or more second layers 308 .

[0076] Go to Figure 6 Example H of Example H shows a first channel 208h configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208h may be configured to extend across a portion of the substrate 200 and fluidically couple to a second channel 312h of the die 300h via an opening 212h. The opening 212h may extend from the first channel 208h to the second channel 312h through the substrate 200 and the die 300h. In this case, the opening 212h is substantially smaller than the bottom surface 316h of the second channel 312h. In some cases, the second channel 312h may be a bridge between the first channel 208h and another first channel 208hh. In other words, the second channel 312h may fluidically couple the first channel 208h to another first channel 208hh via another opening 212hh extending through the substrate 200 and the die 300h. In this case, the other opening 212hh is substantially smaller than the bottom surface 314h of the second channel 312h. In some cases, the other opening 212hh may be approximately the same size or the same shape as the opening 212h, or may be a different size or a different shape than the opening 212h. In various cases, the second channel 212h may be completely contained within the die 300h. This embodiment is particularly beneficial when there is a mold compound 304, air, or other components of the semiconductor device 100d positioned within the substrate 200 between the first channel 208h and the other first channel 208hh. In this way, the fluid in the second channel 312h can be arranged around the mold compound 304, air, or other components of the semiconductor device 100d, and prevented from contacting the mold compound 304, air, or other components of the semiconductor device 100d. If the fluid would contact the mold compound, the fluid could cause the mold compound 304 to dissolve, etc. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306h of the die 300h may include one or more bonding surfaces, which, as discussed above, may be configured to seal the first channel 208h, the second channel 312h and the opening 212h, another first channel 208hh, or another opening 212hh and prevent fluid from leaking to other portions of the semiconductor device 100a.

[0077] Figure 7 Another cross-sectional view of another embodiment of a semiconductor device 100d is shown. The semiconductor device 100d may be similar to the semiconductor device 100a. However, the arrangement of the one or more first channels 208 and the one or more second channels 312 may be different. Figure 7 Not shown are the one or more first layers 206 or the one or more second layers 308. However, as described above, Figure 7The cross-section of may or may not include one or more first layers 206 or one or more second layers 308 .

[0078] Go to Figure 7 Example I of Example I shows a first channel 208i configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208i can be configured to extend across a portion of the substrate 200 and fluidically coupled to a second channel 312i of the die 300i via an opening 212i. The opening 212i can extend from the first channel 208i to the second channel 312i through the substrate 200. In some cases, the second channel 312i can be a bridge between the first channel 208i and another first channel 208ii. In other words, the second channel 312i can fluidically couple the first channel 208i to another first channel 208ii via another opening 212ii extending through the substrate 200. In this case, the other opening 212ii is substantially smaller than the bottom surface 314i of the second channel 312i. In various cases, the second channel 312i can be completely contained within the die 300i. However, the top surface 202 of the substrate 200 may be the bottom surface 316i of the second channel 312i. This embodiment is particularly beneficial when another component 320i of the semiconductor device 100d (e.g., mold compound 304, air, or other component) is positioned within the substrate 200 between the first channel 208i and the other first channel 208ii. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306i of the die 300i may include one or more bonding surfaces, as discussed above, which may be configured to seal the first channel 208i, the second channel 312i, the opening 212i, the other first channel 208ii, or the other opening 212ii and prevent fluid from leaking to other portions of the semiconductor device 100d.

[0079] Figure 8 Another cross-sectional view of another embodiment of a semiconductor device 100e is shown. The semiconductor device 100e may be similar to the semiconductor device 100a. However, the arrangement of the one or more first channels 208 and the one or more second channels 312 may be different. Figure 8 Not shown are the one or more first layers 206 or the one or more second layers 308. However, as described above, Figure 8 The cross-section of may or may not include one or more first layers 206 or one or more second layers 308 .

[0080] Go to Figure 8Example J of Example J shows a first channel 208j configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208j can be configured to extend across a portion of the substrate 200 and fluidically coupled to a second channel 312j of the die 300j via an opening 212j. The opening 212j can extend from the first channel 208i to the second channel 312j through the substrate 200. In some cases, the second channel 312j can be a bridge between the first channel 208j and another first channel 208jj. In other words, the second channel 312j can fluidically couple the first channel 208j to another first channel 208jj via another opening 212jj extending through the substrate 200. In various cases, the second channel 312j can extend between the substrate 200 and the die 300j such that only a portion 310j of the second channel 312j is contained within the die 300j. This embodiment is particularly beneficial when another component 320j of the semiconductor device 100d is positioned within the substrate 200 between the first channel 208j and the other first channel 208jj. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306j of the die 300j may include one or more bonding surfaces, as discussed above, which may be configured to seal the first channel 208j, the second channel 312j, the opening 212j, the other first channel 208jj, the other opening 212jj and prevent fluid from leaking to other portions of the semiconductor device 100e.

[0081] Fig. 9 Another cross-sectional view of another embodiment of a semiconductor device 100f is shown. The semiconductor device 100f may be similar to the semiconductor device 100a. However, the arrangement of the semiconductor device 100f (eg, the arrangement of the one or more first channels 208, the one or more second channels 312, or the one or more dies, etc.) may be different. Fig. 9 Not shown are the one or more first layers 206 or the one or more second layers 308. However, as described above, Fig. 9 The cross-section of may or may not include one or more first layers 206 or one or more second layers 308 .

[0082] The semiconductor device 100f may have a first row or stack 302 of one or more first dies 300 and a second row or stack 402 of one or more second dies 400. The one or more second dies 400 may be similar to the one or more first dies 300 and stacked on top of the one or more first dies 300. The height or plane of the top surface 314 of the first row or stack 302 of the one or more dies 300 and the mold compound 304 may be substantially uniform or substantially flat in order to ensure that the top surface 314 of the one or more dies 300 may be bonded (e.g., zero gap bonded, directly bonded, etc.) to the bottom surface 404 of the one or more dies 400. In various cases not shown, between the first row or stack 302 of one or more dies 300 and the second row or stack 402 of one or more other dies 400, there may be one or more layers similar to the one or more first layers 206 or the one or more second layers 308.

[0083] Go to Fig. 9 Example K of Example K shows a first channel 208k configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208k may be configured to extend across the substrate 200 and fluidically coupled to a second channel 312k of a die 300k via an opening 212k. The opening 212k may extend from the first channel 208k through the substrate 200 to the second channel 312k. In some cases, the second channel 312k may include a second opening 322k extending from the second channel 312k to a third channel 406k of another die 400k stacked on top of the die 300k. The third channel 406k may serve as a bridge between the die 300k and another die 300kk and include another second opening 322kk extending between the third channel 406k and another second channel 312kk. It should be noted that the third channel 406k and the further second channel 312kk may have similar features or functions as discussed above with respect to one or more second channels, and in Fig. 9 and 10Only a few possible embodiments are shown in FIG. Another second channel 312kk may be configured to deliver the fluid 216 to a top portion 324k of another die 300kk. In some cases, the top surface 202 of the substrate 200 or the bottom surface 306k of the die 300k may include one or more bonding surfaces, as discussed above, which may be configured to seal the first channel 208k, the second channel 312k, and the opening 212k and prevent the fluid from leaking to other portions of the semiconductor device 100f. Additionally, in some cases, the top surface 314k of the die 300k, the bottom surface 404k of the die 400k, or the top surface 314kk of another die 300kk may include one or more bonding surfaces, which, as discussed above, may be configured to seal the second channel 312, the third channel 406k, the second opening 322k, another second opening 322kk, or another second channel 312kk and prevent fluid from leaking to other portions of the semiconductor device 100f.

[0084] Go to Fig. 92 , Example L shows a first channel 208k configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208k may be configured to extend across the substrate 200 and fluidically coupled to a second channel 312l of the die 300l via an opening 212l. The opening 212l may extend through the substrate 200 from the first channel 208k to the second channel 312k. In some cases, the second channel 312k may include a second opening 322l extending from the second channel 312k to a third channel 406l of another die 400l stacked on top of the die 300l. The third channel 406l may be configured to have a first portion 408l of the third channel 406l within the die 300l and a second portion 410l of the third channel 406l within the die 400l. The third channel 4061 can be used as a bridge between the second opening 3221 and another second opening 32211 extending between the third channel 4061 and the second channel 3121. The second opening 3221 and the other second opening 32211 can be configured to deliver fluid to various locations of the die 3001 (e.g., active areas, other areas that need cooling, etc.). In some cases, the top surface 202 of the substrate 200 or the bottom surface 3061 of the die 300k can include one or more bonding surfaces, as discussed above, which can be configured to seal the first channel 208k, the second channel 3121, and the opening 2121 and prevent the fluid from leaking to other parts of the semiconductor device 100f. Additionally, in some cases, the top surface 3141 of the die 3001 or the bottom surface 4041 of the die 4001 may include one or more bonding surfaces, which, as discussed above, may be configured to seal the second channel 3121, the third channel 4061, the second opening 3221, or the other second opening 32211 and prevent fluid from leaking to other portions of the semiconductor device 100f.

[0085] Examples A to M are only some possible arrangements of the one or more first channels 208, the one or more second channels 312, the one or more openings 212, the one or more third channels 406, or the one or more openings 322, and many other arrangements are possible and within the scope of the embodiments. Each of the channels or openings can be arranged to deliver cooling fluid to the substrate 200, the one or more dies 300, or the one or more dies 400, or other rows of dies or portions of the substrate where there are active areas or other components that need cooling. In various cases, the one or more first channels 208, the one or more second channels 312, the one or more openings 212, the one or more third channels 406, or the one or more openings 322, etc. can be arranged in any arrangement according to design requirements without limitation.

[0086] Fig.10Another cross-sectional view of another embodiment of a semiconductor device 100g is shown. The semiconductor device 100g may be similar to the semiconductor device 100f. However, the arrangement of the semiconductor device 100g (eg, the arrangement of the one or more first channels 208, the one or more second channels 312, or the one or more dies, etc.) may be different. Fig.10 Not shown are the one or more first layers 206 or the one or more second layers 308. However, as described above, Fig.10 The cross-section of may or may not include one or more first layers 206 or one or more second layers 308 .

[0087] Go to Fig.10 Example M of Example M shows a first channel 208m configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208m may be configured to extend across the substrate 200 and fluidically coupled to a second channel 312m of a die 300m via an opening 212m. The opening 212m may extend from the first channel 208m to the second channel 312m through the substrate 200. In some cases, the second channel 312k may include a second opening 322m extending from the second channel 312m to a third channel 406m of another die 400m stacked on top of the die 300m. The bottom 412m of the third channel 406m may be the top surface 314m of the die 300m. The third channel 406m may serve as a bridge between the second opening 322m and another second opening 322mm extending between the third channel 406m and the second channel 312m. The second opening 322m and the further second opening 322mm may be configured to deliver fluid to various locations of the die 300m (e.g., active areas, other areas requiring cooling, etc.). In some cases, the top surface 202 of the substrate 200 or the bottom surface 306m of the die 300m may include one or more bonding surfaces, as discussed above, which may be configured to seal the first channel 208m, the second channel 312m, and the opening 212m and prevent fluid from leaking to other parts of the semiconductor device 100g. Additionally, in some cases, the top surface 314m of the die 300m or the bottom surface 404m of the die 400m may include one or more bonding surfaces, as discussed above, which may be configured to seal the second channel 312m, the third channel 406m, the opening 322m, or the further opening 322mm and prevent fluid from leaking to other parts of the semiconductor device 100g.

[0088] Go to Fig.10Example N of Example N shows a first channel 208m configured to transmit a fluid 216 to or receive a fluid 216 from a port 214. The first channel 208 may be configured to extend across the substrate 200 and be fluidically coupled to the opening 212n. The opening 212n may extend from the first channel 208n to the third channel 406n through the substrate 200, the die 300n, or the die 400n. The opening 212n may be configured to deliver the fluid to various locations of the die 300n (e.g., active areas, other areas requiring cooling, etc.). In some cases, the top surface 202 of the substrate 200 or the bottom surface 306n of the die 300m may include one or more bonding surfaces, as discussed above, which may be configured to seal the first channel 208m and the opening 212n and prevent the fluid from leaking to other parts of the semiconductor device 100g. Additionally, in some cases, top surface 314n of die 300n or bottom surface 404n of die 400n may include one or more bonding surfaces, which, as discussed above, may be configured to seal opening 212n or third channel 406n and prevent fluid leakage to other portions of semiconductor device 100g.

[0089] Fig.11 is a flow chart of a method 1100 of fabricating a semiconductor device according to various embodiments. Fig.11 The method 1100 described herein may be used to manufacture Figures 1 to 10 However, other methods can be used to make Figures 1 to 10 components.

[0090] Go to Fig.11 , method 1100 may begin at block 1105 by providing or forming a substrate (e.g., substrate 200 or other component of a semiconductor device including one or more first channels, etc.). Next, at block 1110, one or more first channels (e.g., first channel 208, etc.) may be formed within the first substrate. One or more fins, ridges, or other structures, etc. may be formed in the one or more first channels and may be used to separate the one or more first channels from another of the one or more first channels.

[0091] The method 1100 may further include, at optional block 1115, forming one or more first layers on a surface of the substrate. The one or more first layers may be one or more bonding layers or include one or more bonding surfaces as discussed above. This step is optional because the one or more first layers may alternatively be formed as one or more second layers on a die coupled to the substrate. In some cases, both the one or more first layers and the one or more second layers may be formed. The method 1100 may further include, at optional block 1120, forming or etching one or more openings (e.g., opening 212, etc.) in the substrate or the one or more first layers. The one or more openings may be configured to correspond to a second channel positioned on the one or more first dies or one or more other openings formed in the one or more first dies.

[0092] Next, the method 1100 may continue to optional block 1125 and include etching or adjusting a thickness or planarity of a top surface of the one or more first layers or substrates to ensure that the top surface of the one or more first layers or substrates is substantially uniform or substantially flat.

[0093] The method 1100 may continue at block 1030 by providing or forming a first row or stack (e.g., first row or stack 302, etc.) of one or more first dies (e.g., one or more dies 300 or other components of a semiconductor device including one or more channels, etc.). In various cases, the one or more dies 300 may be formed simultaneously with the substrate or at a different time. In various cases, the substrate and the one or more first dies may be manufactured using different manufacturers or the same manufacturer.

[0094] Next, one or more second channels (e.g., second channel 312, etc.) or a portion of one or more second channels may be formed within the one or more first dies at block 1135. One or more fins, ridges, or other structures, etc. may be formed in the one or more second channels and may be used to separate one or more second channels from another of the one or more second channels.

[0095] The method 1100 may further include, at optional block 1140, optionally forming one or more second layers on a first surface of one of the one or more first dies. The first surface of the one or more first dies may be a surface configured to couple to a substrate. The one or more second layers may be one or more bonding layers or include one or more bonding surfaces as discussed above. Next, the method 1100 may continue to optional block 1145 and include forming or etching one or more openings (e.g., opening 212, etc.) corresponding to the openings of the one or more first layers or the one or more first dies or corresponding to the one or more first channels of the substrate.

[0096] Next, the method can continue to optional block 1150 and include etching or adjusting the thickness or plane of the surface of the one or more second layers or the one or more first dies to ensure that the surface of the one or more second layers or the one or more first dies is substantially uniform or substantially flat. By having a substantially flat surface between the one or more first dies and the substrate, the surface between the one or more first dies and the substrate can be configured to seal openings and channels between the one or more first dies and the substrate.

[0097] Next, at block 1155, the one or more first dies may be coupled to the substrate, and one or more openings or channels between the substrate and the one or more dies may be fluidly coupled together to transfer fluid between the one or more first channels and the one or more second channels.

[0098] In various cases, when there is a second row (e.g., second row 402, etc.) of one or more second dies (e.g., second die 400, etc.), the one or more first dies may further undergo various method steps. These steps may occur before the one or more first dies are coupled to the substrate or after the one or more first dies are coupled to the substrate. The method 1100 may continue at optional block 1160 by forming one or more third layers on a second surface of the one or more first dies, the second surface being opposite to the first surface coupled to or configured to be coupled to the substrate. The one or more third layers may be one or more bonding layers or include one or more bonding surfaces as discussed above. Next, the method 1100 may continue to optional block 1165 and include forming or etching one or more second openings (e.g., opening 322, etc.) in the one or more third layers or the one or more first dies. The one or more second openings may be configured to correspond to one or more third channels or one or more second openings of the one or more second dies, etc.

[0099] Next, the method may continue to optional block 1170 and include etching or adjusting a thickness or planarity of the second surface of the one or more third layers or the one or more first dies to ensure that a surface of the one or more third layers or the one or more first dies is substantially uniform or substantially flat.

[0100] The method 1100 may continue at block 1175 by providing or forming a second row (e.g., second row 402, etc.) of one or more second dies (e.g., one or more dies 400 or other components of a semiconductor device including one or more channels, etc.). In various cases, the one or more second dies may be formed simultaneously with the substrate or the one or more first dies or at a different time. In various cases, different manufacturers or the same manufacturer may be used to manufacture the substrate, the one or more first dies, or the one or more second dies.

[0101] Next, one or more third channels (e.g., third channel 406, etc.) or a portion of one or more third channels may be formed within the one or more second dies at block 1180. One or more fins, ridges, or other structures, etc. may be formed in the one or more third channels and may be used to separate the one or more second channels from another of the one or more third channels.

[0102] The method 1100 may further include, at optional block 1185, optionally forming one or more fourth layers on a first surface of one of the one or more second dies. The first surface of the one or more second dies may be a surface configured to couple to the one or more first dies. The one or more fourth layers may be one or more bonding layers or include one or more bonding surfaces as discussed above. Next, the method 1100 may continue to optional block 1190 and include forming or etching one or more openings (e.g., opening 322, etc.) corresponding to the one or more third layers or the one or more first dies or corresponding to the one or more second channels of the one or more first dies in the one or more fourth layers or the one or more second dies.

[0103] Next, the method 1100 can continue to optional block 1195 and include etching or adjusting the thickness or plane of the surface of the one or more fourth layers or the one or more second dies to ensure that the top surface of the one or more fourth layers or the one or more second dies is substantially uniform or substantially flat. By having a substantially flat surface between the one or more first dies and the one or more second dies, the surface between the one or more first dies and the one or more second dies can be configured to seal the openings and channels between the one or more first dies and the one or more second dies.

[0104] Next, at block 1197, the one or more first dies may be coupled to the one or more second dies, and one or more openings or channels between the one or more first dies and the one or more second dies may be fluidly coupled together to transfer fluid between the one or more second channels and the one or more third channels. This process may be repeated until the desired number of rows of dies or substrates is reached.

[0105] Although some features and aspects have been described for embodiments, those skilled in the art will recognize that various modifications may be made. In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context otherwise indicates. In addition, the procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a specific structural system and / or with respect to one system may be organized in an alternative structural system and / or incorporated into other described systems. Therefore, although various embodiments with or without some features are described for ease of description and explanation of aspects of those embodiments, various components and / or features described herein with respect to a specific embodiment may be replaced, added, and / or subtracted in other described embodiments unless the context otherwise indicates. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate comprising a first channel; a first die coupled to the substrate and comprising at least a first portion of a second channel; and A first opening extends from the first channel to the second channel and fluidly couples the first channel to the second channel.

2. The semiconductor device according to claim 1, wherein: At least one of the substrates further comprises a first layer or the first die comprises a second layer; and Wherein the first opening extends from the first channel to the second channel through at least one of the first layer or the second layer. 3 . The semiconductor device of claim 2 , wherein at least one of the first layer or the second layer comprises a dielectric layer.

4. The semiconductor device of claim 2, wherein at least one of a first surface of the first layer is directly coupled to the first die or a second surface of the second layer, or a third surface of the second layer is directly coupled to the substrate or a fourth surface of the first layer.

5. The semiconductor device of claim 1 , further comprising an interface between the substrate and the first die, wherein the interface directly couples a first surface of the substrate to a second surface of the first die, and wherein the first opening extending from the first channel to at least the first portion of the second channel extends through the interface. 6 . The semiconductor device according to claim 5 , wherein the interface is formed using at least one of surface activated bonding or hybrid bonding. 7 . The semiconductor device of claim 5 , wherein the interface is configured to form a seal around the first opening extending from the first channel to at least the first portion of the second channel. 8 . The semiconductor device of claim 7 , further comprising a fluid contained within the first channel and the second channel, wherein the fluid is configured to flow from the first channel to the second channel through the first opening. 9 . The semiconductor device of claim 1 , wherein the opening is substantially the same size as a bottom surface of the second channel. 10 . The semiconductor device of claim 1 , wherein the second channel is formed in the first die and a bottom surface of the second channel is a top surface of the substrate.

11. The semiconductor device of claim 1, wherein a second portion of the second channel is at least partially formed within the substrate, and wherein the second portion of the second channel is in fluid communication with at least the first portion of the second channel. 12 . The semiconductor device of claim 1 , wherein the second channel is completely contained within the first die and the first die forms a bottom surface of the second channel.

13. The semiconductor device according to claim 12, wherein the substrate further comprises another first channel, wherein the semiconductor device further comprises a second opening, wherein the first opening extends from the first channel to the second channel at a first position, and wherein the second opening extends from the another first channel to the second channel at a second position, and wherein the second channel bridges the first channel and the another first channel.

14. The semiconductor device according to claim 1, wherein the substrate further comprises another first channel, wherein the semiconductor device further comprises a second opening, wherein the first opening extends from the first channel to the second channel at a first position, and wherein the second opening extends from the another first channel to the second channel at a second position, and wherein the second channel bridges the first channel and the another first channel.

15. The semiconductor device according to claim 1, further comprising: a second die coupled to the first die and comprising at least a portion of a third channel, wherein the first die is between the substrate and the second die; and A third opening extends from the first channel to the third channel or from the second channel to the third channel through the first die. 16 . The semiconductor device of claim 15 , wherein the semiconductor device further comprises a fourth opening extending from the third channel to at least a portion of a fourth channel contained within the first die or another first die. 17 . The semiconductor device of claim 1 , wherein the semiconductor device further comprises a port coupled to the first channel, the port configured to allow a fluid to flow into or out of the first channel.

18. A method for manufacturing a semiconductor device, the method comprising: forming a substrate, comprising: forming a first channel in the substrate; and forming a first layer on the substrate and forming a first opening extending from the first channel through the first layer; Wherein the first layer includes an interface configured to be directly coupled to a surface of a die including at least a first portion of a second channel.

19. The method according to claim 18, further comprising: forming the die, comprising: forming at least the first portion of the second channel in the die; and coupling the substrate to the surface of the die via the interface; Wherein the first opening extends from the first channel to the second channel and fluidly couples the first channel to the second channel.

20. A semiconductor device comprising: a substrate comprising a first channel; a die coupled to the substrate and comprising at least a first portion of a second channel; a first opening extending from the first passage to the second passage; and A fluid is contained within the first channel and the second channel and is configured to flow between the first channel and the second channel through the first opening.

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