Semiconductor packaging structure, semiconductor module and vehicle

Abstract

The invention discloses a semiconductor packaging structure, a semiconductor module and a vehicle. The semiconductor packaging structure comprises a substrate and at least one power chip. The substrate comprises a drain electrode power conducting layer, a source electrode power conducting layer and a driving conducting layer which are arranged at intervals, the source electrode power conducting layer and the driving conducting layer are arranged on the two sides of the drain electrode power conducting layer respectively, the power chip is arranged on the drain electrode power conducting layer, and a drain electrode of the power chip is electrically connected with the drain electrode power conducting layer. The source electrode of the power chip is electrically connected with the source electrode power conductive layer, and the driving electrode of the power chip is electrically connected with the driving conductive layer. Therefore, the layout of the semiconductor packaging structure can be optimized, the flexibility of connection between the power chip and each conductive layer can be improved, and the power chip can be electrically connected with different conductive layers in different directions conveniently, so that the heat dissipation performance of the semiconductor packaging structure can be improved, and the power chip can continuously, stably and efficiently work.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure, a semiconductor module and a vehicle. Background Art

[0002] Currently, a single tube is usually packaged by a power chip, which is more flexible in use. However, the traditional single-tube package pins are small and the current capacity is limited. The source power terminal is bonded to the source on the power chip, and insulation and heat dissipation rely on external thermal interface materials or plastic packaging. However, after bonding, the temperature of the power chip rises significantly, and the heat dissipation effect is not ideal. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the first object of the present invention is to provide a semiconductor packaging structure, wherein the housing improves the heat dissipation capability of the semiconductor module.

[0004] A second objective of the present invention is to provide a semiconductor module, comprising the semiconductor package structure described above.

[0005] A third object of the present invention is to provide a vehicle comprising the semiconductor module described above.

[0006] According to the first aspect of the present invention, the semiconductor packaging structure of the embodiment includes: a substrate and at least one power chip, the substrate includes a drain power conductive layer, a source power conductive layer and a driving conductive layer which are arranged at intervals, the source power conductive layer and the driving conductive layer are respectively arranged on both sides of the drain power conductive layer, the power chip is arranged on the drain power conductive layer, the drain of the power chip is electrically connected to the drain power conductive layer, the source of the power chip is electrically connected to the source power conductive layer, and the driving electrode of the power chip is electrically connected to the driving conductive layer.

[0007] According to the semiconductor packaging structure of the embodiment of the present invention, by arranging the source power conductive layer on the substrate, the source of the power chip and the source power conductive layer are electrically connected to other components led out to the semiconductor packaging structure, which can optimize the layout of the semiconductor packaging structure and improve the flexibility of the connection between the power chip and each conductive layer. At the same time, since the driving conductive layer and the source power conductive layer are placed on both sides of the drain power conductive layer, it is convenient for the power chip to be electrically connected to different conductive layers in different directions, thereby improving the heat dissipation of the semiconductor packaging structure, so that the power chip can work continuously, stably and efficiently.

[0008] In some embodiments, the drain power conductive layer, the source power conductive layer and the driving conductive layer are extended along a first direction on the substrate.

[0009] In some embodiments, the drain power conductive layer includes a drain power conductive layer body and an end drain power conductive portion, the end drain power conductive portion is connected to the drain power conductive layer body, and the at least one power chip is disposed in the drain power conductive layer body.

[0010] In some embodiments, the end drain power conductive portion protrudes from the drain power conductive layer body along the second direction, the drain power conductive layer body extends along the first direction, the drain power conductive layer body is located between the driving conductive layer and the source power conductive layer, and the first direction is perpendicular to the second direction.

[0011] In some embodiments, the source power conductive layer includes an end source power conductive portion and a source power conductive layer body, the end source power conductive portion is connected to one end of the source power conductive layer body, the source power conductive layer body extends along a first direction, and the end source power conductive portion protrudes from the source power conductive layer body.

[0012] In some embodiments, the end source power conductive portion is arranged opposite to the drain power conductive layer body, and the end source power conductive portion is arranged at intervals and covers the extended end of the drain power conductive layer body.

[0013] In some embodiments, the end drain power conductive portion protrudes from two ends of the drain power conductive layer body, and is respectively spaced apart and covers the end of the source power conductive layer body and the end of the driving conductive layer.

[0014] In some embodiments, the driving conductive layer includes a driving gate conductive layer, the driving gate conductive layer extends along a first direction, the driving electrode includes a driving gate, and the driving gate conductive layer is electrically connected to the driving gate.

[0015] In some embodiments, the driving conductive layer further includes: a driving source conductive layer, the driving source power conductive layer extending along a first direction; the driving electrode includes a driving source electrode, and the driving source electrode is electrically connected to the driving source conductive layer.

[0016] In some embodiments, the driving source conductive layer and the driving gate conductive layer are spaced apart in a second direction, and the second direction is perpendicular to the first direction.

[0017] In some embodiments, the driving source conductive layer and the driving gate conductive layer are arranged in parallel in the second direction.

[0018] In some embodiments, the semiconductor package structure includes a drain power terminal electrically connected to the drain power conductive layer.

[0019] In some embodiments, the semiconductor package structure includes a source power terminal, and the source power terminal is electrically connected to the source power conductive layer.

[0020] In some embodiments, the semiconductor package structure further includes a driving terminal, and the driving terminal is electrically connected to the driving conductive layer.

[0021] In some embodiments, the driving terminal includes a gate driving terminal, and the gate driving terminal is electrically connected to the driving gate conductive layer.

[0022] In some embodiments, the driving terminal includes a source driving terminal, and the source driving terminal is electrically connected to the driving source conductive layer.

[0023] In some embodiments, the source driving terminal and the driving source conductive layer are arranged opposite to each other along a first direction, and the gate driving terminal and the driving gate conductive layer are arranged opposite to each other along the first direction.

[0024] In some embodiments, the drive terminal and the source power terminal are located on the same side of the substrate.

[0025] In some embodiments, the drain electrode of the power chip is welded to the drain power conductive layer to form an electrical connection.

[0026] In some embodiments, the source of the power chip is electrically connected to the source power conductive layer through a bonding wire.

[0027] In some embodiments, a source power lead-out terminal is included, and the source of the power chip is electrically connected to the source power conductive layer through the source power lead-out terminal.

[0028] In some embodiments, the driving electrode of the power chip is electrically connected to the driving conductive layer through a bonding wire.

[0029] In some embodiments, there are a plurality of power chips, and the plurality of power chips are spaced apart along a first direction and arranged on the drain power conductive layer.

[0030] In some embodiments, the drain power conductive layer includes a plurality of drain power conductive layer bodies and at least one end drain power conductive part, the plurality of drain power conductive layer bodies are spaced apart along a second direction, each of the drain power conductive layer bodies is provided with at least one power chip, and the second direction is perpendicular to the extension direction of the drain power conductive layer body.

[0031] In some embodiments, there are multiple power chips, and the multiple power chips include at least a first power chips group and a second power chips group, the first power chips group includes multiple first power chips, the second power chips group includes multiple second power chips, and the multiple drain power conductive layer bodies include at least a first drain power conductive layer body and a second drain power conductive layer body spaced apart along the second direction; multiple first power chips are spaced apart from each other along the first direction and are spaced apart from each other on the first drain power conductive layer body, and multiple second power chips are spaced apart from each other along the first direction and are spaced apart from each other on the second drain power conductive layer body, and the first direction is the same as the direction in which the drain power conductive layer body extends.

[0032] In some embodiments, there are multiple source power conductive layers, and the multiple source power conductive layers include at least a first source power conductive layer and a second source power conductive layer. The first source power conductive layer is arranged adjacent to the first drain power conductive layer body, and the second source power conductive layer is arranged adjacent to the second drain power conductive layer body.

[0033] In some embodiments, at least one source power terminal is further included, and the source power terminal is electrically connected to the plurality of source power conductive layers.

[0034] In some embodiments, the source power terminal includes at least a first source power terminal portion and a second source power terminal portion, the first source power terminal portion is electrically connected to the first source power conductive layer, and the second source power terminal portion is electrically connected to the second source power conductive layer.

[0035] In some embodiments, one end of the driving conductive layer is located between the plurality of drain power conductive layer bodies, and is used for being electrically connected to the driving electrodes of the plurality of power chips.

[0036] In some embodiments, the semiconductor package structure further includes a driving terminal, and the other end of the driving conductive layer is electrically connected to the driving terminal.

[0037] In some embodiments, the driving conductive layer includes a driving conductive layer body and an end driving conductive portion, the driving conductive layer body is located between two adjacent drain power conductive layer bodies, and the end driving conductive portion is electrically connected to the driving terminal.

[0038] In some embodiments, the drain power terminal, the source power terminal, and the drive terminal are located on a same side of the substrate.

[0039] In some embodiments, the driving conductive layer, the drain power conductive layer and the source power conductive layer are arranged sequentially along the second direction, the driving terminal, the drain power terminal and the source power terminal are arranged sequentially along the second direction, and the driving terminal, the drain power terminal and the source power terminal are respectively arranged corresponding to the driving conductive layer, the drain power conductive layer and the source power conductive layer.

[0040] A semiconductor module according to an embodiment of the second aspect of the present invention comprises the semiconductor packaging structure described in any one of the above embodiments.

[0041] A vehicle according to an embodiment of the third aspect of the present invention comprises the semiconductor packaging structure described in any one of the above embodiments.

[0042] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0044] Figure 1 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present invention.

[0045] Figure 2 Schematic diagram of conductive layer and terminal arrangement according to an embodiment of the present invention.

[0046] Figure 3 It is a schematic diagram of connection using bonding wires according to an embodiment of the present invention.

[0047] Figure 4 It is a schematic diagram of connection using a CLIP connection method according to an embodiment of the present invention.

[0048] Figure 5 It is a schematic diagram of an arrangement of multiple power chips according to an embodiment of the present invention.

[0049] Figure 6 is an equivalent circuit diagram according to an embodiment of the present invention.

[0050] Figure 7 Schematic diagram of conductive layer and terminal arrangement according to another embodiment of the present invention.

[0051] Figure 8 FIG. 4 is a schematic diagram of the conductive layer and terminal arrangement according to another embodiment of the present invention.

[0052] Fig. 9It is a temperature simulation effect diagram of a semiconductor packaging structure in the prior art.

[0053] Fig.10 It is a temperature simulation cross-sectional effect diagram of a semiconductor packaging structure in the prior art.

[0054] Fig.11 4 is a diagram showing the temperature simulation effect of a semiconductor packaging structure according to an embodiment of the present invention.

[0055] Fig.12 It is a cross-sectional effect diagram of a temperature simulation of a semiconductor packaging structure according to an embodiment of the present invention.

[0056] Reference numerals:

[0057] 100. Semiconductor packaging structure;

[0058] 10. Substrate; 11. Drain power conductive layer; 111. Drain power conductive layer body; 1111. First drain power conductive layer body; 1112. Second drain power conductive layer body; 112. End drain power conductive portion; 12. Source power conductive layer; 121. Source power conductive layer body; 122. End source power conductive portion; 123. First source power conductive layer; 124. Second source power conductive layer; 13. Driving conductive layer; 131. Driving gate conductive layer; 132. Driving source conductive layer; 133. Driving conductive layer body; 134. End driving conductive portion; 14. Insulating layer; 15. Second metal layer;

[0059] 20, power chip; 21, driving pole; 211, driving gate; 212, driving source; 22, first power chip group; 221, first power chip; 23, second power chip group; 231, second power chip;

[0060] 31. drain power terminal; 32. source power terminal; 321. first source power terminal portion; 322. second source power terminal portion; 33. source power extraction terminal;

[0061] 40. driving terminal; 41. source driving terminal; 42. gate driving terminal;

[0062] 50. Plastic casing. DETAILED DESCRIPTION

[0063] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Figure 1-Figure 12 A semiconductor package structure 100 according to an embodiment of the present invention is described, comprising: a substrate 10 and at least one power chip 20 .

[0064] Specifically, if Figure 1-Figure 4As shown, the substrate 10 includes a drain power conductive layer 11, a source power conductive layer 12 and a driving conductive layer 13 which are arranged at intervals. The source power conductive layer 12 and the driving conductive layer 13 are respectively arranged on both sides of the drain power conductive layer 11. The power chip 20 is arranged on the drain power conductive layer 11. The drain of the power chip 20 is electrically connected to the drain power conductive layer 11, the source of the power chip 20 is electrically connected to the source power conductive layer 12, and the driving electrode 21 of the power chip 20 is electrically connected to the driving conductive layer 13.

[0065] The substrate 10 includes a first metal layer, a second metal layer 15 and an insulating layer 14 disposed between the first metal layer and the second metal layer 15. The first metal layer is constructed as a drain power conductive layer 11. The insulating layer 14 may be a ceramic layer, which may be used to achieve insulation inside the substrate 10 and ensure good heat dissipation capability of the substrate 10. The substrate 10 may be an AMB (Active Metal Brazing) substrate. The drain power conductive layer 11, the source power conductive layer 12 and the driving conductive layer 13 are disposed on a side of the insulating layer 14 away from the second metal layer 15. The power chip 20 may be connected to a side of the drain power conductive layer 11 away from the insulating layer 14 through a sintering process, and the power chip 20 is placed in the middle of the semiconductor packaging structure 100, so that the peripheral side of the power chip 20 may be used to package the power chip 20.

[0066] On the semiconductor package structure 100, the drain power conductive layer 11 and the source power conductive layer 12 are arranged at intervals, and the power chip 20 has a source, a drain and a driving electrode 21, wherein the source, the drain and the driving electrode 21 are part of the power chip 20, and are areas on the surface of the power chip 20 divided according to different functions. The source is electrically connected to the source power conductive layer 12, the drain is electrically connected to the drain power conductive layer 11, and the driving electrode 21 is electrically connected to the driving conductive layer 13. Each electrode of the power chip 20 corresponds to each distributed conductive layer one by one, which can effectively avoid misconnection and wrong connection, and improve the packaging efficiency of the semiconductor package structure 100.

[0067] The semiconductor package structure 100 includes a plastic package shell 50, thereby forming protection and support for the semiconductor package structure 100, and during the molding process, at least a portion of the substrate 10, such as the second metal layer 15, leaks out of the bottom of the plastic package shell 50, so that the second metal layer 15 can be used to increase the heat dissipation of the semiconductor package structure 100. The power chip 20 is a SiC MOSFET power chip.

[0068] According to the semiconductor package structure 100 of the embodiment of the present invention, by providing the source power conductive layer 12 on the substrate 10, the source of the power chip 20 is electrically connected to the source power conductive layer 12 on other components led out to the semiconductor package structure 100, so that the layout of the semiconductor package structure 100 can be optimized and the flexibility of the connection between the power chip 20 and each conductive layer can be improved. At the same time, since the driving conductive layer 13 and the source power conductive layer 12 are placed on both sides of the drain power conductive layer 11, it is convenient for the power chip 20 to be electrically connected to different conductive layers in different directions, thereby improving the heat dissipation of the semiconductor package structure 100, so that the power chip 20 can continue to work stably and efficiently.

[0069] In some embodiments, Figure 2 As shown, the drain power conductive layer 11, the source power conductive layer 12 and the driving conductive layer 13 are extended along the first direction A on the substrate 10, and the source power conductive layer 12 and the driving conductive layer 13 are arranged on both sides of the drain power conductive layer 11 along the first direction A. Therefore, the drain power conductive layer 11, the source power conductive layer 12 and the driving conductive layer 13 extend along the first direction A, and their width in the second direction B perpendicular to the first direction A can be reduced, which is convenient for reducing the width of the semiconductor package structure 100 in the second direction B, reducing the length of the connecting member between the power chip 20 arranged on the drain power conductive layer 11 and the source power conductive layer 12 and the driving conductive layer 13, and optimizing the space inside the semiconductor package structure 100, so that the direction of the connecting member between the conductive layers is clearer.

[0070] In some embodiments, in combination Figure 2 The drain power conductive layer 11 includes a drain power conductive layer body 111 and an end drain power conductive portion 112. The end drain power conductive portion 112 is connected to the drain power conductive layer body 111. At least one power chip 20 is disposed on the drain power conductive layer body 111. Thus, the power chip 20 is disposed on the drain power conductive layer body 111 so that the distance between the power chip 20 and different conductive layers is close. While optimizing the electrical connection between the power chip 20 and different conductive layers, the heat of the power chip 20 can be dissipated in different directions, thereby improving the heat dissipation capacity of the semiconductor packaging structure 100.

[0071] Further, refer to Figure 2, the end drain power conductive portion 112 protrudes from the drain power conductive layer body 111 along the second direction B, the drain power conductive layer body 111 extends along the first direction A, the drain power conductive layer body 111 is located between the driving conductive layer 13 and the source power conductive layer 12, and the first direction A is perpendicular to the second direction B. That is, one end of the drain power conductive layer body 111 along the first direction A is provided with end drain power conductive portions 112 on both sides along the first direction A, wherein the drain power conductive layer body 111 is provided between the source power conductive layer 12 and the driving conductive layer 13, and is spaced apart from the source power conductive layer 12 and the driving conductive layer 13 along the second direction B. The power chip 20 is suitable for the drain power conductive layer body 111, the source power conductive layer 12 is electrically connected to the source of the power chip 20 on one side of the drain power conductive layer body 111 along the first direction A, and the driving conductive layer 13 is electrically connected to the driving electrode 21 of the power chip 20 on the other side of the drain power conductive layer body 111 along the first direction A.

[0072] Therefore, the source power conductive layer 12 and the driving conductive layer 13 are arranged on both sides of the drain power conductive layer body 111 along the second direction B, and the power chip 20 is arranged on the drain power conductive layer body 111, so that the distance between the power chip 20 and the driving conductive layer 13 and the source power conductive layer 12 is close or equal, and the connectors for connecting the source power conductive layer 12 and the connectors for connecting the driving conductive layer 13 are distributed on both sides of the drain power conductive layer body 111 along the first direction A, which can reduce the mutual interference between the source power conductive layer 12 and the driving conductive layer 13, and optimize the semiconductor packaging structure 100.

[0073] In some embodiments, Figure 2 As shown, the source power conductive layer 12 includes an end source power conductive portion 122 and a source power conductive layer body 121, the end source power conductive portion 122 is connected to one end of the source power conductive layer body 121, the source power conductive layer body 121 extends along the first direction A, and the end source power conductive portion 122 protrudes from the source power conductive layer body 121. That is, the source power conductive layer body 121 extends along the first direction A and is arranged on one side of the drain power conductive layer body 111 along the second direction B, the end source power conductive portion 122 is arranged at one end of the source power conductive layer body 121 away from the end drain power conductive portion 112 along the first direction A, and the end source power conductive portion 122 extends toward the driving conductive layer 13 along the second direction B. Therefore, the arrangement of the source power conductive layer 12 can facilitate electrical connection with the power chip 20 while making full use of the space inside the semiconductor package structure 100.

[0074] For example, the end source power conductive portion 122 is arranged opposite to the drain power conductive layer body 111, and the end source power conductive portion 122 is arranged at intervals and covers the extended end of the drain power conductive layer body 111. The end source power conductive portion 122 is opposite to the drain power conductive layer body 111 in the first direction A and is arranged at intervals, and the end of the end source power conductive portion 122 away from the source power conductive layer body 121 along the second direction B is flush with the side of the drain power conductive layer body 111 away from the source power conductive layer body 121 along the first direction A, and the source power conductive layer 12 covers the drain power conductive layer body 111 on one side of the first direction A and one side of the second direction B, and is arranged at intervals between the drain power conductive layer body 111.

[0075] Therefore, the source power conductive layer body 121 is arranged on one side of the drain power conductive layer body 111, which can facilitate the electrical connection between the source power conductive layer body 121 and the drain power conductive layer body 111, and facilitate the arrangement of the source power conductive layer 12 on the substrate 10, so that the structure of the semiconductor packaging structure 100 is more compact after the source power conductive layer 12 and the drain power conductive layer 11 arranged on the substrate 10 are arranged.

[0076] In some embodiments, Figure 2 As shown, the end drain power conductive portion 112 protrudes from both ends of the drain power conductive layer body 111, and is respectively arranged at intervals and covers the end of the source power conductive layer body 121 and the end of the driving conductive layer 13. In this embodiment, there are two end drain power conductive portions 112, and the two end drain power conductive portions 112 are arranged at one end of the drain power conductive layer body 111 away from the end source power conductive portion 122 along the first direction A, and are respectively arranged on both sides of the drain power conductive layer body 111 along the second direction B, and extend in directions away from each other.

[0077] One end of the driving conductive layer 13 is opposite to one of the end drain power conductive parts 112 along the first direction A, and one of the end drain power conductive parts 112 and the drain power conductive layer body 111 form a covering for the one end of the driving conductive layer 13. One end of the source power conductive layer body 121 away from the end source power conductive part 122 is opposite to the other end drain power conductive part 112 along the first direction A, and the other end drain power conductive part 112 and the drain power conductive layer body 111 form a covering for the one end of the source power conductive layer body 121.

[0078] Thus, the source power conductive layer 12, the drain power conductive layer 11 and the driving conductive layer 13 are reasonably arranged on the substrate 10, the space on the substrate 10 is fully utilized, the length of the drain power conductive layer 11 in the second direction B and the length of the end source power conductive part 122 in the second direction B are increased, and the source power conductive layer 12 and the drain power conductive layer 11 are conveniently electrically connected to other components.

[0079] In some embodiments, Figure 3 and Figure 4 As shown, the driving conductive layer 13 includes a driving gate conductive layer 131, the driving gate conductive layer 131 extends along the first direction A, the driving electrode 21 includes a driving gate 211, and the driving gate conductive layer 131 is electrically connected to the driving gate 211. Therefore, the arrangement of the driving gate 211 facilitates electrical connection with the driving gate conductive layer 131, ensures the accuracy of the connection between the driving conductive layer 13 and the driving electrode 21, and controls the on and off of the semiconductor package structure 100.

[0080] Combination Figure 3 and Figure 4 , the driving conductive layer 13 also includes: a driving source conductive layer 132, the driving source 212 power conductive layer 12 extends along the first direction A, the driving pole 21 includes the driving source 212, and the driving source 212 is electrically connected to the driving source conductive layer 132. That is, the driving pole 21 includes a driving gate 211 and a driving source 212, the driving gate conductive layer 131 and the driving source conductive layer 132 included in the driving, the driving gate 211 is electrically connected to the driving gate conductive layer 131, and the driving source 212 is electrically connected to the driving source conductive layer 132. As a result, different areas of the driving pole 21 are electrically connected to different driving conductive layers 13, which facilitates the precise connection inside the semiconductor packaging structure 100 and improves the installation rate of the semiconductor packaging structure 100.

[0081] In some embodiments, the driving source conductive layer 132 and the driving gate conductive layer 131 are spaced apart in the second direction B, and the second direction B is perpendicular to the first direction A. Thus, the driving source conductive layer 132 and the driving gate conductive layer 131 are spaced apart, so that interference between the driving gate conductive layer 131 and the driving source conductive layer 132 can be avoided.

[0082] In some embodiments, the driving source conductive layer 132 and the driving gate conductive layer 131 are arranged in parallel in the second direction B. Therefore, the driving source conductive layer 132 and the driving gate conductive layer 131 are arranged in parallel, which can facilitate the arrangement of the driving gate conductive layer 131 and the driving source conductive layer 132, reduce the inductance effect between the driving source conductive layer 132 and the driving gate conductive layer 131, optimize the structure of the driving conductive layer 13, and facilitate the arrangement of the driving conductive layer 13 on the substrate 10.

[0083] In some embodiments, Figure 3 and Figure 4 As shown, the semiconductor package structure 100 includes a drain power terminal 31, which is electrically connected to the drain power conductive layer 11. The drain power terminal 31 is disposed at an end of the drain power conductive layer 11 away from the end source power conductive portion 122 along the first direction A, and the drain power terminal 31 is mounted on the substrate 10.

[0084] Therefore, the source power terminal 32 is electrically connected to the drain power conductive layer 11, and the source power terminal 32 is arranged adjacent to the drain power conductive layer 11, which can shorten the length of the connector for electrically connecting the source power terminal 32 and the drain power conductive layer 11, optimize the arrangement of the drain power terminal 31 and the drain power conductive layer 11, and avoid the connector for electrical connection crossing or contacting with the connectors between other conductive layers to cause coupling mutual inductance.

[0085] In some embodiments, Figure 3 As shown, the semiconductor package structure 100 includes a source power terminal 32, and the source power terminal 32 is electrically connected to the source power conductive layer 12. The source power terminal 32 is arranged at one end of the source power conductive layer 12 away from the drain power terminal 31 along the first direction A. At this time, the source power terminal 32 and the drain power terminal 31 are respectively arranged at two ends of the substrate 10 along the first direction A. The connector drawn from the drain power conductive layer 11 extends toward the drain power terminal 31 and is electrically connected to the drain power terminal 31. The connector drawn from the source power conductive layer 12 extends toward the source power terminal 32 and is electrically connected to the source power terminal 32. Therefore, it is possible to effectively avoid the connector connecting the source power terminal 32 and the source power conductive layer 12 from interfering with the connector connecting the drain power terminal 31 and the drain power conductive layer 11, improve the accuracy of the connector connecting the corresponding conductive layers, and at the same time, increase the distance between the connectors connecting different conductive layers, and reduce the possibility of coupling mutual inductance between the connectors connecting different conductive layers.

[0086] In some embodiments, the semiconductor package structure 100 further includes a driving terminal 40, and the driving terminal 40 is electrically connected to the driving conductive layer 13. Figure 3 , Figure 4 , Figure 5 , Figure 7 In the embodiment shown, the driving terminal 40 is arranged at one end of the substrate 10 and is located at the same end of the substrate 10 along the first direction A as the source driving terminal 41, and the driving terminal 40 and the source driving terminal 41 are spaced apart along the second direction B, and the driving terminal 40 is opposite to the driving conductive layer 13 in the first direction A.

[0087] Further, the driving terminal 40 includes a gate driving terminal 42, and the gate driving terminal 42 is electrically connected to the driving gate conductive layer 131. The driving terminal 40 includes a source driving terminal 41, and the source driving terminal 41 is electrically connected to the driving source conductive layer 132. The source driving terminal 41 and the driving source conductive layer 132 are arranged opposite to each other along the first direction A, and the gate driving terminal 42 and the driving gate conductive layer 131 are arranged opposite to each other along the first direction A.

[0088] That is, the driving terminal 40 includes a gate driving terminal 42 and a source driving terminal 41, and the gate driving terminal 42 and the source driving terminal 41 are located on the same side of the substrate 10 and are spaced apart along the second direction B. In order to facilitate the driving terminal 40 to correspond to the corresponding driving conductive layer 13, the gate driving terminal 42 is opposite to the driving gate conductive layer 131 along the first direction A, and the source driving terminal 41 is opposite to the driving source conductive layer 132 along the first direction A. This ensures that the connector connecting the gate driving terminal 42 and the driving gate conductive layer 131 and the connector connecting the source driving terminal 41 and the driving source conductive layer 132 are parallel to each other, avoiding the cross-coupling mutual inductance between the two connectors, reducing the influence between the circuits where the gate driving terminal 42 and the source driving terminal 41 are located, ensuring the performance of the circuit, improving the stability, and avoiding circuit failures.

[0089] Alternatively, if Figure 2-Figure 7 As shown, the driving terminal 40 and the source power terminal 32 are located on the same side of the substrate 10. The driving conductive layer 13 and the source power conductive layer 12 both extend along the first direction A and are arranged at intervals along the second direction B. The driving terminal 40 and the source power terminal 32 are arranged on the same side, which can facilitate the driving terminal 40 to be arranged adjacent to the driving conductive layer 13 and form an electrical connection, and the source power terminal 32 to be arranged adjacent to the source power conductive layer 12 and form an electrical connection, optimize the space inside the semiconductor package structure 100 and the arrangement of each conductive layer and terminal inside, and facilitate the miniaturization design of the semiconductor package structure 100.

[0090] In some embodiments, the drain of the power chip 20 is welded to the drain power conductive layer 11 to form an electrical connection. That is, the power wash plate can be arranged on the drain power conductive layer 11 by welding, so that the drain of the power chip 20 is electrically connected to the drain power conductive layer 11. Therefore, the welding process is simple and has good reliability.

[0091] In some embodiments, the source of the power chip 20 is electrically connected to the source power conductive layer 12 through a bonding wire. Therefore, the connection method of the bonding wire is simple and direct, which can improve the connection efficiency, and the chemical properties of the bonding wire are stable, and it is not easy to form intermetallic compounds to affect the power chip 20. At the same time, the source and the source power conductive layer 12 connected by the bonding wire can make the bonding force between the source and the source power conductive layer 12 strong, have good plasticity, and can maintain a certain geometric shape during the bonding process, thereby improving the stability and reliability of the semiconductor packaging structure 100.

[0092] In some embodiments, Figure 3 As shown, the source includes a source power lead-out terminal 33, and the source of the power chip 20 is electrically connected to the source power conductive layer 12 through the source power lead-out terminal 33. For example, the source includes two source power lead-out terminals 33, and the two source power lead-out terminals 33 are arranged at intervals at the source, and the two source power lead-out terminals 33 are respectively electrically connected to the source power conductive layer 12, and a loop is formed by the arrangement of bonding wires. Therefore, the arrangement of the source lead-out terminal ensures the accuracy of the bonding position and the quality of the bonding wire when the source is connected to the source power terminal 32.

[0093] In some embodiments, in combination Figure 2-Figure 4 The driving electrode 21 of the power chip 20 is electrically connected to the driving conductive layer 13 through a bonding wire. Therefore, by bonding the driving electrode 21 and the corresponding driving conductive layer 13 by means of a bonding wire, the stability of the electrical connection between the driving electrode 21 and the driving conductive layer 13 can be ensured.

[0094] In some embodiments, Figure 2-Figure 5 As shown, there are multiple power chips 20, and the multiple power chips 20 are arranged on the drain power conductive layer 11 at intervals along the first direction A. The multiple power chips 20 are arranged on the drain power conductive layer body 111 at intervals along the first direction A, and the arrangement direction of the power chips 20 is the same as the extension direction of the drain power conductive layer body 111, which increases the utilization of the drain power conductive layer 11 space by the power chips 20, facilitates the parallel design of multiple power chips 20, and improves the current carrying capacity of the semiconductor packaging structure 100.

[0095] In some embodiments, Figure 7 As shown, the drain power conductive layer 11 includes a plurality of drain power conductive layer bodies 111 and at least one end drain power conductive portion 112, the plurality of drain power conductive layer bodies 111 are spaced apart along a second direction B, each drain power conductive layer body 111 is provided with at least one power chip 20, and the second direction B is perpendicular to the extension direction of the drain power conductive layer body 111.

[0096] In this embodiment, in order to increase the number of power chips 20, reduce the volume of the semiconductor package structure 100, such as reducing the length of the drain power conductive layer body 111 in the first direction A, and facilitate the use of the semiconductor package structure 100 in a specific scenario, the drain power conductive layer 11 includes a plurality of drain power conductive layer bodies 111, and the plurality of drain power conductive layer bodies 111 are arranged at intervals along the second direction B and extend along the first direction A. At least one power chip 20 is arranged on each drain power conductive layer body 111. If a plurality of power chips 20 are arranged on each drain power conductive layer body 111, the plurality of power chips 20 are arranged at intervals in the length direction of the drain power conductive layer body 111.

[0097] Furthermore, if Figure 7 As shown, there are multiple power chips 20, and the multiple power chips 20 at least include a first power chip group 22 and a second power chip group 23. The first power chip group 22 includes multiple first power chips 221, and the second power chip group 23 includes multiple second power chips 231. The multiple drain power conductive layer bodies 111 at least include a first drain power conductive layer body 111 and a second drain power conductive layer body 111 arranged at intervals along the second direction B. The multiple first power chips 221 are arranged on the first drain power conductive layer body 111 at intervals along the first direction A, and the multiple second power chips 231 are arranged on the second drain power conductive layer body 111 at intervals along the first direction A. The first direction A is the same as the direction in which the drain power conductive layer body 111 extends. Here, the number of drain power conductive layer bodies 111 arranged at intervals along the second direction B is not specifically limited to two, including but not limited to two, and the power chip 20 arranged on each drain power conductive layer body 111 includes but is not limited to one, and can be two or more. Specifically, a reasonable selection can be made according to the location where the semiconductor package structure 100 is set, the conditions of use, and the power to be achieved.

[0098] Therefore, multiple power chip 20 groups are arranged so that the multiple power chips 20 can be expanded and arranged in the second direction B of the base, thereby increasing the number of power chips 20, improving the current carrying capacity of the semiconductor packaging structure 100, avoiding mutual interference between the bonding wires used for electrical connection between the multiple power chips 20, and reducing parasitic inductance and resistance introduced when packaging semiconductors.

[0099] Another example Figure 7 As shown, there are multiple source power conductive layers 12, and the multiple source power conductive layers 12 include at least a first source power conductive layer 123 and a second source power conductive layer 124. The first source power conductive layer 123 is arranged adjacent to the first drain power conductive layer body 111, and the second source power conductive layer 124 is arranged adjacent to the second drain power conductive layer body 111.

[0100] For example, the first source power conductive layer 123 and the second source power conductive layer 124 are arranged at intervals along the second direction B, and the first source power conductive layer 123 is opposite to the first drain power conductive layer body 111, and the second source power conductive layer 124 is opposite to the second drain power conductive layer body 111. The first source power conductive layer 123 includes a first source power conductive layer body 121 and a first end source power conductive portion 122 connected to each other, the first source power conductive layer body 121 is arranged on a side of the first drain power conductive layer body 111 away from the second drain power conductive layer body 111 along the second direction B, and the first end source power conductive portion 122 is arranged on a side of the first drain power conductive layer body 111 away from the end drain power conductive portion 112 along the first direction A. The second source power conductive layer 124 includes a second source power conductive layer body 121 and a second end source power conductive portion 122 connected to each other. The second source power conductive layer body 121 is arranged along the second direction B on a side of the second drain power conductive layer body 111 away from the first drain power conductive layer body 111, and the second end source power conductive portion 122 is arranged along the first direction A on a side of the second drain power conductive layer body 111 away from the end drain power conductive portion 112.

[0101] Therefore, the arrangement of the first and second source power conductive layers 124 facilitates the first and second source power conductive layers 124 to be opposite to the first and second drain power conductive layer bodies 111, and facilitates the bonding wires led out from the power chips 20 arranged on the first and second drain power conductive layer bodies 111 to be electrically connected to the corresponding source power conductive layer bodies 121 along the second direction B in a direction away from each other, thereby avoiding mutual inductance caused by the proximity or crossing of the bonding wires used for electrical connection, reducing mutual interference between the circuit where the first source power conductive layer 123 is located and the circuit where the second source power conductive layer 124 is located, effectively improving the heat dissipation of the semiconductor packaging structure 100, and avoiding confusion of the bonding wires when connected through bonding wires.

[0102] A plurality of power chips 20 are disposed on each drain power conductive layer body 111 . The plurality of power chips 20 are connected in parallel in the substrate 10 . The bonding wires on two adjacent power chips 20 are spaced apart to avoid mutual interference of inductances on the bonding wires connecting different power chips 20 .

[0103] Optionally, in an embodiment of the present invention, in combination with Figure 5 There may be more than two power chips 20, for example, four power chips 20 may be arranged at intervals along the first direction A on the drain power conductive layer body 111. At this time, the size of the drain power conductive layer body 111 may be increased to meet the arrangement requirements of a larger number of power chips 20, thereby realizing a parallel design of multiple power chips 20 and improving the current carrying capacity of the semiconductor packaging structure 100.

[0104] like Figure 6 As shown in the equivalent circuit diagram according to the embodiment of the present invention, the drain power conduction of the plurality of power chips 20 is

[0105] In some embodiments, Figure 2-Figure 8 As shown, at least one source power terminal 32 is also included, and the source power terminal 32 is electrically connected to the multiple source power conductive layers 12. That is, the source power terminal 32 is arranged on one side of the substrate 10, the source power terminal 32 is electrically connected to the source power conductive layer 12, and the source power conductive layer 12 is electrically connected to the power chip 20. Therefore, the setting of the source power conductive layer 12 can enable the source power terminal 32 and the source of the power chip 20 to be electrically connected through the source power conductive layer 12, avoiding direct bonding between the source power terminal 32 and the power chip 20, and because the power source terminal is in contact with the overtime, the heat dissipation capacity of the source power terminal 32 can be increased, the heat of the power chip 20 can be reduced, the heat dissipation capacity of the power chip 20 can be improved, and the performance of the power chip 20 can be guaranteed. At the same time, the arrangement of the bonding wires electrically connected between the source power terminal 32 and the power chip 20 is more free and flexible, avoiding coupling mutual inductance with the bonding wires of other circuits.

[0106] In some embodiments, reference Figure 7 The source power terminal 32 at least includes a first source power terminal portion 321 and a second source power terminal portion 322. The first source power terminal portion 321 is electrically connected to the first source power conductive layer 123, and the second source power terminal portion 322 is electrically connected to the second source power conductive layer 124. The first source power terminal portion 321 and the second source power terminal portion 322 are opposite to the first source power conductive layer 123 and the second source power conductive layer 124, respectively. The first source power terminal portion 321 and the second source power terminal portion 322 are arranged at intervals along the second direction B, so that the source power terminal 32 can be electrically connected to two source power conductive layers 12 at the same time, so that the bonding wires used to connect different source power conductive layers 12 and the source power terminal 32 can be reasonably distributed in the semiconductor package structure 100, avoiding the mutual influence of the crossing bonding wires.

[0107] In some embodiments, in combination Figure 7, one end of the driving conductive layer 13 is located between a plurality of drain power conductive layer bodies 111, and is used to be electrically connected to the driving electrodes 21 of a plurality of power chips 20. The driving conductive layer 13 is disposed between two drain power conductive layer bodies 111 along the second direction B, and is spaced apart from the drain power conductive layer bodies 111. The drain power conductive layer body 111 is disposed between the source power conductive layer 12 and the driving conductive layer 13 along the second direction B. The bonding wires drawn from the source of the power chip 20 and the bonding wires drawn from the driving electrode 21 extend in a direction away from each other along the second direction B to the source power conductive layer 12 and the driving conductive layer 13 in the corresponding direction.

[0108] Therefore, the driving conductive layer 13 and the source power conductive layer 12 are arranged on both sides of the drain power conductive layer body 111 along the second direction B, that is, on both sides of the power chip 20, so that the bonding wires led out from the source of the power chip 20 and the bonding wires led out from the driving electrode 21 can extend in different directions, increase the distance between the driving circuit where the driving conductive layer 13 is located and the power circuit where the source power conductive layer 12 is located, avoid the bonding wires connected to the source and the bonding wires connected to the driving electrode 21 from being close to or intersecting, and can greatly reduce the coupling mutual inductance between the power circuit where the source power conductive layer 12 is located and the driving circuit where the driving conductive layer 13 is located, thereby reducing the influence of the current change in the power circuit on the driving circuit.

[0109] Furthermore, if Figure 7 As shown, the semiconductor package structure 100 further includes a driving terminal 40, and the other end of the driving conductive layer 13 is electrically connected to the driving terminal 40. The driving terminal 40 is disposed on one side of the substrate 10 along the first direction A, and the driving terminal 40 is electrically connected to the driving conductive layer 13 to achieve communication with an external circuit or device. The driving terminal 40 is disposed on the base to increase the heat dissipation of the driving terminal 40.

[0110] Among them, the driving conductive layer 13 includes a driving conductive layer body 133 and an end driving conductive part 134, the driving conductive layer body 133 is located between two adjacent drain power conductive layer bodies 111, and the end driving conductive part 134 is electrically connected to the driving terminal 40. That is, the driving conductive layer 13 includes a driving conductive layer body 133 and an end driving conductive part 134, the driving conductive layer body 133 is arranged between two adjacent drain power conductive layer bodies 111, and the end driving conductive part 134 is arranged at one end of the driving conductive layer body 133 away from the end drain power conductive part 112 along the first direction A, and extends toward the driving terminal 40, and can realize electrical connection to the driving terminal 40 by bonding wires. In this embodiment, the end driving conductive part 134 is arranged between the source power conductive layer 12 and the driving terminal 40. Therefore, the design of the driving conductive layer 13 can facilitate the use of the space on the substrate 10, so that the bonding wires inside the semiconductor package structure 100 can be clearly arranged to avoid mutual inductance between the bonding wires.

[0111] In some embodiments, Figure 8 As shown, the drain power terminal 31, the source power terminal 32 and the driving terminal 40 are located on the same side of the substrate 10. The driving terminal 40 and the source power terminal 32 are spaced apart along the second direction B. Thus, the driving terminal 40 and the source power terminal 32 are located on the same side of the substrate 10, which can increase the space utilization rate on the substrate 10 on the side where the source power terminal 32 is located, and avoid the power terminals being connected in reverse or connected to the same conductive layer to affect the quality of the semiconductor package structure 100.

[0112] In this embodiment, the source power terminal 32, the drain power terminal 31 and the driving terminal 40 are arranged on the same side of the substrate 10 along the first direction A, and the source power terminal 32 is arranged adjacent to the source driving conductive layer 13, the drain power terminal 31 is arranged adjacent to the drain driving conductive layer 13, and the driving terminal 40 is arranged adjacent to the driving conductive layer 13. The source driving conductive layer 13, the drain driving conductive layer 13 and the driving conductive layer 13 are arranged at intervals along the second direction B, and the source power conductive layer 12 and the driving conductive layer 13 are respectively arranged on both sides of the drain driving conductive layer 13.

[0113] That is, the driving conductive layer 13, the drain power conductive layer 11 and the source power conductive layer 12 are arranged in sequence along the second direction B, the driving terminal 40, the drain power terminal 31 and the source power terminal 32 are arranged in sequence along the second direction B, and the driving terminal 40, the drain power terminal 31 and the source power terminal 32 are respectively arranged corresponding to the driving conductive layer 13, the drain power conductive layer 11 and the source power conductive layer 12.

[0114] Thus, multiple terminals are electrically connected to the corresponding conductive layers. The above arrangement can shorten the distance between the terminals and the corresponding conductive layers and the length of the bonding wires for realizing electrical connection, thereby optimizing the semiconductor packaging structure 100, effectively avoiding the influence between adjacent bonding wires, and improving the power of the semiconductor packaging structure 100 while enhancing the current carrying capacity of the semiconductor packaging structure 100.

[0115] In the above embodiment, if Figure 3 As shown, the power chip 20 and the source power conductive layer 12 and the driving conductive layer 13, the source power terminal 32 and the source power conductive layer 12, the drain power terminal 31 and the drain power conductive layer 11, and the driving terminal 40 and the driving conductive layer 13 can all be electrically connected through bonding wires. The bonding wires can be used to connect the drain power terminal 31 and the drain power conductive layer 11, the power chip 20 and the source power conductive layer 12, and then connect the source power terminal 32. The driving electrode 21 is connected to the driving conductive layer 13 through the bonding wires, and then connected to the driving terminal 40, and the source is connected to the source power conductive layer 12 through the bonding wires to form a Kelvin connection, and then connected to the source driving terminal 41 through the bonding wires.

[0116] In the above embodiment, if Figure 4 , Figure 5 , Figure 7 and Figure 8 As shown, the power chip 20 and the source power conductive layer 12, the drain power terminal 31 and the drain power conductive layer 11, and the source power terminal 32 and the source power conductive layer 12 can be electrically connected through copper sheets, and the drive circuits formed between other conductive layers and terminals can be connected through a bonding wire process, so that this embodiment adopts the CLIP connection method. The drain power terminal 31 is directly connected to the drain conductor, and preferably, the connection method is ultrasonic welding. The power chip 20 is connected to the source power conductive layer 12 through the power chip 20 source CLIP, and preferably, the connection method is sintering. The source power terminal 32 is directly connected to the source power conductive layer 12, and preferably, the connection method is ultrasonic welding.

[0117] like Figure 6As shown, according to the equivalent circuit diagram of the embodiment of the present invention, the drain power conductive layer 11 and the source power conductive layer 12 of the multiple power chips 20 are respectively connected to form a parallel structure between the multiple power chips 20, and an interface for connecting to an external circuit is provided through a drain power terminal 31 electrically connected to the drain power conductive layer 11 and a source power terminal 32 electrically connected to the source power conductive layer 12. The gates of the multiple power chips 20 are electrically connected to the driving gate conductive layer 131, and a connection interface with an external driving circuit is provided through a gate driving terminal 42. The sources of the multiple power chips 20 are electrically connected to the driving source conductive layer 132, and an external connection interface is provided through a source driving terminal 41, forming a Kelvin connection to eliminate the influence of the common source inductance on the switching performance of the power chip 20. Among them, the Kelvin connection is a simple method for eliminating the influence of the voltage drop generated on the wire in the circuit.

[0118] Combination Figure 9-10 , showing the thermal simulation of existing products, the simulation conditions are typical working conditions (current 200A, single power chip 20 loss 200W, the surface temperature of the second metal layer 15 at the bottom of the substrate 10 is 90℃, and the heat transfer coefficient of the remaining surface is 5W / (m 2 K)). For the internal heat conduction of the packaged structure of the peninsula, the SiC power chip 20 and the AMB substrate have extremely high thermal conductivity, and the thermal conductivity of the plastic packaging material is much lower than that of the AMB substrate. For external heat dissipation, the bottom surface in contact with the heat sink is the main heat dissipation path, and the rest of the surface is in contact with the air, and the heat dissipation efficiency is extremely low.

[0119] from Fig. 9 It can be seen from the partial view of the terminal that since the source power terminal 32 is in direct contact with the SiC power chip 20 and the temperature of the SiC power chip 20 is relatively high during operation, the heat generated by the current flowing through the terminal cannot be conducted to the AMB substrate through the SiC power chip 20 and can only be conducted through the plastic package shell 50. Therefore, the source power terminal 32 has a very high temperature rise, and the overall temperature exceeds 130°C.

[0120] In addition, due to the high temperature of the source power terminal 32, the overall temperature rise of the plastic package housing 50 is also high. Fig.10 shown.

[0121] like Figure 11-Figure 12 The following are the simulation results of this application under the same conditions. Fig.11It can be seen from the partial view of the terminal that the source power terminal 32 in this patent is in direct contact with the AMB substrate, and the heat generated by the flow can be directly transferred to the heat dissipation bottom surface through the AMB substrate, with higher heat dissipation efficiency and extremely low temperature rise. The overall temperature of the terminal is about 93°C, which is only about 3°C ​​higher than the temperature rise of the heat dissipation bottom surface. The thermal simulation results show that in high-power applications, the patent solution has a greater flow capacity when the terminal cross-sectional area is the same. In addition, Fig.12 As shown, in the present patent, the area of ​​the plastic-encapsulated housing 50 affected by high temperature is smaller, which is beneficial to improving reliability.

[0122] A semiconductor module according to an embodiment of the second aspect of the present invention includes any one of the semiconductor packaging structures 100 described above.

[0123] According to the semiconductor module of the embodiment of the present invention, a source power conductive layer 12 is arranged on the substrate 10 of the semiconductor packaging structure 100, so that the source power terminal 32 and the source of the power chip 20 are respectively electrically connected to the source power conductive layer 12 through bonding wires, which can improve the heat dissipation capability of the semiconductor packaging structure 100, achieve lower parasitic inductance, and enhance the current carrying capacity of the semiconductor module. In addition, since the driving terminal 40 and the source power terminal 32 are all arranged on the substrate 10, combined with the insulation and heat dissipation capabilities inside the substrate 10, the power chip 20 and the semiconductor module can maintain good performance.

[0124] A vehicle according to an embodiment of the third aspect of the present invention comprises a semiconductor packaging structure 100 according to any one of the above embodiments.

[0125] According to the vehicle of the present invention, by using the semiconductor package structure 100 described above, the vehicle has good performance.

[0126] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0127] In the description of the present invention, "first feature" and "second feature" may include one or more of the features. In the description of the present invention, "plurality" means two or more. In the description of the present invention, a first feature "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. In the description of the present invention, a first feature "above", "above" and "above" a second feature may include the first feature being directly above and obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature.

[0128] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0129] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor packaging structure, characterized in that: include: A substrate, the substrate comprising a drain power conductive layer, a source power conductive layer and a driving conductive layer which are arranged at intervals, wherein the source power conductive layer and the driving conductive layer are respectively arranged on both sides of the drain power conductive layer; At least one power chip is disposed on the drain power conductive layer, the drain of the power chip is electrically connected to the drain power conductive layer, the source of the power chip is electrically connected to the source power conductive layer, and the driving electrode of the power chip is electrically connected to the driving conductive layer.

2. The semiconductor package structure according to claim 1, wherein: The drain power conductive layer, the source power conductive layer and the driving conductive layer are extended along a first direction on the substrate.

3. The semiconductor package structure according to claim 2, characterized in that: The drain power conductive layer comprises a drain power conductive layer body and an end drain power conductive portion, the end drain power conductive portion is connected to the drain power conductive layer body, and the at least one power chip is arranged on the drain power conductive layer body.

4. The semiconductor package structure according to claim 3, characterized in that: The end drain power conductive portion protrudes from the drain power conductive layer body along the second direction. The drain power conductive layer body extends along the first direction. The drain power conductive layer body is located between the driving conductive layer and the source power conductive layer. The first direction is perpendicular to the second direction.

5. The semiconductor package structure according to claim 4, characterized in that: The source power conductive layer includes an end source power conductive part and a source power conductive layer body, wherein the end source power conductive part is connected to one end of the source power conductive layer body, the source power conductive layer body extends along a first direction, and the end source power conductive part protrudes from the source power conductive layer body.

6. The semiconductor package structure according to claim 5, characterized in that: The end source power conductive part is arranged opposite to the drain power conductive layer body, and the end source power conductive part is arranged at intervals and covers the extended end of the drain power conductive layer body.

7. The semiconductor package structure according to claim 6, characterized in that: The end drain power conductive part protrudes from two ends of the drain power conductive layer body, and is respectively arranged at intervals and covers the end of the source power conductive layer body and the end of the driving conductive layer.

8. The semiconductor package structure according to claim 1, wherein: The driving conductive layer comprises a driving gate conductive layer, and the driving gate conductive layer extends along a first direction; The driving electrode includes a driving gate, and the driving gate conductive layer is electrically connected to the driving gate.

9. The semiconductor package structure according to claim 8, characterized in that: The driving conductive layer further comprises: a driving source conductive layer, wherein the driving source power conductive layer extends along a first direction; The driving electrode includes a driving source electrode, and the driving source electrode is electrically connected to the driving source electrode conductive layer.

10. The semiconductor package structure according to claim 9, wherein: The driving source conductive layer and the driving gate conductive layer are spaced apart in a second direction, and the second direction is perpendicular to the first direction.

11. The semiconductor package structure according to claim 10, characterized in that: The driving source conductive layer and the driving gate conductive layer are arranged in parallel in the second direction.

12. The semiconductor package structure according to claim 9, wherein: include: A drain power terminal is electrically connected to the drain power conductive layer.

13. The semiconductor package structure according to claim 12, wherein: include: A source power terminal is electrically connected to the source power conductive layer.

14. The semiconductor package structure according to claim 13, characterized in that: Also includes: A driving terminal is electrically connected to the driving conductive layer.

15. The semiconductor package structure according to claim 14, characterized in that: The driving terminal includes: a gate driving terminal, and the gate driving terminal is electrically connected to the driving gate conductive layer.

16. The semiconductor package structure according to claim 15, characterized in that: The driving terminal includes: a source driving terminal, and the source driving terminal is electrically connected to the driving source conductive layer.

17. The semiconductor package structure according to claim 16, wherein: The source driving terminal and the driving source conductive layer are arranged opposite to each other along a first direction, and the gate driving terminal and the driving gate conductive layer are arranged opposite to each other along the first direction.

18. The semiconductor package structure according to claim 14, wherein: The driving terminal and the source power terminal are located on the same side of the substrate.

19. The semiconductor package structure according to claim 1, wherein: The drain of the power chip is welded to the drain power conductive layer to form an electrical connection.

20. The semiconductor package structure according to claim 1, wherein: The source of the power chip is electrically connected to the source power conductive layer through a bonding wire.

21. The semiconductor package structure according to claim 1, wherein: include: A source power lead-out terminal, through which the source of the power chip is electrically connected to the source power conductive layer.

22. The semiconductor package structure according to claim 1, wherein: The driving electrode of the power chip is electrically connected to the driving conductive layer through a bonding wire.

23. The semiconductor package structure according to any one of claims 1 to 22, characterized in that: There are a plurality of power chips, and the plurality of power chips are arranged on the drain power conductive layer at intervals along a first direction.

24. The semiconductor package structure according to any one of claims 1 to 22, characterized in that: The drain power conductive layer includes a plurality of drain power conductive layer bodies and at least one end drain power conductive part, the plurality of drain power conductive layer bodies are spaced apart along a second direction, each of the drain power conductive layer bodies is provided with at least one power chip, and the second direction is perpendicular to the extension direction of the drain power conductive layer bodies.

25. The semiconductor package structure according to claim 24, characterized in that: There are multiple power chips, the multiple power chips at least include a first power chips group and a second power chips group, the first power chips group includes multiple first power chips, the second power chips group includes multiple second power chips, and the multiple drain power conductive layer bodies at least include a first drain power conductive layer body and a second drain power conductive layer body spaced apart along the second direction; A plurality of the first power chips are arranged in the first drain power conductive layer body and spaced apart from each other along a first direction, and a plurality of the second power chips are arranged in the second drain power conductive layer body and spaced apart from each other along the first direction, and the first direction is the same as the direction in which the drain power conductive layer body extends.

26. The semiconductor package structure according to claim 25, characterized in that: There are multiple source power conductive layers, and the multiple source power conductive layers at least include a first source power conductive layer and a second source power conductive layer. The first source power conductive layer is arranged adjacent to the first drain power conductive layer body, and the second source power conductive layer is arranged adjacent to the second drain power conductive layer body.

27. The semiconductor package structure according to claim 26, wherein: Also includes: At least one source power terminal is electrically connected to the plurality of source power conductive layers.

28. The semiconductor package structure according to claim 26, wherein: The source power terminal includes at least a first source power terminal portion and a second source power terminal portion, the first source power terminal portion is electrically connected to the first source power conductive layer, and the second source power terminal portion is electrically connected to the second source power conductive layer.

29. The semiconductor package structure according to claim 24, wherein: One end of the driving conductive layer is located between the plurality of drain power conductive layer bodies and is used for being electrically connected to the driving electrodes of the plurality of power chips.

30. The semiconductor package structure according to claim 29, wherein: Also includes: A driving terminal, the other end of the driving conductive layer is electrically connected to the driving terminal.

31. The semiconductor package structure according to claim 29, wherein: The driving conductive layer comprises: a driving conductive layer body and an end driving conductive portion, the driving conductive layer body is located between two adjacent drain power conductive layer bodies, and the end driving conductive portion is electrically connected to the driving terminal.

32. The semiconductor package structure according to claim 14, characterized in that: The drain power terminal, the source power terminal and the drive terminal are located on a same side of the substrate.

33. The semiconductor package structure according to claim 32, characterized in that: The driving conductive layer, the drain power conductive layer and the source power conductive layer are arranged in sequence along the second direction, the driving terminal, the drain power terminal and the source power terminal are arranged in sequence along the second direction, and the driving terminal, the drain power terminal and the source power terminal are respectively arranged corresponding to the driving conductive layer, the drain power conductive layer and the source power conductive layer.

34. A semiconductor module, characterized in that: Comprising the semiconductor package structure as claimed in any one of claims 1 to 33.

35. A vehicle, characterized in that: Comprising the semiconductor package structure as claimed in any one of claims 1 to 33.

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