Semiconductor package

Abstract

A semiconductor package includes: a first wiring structure; an extension structure disposed on the first wiring structure, including an extension base layer and a plurality of via structures including a plurality of via connection patterns, and having a mounting space passing through the extension base layer; a semiconductor chip disposed in the mounting space and electrically connected to the first wiring structure; the filling insulating layer is used for filling the mounting space; and a second wiring structure disposed on the extension structure and the filling insulating layer and electrically connected to the first wiring structure. A lowermost via connection pattern among the plurality of via connection patterns includes a plurality of first lower connection pads, and the extended base layer includes base dams respectively passing through the plurality of first lower connection pads.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor package, and more particularly, to a fan-out panel level package (FOPLP) and a package-on-package (POP) including the FOPLP. Background Art

[0002] According to the rapid development of the electronics industry and the needs of users, electronic devices are becoming more compact, multifunctional, and larger in capacity, and thus, highly integrated semiconductor chips are being developed.

[0003] Therefore, for highly integrated semiconductor chips with an increased number of input / output (I / O) connection terminals, semiconductor packages with connection terminals that ensure connection reliability have been designed. For example, in order to prevent interference between connection terminals, fan-out semiconductor packages such as fan-out panel level packages (FOPLP) have been developed to increase the distance between connection terminals. Summary of the invention

[0004] A semiconductor package includes a first wiring structure. An extension structure is arranged on the first wiring structure, the extension structure includes an extension base layer and a plurality of via structures, and has an installation space passing through the extension base layer, wherein the plurality of via structures include a plurality of via connection patterns and a plurality of extension vias, the plurality of via connection patterns are arranged on the upper surface and the lower surface of the extension base layer, the plurality of extension vias connect two via connection patterns among the plurality of via connection patterns to each other, and the two via connection patterns are at different vertical heights from each other. A semiconductor chip is arranged in the installation space and electrically connected to the first wiring structure. A filling insulating layer fills the installation space. A second wiring structure is arranged on the extension structure and the filling insulating layer and electrically connected to the first wiring structure through the plurality of via structures. The lowest via connection pattern among the plurality of via connection patterns includes a plurality of first lower connection pads. The extension base layer includes base dams that pass through the plurality of first lower connection pads and protrude and extend from the plurality of first lower connection pads, respectively.

[0005] A semiconductor package includes a first wiring structure. A second wiring structure is arranged above the first wiring structure. An extension structure is arranged between the first wiring structure and the second wiring structure, and has an installation space passing through the extension structure from the upper surface to the lower surface of the extension structure. A semiconductor chip is arranged inside the installation space. A filling insulating layer fills the installation space and covers the upper surface of the semiconductor chip and the upper surface of the extension structure. The extension structure includes a plurality of extension base layers stacked on each other, a plurality of via connection patterns, and a plurality of extension vias, the plurality of via connection patterns being arranged on the upper surface and the lower surface of each of the plurality of extension base layers, the plurality of extension vias passing through at least one of the plurality of extension base layers and connecting two via connection patterns among the plurality of via connection patterns to each other, the two via connection patterns being at different vertical heights from each other. The lowest via connection pattern among the plurality of via connection patterns includes a plurality of first lower connection pads and a plurality of second lower connection pads, the plurality of first lower connection pads being arranged around the installation space and each having a pad groove, and the plurality of second lower connection pads at least partially surrounding the plurality of first lower connection pads. The extended base layer includes a base dam that passes through each of the plurality of first lower connection pads while filling the pad groove and protrudes downward from a lower surface of each of the plurality of first lower connection pads.

[0006] A semiconductor package includes a first wiring structure, the first wiring structure includes a first redistribution insulating layer, a plurality of first redistribution line patterns and a plurality of first redistribution paths, the plurality of first redistribution line patterns are arranged on at least one of the upper surface and the lower surface of the first redistribution insulating layer, the plurality of first redistribution paths pass through the first redistribution insulating layer and are respectively connected to some of the plurality of first redistribution line patterns. An extension structure is arranged on the first wiring structure, the extension structure includes a plurality of extension base layers and a plurality of path structures passing through the plurality of extension base layers and connected to some of the plurality of first redistribution paths, and has an installation space passing through the plurality of extension base layers. A semiconductor chip is arranged in the installation space and includes a plurality of chip pads connected to other first redistribution paths among the plurality of first redistribution paths. A filling insulating layer fills the installation space and covers the upper surface of the semiconductor chip and the upper surface of the extension structure. The second wiring structure is arranged on the filling insulation layer and includes a second redistribution insulation layer, a plurality of second redistribution line patterns and a plurality of second redistribution vias, the plurality of second redistribution line patterns are arranged on at least one of the upper surface and the lower surface of the second redistribution insulation layer, the plurality of second redistribution vias pass through the second redistribution insulation layer and are respectively connected to some of the second redistribution line patterns among the plurality of second redistribution line patterns. The second wiring structure is electrically connected to the first wiring structure through the plurality of via structures. The plurality of via structures include a plurality of via connection patterns and a plurality of extended vias, the plurality of via connection patterns are arranged on the upper surface and the lower surface of each of the plurality of extended base layers, the plurality of extended vias pass through at least one extended base layer and connect two via connection patterns among the plurality of via connection patterns to each other, the two via connection patterns being at different vertical heights from each other. The lowest via connection pattern among the plurality of via connection patterns is buried in the lowest extended base layer among the plurality of extended base layers, and includes a plurality of first lower connection pads and a plurality of second lower connection pads, the plurality of first lower connection pads being arranged around the mounting space and each having a pad groove, the plurality of second lower connection pads at least partially surrounding the plurality of first lower connection pads. The extended base layer includes a base dam, the base dam passing through each of the plurality of first lower connection pads while filling the pad groove, and extending into the first redistribution insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1Ais a cross-sectional view of a semiconductor package as a fan-out panel level package (FOPLP) according to an embodiment;

[0009] Figure 1B It shows Figure 1A An enlarged cross-sectional view of the IB region;

[0010] Figure 1C It shows Figure 1A An enlarged cross-sectional view of the IC region;

[0011] Figure 1D It shows Figure 1C An enlarged cross-sectional view of the ID region;

[0012] FIG. 2A to FIG. 2J is an enlarged top view showing a lower extended connection pad and its surrounding area in a semiconductor package as a FOPLP according to an embodiment;

[0013] Figure 3A is a top view of a semiconductor package as a FOPLP according to an embodiment;

[0014] Figure 3B is an enlarged top view showing the second lower connection pad and its surrounding area;

[0015] Figure 3C is an enlarged top view showing the first lower connecting pad and its surrounding area;

[0016] Figure 4A is a top view of a semiconductor package as a FOPLP according to an embodiment;

[0017] Figure 4B is an enlarged top view showing the second lower connection pad and its surrounding area;

[0018] Figure 4C is an enlarged top view showing the first lower connecting pad and its surrounding area;

[0019] FIG. 5A to FIG. 5L is a cross-sectional view describing a method of manufacturing a semiconductor package as a FOPLP according to an embodiment; and

[0020] Figure 6 is a cross-sectional view of a semiconductor package as a stacked package according to an embodiment. DETAILED DESCRIPTION

[0021] Figures 1A to 1D is a cross-sectional view of a semiconductor package 1 as a fan-out panel level package (FOPLP) according to an embodiment.

[0022] Reference together Figures 1A to 1D, the semiconductor package 1 may include: a first wiring structure 200; a second wiring structure 400, which is arranged above the first wiring structure 200; at least one semiconductor chip 100, which is arranged between the first wiring structure 200 and the second wiring structure 400; and an expansion layer 300 (or referred to as an extension structure), which is arranged between the first wiring structure 200 and the second wiring structure 400 and at least partially surrounds the at least one semiconductor chip 100. The extension structure 300 can electrically connect the first wiring structure 200 and the second wiring structure 400 to each other. In some embodiments, the semiconductor package 1 may include a fan-out panel level package (FOPLP). The semiconductor package 1 may have a chip accommodating area CAR and a chip peripheral area CER surrounding the chip accommodating area CAR, and at least one semiconductor chip 100 is located in the chip accommodating area CAR. The chip accommodating area CAR may be rectangular in a top view, and the chip peripheral area CER may at least partially surround the chip accommodating area CAR in a top view.

[0023] In some embodiments, at least one of the first wiring structure 200 and the second wiring structure 400 may be formed by a redistribution process. The first wiring structure 200 and the second wiring structure 400 may be referred to as a first redistribution structure and a second redistribution structure, respectively, or may be referred to as a lower redistribution structure and an upper redistribution structure, respectively. In some embodiments, the semiconductor package 1 may be formed by a chip-first method in which an extension structure 300 and at least one semiconductor chip 100 are formed, and then the first wiring structure 200 and the second wiring structure 400 are formed. In some embodiments, at least one of the first wiring structure 200 and the second wiring structure 400 may include a printed circuit board.

[0024] The first wiring structure 200 may include a first redistribution insulating layer 210 and a plurality of first redistribution patterns 220. The first redistribution insulating layer 210 may at least partially surround the plurality of first redistribution patterns 220. In some embodiments, the first wiring structure 200 may include a plurality of first redistribution insulating layers 210 stacked on each other. The first redistribution insulating layer 210 may include an organic material. For example, the first redistribution insulating layer 210 may include a photoimageable dielectric or a photosensitive polyimide or include a build-up film such as an Ajinomoto build-up film (ABF).

[0025] The plurality of first redistribution patterns 220 may include a plurality of first redistribution line patterns 222 and a plurality of first redistribution paths 224. In some embodiments, the plurality of first redistribution patterns 220 may further include a plurality of first redistribution seed layers. The plurality of first redistribution patterns 220 may include, for example, metals such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga) and ruthenium (Ru), or alloys of these metals, but the embodiments are not necessarily limited thereto. In some embodiments, the first redistribution line patterns 222 and the first redistribution paths 224 may include the same material. The first redistribution seed layer may include a material different from the material of the first redistribution line patterns 222 and the first redistribution paths 224. In some embodiments, each of the first redistribution line patterns 222 and the first redistribution paths 224 may include copper. For example, the first redistribution line pattern 222 and the first redistribution via 224 may include copper or an alloy of copper. In some embodiments, the first redistribution seed layer may include titanium. For example, the first redistribution seed layer may include titanium or titanium nitride.

[0026] The plurality of first redistribution vias 224 may pass through at least one first redistribution insulating layer 210, and then may contact and be connected to some of the plurality of first redistribution line patterns 222. In some embodiments, the plurality of first redistribution vias 224 may each have a tapered shape extending from bottom to top with decreasing horizontal width. For example, the horizontal width of the plurality of first redistribution vias 224 may increase in a direction away from at least one semiconductor chip 100.

[0027] In some embodiments, at least some of the plurality of first redistribution line patterns 222 may be formed together with some of the plurality of first redistribution paths 224 to form an integrated body. For example, the first redistribution line pattern 222 and the first redistribution path 224 in contact with the upper surface of the first redistribution line pattern 222 (e.g., the first redistribution path 224 extending from the upper surface of the first redistribution line pattern 222) may be formed together to form an integrated body. For example, the horizontal width of each of the plurality of first redistribution paths 224 may decrease in a direction away from the first redistribution line pattern 222 integrated therewith. The first redistribution seed layer may cover the upper portions of the first redistribution line pattern 222 and the first redistribution path 224 integrated with each other. For example, among the surfaces of the first redistribution line pattern 222 and the first redistribution path 224 integrated with each other, the first redistribution seed layer may cover the upper surface of the first redistribution line pattern 222 and the side surface and the upper surface of the first redistribution path 224. The first redistribution seed layer may not cover side surfaces and lower surfaces of the first redistribution line patterns 222 .

[0028] The first wiring structure 200 may include a plurality of lower connection pads PAD-L disposed on the lower surface of the first wiring structure 200. In some embodiments, each of the plurality of lower connection pads PAD-L may include a portion of the first redistribution line pattern 222 and a lower connection pad layer 230 covering the lower surface of the portion of the first redistribution line pattern 222. The lower connection pad layer 230 may include a first lower metal layer 232 and a second lower metal layer 234 sequentially stacked on the lower surface of the portion of the first redistribution line pattern 222. In some embodiments, the first lower metal layer 232 may include nickel (Ni), and the second lower metal layer 234 may include gold (Au), but the embodiment is not necessarily limited thereto. A plurality of external connection terminals 500 may be attached to the plurality of lower connection pads PAD-L, respectively. The plurality of external connection terminals 500 may connect the semiconductor package 1 to an external circuit, such as a printed circuit board (PCB).

[0029] At least one semiconductor chip 100 may be attached to the first wiring structure 200. The semiconductor chip 100 may include a semiconductor substrate 110, a semiconductor device 112, and a plurality of chip pads 120, the semiconductor substrate 110 having an active surface and an inactive surface opposite to each other, the semiconductor device 112 being formed on the active surface of the semiconductor substrate 110, and the plurality of chip pads 120 being disposed on the semiconductor device 112. The semiconductor chip 100 may have a first surface and a second surface opposite to each other. The plurality of chip pads 120 may be disposed on the first surface of the semiconductor chip 100. The second surface of the semiconductor chip 100 may include an inactive surface of the semiconductor substrate 110. The active surface of the semiconductor substrate 110 is close to the first surface of the semiconductor chip 100, and therefore, the active surface of the semiconductor substrate 110 and the first surface of the semiconductor chip 100 are shown indistinguishably. In some embodiments, the plurality of chip pads 120 may protrude from the first surface of the semiconductor chip 100 and be buried in the first wiring structure 200. For example, at least a portion of each of the plurality of chip pads 120 may be buried in the uppermost first redistribution insulating layer 210 among the plurality of first redistribution insulating layers 210. The plurality of chip pads 120 may be in contact with and connected to some of the plurality of first redistribution patterns 220. For example, the plurality of chip pads 120 may be connected to some of the uppermost redistribution vias 224 among the first redistribution vias 224.

[0030] The semiconductor substrate 110 may include semiconductor materials such as silicon (Si) and germanium (Ge). Likewise, the semiconductor substrate 110 may include compound semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate 110 may include a conductive region, such as a well doped with impurities. The semiconductor substrate 110 may have various device isolation structures, such as a shallow trench isolation structure.

[0031] A semiconductor device 112 including a plurality of individual devices of various types may be formed on an active surface of the semiconductor substrate 110. The plurality of individual devices may include various microelectronic devices, for example, metal oxide semiconductor field effect transistors (MOSFETs) such as complementary metal oxide semiconductor (CMOS) transistors, system large scale integration (LSI), active elements, passive elements, etc. The plurality of individual devices may be electrically connected to a conductive region of the semiconductor substrate 110. The semiconductor device 112 may also include conductive wires or conductive plugs that electrically connect at least two of the plurality of individual devices to each other or electrically connect the plurality of individual devices to a conductive region of the semiconductor substrate 110. Likewise, each of the plurality of individual devices may be electrically separated from an adjacent individual device by an insulating film.

[0032] In some embodiments, the semiconductor chip 100 may include a logic element. For example, the semiconductor chip 100 may include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In some embodiments, the semiconductor chip 100 may include a memory semiconductor chip having a memory element. For example, the memory element may include a non-volatile memory element, such as a flash memory, a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), and a resistive random access memory (RRAM). The flash memory may include, for example, a negative AND (NAND) flash memory or a vertical NAND (V-NAND) flash memory. In some embodiments, the memory element may include a volatile memory element, such as a dynamic random access memory (DRAM) and a static random access memory (SRAM). In some embodiments, when the semiconductor package 1 includes a plurality of semiconductor chips 100, at least one semiconductor chip 100 of the plurality of semiconductor chips 100 may include a CPU chip, a GPU chip, or an AP chip, and at least another semiconductor chip 100 of the plurality of semiconductor chips 100 may include a memory semiconductor chip having a memory element.

[0033] In some embodiments, the semiconductor chip 100 may have a face-down arrangement in which a first surface of the semiconductor chip 100 faces the first wiring structure 200, and thus may be attached to an upper surface of the first wiring structure 200. For example, the semiconductor chip 100 may be disposed on the first wiring structure 200 such that the plurality of chip pads 120 face the first wiring structure 200. In this case, the first surface of the semiconductor chip 100 may be referred to as a lower surface of the semiconductor chip 100, and the second surface of the semiconductor chip 100 may be referred to as an upper surface of the semiconductor chip 100.

[0034] The extension structure 300 may include an extension base layer 310 and a plurality of passage structures 320. The extension structure 300 may have a mounting space 300G in which at least one semiconductor chip 100 is located. The plurality of passage structures 320 may pass through the extension base layer 310 from the upper surface to the lower surface of the extension base layer 310. The extension structure 300 may include an embedded trace substrate (ETS), a printed circuit board (PCB), a ceramic substrate, a package manufacturing wafer, or a built-in layer. In some embodiments, the extension structure 300 may include two or more extension base layers 310 stacked on each other. For example, the extension structure 300 may include a multi-layer ETS or a multi-layer PCB.

[0035] The mounting space 300G may include an opening or a cavity formed in the extension structure 300. The mounting space 300G may be formed in a local area of ​​the extension structure 300, for example, in a central area thereof in a top view. The mounting space 300G may pass through the extension structure 300 from an upper surface to a lower surface of the extension structure 300.

[0036] The mounting space 300G may be located in the chip accommodating region CAR of the extension structure 300, and the extension base layer 310 and the plurality of via structures 320 may be located in the chip peripheral region CER. For example, in a top view, the chip accommodating region CAR may include a region in which the mounting space 300G is located, and the chip peripheral region CER may include a region in which the extension base layer 310 and the plurality of via structures 320 are located.

[0037] The extension base layer 310 may include a phenolic resin, an epoxy resin and / or a polyimide. The extension base layer 310 may include, for example, flame retardant 4 (FR-4), a tetrafunctional epoxy resin, polyphenylene oxide, epoxy resin / polyphenylene oxide, bismaleimide triazine (BT), Thermount, cyanate ester, polyimide and / or a liquid crystal polymer. In some embodiments, the extension base layer 310 may include a prepreg. For example, the extension base layer 310 may be in the form of a sheet made by impregnating a reinforcing material with a bonding material. The reinforcing material may include glass cloth, carbon cloth, non-woven glass fabric, or aramid cloth. The bonding material may include a thermosetting resin (such as epoxy resin, polyester resin, and polyimide) or a thermoplastic resin. In some embodiments, the extension base layer 310 may include a filler. For example, the filler may include a ceramic-based material having non-conductive insulating properties. In some embodiments, the filler may include AlN, BN, Al 2 O 3 At least one of SiC and MgO. For example, the filler may include a silica filler or an alumina filler. The average diameter of the filler may be several μm to several tens of μm.

[0038] Each of the plurality of passage structures 320 may include a passage connection pattern 322 and an extension passage 324. The passage connection pattern 322 may be disposed on the lower surface and the upper surface of the extension base layer 310. For example, when the extension structure 300 includes a plurality of extension base layers 310 stacked on each other, the passage connection pattern 322 may be disposed at least in some positions, such as in a region of the upper surface of the uppermost extension base layer 310 among the extension base layers 310, in a region of the lower surface of the lowermost extension base layer among the extension base layers 310, and in a region between two adjacent extension base layers 310 among the plurality of extension base layers 310. The extension passage 324 may pass through at least one extension base layer 310 and extend in a vertical direction (e.g., Z direction). The extension passage 324 may connect two passage connection patterns 322 at different vertical heights to each other.

[0039] In some embodiments, the via connection pattern 322 may include an electrolytically deposited (ED) copper foil, a rolled annealed (RA) copper foil, a stainless steel foil, an aluminum foil, an ultra-thin copper foil, a sputtered copper, a copper alloy, etc. In some embodiments, the extended via 324 may include copper (Cu) or an alloy containing copper (Cu). For example, the extended via 324 may have a structure in which copper (Cu) or an alloy of copper (Cu) is laminated on a seed layer, and the seed layer contains copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), Cu / Ti laminated on titanium, or Cu / TiW laminated on titanium tungsten, but the embodiment is not necessarily limited thereto.

[0040] Among the plurality of via connection patterns 322 of the plurality of via structures 320, each uppermost of the via connection patterns 322 may be referred to as an upper extension connection pad 322P1, and each lowermost of the via connection patterns 322 may be referred to as a lower extension connection pad 322P2. The lower surfaces of the plurality of lower extension connection pads 322P2 may be at a vertical height higher than the lower surface of the lowermost of the extension base layers 310, and define a plurality of lower recesses 322R. The plurality of upper extension connection pads 322P1 may not be buried in the extension base layer 310, but may protrude upward from the upper surface of the extension base layer 310.

[0041] The semiconductor package 1 may further include a filling insulating layer 390 filling the mounting space 300G. The filling insulating layer 390 may fill the space between the extended base layer 310 and at least one semiconductor chip 100 located in the mounting space 300G. The filling insulating layer 390 may fill the mounting space 300G and may cover the upper surface of the extension structure 300 and the upper surface of the semiconductor chip 100 (e.g., the second surface of the semiconductor chip 100). For example, the filling insulating layer 390 may include a thermosetting resin (such as epoxy resin, polyester resin and polyimide) or a thermoplastic resin. In some embodiments, the filling insulating layer 390 may include a filler. In some embodiments, the filling insulating layer 390 may not include a reinforcing material such as glass cloth, carbon cloth, non-woven glass fabric and aramid cloth. For example, the filling insulating layer 390 may include ABF, FR-4, BT, etc. Similarly, the filling insulating layer 390 may include a molding material (such as epoxy molding compound (EMC)) or a photosensitive material (such as a photoimageable encapsulant (PIE)). In some embodiments, a portion of the filling insulation layer 390 may include an insulating material such as a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0042] In some embodiments, the first surface of the at least one semiconductor chip 100, the lower surface of the extended base layer 310, and the lower surface of the filling insulation layer 390 may be at the same vertical height and form a coplanar surface. For example, the bottom of the filling insulation layer 390 may be at a lower vertical height than the first surface of the at least one semiconductor chip 100 and the lower surface of the extended base layer 310, but may be at a higher vertical height than the lower surface of the plurality of chip pads 120.

[0043] The plurality of via connection patterns 322 of the extension structure 300 may form a plurality of wiring layers. A wiring layer refers to a place where an electronic path extending along a horizontal plane formed in a first horizontal direction (e.g., X direction) and a second horizontal direction (e.g., Y direction) may be formed. For example, the extension structure 300 may have one more wiring layer than the number of the extension base layers 310 of the extension structure 300. For example, the plurality of wiring layers may include a first wiring layer L1, a second wiring layer L2, a third wiring layer L3, and a fourth wiring layer L4 at different vertical heights. The first wiring layer L1, the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 may be arranged sequentially from the upper end portion to the lower end portion of the extension structure 300. When the extension structure 300 includes three extension base layers 310 and constitutes four wiring layers including a first wiring layer L1, a second wiring layer L2, a third wiring layer L3, and a fourth wiring layer L4, the uppermost via connection pattern 322 among the plurality of via connection patterns 322 may form the first wiring layer L1, and the lowermost via connection pattern 322 among the plurality of via connection patterns 322 may form the fourth wiring layer L4. Each via connection pattern 322 constituting the first wiring layer L1 may include an upper extension connection pad 322P1, and each via connection pattern 322 constituting the fourth wiring layer L4 may include a lower extension connection pad 322P2.

[0044] Each via connection pattern 322 constituting each of the first wiring layer L1, the second wiring layer L2, and the third wiring layer L3 may have a first thickness T1, and each via connection pattern 322 constituting the fourth wiring layer L4 may have a second thickness T2. The first thickness T1 may be greater than the second thickness T2. The second thickness T2 may be smaller than the first thickness T1 by about 2 μm to about 5 μm. For example, the first thickness T1 may be about 15 μm to about 20 μm. Similarly, the second thickness T2 may be smaller than the first thickness T1 and may be about 10 μm to about 15 μm. The thickness of the via connection pattern 322 constituting the first wiring layer L1, the thickness of the via connection pattern 322 constituting the second wiring layer L2, and the thickness of the via connection pattern 322 constituting the third wiring layer L3 may be substantially equal to each other, but the embodiment is not necessarily limited thereto. For example, the thickness of the via connection pattern 322 constituting the first wiring layer L1 may be different from the thickness of the via connection pattern 322 constituting the second wiring layer L2 and the thickness of the via connection pattern 322 constituting the third wiring layer L3. However, the thickness of the via connection pattern 322 constituting the first wiring layer L1, the thickness of the via connection pattern 322 constituting the second wiring layer L2, and the thickness of the via connection pattern 322 constituting the third wiring layer L3 may all have a value greater than the second thickness T2.

[0045] At least some of the plurality of via connection patterns 322 may be buried in the extended base layer 310. In some embodiments, the via connection patterns 322 constituting the first wiring layer L1 may not be buried in the extended base layer 310, but the via connection patterns 322 constituting the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 may be buried in the extended base layer 310. In some embodiments, the lower surface of the via connection pattern 322 constituting the fourth wiring layer L4 may be at a higher vertical height than the lower surface of the extended base layer 310 in which the via connection pattern 322 constituting the fourth wiring layer L4 is buried. The lower surface of the via connection pattern 322 constituting the second wiring layer L2 may be at the same vertical height as the lower surface of the extended base layer 310 in which the via connection pattern 322 constituting the second wiring layer L2 is buried. The lower surface of the via connection pattern 322 constituting the third wiring layer L3 may be at the same vertical height as the lower surface of the extended base layer 310 in which the via connection pattern 322 constituting the third wiring layer L3 is buried.

[0046] The extension structure 300 may have a plurality of depressions 322R formed in its lower surface. The plurality of depressions 322R may be defined by the via connection pattern 322 constituting the fourth wiring layer L4 and the extension base layer 310. Each depression 322R may have a first depth D1 from the bottom of the extension structure 300. The first depth D1 may be about 2 μm to about 5 μm.

[0047] The via connection pattern 322 (e.g., multiple lower extension connection pads 322P2) constituting the fourth wiring layer L4 may include multiple first lower connection pads 322P2C adjacent to the mounting space 300G and multiple second lower connection pads 322P2E spaced apart from the mounting space 300G, and the multiple first lower connection pads 322P2C are disposed between the multiple second lower connection pads 322P2E and the mounting space 300G. In a top view, the multiple first lower connection pads 322P2C may be arranged around the mounting space 300G and may at least partially surround the mounting space 300G. In a top view, the multiple second lower connection pads 322P2E may at least partially surround the multiple first lower connection pads 322P2C.

[0048] Each of the plurality of first lower connection pads 322P2C may have a pad groove 322T. The pad groove 322T may pass through the first lower connection pad 322P2C so that the first lower connection pad 322P2C is not divided into two parts and may be spaced apart from the edge of the first lower connection pad 322P2C in a top view. The pad groove 322T may be located in the first lower connection pad 322P2C between the extension path 324 connected to the first lower connection pad 322P2C and the first redistribution path 224 and the mounting space 300G. The pad groove 322T may extend from the upper surface of the first lower connection pad 322P2C to the lower surface, and extend into the first redistribution insulation layer 210 in contact with the first lower connection pad 322P2C.

[0049] The extended base layer 310 in which a plurality of lower extended connection pads 322P2 are buried includes a base dam 310D filling the pad groove 322T of the first lower connection pad 322P2C. The base dam 310D may have a first horizontal width W1. For example, the first horizontal width W1 may be about 10 μm to about 30 μm. The base dam 310D may protrude downward from the lower surface of the first lower connection pad 322P2C and extend into the first redistribution insulating layer 210. The height of the protruding area of ​​the base dam 310D protruding downward from the lower surface of the first lower connection pad 322P2C may correspond to the first depth D1. For example, the height of the protruding area of ​​the base dam 310D protruding downward from the lower surface of the first lower connection pad 322P2C may be about 2 μm to about 5 μm.

[0050] The bottom of the extended base layer 310 in which the plurality of lower extended connection pads 322P2 are buried and the lower surface of the base dam 310D may be at the same vertical height. In some embodiments, the bottom of the extended base layer 310 in which the plurality of lower extended connection pads 322P2 are buried, the lower surface of the base dam 310D, and the first surface of the semiconductor chip 100 may be at the same vertical height.

[0051] The filling insulating layer 390 may include a bleeding portion 390BD extending from the mounting space 300G along the lower surface of the extension structure 300 and / or the first surface of the semiconductor chip 100. Among the bleeding portions 390BD, a portion disposed on the lower surface of the extension structure 300 may be referred to as a first bleeding portion 390BDa, and a portion disposed on the first surface of the semiconductor chip 100 may be referred to as a second bleeding portion 390BDb. In some embodiments, the bleeding portion 390BD may include only the first bleeding portion 390Bda, and may not include the second bleeding portion 390BDb.

[0052] The first oozing portion 390BDa may extend from the mounting space 300G along the lower surface of the extension structure 300, extend into the lower recess 322R, and contact the first lower connecting pad 322P2C. The oozing portion 390BD including the first oozing portion 390BDa and the second oozing portion 390BDb may extend into the lower recess 322R defined by the extension base layer 310 and the lower surface of the first lower connecting pad 322P2C, but may not extend into the lower recess 322R defined by the extension base layer 310 and the lower surface of the second lower connecting pad 322P2E. Figure 1D It is shown that the first seepage portion 390BDa does not contact the base dam 310D in the lower recess 322R. However, this is an example, and embodiments are not necessarily limited to this. For example, the first seepage portion 390BDa may contact the base dam 310D inside the lower recess 322R. The first seepage portion 390BDa may contact a portion of the lower surface of the first lower connecting pad 322P2C based on the base dam 310D close to the mounting space 300G, but may not contact a portion of the lower surface of the first lower connecting pad 322P2C based on the base dam 310D away from the mounting space 300G. Refer to the following FIG. 2A to FIG. 2J This is described in detail.

[0053] The thickness of the oozing portion 390BD including the first oozing portion 390BDa and the second oozing portion 390BDb may be smaller than the thickness of each of the plurality of chip pads 120. The second oozing portion 390BDb may extend from the mounting space 300G along the first surface of the semiconductor chip 100. Likewise, the second oozing portion 390BDb may not contact the plurality of chip pads 120, or may contact only a portion of the side surface of some of the plurality of chip pads 120. However, the second oozing portion 390BDb may not contact the lower surface of the plurality of chip pads 120.

[0054] The pad groove 322T and the base dam 310D filling the pad groove 322T are located between the first redistribution path 224 connected to the first lower connection pad 322P2C and the mounting space 300G. Therefore, even if the seepage portion 390BD covers a portion of the lower surface of the first lower connection pad 322P2C, the base dam 310D can prevent the seepage portion 390BD from extending to the first redistribution path 224.

[0055] The second wiring structure 400 may include a second redistribution insulating layer 410 and a plurality of second redistribution patterns 420. The plurality of second redistribution patterns 420 may include a plurality of second redistribution line patterns 422 and a plurality of second redistribution paths 424. In some embodiments, the plurality of second redistribution patterns 420 may further include a plurality of second redistribution seed layers. The second redistribution insulating layer 410 and the plurality of second redistribution patterns 420 of the second wiring structure 400 are substantially similar to the first redistribution insulating layer 210 and the plurality of first redistribution patterns 220 of the first wiring structure 200, and therefore, to the extent that an element is not described in detail with respect to this figure, it is understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

[0056] In some embodiments, the thickness of the second wiring structure 400 may be less than the thickness of the first wiring structure 200. For example, the first wiring structure 200 may have a thickness of about 30 μm to about 50 μm. Likewise, the second wiring structure 400 may be thinner than the first wiring structure 200 and may have a thickness of about 20 μm to about 40 μm. In some embodiments, the second wiring structure 400 may include a plurality of second redistribution insulating layers 410 stacked on each other. For example, the number of second redistribution insulating layers 410 stacked on each other in the second wiring structure 400 may be less than the number of first redistribution insulating layers 210 stacked on each other in the first wiring structure 200. The upper surface of the filling insulating layer 390 and the lower surface of the second redistribution insulating layer 410 may be at the same vertical height.

[0057] The plurality of first redistribution vias 424 may pass through at least one second redistribution insulating layer 410, and then may contact and be connected to some of the plurality of second redistribution line patterns 422. In some embodiments, the plurality of second redistribution vias 424 may each be in a tapered shape extending from bottom to top with increasing horizontal widths. For example, the horizontal widths of the plurality of second redistribution vias 424 may increase away from at least one semiconductor chip 100. The lowermost second redistribution via 424 of the plurality of second redistribution vias 424 may be connected to the upper surface of the via structure 320. In some embodiments, the lowermost second redistribution via 424 of the plurality of second redistribution vias 424 may pass through the filling insulating layer 390 and be connected to the upper surface of the via structure 320.

[0058] In some embodiments, at least some of the second redistribution line patterns 422 of the plurality of second redistribution line patterns 422 may be formed together with some of the second redistribution paths 424 of the plurality of second redistribution passages 424 to form an integrated body. For example, the second redistribution line pattern 422 and the second redistribution path 424 in contact with the lower surface of the second redistribution line pattern 422 (e.g., the second redistribution path 424 extending from the lower surface of the second redistribution line pattern 422) may be formed together to form an integrated body. For example, the horizontal width of each of the plurality of second redistribution paths 424 may decrease in a direction away from the second redistribution line pattern 422 integrated therewith. The second redistribution seed layer may cover the lower portion of the second redistribution line pattern 422 and the second redistribution path 424 integrated with each other. For example, among the surfaces of the second redistribution line pattern 422 and the second redistribution path 424 integrated with each other, the second redistribution seed layer may cover the lower surface of the second redistribution line pattern 422 and the side surface and the lower surface of the second redistribution path 424. The second redistribution seed layer may not cover side surfaces and upper surfaces of the second redistribution line patterns 422 .

[0059] The second wiring structure 400 may include a plurality of upper connection pads PAD-U disposed on an upper surface of the second wiring structure 400. In some embodiments, each of the plurality of upper connection pads PAD-U may include a portion of the second redistribution line pattern 422 and an upper connection pad layer 430 covering an upper surface of the portion of the second redistribution line pattern 422. The upper connection pad layer 430 may include a first upper metal layer 432 and a second upper metal layer 434 sequentially stacked on the second redistribution line pattern 422. In some embodiments, the first upper metal layer 432 may include nickel (Ni), and the second upper metal layer 434 may include gold (Au), but embodiments are not necessarily limited thereto.

[0060] In the semiconductor package 1, according to the inventive concept, the extension structure 300 includes the base dam 310D. Therefore, even if the filling insulating layer 390 includes the seepage portion 390BD extending from the mounting space 300G along the lower surface of the extension structure 300, the seepage portion 390BD can be prevented from extending to the portion of the lower extension connection pad 322P2 that contacts the first redistribution via 224. Therefore, the first redistribution pattern 220 of the first wiring structure 200 and the via structure 320 of the extension structure 300 can be prevented from being short-circuited by the seepage portion 390BD, and therefore, the reliability of the electrical connection of the semiconductor package 1 can be improved.

[0061] FIG. 2A to FIG. 2J 2 is an enlarged top view showing a first lower connection pad 322P2C and its surrounding area in a semiconductor package as a FOPLP according to an embodiment. Specifically, FIG. 2A to FIG. 2J When viewed from below Figures 1A to 1D An enlarged top view of the extension structure 300 of the semiconductor package 1 is shown.

[0062] refer to Figure 2A , as the first lower connection pad 322P2C of the path connection pattern 322 constituting the fourth wiring layer L4, it can be positioned adjacent to the installation space 300G. The first lower connection pad 322P2C can be buried in the extended base layer 310. The semiconductor chip 100 and the filling insulation layer 390 at least partially surrounding the semiconductor chip 100 can fill the installation space 300G. In some embodiments, the first lower connection pad 322P2C can have a shape in which a semicircle and a rectangle are coupled to each other in a top view. For example, the first lower connection pad 322P2C can include a first portion P1 in a semicircular shape in a top view and a second portion P2 in a rectangular shape in a top view. The first portion P1 and the second portion P2 of the first lower connection pad 322P2C can be integrated with each other. The second portion P2 can be located between the first portion P1 and the installation space 300G. For example, the first portion P1 can be positioned away from the installation space 300G, but the second portion P2 can be positioned close to the installation space 300G. In some embodiments, the extension path 324 connected to the first lower connection pad 322P2C may overlap the first portion P1 and the second portion P2 in a vertical direction (e.g., Z direction). For example, a portion of the extension path 324 may overlap the first portion P1 in a vertical direction (e.g., Z direction), and another portion of the extension path 324 may overlap the second portion P2. In some embodiments, the radius of the semicircular first portion P1 may be smaller than the length of the short side of the rectangular second portion P2.

[0063] The first lower connection pad 322P2C may have a pad groove 322T. The extended base layer 310 in which the first lower connection pad 322P2C is buried may include a base dam 310D filling the pad groove 322T. The pad groove 322T may pass through the first lower connection pad 322P2C so that the first lower connection pad 322P2C is not divided into two parts and may be spaced apart from the edge of the first lower connection pad 322P2C in a top view. The pad groove 322T may be located in the first lower connection pad 322P2C between the mounting space 300G and the extension path 324 connected to the first lower connection pad 322P2C. The pad groove 322T may be located in the second part P2 of the first lower connection pad 322P2C.

[0064] In some embodiments, the pad groove 322T and the base dam 310D filling the pad groove 322T may be in an arc shape in a top view. In a top view, the center of the arc shape of the pad groove 322T and the base dam 310D may substantially coincide with the center of the semicircular shape of the first portion P1 of the first lower connecting pad 322P2C, but the embodiment is not necessarily limited thereto. In a top view, the pad groove 322T and the base dam 310D may at least partially surround the area of ​​the extension passage 324 facing the mounting space 300G. In a top view, the radius of the arc shape of the pad groove 322T and the base dam 310D filling the pad groove 322T may be greater than the radius of the semicircular shape of the first portion P1 of the first lower connecting pad 322P2C.

[0065] In some embodiments, the extension path 324 connected to the first lower connection pad 322P2C in a top view may be circular in shape. In a top view, the center of the circular shape of the extension path 324 connected to the first lower connection pad 322P2C may substantially coincide with the center of the arc shape of the pad groove 322T and the base dam 310D and / or the center of the semicircular shape of the first portion P1 of the first lower connection pad 322P2C, but the embodiment is not necessarily limited thereto. In a top view, the radius of the circular shape of the extension path 324 connected to the first lower connection pad 322P2C may be smaller than the radius of the arc shape of the pad groove 322T and the base dam 310D filling the pad groove 322T and the radius of the semicircular shape of the first portion P1 of the first lower connection pad 322P2C.

[0066] The filling insulating layer 390 may include an oozing portion 390BD extending from the mounting space 300G to the lower side of the extension structure 300 and / or the semiconductor chip 100. In the oozing portion 390BD, the portion disposed below the extension structure 300 may be referred to as a first oozing portion 390BDa, and the portion disposed below the semiconductor chip 100 may be referred to as a second oozing portion 390BDb. In some embodiments, the oozing portion 390BD may include only the first oozing portion 390Bda, and may not include the second oozing portion 390BDb. During the process of forming the filling insulating layer 390 filling the mounting space 300G, the oozing portion 390BD may be formed as a portion of the material forming the filling insulating layer 390 penetrates the lower side of the extension structure 300 and / or the semiconductor chip 100 from the mounting space 300G.

[0067] The seepage portion 390BD may extend from the mounting space 300G to the lower side of the extension structure 300, and may cover a portion of the first lower connection pad 322P2C. The seepage portion 390BD may extend from the mounting space 300G to the lower side of the semiconductor chip 100, and may cover a portion of the first lower connection pad 322P2C. However, the seepage portion 390BD may not extend further due to the base dam 310D, and therefore may not cover another portion of the first lower connection pad 322P2C. For example, the seepage portion 390BD may cover a portion of the second portion P2 of the first lower connection pad 322P2C adjacent to the mounting space 300G based on the base dam 310D, but may not cover another portion of the first portion P1 and the second portion P2 separated from the mounting space 300G based on the base dam 310D. In a top view, the seepage portion 390BD may not overlap with the extension path 324 and a portion of the first lower connection pad 322P2C adjacent to the extension path 324.

[0068] refer to Figure 2B , the pad groove 322T of the first lower connection pad 322P2C may include a first pad groove 322T1 and a second pad groove 322T2 spaced apart from each other. The base dam 310D of the extended base layer 310 in which the first lower connection pad 322P2C is buried may include a first base dam 310D1 filling the first pad groove 322T1 and a second base dam 310D2 filling the second pad groove 322T2. In a top view, the first base dam 310D1 filling the first pad groove 322T1 and the second base dam 310D2 filling the second pad groove 322T2 may be spaced apart from each other between the first redistribution path 224 connected to the first lower connection pad 322P2C and the mounting space 300G.

[0069] In some embodiments, the first pad groove 322T1, the first base dam 310D1 filling the first pad groove 322T1, the second pad groove 322T2, and the second base dam 310D2 filling the second pad groove 322T2 may each be in an arc shape. In a top view, the center of the arc shape of the first pad groove 322T1 and the first base dam 310D1 filling the first pad groove 322T1 may substantially coincide with the center of the arc shape of the second pad groove 322T2 and the second base dam 310D2 filling the second pad groove 322T2. In a top view, the radius of the arc shape of the first pad groove 322T1 and the first base dam 310D1 filling the first pad groove 322T1 may be greater than the radius of the arc shape of the second pad groove 322T2 and the second base dam 310D2 filling the second pad groove 322T2. In the top view, the second pad groove 322T2 and the second base dam 310D2 may at least partially surround the area of ​​the extension passage 324 facing the mounting space 300G, and the first pad groove 322T1 and the first base dam 310D1 may at least partially surround the area of ​​the second pad groove 322T2 and the area of ​​the second base dam 310D2 facing the mounting space 300G.

[0070] When the seepage portion 390BD extends from the mounting space 300G to the lower side of the extension structure 300 while covering a portion of the first lower connection pad 322P2C, even if the seepage portion 390BD extends while covering the first base dam 310D1, the seepage portion 390BD may not extend further due to the second base dam 310D2. Therefore, the seepage portion 390BD may not cover the first portion P1 and another portion of the second portion P2 separated from the mounting space 300G based on the second base dam 310D2.

[0071] refer to Figure 2C In some embodiments, the pad trench 322T and the base dam 310D filling the pad trench 322T may be U-shaped. In a top view, the pad trench 322T and the base dam 310D may at least partially surround a region of the extension via 324 facing the mounting space 300G.

[0072] refer to Figure 2D The pad groove 322T of the first lower connection pad 322P2C may include a first pad groove 322T1 and a second pad groove 322T2 spaced apart from each other. The base dam 310D of the extended base layer 310 in which the first lower connection pad 322P2C is buried may include a first base dam 310D1 filling the first pad groove 322T1 and a second base dam 310D2 filling the second pad groove 322T2.

[0073] In some embodiments, the first pad groove 322T1, the first base dam 310D1 filling the first pad groove 322T1, the second pad groove 322T2, and the second base dam 310D2 filling the second pad groove 322T2 may each be in a U-shape. In a top view, the second pad groove 322T2 and the second base dam 310D2 may at least partially surround the area of ​​the extension passage 324 facing the mounting space 300G, and the first pad groove 322T1 and the first base dam 310D1 may at least partially surround the area of ​​the second pad groove 322T2 and the area of ​​the second base dam 310D2 facing the mounting space 300G.

[0074] refer to Figure 2E In some embodiments, the pad groove 322T and the base dam 310D filling the pad groove 322T may be in a strip shape. In a top view, the pad groove 322T and the base dam 310D may be in a strip shape extending between the mounting space 300G and the extension passage 324 along the edge of the mounting space 300G adjacent thereto.

[0075] refer to Figure 2F The pad groove 322T of the first lower connection pad 322P2C may include a first pad groove 322T1 and a second pad groove 322T2 spaced apart from each other. The base dam 310D of the extended base layer 310 in which the first lower connection pad 322P2C is buried may include a first base dam 310D1 filling the first pad groove 322T1 and a second base dam 310D2 filling the second pad groove 322T2.

[0076] In some embodiments, the first pad trench 322T1 , the first base dam 310D1 filling the first pad trench 322T1 , the second pad trench 322T2 , and the second base dam 310D2 filling the second pad trench 322T2 may each have a stripe shape.

[0077] Figure 2F It is shown that the extension length of the strip shape of the first pad trench 322T1 and the first base dam 310D1 is the same as the extension length of the strip shape of the second pad trench 322T2 and the second base dam 310D2. However, this is an example, and embodiments are not necessarily limited thereto. In some embodiments, the extension length of the strip shape of the first pad trench 322T1 and the first base dam 310D1 may be greater than the extension length of the strip shape of the second pad trench 322T2 and the second base dam 310D2.

[0078] refer to Figure 2GIn some embodiments, the pad trench 322T and the base dam 310D filling the pad trench 322T may be V-shaped. In a top view, the pad trench 322T and the base dam 310D may at least partially surround a region of the extension via 324 facing the mounting space 300G.

[0079] refer to Figure 2H The pad groove 322T of the first lower connection pad 322P2C may include a first pad groove 322T1 and a second pad groove 322T2 spaced apart from each other. The base dam 310D of the extended base layer 310 in which the first lower connection pad 322P2C is buried may include a first base dam 310D1 filling the first pad groove 322T1 and a second base dam 310D2 filling the second pad groove 322T2.

[0080] In some embodiments, the first pad groove 322T1, the first base dam 310D1 filling the first pad groove 322T1, the second pad groove 322T2, and the second base dam 310D2 filling the second pad groove 322T2 may each be in a V shape. In a top view, the second pad groove 322T2 and the second base dam 310D2 may at least partially surround the area of ​​the extension passage 324 facing the mounting space 300G, and the first pad groove 322T1 and the first base dam 310D1 may at least partially surround the area of ​​the second pad groove 322T2 and the area of ​​the second base dam 310D2 facing the mounting space 300G.

[0081] refer to Fig.2I , the first lower connection pad 322P2C may be circular in a top view. The first lower connection pad 322P2C may have a pad trench 322T. The extended base layer 310 in which the first lower connection pad 322P2C is buried may include a base dam 310D filling the pad trench 322T. Fig.2I The pad trench 322T and the base dam 310D filling the pad trench 322T are shown to be similar to Figure 2A The pad trench 322T and the base dam 310D filling the pad trench 322T are shown in an arc shape. However, this is an example, and the embodiment is not necessarily limited thereto. For example, the pad trench 322T and the base dam 310D may be as shown in FIG. Figure 2C , Figure 2E and Fig.2I The pad trench 322T and the base dam 310D shown in FIG. 3 may be in one of the U-shape, stripe-shape, and V-shape. Figure 2B , Figure 2F and Figure 2H The pad trench 322T and the base dam 310D are shown in one of a double U shape, a double stripe shape, and a double V shape.

[0082] refer to Figure 2J , the first lower connection pad 322P2C may be rectangular or square in a top view. The first lower connection pad 322P2C may have a pad groove 322T. The extended base layer 310 in which the first lower connection pad 322P2C is buried may include a base dam 310D filling the pad groove 322T. Figure 2J The pad trench 322T and the base dam 310D filling the pad trench 322T have similar Figure 2A The pad groove 322T and the base dam 310D filling the pad groove 322T are arc-shaped. However, this is an example, and the embodiment is not necessarily limited thereto. For example, the pad groove 322T and the base dam 310D may have an arc shape as shown in FIG. Figure 2C , Figure 2E and Fig.2I The pad trench 322T and the base dam 310D shown in FIG. 3 may have one of a U-shape, a stripe shape, and a V-shape. Similarly, the pad trench 322T and the base dam 310D may have a shape such as Figure 2B , Figure 2F and Figure 2H The pad trench 322T and the base dam 310D are shown in one of a double U shape, a double stripe shape, and a double V shape.

[0083] Figure 3A is a top view of a semiconductor package 1a as a FOPLP according to an embodiment, Figure 3B is an enlarged top view showing the second lower connection pad 322P2E and its surrounding area, and Figure 3C is an enlarged top view showing the first lower connection pad 322P2C and its surrounding area.

[0084] Reference together FIG. 3A to FIG. 3C , the extension structure 300 of the semiconductor package 1a includes a plurality of first lower extension connection pads 322P2 as the via connection pattern 322 constituting the fourth wiring layer L4. The plurality of first lower connection pads 322P2C may be buried in the extension base layer 310. The semiconductor chip 100 and the filling insulation layer 390 at least partially surrounding the semiconductor chip 100 may fill the mounting space 300G.

[0085] The plurality of first lower extension connection pads 322P2 may include a plurality of first lower connection pads 322P2C adjacent to the mounting space 300G and a plurality of second lower connection pads 322P2E spaced apart from the mounting space 300G, and the plurality of first lower connection pads 322P2C are located between the plurality of second lower connection pads 322P2E and the mounting space 300G. In a top view, the plurality of first lower connection pads 322P2C may be arranged around the mounting space 300G and at least partially surround the mounting space 300G. In a top view, the plurality of second lower connection pads 322P2E may at least partially surround the plurality of first lower connection pads 322P2C.

[0086] In some embodiments, in a top view, a plurality of first lower connection pads 322P2C may extend in a row along an edge of the mounting space 300G. For example, only one first lower connection pad 322P2C among the plurality of first lower connection pads 322P2C may be located between the mounting space 300G and each of the plurality of second lower connection pads 322P2E. In a top view, the plurality of second lower connection pads 322P2E may at least partially surround the plurality of first lower connection pads 322P2C and at least partially surround the mounting space 300G. In a top view, some of the plurality of second lower connection pads 322P2E may be arranged along an edge of the semiconductor package 1a.

[0087] In some embodiments, each second lower connecting pad 322P2E may have a circular shape or an elliptical shape in a top view.All extension vias 324 connected to the second lower connecting pads 322P2E may overlap the second lower connecting pads 322P2E in a vertical direction (eg, Z direction).

[0088] Figure 3A and Figure 3C The first lower connection pad 322P2C, the pad trench 322T and the base dam 310D are shown. Figure 2A The first lower connection pad 322P2C, the pad groove 322T and the base dam 310D are substantially the same. However, this is an example, and embodiments are not necessarily limited thereto. For example, the first lower connection pad 322P2C, the pad groove 322T and the base dam 310D may include FIG. 2B to FIG. 2J The first lower connecting pad 322P2C, the pad trench 322T and the base dam 310D shown in any one of them.

[0089] Figure 4A is a top view of a semiconductor package 1 b as a FOPLP according to an embodiment, Figure 4B is an enlarged top view showing the second lower connection pad 322P2E and its surrounding area, and Figure 4C is an enlarged top view showing the first lower connection pad 322P2C and its surrounding area.

[0090] Reference together FIG. 4A to FIG. 4C , the extension structure 300 of the semiconductor package 1b includes a plurality of first lower extension connection pads 322P2 as the via connection pattern 322 constituting the fourth wiring layer L4. The plurality of first lower connection pads 322P2C may be buried in the extension base layer 310. The semiconductor chip 100 and the filling insulation layer 390 at least partially surrounding the semiconductor chip 100 may fill the mounting space 300G.

[0091] The plurality of first lower extension connection pads 322P2 may include a plurality of first lower connection pads 322P2C adjacent to the mounting space 300G and a plurality of second lower connection pads 322P2E spaced apart from the mounting space 300G, and the plurality of first lower connection pads 322P2C are located between the plurality of second lower connection pads 322P2E and the mounting space 300G. In a top view, the plurality of first lower connection pads 322P2C may be arranged around the mounting space 300G and at least partially surround the mounting space 300G. In a top view, the plurality of second lower connection pads 322P2E may at least partially surround the plurality of first lower connection pads 322P2C.

[0092] In some embodiments, each second lower connecting pad 322P2E may have a rectangular shape or a square shape in a top view.All extension vias 324 connected to the second lower connecting pads 322P2E may overlap the second lower connecting pads 322P2E in a vertical direction (eg, Z direction).

[0093] Figure 4A and Figure 4C The first lower connection pad 322P2C, the pad trench 322T and the base dam 310D are shown. Figure 2A The first lower connection pad 322P2C, the pad groove 322T and the base dam 310D are substantially the same. However, this is an example, and embodiments are not necessarily limited thereto. For example, the first lower connection pad 322P2C, the pad groove 322T and the base dam 310D may include FIG. 2B to FIG. 2J The first lower connecting pad 322P2C, the pad trench 322T and the base dam 310D shown in any one of them.

[0094] FIG. 5A to FIG. 5D 2 is a cross-sectional view describing a method of manufacturing a semiconductor package as a FOPLP according to an embodiment.

[0095] refer to Figure 5A, a first support substrate 10 is prepared, the first support substrate 10 having a seed layer 20 formed on each of its upper and lower surfaces. The first support substrate 10 may have a chip accommodating area CAR and a chip peripheral area CER surrounding the chip accommodating area CAR. In some embodiments, the first support substrate 10 may include a prepreg layer or core layer having phenolic resin, epoxy resin and polyimide, a semiconductor substrate, a glass substrate, a ceramic substrate and / or a plastic substrate. The seed layer 20 may include ED copper foil, RA copper foil, stainless steel foil, aluminum foil, ultra-thin copper foil, sputtered copper, copper alloy, etc.

[0096] refer to Figure 5B , forming a via connection pattern 322 on the seed layer 20. The via connection pattern 322 may include Figure 1A and Figure 1B 322 of the fourth wiring layer L4 shown. In some embodiments, the via connection pattern 322 may be formed by a plating process (such as electroplating or chemical plating) using the seed layer 20 as a seed. In some embodiments, a mask pattern is formed on the seed layer 20, and a plating process is performed using the seed layer 20 as a seed to form a metal layer. Subsequently, the mask pattern and a portion of the metal layer located on the mask pattern are removed by performing a stripping process, and thus, the via connection pattern 322 may be formed. The via connection pattern 322 adjacent to the chip accommodating area CAR among the via connection patterns 322 may have a pad groove 322T.

[0097] refer to Figure 5C , an extended base layer 310 is formed on the seed layer 20 and the via connection pattern 322 constituting the fourth wiring layer L4. Subsequently, a portion of the extended base layer 310 is removed to form a through hole exposing portions of the via connection pattern 322 constituting the fourth wiring layer L4. The extended base layer 310 may include a base dam 310D that fills a pad groove 322T of a via connection pattern 322 adjacent to the chip accommodating area CAR among the via connection patterns 322 constituting the fourth wiring layer L4. Subsequently, an extended via 324 and a via connection pattern 322 are formed. The extended via 324 fills the through hole, and the via connection pattern 322 is connected to the extended via 324 and is disposed on the extended base layer 310 to form Figure 1A and Figure 1B The third wiring layer L3 shown. The extended base layer 310 may be used as an insulating layer D34 located between the via connection pattern 322 constituting the third wiring layer L3 and the via connection pattern 322 constituting the fourth wiring layer L4. The extended via 324 may be used as a connecting via V23 that electrically connects the via connection pattern 322 constituting the third wiring layer L3 to the via connection pattern 322 constituting the fourth wiring layer L4.

[0098] In some embodiments, an extended base layer 310 is formed on the seed layer 20 and the via connection pattern 322 constituting the fourth wiring layer L4. Subsequently, a seed layer similar to the seed layer 20 may be formed on the extended base layer 310, and a through hole may be formed through the seed layer and the extended base layer 310.

[0099] refer to Figure 5D , similar to Figure 5C As described in the above, the via connection pattern 322 constituting the second wiring layer L2 is formed. Likewise, an extended via 324 serving as a connection via V23 for electrically connecting the via connection pattern 322 constituting the second wiring layer L2 to the via connection pattern 322 constituting the third wiring layer L3 is formed. Likewise, an extended base layer 310 serving as an insulating layer D23 located between the via connection pattern 322 constituting the second wiring layer L2 and the via connection pattern 322 constituting the third wiring layer L3 is formed.

[0100] refer to Figure 5E , similar to Figure 5C and Figure 5D As described in the above, the via connection pattern 322 constituting the first wiring layer L1 is formed. Likewise, an extension via 324 serving as a connection via V12 for electrically connecting the via connection pattern 322 constituting the first wiring layer L1 to the via connection pattern 322 constituting the second wiring layer L2 is formed. Likewise, an extension base layer 310 serving as an insulating layer D12 located between the via connection pattern 322 constituting the first wiring layer L1 and the via connection pattern 322 constituting the second wiring layer L2 is formed. Thus, the extension structure 300 is formed on the upper surface and the lower surface of the first support substrate 10, respectively.

[0101] refer to Fig. 5F , the extension structure 300 is respectively separated from the upper and lower surfaces of the first support substrate 10. When the extension structure 300 is separated from the upper and lower surfaces of the first support substrate 10, the seed layer 20 may be separated from the first support substrate 10 while being attached to the extension structure 300.

[0102] Reference together Fig. 5F and Figure 5G , the seed layer 20 is removed from the extension structure 300. During the process of removing the seed layer 20, a portion (eg, a lower portion thereof) of the via connection pattern 322 constituting the fourth wiring layer L4 is removed, and thus, a plurality of lower recesses 322R may be formed.

[0103] Reference together Figure 5G and Figure 5H, a mounting space 300G is formed through the extension structure 300. The mounting space 300G may be formed by removing a portion of the extension structure 300 located in the chip receiving region CAR (eg, a portion of the plurality of extension base layers 310).

[0104] Each of the via connection patterns 322 constituting the first wiring layer L1 may include an upper extension connection pad 322P1 , and each of the via connection patterns 322 constituting the fourth wiring layer L4 may include a lower extension connection pad 322P2 .

[0105] refer to Fig.5I , the extension structure 300 is attached to the second support substrate 50, and then, the semiconductor chip 100 accommodated in the mounting space 300G is attached to the second support substrate 50. The semiconductor chip 100 can be attached to the second support substrate 50 so that the plurality of chip pads 120 face the second support substrate 50. The second support substrate 50 may include a semiconductor substrate, a glass substrate, a ceramic substrate, or a plastic substrate. In some embodiments, the second support substrate 50 may include an adhesive layer located on its upper side. The semiconductor chip 100 can be attached to the second support substrate 50 so that the plurality of chip pads 120 are buried in the adhesive layer. In some embodiments, the extension structure 300 can be attached to the second support substrate 50 so that the adhesive layer fills Figure 5G A plurality of lower recesses 322R are shown.

[0106] refer to Figure 5J A filling insulating layer 390 filling the mounting space 300G and covering the upper surface of the extension structure 300 and the upper surface of the semiconductor chip 100 is formed. The filling insulating layer 390 may fill the space between the extension base layer 310 and the semiconductor chip 100 located in the mounting space 300G.

[0107] refer to Figure 5J and Figure 5K , the extension structure 300, the semiconductor chip 100, and the filling insulating layer 390 are separated from the second support substrate 50. Subsequently, the resulting object including the extension structure 300, the semiconductor chip 100, and the filling insulating layer 390 is turned upside down and attached to the third support substrate 52. The filling insulating layer 390 may contact the third support substrate 52.

[0108] Subsequently, a first wiring structure 200 including a first redistribution insulating layer 210 and a plurality of first redistribution patterns 220 is formed on the extension structure 300, the semiconductor chip 100, and the filling insulating layer 390. The first wiring structure 200 may be formed on the extension structure 300, the semiconductor chip 100, and the filling insulating layer 390 such that the plurality of first redistribution patterns 220 are electrically connected to the plurality of chip pads 120 and the plurality of via structures 320.

[0109] Reference together Figure 5K and Figure 5L , the third support substrate 52 is separated from the filling insulating layer 390. Subsequently, the resulting object including the extension structure 300, the semiconductor chip 100, the filling insulating layer 390, and the first wiring structure 200 is turned upside down and attached to the fourth support substrate 54. The first wiring structure 200 may contact the fourth support substrate 54.

[0110] Subsequently, a second wiring structure 400 including a second redistribution insulation layer 410 and a plurality of second redistribution patterns 420 is formed on the filling insulation layer 390. A lowermost second redistribution via 424 of the plurality of second redistribution vias 424 of the plurality of second redistribution patterns 420 may pass through the filling insulation layer 390 and be connected to an upper surface of the via structure 320.

[0111] Subsequently, the fourth support substrate 54 is separated from the first wiring structure 200, and the plurality of external connection terminals 500 are formed. Figure 1A The semiconductor package 1 is shown attached to the lower surface of the first wiring structure 200. Thus, the semiconductor package 1 can be formed.

[0112] Figure 6 is a cross-sectional view of a semiconductor package 1000 as a stacked package according to an embodiment.

[0113] refer to Figure 6 , the semiconductor package 1000 may include a stacked package in which an upper package UP is attached to a lower package LP. The lower package LP may include Figure 1A A semiconductor package 1 is shown.

[0114] The lower package LP may include a first wiring structure 200, an extension structure 300 having a mounting space 300G on the first wiring structure 200, at least one semiconductor chip 100 accommodated in the mounting space 300G, a filling insulation layer 390 filling the mounting space 300G and covering the at least one semiconductor chip 100 and the extension structure 300, and a second wiring structure 400 located on the filling insulation layer 390.

[0115] The upper package UP may be attached to the second wiring structure 400. The upper package UP may be electrically connected to the plurality of second redistribution patterns 420 of the second wiring structure 400. For example, the upper package UP may be connected to the plurality of upper connection pads PAD-U. For example, a plurality of package connection terminals 950 may be arranged between the upper package UP and the plurality of upper connection pads PAD-U. For example, a plurality of package connection terminals 950 may be attached to the plurality of upper connection pad layers 430. The plurality of package connection terminals 950 may electrically connect the lower package LP and the upper package to each other. In some embodiments, each of the plurality of package connection terminals 950 may include a bump, a solder ball, or the like.

[0116] The upper package UP includes a package substrate 700 and an auxiliary semiconductor chip 800 mounted on the package substrate 700. The auxiliary semiconductor chip 800 may include an auxiliary semiconductor substrate 810 having an active surface and an inactive surface opposite to each other, an auxiliary semiconductor device 812 formed on the active surface of the auxiliary semiconductor substrate 810, and a plurality of auxiliary chip pads 820 disposed on a third surface of the auxiliary semiconductor chip 800. The third surface of the auxiliary semiconductor chip 800 and the fourth surface of the auxiliary semiconductor chip 800 are opposite to each other, and the fourth surface of the auxiliary semiconductor chip 800 refers to the inactive surface of the auxiliary semiconductor substrate 810. The active surface of the auxiliary semiconductor substrate 810 is close to the third surface of the auxiliary semiconductor chip 800, and therefore, the active surface of the auxiliary semiconductor substrate 810 and the third surface of the auxiliary semiconductor chip 800 are shown indistinguishably.

[0117] The auxiliary semiconductor chip 800 may include a memory semiconductor chip. For example, the auxiliary semiconductor chip 800 may include a DRAM chip, an SRAM chip, a flash memory chip, an electrically erasable programmable read-only memory (EPROM) chip, a PRAM chip, a magnetic random access memory (MRAM) chip, or an RRAM chip. The auxiliary semiconductor substrate 810 and the auxiliary chip pad 820 are similar to the semiconductor substrate 110 and the chip pad 120, respectively, and therefore, insofar as the elements are not described in detail with respect to this figure, it can be understood that the elements are at least similar to the corresponding elements described elsewhere in the present disclosure. The semiconductor chip 100, the semiconductor substrate 110, the semiconductor device 112, and the chip pad 120 may be referred to as a first semiconductor chip, a first semiconductor substrate, a first semiconductor device, and a first chip pad, or as a lower semiconductor chip, a lower semiconductor substrate, a lower semiconductor device, and a lower chip pad. The auxiliary semiconductor chip 800, the auxiliary semiconductor substrate 810, the auxiliary semiconductor device 812 and the auxiliary chip pad 820 are referred to as a second semiconductor chip, a second semiconductor substrate, a second semiconductor device and a second chip pad, or as an upper semiconductor chip, an upper semiconductor substrate, an upper semiconductor device and an upper chip pad.

[0118] In some embodiments, the auxiliary semiconductor chip 800 may be electrically connected to the package substrate 700 by a plurality of bonding wires 830 connected to a plurality of auxiliary chip pads 820, and may be mounted on the package substrate 700 using a die attach film (DAF) 840. In some embodiments, the upper package UP may include a plurality of auxiliary semiconductor chips 800 spaced apart from each other in the horizontal direction, and may also include a plurality of auxiliary semiconductor chips 800 stacked in the vertical direction. Likewise, the upper package UP may include a plurality of auxiliary semiconductor chips 800 electrically connected by through electrodes and stacked in the vertical direction. Likewise, the auxiliary semiconductor chip 800 may be mounted on the package substrate 700 using a flip chip method.

[0119] The package substrate 700 may include a PCB. For example, the package substrate 700 may include a double-sided PCB or a multi-layer PCB. The package substrate 700 may include at least one base insulating layer 710 and a plurality of wiring patterns 720. The plurality of wiring patterns 720 may include a plurality of lower conductive patterns 722, a plurality of upper conductive patterns 724, and a plurality of via patterns 726. The plurality of lower conductive patterns 722 may be disposed on the lower surface of the base insulating layer 710, the plurality of upper conductive patterns 724 may be disposed on the upper surface of the base insulating layer 710, and the plurality of via patterns 726 may pass through the base insulating layer 710 to connect the plurality of lower conductive patterns 722 and the plurality of upper conductive patterns 724 to each other. The base insulating layer 710 and the wiring patterns 720 are substantially similar to the extended base layer 310 and the via structure 320, respectively, and therefore, insofar as an element is not described in detail with respect to this figure, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure. Figure 6 The package substrate 700 is illustrated as including a single layer of a base insulating layer 710. However, this is an example, and embodiments are not necessarily limited thereto. For example, the package substrate 700 may include two or more base insulating layers 710 stacked on each other, and may further include a conductive pattern located between the two or more base insulating layers 710.

[0120] In some embodiments, the package substrate 700 may include a solder resist layer 730 disposed on the upper and lower surfaces of the base insulating layer 710. The solder resist layer 730 may include a lower solder resist layer 732 disposed on the lower surface of the base insulating layer 710 and an upper solder resist layer 734 disposed on the upper surface of the base insulating layer 710. A plurality of lower conductive patterns 722 among the plurality of wiring patterns 720 may be exposed to the lower surface of the package substrate 700 without being covered by the lower solder resist layer 732, and a plurality of upper conductive patterns 724 among the plurality of wiring patterns 720 may be exposed to the upper surface of the package substrate 700 without being covered by the upper solder resist layer 734.

[0121] A plurality of package connection terminals 950 may be attached to the plurality of lower conductive patterns 722 , respectively, and a plurality of bonding wires 830 may be connected to the plurality of upper conductive patterns 724 , respectively.

[0122] In some embodiments, the upper package UP may further include an encapsulation molding layer 890 that at least partially surrounds the auxiliary semiconductor chip 800 and the plurality of bonding wires 830 on the package substrate 700. For example, the encapsulation molding layer 890 may include a molding member having an EMC.

[0123] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, comprising: a first wiring structure; an extension structure, the extension structure being disposed on the first wiring structure, comprising an extension base layer and a plurality of via structures, and having a mounting space passing through the extension base layer, wherein the plurality of via structures comprises a plurality of via connection patterns and a plurality of extension vias, the plurality of via connection patterns being disposed on the upper surface and the lower surface of the extension base layer, the plurality of extension vias connecting two via connection patterns among the plurality of via connection patterns to each other, the two via connection patterns being at different vertical heights from each other; a semiconductor chip disposed in the mounting space and electrically connected to the first wiring structure; a filling insulating layer, wherein the filling insulating layer fills the installation space; and a second wiring structure, the second wiring structure being disposed on the extension structure and the filling insulating layer and being electrically connected to the first wiring structure through the plurality of via structures, wherein the lowest via connection pattern among the plurality of via connection patterns comprises a plurality of first lower connection pads, and The extended base layer includes base dams respectively passing through the plurality of first lower connection pads and protruding and extending from the plurality of first lower connection pads.

2. The semiconductor package according to claim 1, wherein: The plurality of first lower connection pads are arranged around the mounting space.

3. The semiconductor package according to claim 2, wherein: A lower surface of each of the lowermost via connection patterns among the plurality of via connection patterns is at a higher vertical height than a lower surface of the extended base layer, and Wherein, the extended base layer and the lower surface of the lowermost via connection pattern among the plurality of via connection patterns define a plurality of lower recesses.

4. The semiconductor package according to claim 3, wherein: The filling insulating layer includes an seepage portion extending from the mounting space into some of the plurality of lower recesses.

5. The semiconductor package according to claim 4, wherein: The lowermost via connection pattern among the plurality of via connection patterns further includes a plurality of second lower connection pads at least partially surrounding the plurality of first lower connection pads, and Wherein, the seepage portion of the filling insulation layer extends into a recess among the multiple recesses defined by the extended base layer and the lower surface of the multiple first lower connecting pads, but does not extend into a recess among the multiple recesses defined by the extended base layer and the lower surface of the multiple second lower connecting pads.

6. The semiconductor package according to claim 1, wherein: The base dam is disposed between the mounting space and an extension via connected to each of the plurality of first lower connection pads among the plurality of extension vias.

7. The semiconductor package according to claim 6, wherein: The base dam at least partially surrounds a region of the extension via connected to each of the plurality of first lower connection pads, facing the mounting space.

8. The semiconductor package according to claim 6, wherein: The base dam includes a first base dam and a second base dam spaced apart from each other between the mounting space and the extension via connected to each of the plurality of first lower connection pads.

9. The semiconductor package according to claim 1, wherein: The lowermost via connection pattern among the plurality of via connection patterns has a thickness smaller than a thickness of each of the other via connection patterns among the plurality of via connection patterns.

10. The semiconductor package according to claim 1, wherein The lowermost via connection pattern among the plurality of via connection patterns is buried in the extended base layer, and the uppermost via connection pattern among the plurality of via connection patterns protrudes upward from the upper surface of the extended base layer.

11. A semiconductor package, comprising: a first wiring structure; a second wiring structure, the second wiring structure being disposed above the first wiring structure; an extension structure disposed between the first wiring structure and the second wiring structure and having a mounting space passing through the extension structure from an upper surface to a lower surface of the extension structure; a semiconductor chip, wherein the semiconductor chip is arranged inside the installation space; as well as a filling insulating layer, the filling insulating layer filling the mounting space and covering the upper surface of the semiconductor chip and the upper surface of the extension structure, wherein the extension structure comprises a plurality of extension base layers stacked on each other, a plurality of via connection patterns and a plurality of extension vias, the plurality of via connection patterns being arranged on the upper surface and the lower surface of each of the plurality of extension base layers, the plurality of extension vias passing through at least one of the plurality of extension base layers and connecting two of the plurality of via connection patterns to each other, the two via connection patterns being at different vertical heights from each other, wherein the lowermost via connection pattern among the plurality of via connection patterns comprises a plurality of first lower connection pads and a plurality of second lower connection pads, the plurality of first lower connection pads being arranged around the mounting space and each having a pad groove, the plurality of second lower connection pads at least partially surrounding the plurality of first lower connection pads, and The extended base layer includes a base dam which passes through each of the plurality of first lower connection pads while filling the pad groove and protrudes downward from a lower surface of each of the plurality of first lower connection pads.

12. The semiconductor package according to claim 11, wherein Each of the plurality of first lower connection pads has a shape in which a first portion having a semicircular shape and a second portion having a rectangular shape are coupled to each other, and Wherein, the pad groove is disposed in the second portion of each of the plurality of first lower connecting pads.

13. The semiconductor package according to claim 12, wherein: Each of the pad trench and the base dam has an arc shape.

14. The semiconductor package according to claim 13, wherein: A radius of the arc shape of each of the pad trench and the body dam is greater than a radius of the semicircular shape of the first portion of each of the plurality of first lower connecting pads.

15. The semiconductor package according to claim 11, wherein The plurality of first lower connecting pads and the plurality of second lower connecting pads are buried in a lowermost extended base layer among the plurality of extended base layers, and each has a lower surface at a vertical height higher than a bottom of the lowermost extended base layer.

16. The semiconductor package according to claim 15, wherein: Via connection patterns at a vertical height higher than the lowermost via connection pattern and lower than an uppermost via connection pattern among the plurality of via connection patterns have lower surfaces at the same vertical height and are buried in any one of the plurality of extension base layers.

17. The semiconductor package according to claim 11, wherein: The filling insulating layer includes an oozing portion extending from the mounting space along the lower surface of the extension structure and contacting a lower surface of at least one first lower connecting pad among the plurality of first lower connecting pads.

18. A semiconductor package, comprising: a first wiring structure, the first wiring structure comprising a first redistribution insulating layer, a plurality of first redistribution line patterns, and a plurality of first redistribution vias, the plurality of first redistribution line patterns being disposed on at least one of an upper surface and a lower surface of the first redistribution insulating layer, the plurality of first redistribution vias passing through the first redistribution insulating layer and being respectively connected to some of the plurality of first redistribution line patterns; an extension structure disposed on the first wiring structure, comprising a plurality of extension base layers and a plurality of via structures passing through the plurality of extension base layers and connected to some of the plurality of first redistribution vias, and having a mounting space passing through the plurality of extension base layers; a semiconductor chip disposed in the mounting space and including a plurality of chip pads connected to other first redistribution vias of the plurality of first redistribution vias; A filling insulating layer, wherein the filling insulating layer fills the mounting space and covers an upper surface of the semiconductor chip and an upper surface of the extension structure; as well as a second wiring structure, the second wiring structure being disposed on the filling insulating layer and comprising a second redistribution insulating layer, a plurality of second redistribution line patterns and a plurality of second redistribution vias, the plurality of second redistribution line patterns being disposed on at least one of an upper surface and a lower surface of the second redistribution insulating layer, the plurality of second redistribution vias passing through the second redistribution insulating layer and being respectively connected to some of the plurality of second redistribution line patterns, the second wiring structure being electrically connected to the first wiring structure through the plurality of via structures, wherein the plurality of via structures include a plurality of via connection patterns and a plurality of extended vias, the plurality of via connection patterns being arranged on the upper surface and the lower surface of each of the plurality of extended substrate layers, the plurality of extended vias passing through at least one extended substrate layer and connecting two of the plurality of via connection patterns to each other, the two via connection patterns being at different vertical heights from each other, wherein the lowest via connection pattern among the plurality of via connection patterns is buried in the lowest extended base layer among the plurality of extended base layers and comprises a plurality of first lower connection pads and a plurality of second lower connection pads, the plurality of first lower connection pads being arranged around the mounting space and each having a pad groove, the plurality of second lower connection pads at least partially surrounding the plurality of first lower connection pads, and The extended base layer includes a base dam, which passes through each of the plurality of first lower connection pads while filling the pad trench and extends into the first redistribution insulating layer.

19. The semiconductor package according to claim 18, wherein: Each of the plurality of first lower connecting pads and the plurality of second lower connecting pads has a lower surface at a vertical height of 2 μm to 5 μm higher than a bottom of the lowermost extended base layer.

20. The semiconductor package according to claim 18, wherein The base dam is disposed between the mounting space and an extension via among the plurality of extension vias connected to each of the plurality of first lower connection pads, and extends with a horizontal width of 10 μm to 30 μm to at least partially surround an area of ​​the extension via facing the mounting space.

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