Package substrate and manufacturing method thereof

Abstract

The embodiment relates to a package substrate and a manufacturing method thereof. The package substrate according to the present embodiment includes: a glass core including a first surface and a second surface opposite to each other; and an upper layer laminated above the first surface or a lower layer laminated below the second surface, the corners of the package substrate being processed into curved surfaces or chamfers. Thereby, external impact applied to the glass core may be reduced, and damage and breakage of the glass core may be minimized.

Description

Technical Field

[0001] The present embodiment relates to a semiconductor package substrate and a method for manufacturing the semiconductor package substrate, and is a technology related to a package substrate including a glass core and a method for manufacturing the same. Background Art

[0002] When manufacturing electronic components, realizing circuits on semiconductor wafers is called the front-end (FE) process, and assembling the wafers in a state that can be used in actual products is called the back-end (BE) process, which includes the packaging process.

[0003] As the four core technologies of the semiconductor industry that have recently achieved rapid development of electronic products, there are semiconductor technology, semiconductor packaging technology, manufacturing process technology and software technology. Semiconductor technology is developing in various forms, such as line width of nanometer units below microns, more than 10 million cells, high-speed operation and release of a large amount of heat, but it has not yet received technical support for relatively complete packaging of the above semiconductors. Therefore, the electrical performance of semiconductors sometimes depends on the packaging technology and the corresponding electrical connections, rather than on the performance of the semiconductor technology itself.

[0004] Ceramic or resin is mainly used as a material of a package substrate, but recently research is being conducted on using silicon or glass as a high-end package substrate, and in particular, a package substrate having a cavity structure has been developed by using a glass substrate.

[0005] As related prior arts, there are Korean Granted Patent No. 10-1458663 and Korean Publication Patent No. 10-2012-0096003.

[0006] Summary of the invention

[0007] Problem that the invention aims to solve

[0008] The present embodiment aims to provide a packaging substrate and a method for manufacturing the same, which can protect a glass core or the packaging substrate from external impact and substantially minimize damage and breakage of the glass core.

[0009] In addition, an object of the present embodiment is to provide a packaging substrate and a method for manufacturing the same, which can protect a corner or edge portion of a glass core or a packaging substrate and minimize defects.

[0010] In addition, the present embodiment aims to provide a packaging substrate and a method for manufacturing the same, which can reduce external impact when a glass core or a packaging substrate is placed on a tray or moved.

[0011] Means used to solve problems

[0012] To achieve the above object, a package substrate according to one embodiment includes: a glass core including a first surface and a second surface opposite to each other; and an upper layer stacked above the first surface or a lower layer stacked below the second surface.

[0013] The corners of the packaging substrate may be processed into a curved surface or chamfered.

[0014] The corners of the glass core or the packaging substrate may be processed into a curved surface or chamfered.

[0015] The first surface and the second surface of the glass core may have a quadrilateral shape as a whole, and a part or all of the vertices of the glass core or the encapsulation substrate may be arc-shaped.

[0016] Edges of the upper layer and / or the lower layer may each have an inclined shape that becomes thinner in a direction of a cut surface of the glass core.

[0017] The substrate curvature radius is the curvature radius of the vertex of the arc shape of the glass core or the packaging substrate.

[0018] The glass core or the encapsulation substrate may have a substrate curvature radius of 0.5 mm or more and 8 mm or less.

[0019] The side curvature radius is the curvature radius of the corner of the packaging substrate.

[0020] The side curvature radius of the packaging substrate may be greater than 0.05 mm.

[0021] In order to achieve the above-mentioned purpose, according to one embodiment, a method for manufacturing a packaging substrate may include the following steps: forming an upper layer above the first surface of a glass core including a first surface and a second surface opposite to each other, or forming a lower layer below the second surface; forming a cutting portion for marking a predetermined cutting line on at least one of the upper layer, the lower layer, the first surface and the second surface; cutting the glass core along the cutting portion so that the cutting surface of the packaging substrate is exposed; and grinding the cutting surface of the packaging substrate.

[0022] The upper layer or the lower layer may include an insulating layer, and the step of forming the cutting portion may be a step of removing a part or all of a portion of the insulating layer corresponding to the cutting line.

[0023] The step of cutting the glass core may be performed by scribing or laser cutting.

[0024] The step of grinding the cutting surface may include the step of chamfering the corners of the cutting surface.

[0025] Alternatively, according to another example, the step of grinding the cutting surface may include the step of performing a curving process on the cutting surface.

[0026] The first surface and the second surface of the glass core may have a quadrilateral shape, and the step of grinding the cut surface may further include a process of rounding the apex of the glass core.

[0027] The step of grinding the cut surface may include: a first process of rough-machining the cut surface with a grinding wheel having a first mesh number at a speed greater than a first speed; and a second process of fine-machining the cut surface with a grinding wheel having a second mesh number at a speed less than the first speed. The second mesh number is greater than the first mesh number.

[0028] Effects of the Invention

[0029] The encapsulation substrate and the manufacturing method thereof of the present embodiment can protect the glass core or the encapsulation substrate from external impact and minimize damage and breakage of the glass core or the encapsulation substrate.

[0030] In addition, the present embodiment provides a packaging substrate and a method for manufacturing the same which are capable of protecting a corner or edge portion of a glass core or a packaging substrate and minimizing defects.

[0031] In addition, the present embodiment can alleviate external impact when the glass core or the package substrate is placed on a tray or moved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram for explaining the cross-sectional structure of a package substrate according to the present embodiment.

[0033] Figure 2 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment.

[0034] Figure 3A and Figure 3B Each of them is a schematic diagram illustrating a portion of a package substrate according to the present embodiment in cross section.

[0035] FIG. 4A to FIG. 4E The flowchart is a cross-sectional view of a process for generating a core distribution layer in a process for manufacturing a package substrate according to the present embodiment.

[0036] FIG. 5A to FIG. 5E The flowchart is a cross-sectional view of a process for generating an insulating layer in a process for manufacturing a package substrate according to the present embodiment.

[0037] FIG. 6A to FIG. 6C It is a diagram for explaining a cross section of a glass core according to the present embodiment.

[0038] Fig. 7A and Figure 7B FIG. 2 is a diagram for explaining movement of a packaging substrate according to the present embodiment. Fig. 7A For existing examples placed on a tray (examples with cracks or chips in the glass core), Figure 7B This is an example of the present embodiment in which the substrate is placed on a tray (an example in which the substrate is placed while sliding along the curved surface of the substrate).

[0039] Figure 8 This is a flow chart illustrating the manufacturing process of the packaging substrate according to the present embodiment in cross section, wherein part (a) is a diagram illustrating laser ablation (V-Grooving), part (b) is a diagram illustrating snapping, and part (c) is a diagram illustrating grinding.

[0040] Fig.9A In the figure for explaining the grinding machine according to the present embodiment, S represents a spindle, W represents a grinding wheel, and T represents the height of a processing portion (web) of the grinding wheel, which is equal to or greater than the thickness of a substrate.

[0041] Fig. 9B This is a diagram showing polishing of a package substrate according to the present embodiment, in which arrows indicate the direction of polishing.

[0042] FIG. 10A to FIG. 10C is a photograph of the manufacturing process of the glass core according to this embodiment, Fig. 10A is a cross-sectional view after V-groove processing, where H represents sawtooth, V represents V-groove, and Fig. 10B is the cross section after fracture, Fig. 10C A cross section (a) in which the corner of the package substrate is curved and a cross section (b) in which the corner of the package substrate is chamfered are shown.

[0043] Fig.11 The following is a schematic diagram of a glass substrate according to another embodiment observed from above and a photograph of a portion thereof.

[0044] Description of Reference Numerals

[0045] 100: Semiconductor devices

[0046] 10: Motherboard

[0047] 30: Semiconductor Components

[0048] 32: First semiconductor element

[0049] 34: Second semiconductor element

[0050] 36: The third semiconductor element

[0051] 20: Package substrate

[0052] 21, 21a: Glass core

[0053] 22: Core layer

[0054] 223: Core insulation

[0055] 213: First Surface

[0056] 214: Second Surface

[0057] 23: Core through hole

[0058] 24: Core distribution layer

[0059] 241: Core distribution pattern

[0060] 26: Upper layer

[0061] 25: Upper distribution layer

[0062] 251: Upper distribution pattern

[0063] 253: Upper insulation layer

[0064] 27: Top connection layer

[0065] 271: Electrode connected above

[0066] 272: Connection pattern above

[0067] 28: Cavity

[0068] 281: Interior Space

[0069] 282: Cavity distribution layer

[0070] 40: Cavity components

[0071] 60: Covering layer

[0072] 70: Upper layer

[0073] 80: Lower layer DETAILED DESCRIPTION

[0074] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings so that a person skilled in the art can easily implement the embodiments. However, the embodiments can be implemented in many different ways and are not limited to the embodiments described in this specification. Throughout the specification, the same or similar parts are given the same reference numerals.

[0075] Throughout this specification, the term "combination of..." included in the Markush-type description refers to a mixture or combination of one or more constituent elements selected from the group consisting of the constituent elements of the Markush-type description, thereby meaning that the present invention includes one or more constituent elements selected from the group consisting of the above-mentioned constituent elements.

[0076] Throughout this specification, unless otherwise specified, terms such as "first", "second" or "A", "B" etc. are used to distinguish the same terms from each other. In addition, unless otherwise specified, descriptions indicating the singular should be understood to include the plural.

[0077] In the present specification, the "~" group may mean that a compound equivalent to "~" or a derivative of "~" is included in the compound.

[0078] In the present specification, B being located on A means that B is located on A in direct contact or with another layer therebetween, and should not be limited to the meaning that B is located on the surface of A in contact.

[0079] In the present specification, the meaning of A being connected to B means that A and B are directly connected or are connected through other constituent elements between A and B, and unless otherwise specified, the interpretation is not limited to A and B being directly connected.

[0080] Unless otherwise specified, expressions in the singular in the present specification are interpreted as including the singular or plural meaning as explained in the context.

[0081] In the process of developing a more integrated semiconductor device that can exhibit high performance at a thinner thickness, the inventors realized that in addition to the components themselves, the packaging part is also an important factor in improving performance. In the process, they conducted research and confirmed that, unlike the existing interposers and organic substrates that use two or more cores as packaging substrates on a motherboard, by using a glass core as a single layer and adopting a cavity structure, the packaging substrate can be made thinner and help improve the electrical characteristics of the semiconductor device.

[0082] On the other hand, during the process, the glass core may be damaged by cracks or chipping due to internal stress and / or external impact. In particular, when the package substrate is placed on a fixture such as a tray or a boat for subsequent processes, the substrate is more likely to be damaged, so it is recognized that it is necessary to improve the damage and breakage phenomenon for the movement of the substrate and subsequent processes.

[0083] Therefore, it was confirmed that damage to the substrate can be minimized by processing the cut surface of the package substrate so that the corner or vertex area is curved or chamfered instead of processing it into a straight cross section, thereby completing the present invention.

[0084] Figure 1 Schematic diagram for explaining the cross-sectional structure of a package substrate according to the present embodiment. Figure 2 FIG. 1 is a schematic diagram illustrating a cross-sectional structure of a package substrate according to another embodiment. Figure 3A and Figure 3B Each of them is a schematic diagram illustrating a portion of a package substrate according to the present embodiment in cross section.

[0085] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to the present embodiment includes: a semiconductor element part 30, in which one or more semiconductor elements 32, 34, 36 are located; a packaging substrate 20, which is electrically connected to the semiconductor element; and a motherboard 10, which is electrically connected to the packaging substrate 20, and is connected to the semiconductor elements 32, 34, 36 and transmits external electrical signals.

[0086] The package substrate 20 according to an embodiment includes: a core layer 22 ; an upper layer 26 located on one surface of the core layer 22 ; and a cavity portion 28 in which a cavity element 40 may be located.

[0087] The semiconductor element section 30 refers to an element mounted on a semiconductor device, and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, as the semiconductor element section 30, for example, a computing element such as a CPU, a GPU (a first semiconductor element 32, a second semiconductor element 34), a storage element such as a memory chip (a third semiconductor element 36), etc. can be used, but any semiconductor element mounted on a semiconductor device can be used without limitation.

[0088] The motherboard 10 may be a motherboard of a printed circuit board, a printed wiring board, or the like.

[0089] The packaging substrate 20 may selectively further include a lower layer (not shown in the figure) located below the core layer.

[0090] The core layer 22 may include: a glass core 21 including a first region 221 and a second region 222, wherein the first region 221 has a first thickness 211, and the second region 222 is adjacent to the first region 221 and has a second thickness 212 thinner than the first thickness; a plurality of core through holes 23 penetrating the glass core 21 in a thickness direction; and a core distribution layer 24 located on a surface of the glass core 21 or the core through holes 23, and electrically connecting a first surface 213 of the glass core 21 and a second surface 214 opposite to the first surface through the core through holes 23. That is, the core layer 22 may refer to a glass core 21 including a first surface 213 and a second surface 214 opposite to each other, a core through hole 23, a cavity portion 28, or a glass structure including them.

[0091] The second region 222 of the core layer 22 may function as a cavity structure.

[0092] In the same region, the glass core 21 has a first surface 213 and a second surface 214 opposite to each other, and the two surfaces are substantially parallel to each other, so that the glass core 21 has a constant thickness as a whole.

[0093] The inner space 281 formed by the thickness difference between the first region 221 and the second region 222 plays a role of accommodating a part or the whole of the cavity element 40 .

[0094] The glass core 21 may include a core through hole 23 penetrating the first surface 213 and the second surface 214. The core through hole 23 may be formed in both the first region 221 and the second region 222, and may be formed at an intended pitch and pattern.

[0095] As a packaging substrate for semiconductor devices, a stacked form of silicon substrate and organic substrate has been used in the past. Due to the characteristics of semiconductors, silicon substrates may produce parasitic elements when used in high-speed circuits, and have the disadvantage of relatively large power loss. In addition, organic substrates need to be large in area in order to form more complex distribution patterns, but this does not conform to the trend of manufacturing ultra-miniaturized electronic devices. In order to form a complex distribution pattern within a predetermined size, the pattern needs to be miniaturized, but due to the characteristics of materials such as polymers used for organic substrates, there are actually limitations to pattern miniaturization.

[0096] In this embodiment, as a method for solving the above-mentioned problem, the glass core 21 is used as a support body of the core layer 22. In addition, together with the glass core 21, a core through hole 23 formed through the glass core 21 is also used, thereby providing a package substrate 20 having a shorter current length, more miniaturization, faster response, and less loss characteristics.

[0097] The glass core 21 is preferably a glass substrate suitable for semiconductors, for example, a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0098] The core through hole 23 penetrates the glass core 21. The core through hole 23 may be formed by removing a predetermined region of the glass core 21, and more specifically, may be formed by etching a plate-shaped glass using a physical and / or chemical method.

[0099] Specifically, when forming the core through hole 23, a method of forming a defect (stain) on the surface of the glass core by laser or the like and then performing chemical etching, laser etching, or the like may be used, but the present invention is not limited thereto.

[0100] Based on the unit area (1 cm×1 cm) of the glass core 21, 100 to 3000 core through holes 23 may be provided, or 100 to 2500 core through holes 23 may be provided, or 225 to 1024 core through holes 23 may be provided. When the spacing condition is met, it is more conducive to forming a conductive layer, etc., and the performance of the package substrate may be improved.

[0101] The core distribution layer 24 includes a core distribution pattern 241 and a core insulation layer 223, wherein the core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the glass core through a through hole, and the core insulation layer 223 surrounds the core distribution pattern. The core layer 22 is formed with a conductive layer through the core through hole, so that it can be used as an electrical channel passing through the glass core 21. The core layer 22 connects the upper and lower parts of the glass core at a relatively short distance, thereby achieving faster electrical signal transmission and lower loss characteristics. For example, the conductive layer can be a copper plating layer, but the present invention is not limited thereto.

[0102] The cavity portion 28 is basically circular, triangular, quadrilateral, hexagonal, octagonal, cross-shaped, etc., and its shape is not limited.

[0103] The shape of the cavity element 40 can be roughly cylindrical, rectangular or polygonal.

[0104] The cavity portion 28 may include a cavity distribution pattern as a conductive layer electrically connecting the cavity element 40 and the core distribution layer 24 and an insulating layer surrounding the cavity distribution pattern.

[0105] On the other hand, the cavity portion according to another embodiment may be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed according to the same process as the core through hole 23, and the area and shape of the penetrating glass core 21 may be different from those of the core through hole 23.

[0106] In this embodiment, the insulating layer may be formed after the cavity elements 40 are arranged in the cavity portion. That is, the insulating layer may also be formed in the cavity portion through the process of forming the core insulating layer 223 .

[0107] The core allocation pattern 241 may be formed as a pattern capable of being electrically connected to the cavity member 40 .

[0108] The cavity element 40 may include an active element such as a transistor or a power transmission element such as a multi-layer ceramic capacitor (MLCC), that is, a passive element.

[0109] As the cavity element 40, an element such as a transistor can be used to convert an electrical signal between a motherboard and a semiconductor element portion into an appropriate level. In this case, a transistor is applied to the intersection of the packaging substrate 20, so that a semiconductor device 100 with higher efficiency and higher speed can be provided.

[0110] In addition, power transmission elements such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor elements. There are generally at least 200 types of power transmission elements as passive elements applied to semiconductor elements, and the characteristics of the conductive layer surrounding the element affect the performance of the element when transmitting power. In one embodiment, a non-circular core via that is not a circular core via can be applied to places where a low-resistance conductive layer is required, such as the power transmission element.

[0111] On the other hand, the cavity element 40 may have a form in which a passive element such as a capacitor is inserted alone, or may be formed in a form embedded between insulator layers (cavity element insulating layers) so that electrodes of an element group including a plurality of passive elements are exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the package substrate can be improved more smoothly, and the insulating layer can be more advantageously fully and reliably disposed in the space between the complex elements.

[0112] The glass core 21 plays an intermediate role, that is, an intermediary role, in connecting the semiconductor element part 30 and the motherboard 10 to the upper part and the lower part respectively, and the core through hole 23 is used as a path for transmitting their electrical signals, thereby achieving smooth signal transmission. In order to distinguish it from the core through hole of the second area 222 to be described below, the core through hole set in the first area 221 is called the first area core through hole 231.

[0113] The upper layer 26 is located on the first surface 213 .

[0114] The upper layer 26 includes an upper distribution layer 25 and an upper connection layer 27 located on the upper distribution layer 25 . The uppermost surface of the upper layer 26 may be protected by a cap layer 60 having an opening that allows direct contact between the connection electrodes of the semiconductor element.

[0115] The upper distribution layer 25 includes: an upper insulating layer 253 located on the first surface; and an upper distribution pattern 251, which is a conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, and the upper distribution pattern 251 is built into the upper insulating layer 253. The upper distribution layers 25 disposed above and below each other may be connected to each other through blind holes 252.

[0116] As the upper insulating layer 253 , any material as long as it is applied to a semiconductor element or a package substrate as an insulating layer may be used. For example, epoxy resin including a filler may be used, but the present invention is not limited thereto.

[0117] The insulator layer may be formed by forming a coating and curing it, or may be formed by laminating an insulator film formed in an uncured or semi-cured state on the core layer 22 and curing it. At this time, if a reduced pressure lamination method or the like is adopted, the insulator is embedded in the space inside the core through hole 23, so that the process can be performed efficiently.

[0118] According to one embodiment, even if multiple insulator layers are stacked for use, it may be substantially difficult to distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case, their boundaries may be substantially indistinguishable. Alternatively, according to another embodiment, the boundaries of the insulator layers may be created by setting the pressure and temperature for curing the multiple insulator layers differently.

[0119] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined shape, and can be formed, for example, by a build-up method. Specifically, the conductive layer can be formed by forming an insulator layer, removing unnecessary portions of the insulator layer, and then copper plating, etc., and the unnecessary portions of the conductive layer can be repeatedly selectively removed, an insulator layer is formed again on the conductive layer, the unnecessary portions are removed again, and then the conductive layer is formed by plating, etc., so that the upper distribution pattern 251 with a conductive layer formed in a vertical or horizontal direction according to the desired pattern can be formed.

[0120] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, and is therefore formed to include a fine pattern in at least a portion thereof, so as to smoothly transmit electrical signals with the semiconductor element portion 30 and fully accommodate the required complex pattern. At this time, the fine pattern refers to a pattern whose width and interval are less than 4 μm, or a pattern whose width and interval are less than 3.5 μm, or a pattern whose width and interval are less than 3 μm, or a pattern whose width and interval are less than 2.5 μm, or a pattern whose width and interval are 1 μm to 2.3 μm (hereinafter, the description of the fine pattern is the same).

[0121] The upper connection layer 27 includes: an upper connection pattern 272 located on the upper insulating layer 253 and at least a portion of which is electrically connected to the upper distribution pattern 251 ; and an upper connection electrode 271 that electrically connects the semiconductor element portion 30 and the upper connection pattern 272 .

[0122] The upper connection pattern 272 may be located on one side of the upper insulating layer 253, or may be embedded in a manner that at least a portion thereof is exposed on the upper insulating layer. For example, in the case where the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and in the case where the upper connection pattern is embedded in a manner that a portion thereof is exposed on the upper insulating layer, after forming a copper plating layer or the like, a portion of the insulating layer or the conductive layer may be removed by surface polishing, surface etching or the like.

[0123] Similar to the upper distribution pattern 251 described above, at least a portion of the upper connection pattern 272 may include a fine pattern. The upper connection pattern 272 including the fine pattern as described above allows more components to be electrically connected even in a narrow area, thereby making the electrical signal connection between components or with the outside smoother and enabling a more integrated package.

[0124] The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 through a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball or the like.

[0125] The cavity portion 28 includes a cavity distribution layer 282 located above and / or below the second region 222 and electrically connected to the core distribution pattern 241 and an inner space 281 for disposing the cavity element 40. The cavity distribution layer 282 may be formed through the second region core through hole 232.

[0126] Specifically, the thickness of the glass core 21 in the second region 222 is thinner than that in the first region 221, and the cavity element 40 can be located in the inner space 281 formed due to the thickness difference. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass core 21 function as an electrical connection structure connecting the cavity element 40 and external elements.

[0127] In addition, as described above, a cavity portion in the form of penetrating first region 221 (rather than second region 222 ), ie, penetrating first surface 213 and second surface 214 of glass core 21 may be formed, and cavity element 40 may be arranged in the cavity portion.

[0128] The package substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, and the motherboard 10 can be electrically connected via a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 connected to the motherboard 10 can be connected to the motherboard 10 via a lower layer (not shown in the figure) located at the lower part of the core layer 22. The element connection portion 51 and the board connection portion 52 are collectively referred to as a connection portion 50.

[0129] According to one example, except for the glass core 21 , the package substrate 20 between the semiconductor element portion 30 and the motherboard 10 may not substantially use an additional substrate.

[0130] In the past, the interposer and the organic substrate were stacked together and used to connect the components to the motherboard. It is understood that this multi-level structure is adopted for at least two reasons: one is that there are scale issues when directly bonding the fine patterns of the components to the motherboard, and the other is that during the bonding process or the driving process of the semiconductor device, the difference in thermal expansion coefficient may cause wiring damage.

[0131] In this embodiment, the above problem is solved by using a glass core having a thermal expansion coefficient similar to that of a semiconductor element and forming a fine pattern having a fine scale enough for mounting the element on the first surface of the glass core and its upper layer.

[0132] A method of manufacturing a package substrate according to an embodiment of the present invention will be described below.

[0133] FIG. 4A to FIG. 4E as well as FIG. 5A to FIG. 5E FIG. 1 is a flow chart illustrating a manufacturing process of a package substrate according to the present embodiment in cross section.

[0134] First, if Figure 4AAs shown, a glass core 21a having a flat first surface and a flat second surface is prepared, and a defect (groove 21b) is formed at a predetermined position on the glass surface in order to form a core through hole. The glass core may be a glass core suitable for a substrate of an electronic device, for example, an alkali-free glass core may be used, but is not limited thereto. As a commercial product, products manufactured by manufacturers such as Corning, Schott, and AGC may be used. The defect (groove) may be formed by mechanical etching, laser irradiation, or the like.

[0135] like Figure 4B As shown, an etching step is performed to form a core through hole 23 in the glass core 21a formed with a defect (groove 21b) by a physical or chemical etching process. During the etching process, while a through hole is formed in the defective portion of the glass core, the surface of the glass core 21a may be etched. In order to prevent such etching of the glass surface, a masking film or the like may be used, but considering the cumbersomeness of the process of using and removing the masking film, etc., the glass core itself with the defect may be etched, in which case the thickness of the glass core having the core through hole may be slightly thinner than the thickness of the original glass core.

[0136] Then, if Figure 4C and Figure 4D As shown, the core layer preparation step may be performed by forming a conductive layer 21d on the glass core. Representatively, the conductive layer may be a metal layer including copper metal, but the present invention is not limited thereto.

[0137] The surface of the glass (including the surface of the glass core and the surface of the core through hole) and the surface of the copper metal have different properties, so the adhesion is poor. In this embodiment, the adhesion between the glass surface and the metal is improved by two methods, a dry method and a wet method.

[0138] The dry method is a method using sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by metal sputtering. When forming the seed layer, a dissimilar metal such as titanium, chromium, nickel, etc. can be sputtered together with copper, etc. In this case, it is believed that the adhesion between glass and metal is improved by the surface morphology of the glass and the anchoring effect of the interaction of metal particles.

[0139] Wet method is the method for carrying out primer treatment, is the method for forming primer layer 21c by pre-treating with the compound substance with the functional group such as amine etc. According to the required degree of adhesion, after pre-treating with silane coupling agent, primer treatment can be carried out with the compound or particle with amine functional group.As mentioned above, the support substrate of the present embodiment needs to have the high performance of the degree that is enough to form fine pattern, even after primer treatment, also need to keep this state.Therefore, when this primer comprises nanoparticle, it is preferred to use the nanoparticle with average diameter below 150nm, for example, the particle with amine group is preferably used as nanoparticle.For example, the primer layer can be formed by using the bonding force improving agent manufactured by CZ series etc. of MEC company.

[0140] In the seed layer / primer layer 21c, the conductive layer can selectively form a metal layer with or without removing the portion where the conductive layer is not required to be formed. In addition, the seed layer / primer layer 21c selectively processes the portion where the conductive layer is required to be formed or the portion where the conductive layer is not required to be formed into an activated state or an inactivated state for metal plating to carry out subsequent processes. For example, the activation or inactivation treatment can use a light irradiation treatment with a laser having a specified wavelength or a drug treatment. When forming the metal layer, a copper plating method suitable for manufacturing semiconductor elements can be used, but the present invention is not limited to this.

[0141] like Figure 4E As shown, when a portion of the core distribution layer is not needed, it can be removed, or after partially removing or inactivating the seed layer, metal plating is performed to form a conductive layer in a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0142] FIG. 5A to FIG. 5E A preparation step of forming an insulating layer and an upper distribution pattern according to an embodiment is described.

[0143] like Figure 5A As shown, after forming the core distribution layer as the conductive layer, the core through hole may be subjected to an insulating layer forming step of filling the empty space with an insulating layer. At this time, the insulating layer used may be an insulating layer prepared in the form of a film, for example, a method of reducing pressure laminating an insulating layer in the form of a film, etc. When reducing pressure lamination is performed in this way, the insulating layer is fully embedded in the empty space inside the core through hole to form a core insulating layer without void formation.

[0144] FIG. 5B to FIG. 5E The steps for preparing the upper layer are described.

[0145] The upper layer preparation step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming the insulating layer 23a or by stacking insulating films. Simply, it is preferred to stack insulating films. The stacking of insulating films can be performed by laminating insulating films and curing. At this time, if a reduced pressure lamination method is adopted, the insulating resin can be fully embedded in a layer in which no conductive layer is formed inside the core through hole, etc. At least a portion of the upper insulating layer is also in direct contact with the glass core, so a layer with sufficient adhesion is used. Specifically, the glass core and the upper insulating layer preferably have a property that meets 4B or above according to the adhesion test value of ASTM D3359.

[0146] The upper distribution pattern can be formed by repeatedly forming the insulating layer 23a, forming the conductive layer 23c in a predetermined pattern, and etching unnecessary parts to form an etching layer 23d of the conductive layer, and the conductive layers formed adjacent to each other through the insulating layer are formed by performing a plating process after forming blind holes 23b in the insulating layer. The blind holes can be formed by dry etching methods such as laser etching and plasma etching, wet etching methods using a mask layer and an etching solution, etc.

[0147] Thereafter, although not shown in the drawings, an upper connection layer and a capping layer may be formed.

[0148] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the process of forming the upper distribution layer. Specifically, it can be formed by forming an etching layer of the insulating layer on the insulating layer 23e, forming a conductive layer thereon again, and then forming an etching layer of the conductive layer. However, it is also possible to adopt a method of selectively forming only the conductive layer without using an etching method. An opening portion (not shown in the figure) is formed at a position of the cover layer corresponding to the upper connection electrode, and it can be formed so that the upper connection electrode is exposed and directly connected to the element connection portion or the terminal of the element.

[0149] After the upper layer is generated, the process of forming the lower layer by forming the lower connection layer and the cap layer can be carried out. The lower distribution layer and / or the lower connection layer can be formed in a manner similar to the upper connection layer and the cap layer formation steps described above, and optionally, a cap layer (not shown in the figure) can also be formed.

[0150] According to the present embodiment, during the manufacturing process of the package substrate 20, one or more semiconductor elements are mounted on the substrate. Before or after the mounting, the large-area substrate can be cut into predetermined units, i.e., unit package substrates 20. That is, the package substrate or the glass core (core substrate or core layer) can be cut into a single package substrate or package substrate unit having a pattern of a certain size. The cutting, separation and division process of the substrate as described above can be referred to as dicing or singulation.

[0151] In this specification, cutting or singulation refers to dividing a packaging substrate including a glass substrate as a core layer into a plurality of units. In addition, a glass substrate used as a core layer may be referred to as a core substrate, a glass core, etc., and a substrate having an upper layer and / or a lower layer disposed on the core layer may be referred to as a packaging substrate, etc.

[0152] FIG. 6A to FIG. 6C It is a diagram for explaining a cross section of a package substrate according to the present embodiment.

[0153] As reference Figures 1 to 5E As described, the core through hole and the cavity portion may be formed in the glass core 21, the core distribution layer and the cap layer, etc. may be formed in the upper layer, and the lower layer may also have a multilayer structure including an insulating layer and a metal distribution pattern. In the following drawings, for ease of description, the package substrate 20 including the glass core 21, the upper layer 70 formed on the first surface of the glass core 21, and the lower layer 80 formed on the second surface will be briefly described, and the specific description of the remaining detailed configurations will be omitted.

[0154] according to FIG. 6A to FIG. 6C In the illustrated embodiment, the upper layer 70 may be disposed on a first surface of the glass core 21 , and optionally, the lower layer 80 may be disposed below a second surface.

[0155] The upper layer 70 may include an upper distribution layer 71 and a first cap layer 72, wherein the upper distribution layer 71 has a multilayer stacked structure including an upper metal pattern (upper distribution pattern) and an upper insulating layer, and the first cap layer 72 is formed on the upper portion of the upper distribution layer 71 and protects the substrate. The lower layer 80 may include a lower distribution layer 81 and a second cap layer 82, wherein the lower distribution layer 81 has a multilayer structure including a lower metal pattern (lower distribution pattern) and a lower insulating layer, and the second cap layer 82 is formed on the upper portion of the lower distribution layer 81 and protects the substrate. The specific arrangement of the upper distribution pattern and the upper insulating layer in the upper distribution layer is omitted in the figure. In addition, the arrangement of the lower distribution pattern and the lower insulating layer in the lower distribution layer is omitted in the figure.

[0156] The first cover layer 72 and the second cover layer 82 may be implemented with a solder resist to protect the surface circuit from the external environment. Alternatively, according to an embodiment, the first cover layer 72 and the second cover layer 82 may be implemented as a polyimide film (PI film) as a heat-resistant insulating film with high thermal stability and high mechanical strength.

[0157] The package substrate is made by forming a core through hole, a cavity portion and / or a metal pattern layer in the glass core 21 and selectively mounting a semiconductor element (not shown) in the upper layer 70, and the package substrate is cut into specific units. The cut package substrate 20 may have a Fig. 6A The cross section shown. The package substrate can be cut according to a predetermined cutting line, and the metal pattern layer may not be generated in a portion of the upper layer 70 and / or the lower layer 80 corresponding to the cutting line. That is, a portion of the upper layer 70 and / or the lower layer 80 that is cut may include only an insulating layer and / or a protective layer. In addition, as shown in the figure, the cutting surface A of the cutting area (dashed line portion) of the package substrate 20 is substantially perpendicular to the first surface or the second surface, and the corners may have a sharp straight line shape.

[0158] In such Fig. 6A In the structure shown, during the movement and post-processing of the package substrate 20, the edge area of ​​the cut surface A is likely to be damaged due to external impact ( Fig. 7A ). Damage to the package substrate or glass core, even with some damage to the corners, can affect multiple other package substrates or glass cores arranged in the chamber. In addition, due to the characteristics of the package substrate manufacturing process, which is usually operated in a reduced pressure clean room by automated equipment, such damage is the cause of unintentional particle defects, so the process space must be cleaned, which leads to a decrease in yield. Therefore, in order to reduce the possibility of such damage, according to an embodiment of the present invention, it is proposed as follows Figure 6B or Figure 6C The package substrate is shown.

[0159] like Figure 6B As shown, the corners of the cutting surface A of the package substrate 20 can be curved in a rounded manner, or, as shown in FIG. Figure 6C As shown, the edge region B may be chamfered. That is, the cut surface of the package substrate 20 may be processed into a curved surface in whole or in part, or the corner portion thereof may be chamfered into an obtuse angle instead of a right angle.

[0160] The cut surface or corner area of ​​the package substrate 20 may have the following characteristics after cutting through a grinding process: Figure 6B or Figure 6CIn other words, the glass core 21, the upper layer 70 and the lower layer 80 constituting the package substrate 20 may be ground so that their edges are processed into an inclined shape that becomes thinner toward the cutting surface.

[0161] When the cutting surface is subjected to the curvature treatment or chamfering treatment, the upper layer 70 and / or the lower layer 80 of the glass core 21 may be ground like the glass core 21, i.e., subjected to the curvature treatment or chamfering treatment. Alternatively, according to another embodiment, only the upper layer 70 or the lower layer 80 of the encapsulation substrate 20 may be ground without grinding the glass core 21.

[0162] Alternatively, according to the present embodiment, in the encapsulation substrate 20, the upper layer 70 may be formed only on the first surface of the glass core 21, and the lower layer 80 may not be formed on the second surface. Figure 6C When processing the corners as shown, the second surface of the upper layer 70 and the glass core 21 may be ground.

[0163] In addition, according to an embodiment, when viewed from above, the glass core 21 and the encapsulation substrate 20 may have a quadrilateral shape, and a part or all of the vertices of the quadrilateral shape may be rounded. By setting the curvature of the rounded vertex based on the diameter with the smallest deviation from the predetermined target value, it can be derived to an appropriate value. In addition, the rounding process may be performed together with or separately from the grinding of the edge area of ​​the cut surface.

[0164] Fig. 7A and Figure 7B A diagram for explaining movement of a packaging substrate according to the present embodiment.

[0165] Fig. 7A FIG. 4 shows a conventional packaging substrate, that is, a core substrate having a glass structure, being placed on a tray T. Figure 7B A state in which the core substrate according to the embodiment of the present invention is mounted on a tray T is shown.

[0166] As shown in the figure, if the cut surface of the package substrate has a cross section in a straight line form (rather than a curved line form), that is, the edge portions formed by the upper and lower surfaces of the package substrate and the cut surface are sharp rather than round, the glass core may be more susceptible to impact, and cracks or fragments may occur in the glass core. In other words, when the existing package substrate is incorrectly placed on a tray or a wafer boat, the possibility of damage to the glass core increases due to the angled edge shape.

[0167] On the other hand, when the cut surface is rounded or chamfered according to the embodiment, when the package substrate is placed on a tray or a wafer boat, it can slide along the curved surface of the substrate and be placed on the tray or the wafer boat. Thus, the impact between the tray and the package substrate can be reduced, and the possibility of defects due to damage, etc. can be reduced.

[0168] Figure 8 FIG. 1 is a flow chart illustrating a manufacturing process of a package substrate according to the present embodiment in cross section.

[0169] like Figure 8 As shown in part (a) of FIG. 2 , an upper layer 70 is formed on the first surface of the glass core 21, and a lower layer 80 is formed on the second surface. According to another embodiment, only the upper layer 70 may be formed on the first surface of the glass core 21, and the lower layer may not be formed on the lower surface. A semiconductor element may be mounted on the upper layer 70 (not shown in the figure).

[0170] First, if Figure 8 As shown in part (a) of FIG. 2 , the upper layer 70 is removed along a predetermined cutting line to a predetermined width by using a laser or the like to form a V-shaped groove (laser ablation) on the glass core 21. The V-shaped groove serves as a cutting portion for marking the cutting line on the upper layer or the lower layer, and the cutting line can be marked by removing a portion of the first surface or the second surface of the glass core while removing the upper layer or the lower layer.

[0171] Specifically, a V-shaped groove may be formed in the glass core 21 by removing the laminated upper layer 70 , specifically, an insulating layer such as ABF, along a dicing line such as a dicing street using a green laser or a UV laser.

[0172] The depth of the V-groove may be about 1% to 25% of the thickness of the glass core 21. The depth of the V-groove may be more than 1%, more than 3%, more than 5%, or more than 10% of the thickness of the glass core 21. In addition, the depth of the V-groove may be less than 25%, less than 20%, or less than 15% of the thickness of the glass core 21. According to the thickness of the upper layer 70 and the glass core 21, the laser output intensity and the number of processing times may be optimized, and the depth of the V-groove may be adjusted accordingly.

[0173] like Figure 8 As shown in part (a) of FIG. 1 , the process of removing the upper layer 70 and the process of generating defects in the glass core 21 can be performed simultaneously as a single process. In addition, according to another example, the process of removing the upper layer 70 and the process of generating defects in the glass core 21 can be performed separately by changing the intensity and type of the laser.

[0174] After the upper layer 70 is removed, the upper layer 70 may have an inclined shape thinned along a cut surface of the glass core 21 .

[0175] Then, if Figure 8As shown in part (b) of FIG. 1 , the package substrate 20 may be cut and separated (broken) along the cutting portion such as the V-shaped groove. At this time, the package substrate 20 may be divided into predetermined product units based on a physical force such as tension or rotational force.

[0176] After the package substrate 20 is separated in this way, V-shaped grooves, hackles similar to bird feathers, etc. may appear on the cut surface due to the laser (refer to Fig. 10A ). The glass core 21 may not be broken vertically but may be cut into an inclined shape (refer to Fig. 10B ). That is, if the glass core 21 is cut using external torque or the like, it may have an imperfect appearance shape.

[0177] According to another embodiment, the glass core 21 may be separated using a laser or a dicing saw.

[0178] When the package substrate 20 is separated based on various methods, such as Figure 8 As shown in part (c), the cut surface can be ground to have a curved surface.

[0179] The step of grinding the cutting surface may include the step of chamfering the corners of the cutting surface. According to another example, the step of grinding the cutting surface may include the step of using a grinding device to perform a curved surface processing on the cutting surface.

[0180] The cut surface of the unprocessed glass core after cutting has uneven right angle deviations, and the cut corners will also be jagged, so there is a risk of additional damage such as cracks or fragments of the glass core. Through grinding, it is possible to provide a glass core with a cut surface in the form of a curved edge or chamfer (refer to Fig. 10C ). As a result, the risk of additional damage can be significantly reduced. In addition, when moving the glass core or packaging substrate or transporting the pallet for additional processes, external impacts can also be properly dispersed, and defects due to cracks or fragments can be minimized.

[0181] In another embodiment, the package substrate 20 having the cut surface may be rounded so that its corner portion has a curved surface when viewed from above (see Fig.11). When viewed from above, the quadrilateral package substrate has four corners, each of which is processed to have a predetermined curvature, so that the angled portion can be eliminated. This radius of curvature is called the substrate curvature radius. The substrate curvature radius can be greater than 0.5 mm, greater than 1 mm, greater than 1.2 mm, or greater than 1.5 mm. The substrate curvature radius can be less than 8 mm, less than 7 mm, less than 6 mm, or less than 5 mm. In this case, the occurrence of corner chipping, etc. can be minimized, and at the same time, the area of ​​the upper layer and / or the lower layer provided with the conductive layer can be stably ensured.

[0182] In another embodiment, when viewed from the side (or cross section), the side surface of the package substrate 20 having the cut surface corresponding to the thickness may be ground. For example, the ground side surface may be in the form of chamfering the corner where the side surface and the top surface of the package substrate intersect (straight edge), or the side surface connecting the top surface and the bottom surface may be ground into a round shape so that the central portion of the side surface protrudes (pencil edge), etc.

[0183] The side (edge) of the package substrate 20 may be in a straight line or a broken glass portion immediately after the cut surface is formed, and may be manufactured to have a certain curvature radius by grinding it. At this time, the curvature radius is referred to as the side curvature radius.

[0184] The side curvature radius of the packaging substrate 20 may be greater than 0.05 mm, greater than 0.1 mm, greater than 0.15 mm, or greater than 0.2 mm. The side curvature radius may be less than 2.0 mm, less than 1.8 mm, less than 1.6 mm, less than 1.2 mm, less than 1 mm, less than 0.8 mm, or less than 0.6 mm. In this case, the occurrence of damage to the packaging substrate or the glass substrate during manufacturing and transportation can be minimized to improve workability.

[0185] For example, when grinding, by setting the design angle of the blade to 90°±1° and the cutting amount to 0.08 mm to 0.14 mm, a packaging substrate with an edge curvature radius of 0.241 mm can be manufactured.

[0186] In addition, illustratively, during grinding, by setting the design angle of the blade to 120°±1° and the cutting amount to 0.05 mm to 0.12 mm, a packaging substrate with an edge curvature radius of 0.522 mm can be manufactured.

[0187] Fig.9A FIG. 1 is a diagram for explaining a grinding machine according to the present embodiment. Fig. 9B A diagram for explaining polishing of a package substrate according to the present embodiment.

[0188] As shown in the figure, the grinder 200 may be composed of a grinding wheel 220 for grinding a package substrate, a spindle 210 for rotating the grinding wheel 220 , and a driving unit of the grinding wheel 220 (not shown).

[0189] The grinding wheel 220 as a processing part for processing the package substrate is processed to have the curvature of the final package substrate so as to perform curved surface processing on the corners of the package substrate. That is, the cross section of the grinding wheel 220 has a circular shape corresponding to the curvature of the package substrate to be processed, and the height of the grinding wheel 220 connected to the cutting surface of the package substrate is preferably equal to or greater than the thickness of the substrate.

[0190] According to this embodiment, the diameter of the imaginary curved surface connected to the cutting surface of the grinding wheel 220 can be 5 mm to 20 mm. The diameter can be greater than 5 mm, greater than 8 mm, or greater than 10 mm. The diameter can be less than 20 mm, less than 18 mm, or less than 15 mm.

[0191] The roughness of the grinding wheel 220 may be expressed as mesh.

[0192] According to the present embodiment, the cutting surface roughness of the grinding wheel 220 may be about 600 mesh to 1400 mesh. The cutting surface roughness may be about 600 mesh or more, 700 mesh or more, 800 mesh or more, or 900 mesh or more. The cutting surface roughness may be below 1400 mesh, below 1300 mesh, below 1200 mesh, or below 1100 mesh.

[0193] like Fig. 9B As shown, after placing the package substrate to be processed (unit size or quarter panel size) on the grinding wheel 220 of the grinder 200, the edges and corners of the package substrate 20 can be ground while the grinder 200 is moved along a predetermined direction.

[0194] According to one example, a wet grinding method performed by spraying cutting water or cutting oil on the grinding wheel 220 may be used.

[0195] The grinding speed may be from 10 mm / min to 500 mm / min.

[0196] The cut surface of the package substrate 20 may be ground (removed) by 50 μm to 300 μm. The cut surface may be ground (removed) by 100 μm to 200 μm.

[0197] According to this embodiment, the grinding process may include a step of rough-machining the cut surface of the packaging substrate 20 using a grinding wheel having a first mesh number at a speed greater than a first speed, and a step of fine-machining using a grinding wheel having a second mesh number larger than the first mesh number at a speed less than the first speed.

[0198] According to one example, the roughness of the grinding wheels may each have a mesh value within the above range. In addition, the difference between the first mesh number and the second mesh number may be 400 mesh or more, 450 mesh or more, or 500 mesh or more.

[0199] The larger the mesh number, the smaller the roughness of the grinding wheel 220. The package substrate 20 may be rough-machined once using a grinding wheel with strong roughness, and then fine-machined using a grinding wheel with a larger mesh number and smaller roughness than that used in the rough machining.

[0200] During roughing, the moving speed of the grinding wheel 220 can be a predetermined speed, for example, can be 200 mm / sec to 400 mm / sec. The speed can be more than 200 mm / sec, more than 220 mm / sec, more than 240 mm / sec, more than 260 mm / sec or more than 280 mm / sec. The speed can be less than 400 mm / sec, less than 380 mm / sec, less than 360 mm / sec or less than 340 mm / sec. Finishing can be performed at a speed below the speed of roughing.

[0201] According to another example, the grinding process may be performed through one process, or may be performed through three or more processes. Alternatively, the number of processes may be set differently according to the portion of the package substrate.

[0202] FIG. 10A to FIG. 10C The following are photos taken during the manufacturing process of the package substrate according to the present embodiment.

[0203] Fig. 10A Based on Figure 8 A photograph of a cross section (Sectional View) of a package substrate having a V-groove formed by the process of part (a). For observation purposes, a cut surface is formed on the package substrate sample and observed. Fig. 10A As shown, an upper layer in which ABF and SR are arranged is formed on a first surface which is an upper surface of the glass core, and a lower layer in which ABF and SR are arranged is formed on a second surface which is a lower surface.

[0204] When laser is irradiated to the upper layer of the package substrate having such a structure, a V-shaped groove, that is, a cut portion (defect) is generated, and the V-shaped groove and the sawtooth H resembling a bird's feather can be observed on the glass core.

[0205] Fig. 10B For shooting based on Figure 8(b) is a photograph of a cross section of a package substrate separated by a cutting process (breaking). According to the present embodiment, when the package substrate is separated using a force applied to a defect instead of cutting with a laser or a scriber, as shown in the figure, the cut surface is not broken vertically but is tilted or deviated to one side and separated in a diagonal shape. In addition, the cut surface of the package substrate may have an uneven appearance surface, and damage such as cracks or splinters may appear on the cut surface.

[0206] Fig. 10C For shooting Figure 8 Part (c) shows a photograph of a cross section of the package substrate after the grinding process.

[0207] like Fig. 10C As shown in the left figure of FIG. , the package substrate can be rounded to form a circle, or it can be Fig. 10C As shown in the right picture, chamfering is formed at the corners. Through this grinding, various imperfect defects on the cut surface can be removed.

[0208] The edge of the package substrate may be removed by grinding in the range of about 10 μm to 400 μm, for example, by grinding to a depth of 50 μm to 300 μm. After grinding, the package substrate has an inclined shape that becomes thinner along the cutting surface direction.

[0209] like Fig. 10C As shown in the right figure, the corners of the package substrate can be deformed into C-shaped or R-shaped chamfers by grinding.

[0210] On the other hand, according to this embodiment, the vertices of the quadrilateral package substrate can also be processed into curves by grinding. If the vertex portion is ground, the risk of damage or breakage can be reduced when the package substrate is moved or transported using a pallet or the like. By setting the curvature of the ground vertex portion to a diameter with the smallest deviation from a predetermined target value, an appropriate value can be derived.

[0211] The above-described embodiments can minimize defects such as cracks and chips generated at the edges or corners of the substrate when the package substrate is placed on a fixture such as a tray or a wafer boat for subsequent processes after the semiconductor chip is mounted. Thus, the durability and reliability of the package substrate can be ensured by protecting the package substrate from external impacts.

[0212] The present invention has been described above with reference to the embodiments illustrated in the accompanying drawings, but these are merely examples, and those skilled in the art will understand that various modifications and other equivalent embodiments can be derived therefrom. In other words, the scope of the present invention is not limited to the above-mentioned embodiments, but various changes or modifications by those skilled in the art using the basic concepts of the present embodiments defined in the attached claims fall within the scope of the present embodiments. Therefore, the true technical protection scope of the present invention should be determined by the technical ideas of the attached claims.

Claims

1. A packaging substrate, wherein: include: a glass core including a first surface and a second surface opposite to each other; as well as an upper layer stacked above the first surface or a lower layer stacked below the second surface, The corners of the packaging substrate are processed into curved surfaces or chamfered.

2. The packaging substrate according to claim 1, wherein: The first surface and the second surface of the glass core have a quadrilateral shape, The apex of the glass core or the packaging substrate is arc-shaped.

3. The packaging substrate according to claim 1, wherein: The edge of the upper layer or the lower layer has an inclined shape that becomes thinner along a cut surface direction of the glass core.

4. The packaging substrate according to claim 2, wherein: The substrate curvature radius is the curvature radius of the vertex of the arc of the glass core or the packaging substrate. The glass core or the packaging substrate has a substrate curvature radius of not less than 0.5 mm and not more than 8 mm.

5. The packaging substrate according to claim 1, wherein: The side curvature radius is the curvature radius of the corner of the packaging substrate. The side curvature radius of the packaging substrate is greater than 0.05 mm.

6. A method for manufacturing a packaging substrate, wherein: The steps include: forming an upper layer above the first surface of a glass core including first and second surfaces opposite to each other or forming a lower layer below the second surface; forming a cutting portion for marking a predetermined cutting line on at least one of the upper layer, the lower layer, the first surface, and the second surface; cutting the glass core along the cutting portion so that a cutting surface of the packaging substrate is exposed; as well as The cut surface of the packaging substrate is ground.

7. The method for manufacturing a packaging substrate according to claim 6, wherein: The upper layer or the lower layer includes an insulating layer, The step of forming the cutting portion is a step of removing a part or all of a portion of the insulating layer corresponding to the cutting line.

8. The method for manufacturing a packaging substrate according to claim 6, wherein: The step of cutting the glass core is performed by scribing or laser cutting.

9. The method for manufacturing a packaging substrate according to claim 6, wherein: The step of grinding the cutting surface includes the step of chamfering the corners of the cutting surface.

10. The method for manufacturing a package substrate according to claim 6, wherein: The step of grinding the cut surface includes the step of performing a curved surface processing on the cut surface.

11. The method for manufacturing a packaging substrate according to claim 6, wherein: The first surface and the second surface of the glass core have a quadrilateral shape, The step of grinding the cut surface also includes a process of rounding the top of the glass core.

12. The method for manufacturing a package substrate according to claim 6, wherein: The step of grinding the cut surface comprises: In a first process, the cutting surface is rough-machined at a speed higher than a first speed by using a grinding wheel having a first mesh number; and In the second process, the cutting surface is finely processed by a grinding wheel having a second mesh number at a speed lower than the first speed. The second mesh number is greater than the first mesh number.

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