Semiconductor package

Abstract

A semiconductor package includes a carrier substrate including a first surface and a second surface opposite the first surface. A first electronic component and a second electronic component are mounted side by side on the first surface of the carrier substrate. The first electronic component is provided with a first data pad along a first side directly facing the second electronic component. The second electronic component is provided with a second data bonding pad along a second side close to the first electronic component. The first data pad is directly connected to the second data pad through a first bonding wire.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging. More particularly, the present invention relates to a wire-bonded multi-chip package with reduced package size. Background Art

[0002] In the manufacturing process involving sealing multiple semiconductor chips to form a multi-chip package, electrical connections between semiconductor chips are established by, for example, wire bonding. Wire bonding is a widely used and cost-effective interconnect solution in multi-chip modules and memory device packaging. The dominance of wire bonding is not only due to its superior flexibility and low cost, but also due to the new generation of smart processes that reduce optimization time, improve reliability and ensure higher yields.

[0003] Typically, a wire-bonded multi-chip package includes a system-on-chip (SoC) chip and a known good die (KGD) memory chip mounted side by side on the upper surface of a carrier substrate. The communication between the SoC chip and the KGD memory chip is achieved through substrate bonding fingers and wiring to consider the flexibility of accommodating KGD memory chips from different sources and to achieve KGD memory chip placement for various DDR physical directions and DDR signal pad sequences. However, conventional package bonding and layout methods become an obstacle to package size reduction. Summary of the invention

[0004] An object of the present invention is to provide an improved semiconductor package that can improve the shortcomings or deficiencies of the prior art.

[0005] One aspect of the present invention provides a semiconductor package, including a carrier substrate, including a first surface and a second surface opposite to the first surface. A first electronic component and a second electronic component are mounted side by side on the first surface of the carrier substrate. The first electronic component is provided with a plurality of first data pads along a first side directly facing the second electronic component. The second electronic component is provided with a plurality of second data pads along a second side close to the first electronic component. A plurality of first bonding wires directly connect the plurality of first data pads to the plurality of second data pads.

[0006] According to some embodiments, the first electronic component is further provided with a plurality of first command / address pads along a first side directly facing the second electronic component, and the second electronic component is further provided with a plurality of second command / address pads along a second side directly facing the first electronic component, wherein the plurality of first command / address pads are directly and electrically connected to the second command / address pads through a plurality of second bonding wires.

[0007] According to some embodiments, the first electronic component is further provided with a plurality of first power / ground pads in an extended area in front of the plurality of first data pads and the plurality of first command / address pads on the first side.

[0008] According to some embodiments, the plurality of first power / ground pads are directly and electrically connected to a plurality of first gold fingers on the first surface of the carrier substrate through a plurality of third bonding wires.

[0009] According to some embodiments, the second electronic component is further provided with a plurality of second power / ground pads between the second data pad and the first command / address pad.

[0010] According to some embodiments, the plurality of second power / ground pads are directly and electrically connected to a plurality of second gold fingers on the first surface of the carrier substrate through a plurality of fourth bonding wires.

[0011] According to some embodiments, the semiconductor package further includes a molding compound encapsulating the first electronic component, the second electronic component, the plurality of first bonding wires, the plurality of second bonding wires, the plurality of third bonding wires, and the plurality of fourth bonding wires.

[0012] According to some embodiments, the semiconductor package further includes a plurality of connection elements on the second surface of the carrier substrate.

[0013] According to some embodiments, the first electronic component is a system on a chip (SoC).

[0014] According to some embodiments, the second electronic component is a memory chip.

[0015] Another aspect of the present invention provides a semiconductor package, including a carrier substrate, including a first surface and a second surface opposite to the first surface. A first electronic component and a second electronic component are mounted side by side on the first surface of the carrier substrate. The second electronic component includes at least one lower DRAM chip and an upper DRAM chip stacked on the lower DRAM chip in a stepped manner. The first electronic component is provided with a plurality of high-speed signal pads along a first side directly facing the second electronic component. The plurality of high-speed signal pads include a first data pad group arranged in a first area close to the first side, and a second data pad group arranged in a second area close to the first area. The lower DRAM chip is provided with a plurality of third data pads along a second side close to the first electronic component, and the upper DRAM chip is provided with a plurality of fourth data pads along a third side close to the first electronic component.

[0016] A plurality of first bonding wires directly connect the first data pad group in the first region of the first electronic component to the plurality of third data pads of the lower DRAM chip. A plurality of second bonding wires directly connect the second data pad group in the second region of the first electronic component to the plurality of fourth data pads of the upper DRAM chip.

[0017] According to some embodiments, the first electronic component is also provided with a plurality of first command / address pads in a side segment parallel to the first segment and the second segment, directly facing the second electronic component along the first side, and the lower DRAM chip is also provided with a plurality of second command / address pads along the second side directly facing the first electronic component, wherein the plurality of first command / address pads are directly electrically connected to the plurality of second command / address pads through a plurality of third bonding wires.

[0018] According to some embodiments, the first electronic component is further provided with a plurality of first power / ground pads in an extended section located along the first side and in front of the side section and the first section.

[0019] According to some embodiments, the plurality of first power / ground pads are directly electrically connected to the plurality of first gold fingers on the first surface of the carrier substrate through a plurality of fourth bonding wires.

[0020] According to some embodiments, the second electronic component is further provided with a plurality of second power / ground pads between the third data pad and the first command / address pad.

[0021] According to some embodiments, the plurality of second power / ground pads are directly electrically connected to the plurality of second gold fingers on the first surface of the carrier substrate through a plurality of fifth bonding wires.

[0022] According to some embodiments, the semiconductor package further includes a molding compound encapsulating the first electronic component, the second electronic component, the plurality of first bonding wires, the plurality of second bonding wires, the plurality of third bonding wires, the plurality of fourth bonding wires, and the plurality of fifth bonding wires.

[0023] According to some embodiments, the semiconductor package further includes a plurality of connection elements on the second surface of the carrier substrate.

[0024] According to some embodiments, the first electronic component is a system on a chip (SoC).

[0025] According to some embodiments, the side segment is adjacent to the first segment and the second segment.

[0026] These and other objects of the present invention will become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present invention and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and together with the description are used to explain the principles of the present invention. In the drawings:

[0028] Figure 1 is a schematic top view of a semiconductor package according to one embodiment of the present invention; and

[0029] Figure 2 is along Figure 1 A schematic cross-sectional view taken along line II' in FIG. DETAILED DESCRIPTION

[0030] In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part of this specification and illustrate specific preferred embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized and mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present disclosure. Therefore, the following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the appended claims.

[0031] It should be understood that although the terms first, second, third, primary, secondary, etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another region, layer, or part. Therefore, the first or primary element, component, region, layer, or part discussed below can be referred to as the second or secondary element, component, region, layer, or part without departing from the concept of the present invention.

[0032] Spatially relative terms, such as "below," "beneath," "lower," "under," "above," "higher," "above," and the like, may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element or feature described as "below" or "below" would be oriented as "above" or "above." Thus, the exemplary terms "below" and "below" can encompass both up and down orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it should be understood that when a layer is referred to as "between," it can be the only layer between two layers, or one or more intermediate layers may also be present.

[0033] The terms used herein are only used to describe specific embodiments and are not intended to limit the inventive concept. The singular forms "a", "an" and "the" used herein are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include" and / or "comprise" used herein specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof. The term "and / or" used herein includes any and all combinations of one or more associated listed items and may be abbreviated as " / ".

[0034] It should be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0035] Hereinafter, the term "multi-chip package" or "MCP" refers to multiple integrated circuit (IC) chips or dies with different functions packaged in one package. The term "wire-bonded multi-chip package" or "WBMCP" refers to multiple chips packaged together, and at least one chip is interconnected by wire bonds. The term "system on chip" or "SoC" refers to an integrated circuit that integrates various components of a computer or other electronic system into a single chip. The term "known good die" or "KGD" refers to a known good die.

[0036] See also Figure 1 and Figure 2 ,in Figure 1 is a schematic top view of a semiconductor package according to an embodiment of the present invention, Figure 2 is along Figure 1 A schematic cross-sectional view taken along line II' in FIG. Figure 1 and Figure 2 As shown, the semiconductor package 1 includes a carrier substrate 100 having a first surface 100a and a second surface 100b opposite to the first surface 100a. According to one embodiment of the present invention, for example, the semiconductor package 1 can be a wire-bonded multi-chip package, but is not limited thereto. According to one embodiment of the present invention, the first electronic component 10 and the second electronic component 20 can be mounted side by side on the first surface 100a of the carrier substrate 100. According to one embodiment of the present invention, for example, the first electronic component 10 and the second electronic component 20 can be fixed on the first surface 100a of the carrier substrate 100 by any suitable method known in the art, for example, using an adhesive layer.

[0037] According to one embodiment of the present invention, a plurality of connection elements 110, such as ball grid array (BGA) solder balls, are disposed on the second surface 100b of the carrier substrate 100. The semiconductor package 1 can be attached to a printed circuit board (PCB) or a mainboard (not shown) through the plurality of connection elements 110. According to one embodiment of the present invention, for example, the carrier substrate 100 can be a packaging substrate.

[0038] According to one embodiment of the present invention, for example, the carrier substrate 100 may be an organic encapsulation substrate including metal lines and resin, such as BT (BT: abbreviation of bismaleimide triazine) epoxy resin. However, it should be understood that other materials may be used to form the carrier substrate 100, such as ceramic or plastic. For simplicity, Figure 2 Detailed internal wiring of the carrier substrate 100 is not shown. Figure 2 Only the gold fingers 102 and 104 are shown for illustration.

[0039] According to one embodiment of the present invention, for example, the first electronic component 10 may be a system on chip (SoC), and the second electronic component 20 may be a memory chip, such as a dynamic random access memory (DRAM) package, including but not limited to a plurality of DRAM chips (or DRAM kdgs), such as a double data rate 3 (DDR3) chip or a double data rate 4 (DDR4) chip, etc. For example, the second electronic component 20 may include at least two stacked DRAM chips 21 and 22. According to one embodiment of the present invention, the DRAM chips may be stacked in a stepped manner.

[0040] According to one embodiment of the present invention, the first electronic component 10 and the second electronic component 20 are mounted side by side on the first surface 100 a of the carrier substrate 100 , and the first electronic component 10 is close to the second electronic component 20 , thereby reducing the overall package size.

[0041] According to one embodiment of the present invention, for example, the first electronic component 10 includes four sides E1-E4. According to one embodiment of the present invention, for example, the DRAM chip 21 includes four sides E5-E8. According to one embodiment of the present invention, for example, the DRAM chip 22 includes four sides E9-E12. The side E1 of the first electronic component 10 directly faces the side E5 of the DRAM chip 21 and the side E9 of the DRAM chip 22. According to one embodiment of the present invention, the side E1 is parallel to the sides E2, E5, E6, E9 and E10. According to one embodiment of the present invention, the side E10 overhangs the side E6 because the DRAM chip 22 is stacked on the DRAM chip 21 in a stepped manner.

[0042] According to one embodiment of the present invention, for example, the first electronic component 10 includes a plurality of high-speed signal pads SP arranged along a side E1 directly facing the second electronic component 20. For example, the high-speed signal pads SP may be data (DQ) pads for transmitting high-speed and / or high-frequency data signals between the first electronic component 10 and the second electronic component 20, such as a data transmission rate of 4266Mbps or higher, but not limited thereto. According to one embodiment of the present invention, for example, the high-speed signal pads SP may be divided into two 16-bit DQ pad groups SP1 and SP2, which are arranged in two parallel regions R1 and R2, respectively. According to one embodiment of the present invention, each parallel region R1 and R2 may accommodate at least one row of about 20-30 DQ pads, such as 25 DQ pads.

[0043] According to one embodiment of the present invention, for example, the first electronic component 10 further includes a plurality of signal pads CP for transmitting command / address (CA) signals, arranged along the side E1 directly facing the second electronic component 20. According to one embodiment of the present invention, for example, the plurality of signal pads CP may be arranged in a side region R3 parallel to the regions R1 and R2 along the side E1. According to one embodiment of the present invention, for example, the side region R3 may be adjacent to the regions R1 and R2.

[0044] According to one embodiment of the present invention, for example, the first electronic component 10 further includes a plurality of power / ground pads PP arranged in an extended region R0 extending along the side E1, located in front of the region R1 and the side region R3. According to one embodiment of the present invention, for example, the extended region R0 may be adjacent to the region R1 and the side region R3. According to one embodiment of the present invention, for example, the region R1 is sandwiched between the region R2 and the extended region R0. Although not shown in the figure, it should be understood that the first electronic component 10 may further include input / output (I / O) pads for transmitting power or ground signals, arranged along the other three sides E2-E4. It should be understood that the above-mentioned pad configuration can be implemented by a redistribution layer (RDL) structure, but is not limited thereto.

[0045] According to one embodiment of the present invention, for example, the DRAM chip 21 may include three adjacent regions RL1, RL2 and RL3, arranged along the side E5 facing the first electronic component 10. According to one embodiment of the present invention, for example, the region RL1 accommodates a plurality of 8-bit DQ pads SL1, the region RL2 accommodates a plurality of 8-bit DQ pads SL2, and the region RL3 accommodates a plurality of signal pads CL1 for transmitting command / address (CA) signals. According to one embodiment of the present invention, similarly, the DRAM chip 22 may include three adjacent regions RU1, RU2 and RU3, arranged along the side E9. According to one embodiment of the present invention, for example, the region RU1 accommodates a plurality of 8-bit DQ pads SU1, the region RU2 accommodates a plurality of 8-bit DQ pads SU2, and the region RU3 accommodates a plurality of signal pads CU1 for transmitting command / address (CA) signals.

[0046] According to one embodiment of the present invention, for example, a plurality of power / ground pads PL may be respectively arranged in three adjacent regions RL1, RL2 and RL3. According to one embodiment of the present invention, for example, a plurality of power / ground pads PU may be respectively arranged in three adjacent regions RU1, RU2 and RU3. According to one embodiment of the present invention, for example, the DQ pad SP1 in the region R1 of the first electronic component 10 may be directly electrically connected to the DQ pads SL1 and SL2 in the region RL1 and the region RL2 of the DRAM chip 21 respectively through the bonding wire WS1. According to one embodiment of the present invention, for example, the DQ pad SP2 in the region R2 of the first electronic component 10 may be directly electrically connected to the DQ pads SU1 and SU2 in the region RU1 and the region RU2 of the DRAM chip 22 respectively through the bonding wire WS2. According to one embodiment of the present invention, for example, the bonding wire WS1 and the bonding wire WS2 may have different ring heights. According to one embodiment of the present invention, for example, the ring height of the bonding wire WS1 is less than the ring height of the bonding wire WS2. According to one embodiment of the present invention, for example, the signal pads CP in the side region R3 of the first electronic component 10 can be directly electrically connected to the signal pads CL1 in the region RL3 of the DRAM chip 21 through the bonding wires WS3, respectively. According to one embodiment of the present invention, for example, the signal pads CU1 in the region RU3 of the DRAM chip 22 can be directly electrically connected to the signal pads CL2 in the region RL3 of the DRAM chip 21 through the bonding wires WS6, respectively. According to one embodiment of the present invention, for example, the power / ground pads PP in the extended region R0 of the first electronic component 10 can be directly electrically connected to the gold fingers 102 on the first surface 100a of the carrier substrate 100 through the bonding wires WS4, respectively. According to one embodiment of the present invention, for example, the power / ground pads PL in the regions RL1, RL2 and RL3 of the DRAM chip 21 can be directly electrically connected to the gold fingers 104 on the first surface 100a of the carrier substrate 100 through the bonding wires WS5, respectively. According to one embodiment of the present invention, for example, the power / ground pads PU in regions RU1, RU2, and RU3 of the DRAM chip 22 can be directly electrically connected to the power / ground pads PL_1 in regions RL1, RL2, and RL3 of the DRAM chip 21 through bonding wires WS7, respectively. According to one embodiment of the present invention, for example, the first electronic component 10, the second electronic component 20, and the bonding wires WS1-WS7 are encapsulated by the molding compound 300. According to one embodiment of the present invention, for example, the molding compound 300 may include a polymer or a resin, but is not limited thereto. The molding compound 300 also covers the first surface 100a of the carrier substrate 100.

[0047] The use of the present invention is advantageous because the DQ pads SP1 and SP2 of the first electronic component 10 are directly connected to the corresponding DQ pads SL1, SL2, SU1 and SU2 of the DRAM chips 21 and 22 through bonding wires without DDR wiring through the carrier substrate 100. Therefore, the package size can be reduced.

[0048] In addition, the high-speed signal pads SP of the first electronic component 10 can be divided into two 16-bit DQ pad groups SP1 and SP2, which are arranged in the front region R1 and the rear region R2, respectively. By providing such a configuration, the problem of bonding wire crossing can be avoided.

[0049] Those skilled in the art will readily appreciate that numerous modifications and variations of the apparatus and methods are possible while retaining the teachings of the present invention. Therefore, the above disclosure should be interpreted only in accordance with the scope of the appended claims.

Claims

1. A semiconductor package, comprising: a carrier substrate including a first surface and a second surface opposite to the first surface; A first electronic component and a second electronic component are mounted side by side on a first surface of the carrier substrate, wherein the first electronic component is provided with a plurality of first data pads along a first side directly facing the second electronic component, wherein the second electronic component is provided with a plurality of second data pads along a second side close to the first electronic component; and A plurality of first bonding wires directly connect the plurality of first data pads to the plurality of second data pads.

2. The semiconductor package of claim 1 , wherein the first electronic component is further provided with a plurality of first command / address pads along a first side directly facing the second electronic component, and the second electronic component is further provided with a plurality of second command / address pads along a second side directly facing the first electronic component, wherein the plurality of first command / address pads are directly and electrically connected to the second command / address pads through a plurality of second bonding wires. 3 . The semiconductor package as claimed in claim 2 , wherein the first electronic component is further provided with a plurality of first power / ground pads in an extended area in front of the plurality of first data pads and the plurality of first command / address pads on the first side. 4 . The semiconductor package as claimed in claim 3 , wherein the plurality of first power / ground pads are directly and electrically connected to a plurality of first gold fingers on the first surface of the carrier substrate through a plurality of third bonding wires. 5 . The semiconductor package as claimed in claim 4 , wherein the second electronic component is further provided with a plurality of second power / ground pads between the second data pad and the first command / address pad. 6 . The semiconductor package as claimed in claim 5 , wherein the plurality of second power / ground pads are directly and electrically connected to a plurality of second gold fingers on the first surface of the carrier substrate through a plurality of fourth bonding wires.

7. The semiconductor package of claim 6 further comprising: A molding compound encapsulates the first electronic component, the second electronic component, the plurality of first bonding wires, the plurality of second bonding wires, the plurality of third bonding wires, and the plurality of fourth bonding wires.

8. The semiconductor package of claim 1 further comprising: A plurality of connection elements are on the second surface of the carrier substrate.

9. The semiconductor package as claimed in claim 1, wherein the first electronic component is a system on chip.

10. The semiconductor package as claimed in claim 1, wherein the second electronic component is a memory chip.

11. A semiconductor package, comprising: a carrier substrate including a first surface and a second surface opposite to the first surface; A first electronic component and a second electronic component are mounted side by side on a first surface of the carrier substrate, wherein the second electronic component includes at least one lower DRAM chip and an upper DRAM chip stacked on the lower DRAM chip in a stepped manner, wherein the first electronic component is provided with a plurality of high-speed signal pads along a first side directly facing the second electronic component, wherein the plurality of high-speed signal pads include a first data pad group arranged in a first area close to the first side, and a second data pad group arranged in a second area close to the first area, wherein the lower DRAM chip is provided with a plurality of third data pads along a second side close to the first electronic component, and the upper DRAM chip is provided with a plurality of fourth data pads along a third side close to the first electronic component; A plurality of first bonding wires directly connect the first data pad group in the first region of the first electronic component to the plurality of third data pads of the lower DRAM chip; as well as A plurality of second bonding wires directly connect the second data pad group in the second region of the first electronic component to the plurality of fourth data pads of the upper DRAM chip.

12. A semiconductor package as described in claim 11, wherein the first electronic component is also provided with a plurality of first command / address pads in a side section parallel to the first section and the second section, directly facing the second electronic component along the first side, and the lower DRAM chip is also provided with a plurality of second command / address pads along the second side directly facing the first electronic component, wherein the plurality of first command / address pads are directly electrically connected to the plurality of second command / address pads through a plurality of third bonding wires. 13 . The semiconductor package of claim 12 , wherein the first electronic component is further provided with a plurality of first power / ground pads in an extended section located along the first side and in front of the side section and the first section. 14 . The semiconductor package as claimed in claim 13 , wherein the plurality of first power / ground pads are directly electrically connected to the plurality of first gold fingers on the first surface of the carrier substrate through a plurality of fourth bonding wires. 15 . The semiconductor package of claim 14 , wherein the second electronic component is further provided with a plurality of second power / ground pads between the third data pad and the first command / address pad. 16 . The semiconductor package as claimed in claim 15 , wherein the plurality of second power / ground pads are directly electrically connected to the plurality of second gold fingers on the first surface of the carrier substrate through a plurality of fifth bonding wires.

17. The semiconductor package according to claim 16 further comprising: A molding compound encapsulates the first electronic component, the second electronic component, the plurality of first bonding wires, the plurality of second bonding wires, the plurality of third bonding wires, the plurality of fourth bonding wires, and the plurality of fifth bonding wires.

18. The semiconductor package according to claim 11 further comprising: A plurality of connection elements are provided on the second surface of the carrier substrate.

19. The semiconductor package of claim 11, wherein the first electronic component is a system on chip. 20 . The semiconductor package of claim 11 , wherein the side section is connected to the first section and the second section.

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