Semiconductor integrated device and manufacturing method thereof
By using bonding technology in semiconductor devices to integrate silicon-based devices and using conductive columns to electrically lead out the device ends, the problem of insufficient integration density in high-voltage, high-power, and high-temperature applications of silicon-based chips is solved, achieving the effect of high integration and performance improvement.
Patent Information
- Application Number
- CN202510003440.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-03-28
AI Technical Summary
In applications such as high voltage, high power, and high temperature, silicon-based chips have shortcomings in the integration density and device types. Silicon-carbide-based chips have advantages in these fields but are difficult to achieve high integrated density circuits.
The silicon carbide-based device is integrated with the silicon-based device through bonding, and multiple ends of the silicon carbide-based device are electrically drawn out using the first conductive column to achieve high integration and performance improvement of the device.
The chip size reduction, performance improvement and reliability enhancement are achieved, while reducing the length of interconnection lines between devices and reducing the circuit delay.
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Figure CN119725334A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor device manufacturing, and more specifically, to a semiconductor integrated device and a manufacturing method thereof. Background Art
[0002] At present, in the semiconductor chip processing technology, the processing technology for using silicon as the substrate material, that is, the silicon-based process, is the most mature, and its process node can be as small as a few nanometers, and the types of devices that can be processed are also the most, including analog circuits, digital circuits, silicon-based optoelectronic devices or circuits, etc. However, compared with chips with other materials as substrates, silicon-based chips still have many shortcomings, especially in the application fields of high voltage, high power, and high temperature. For example, the third-generation semiconductor material silicon carbide has obvious advantages in the fields of high voltage, high power and high temperature, but it is not easy to make various circuits with high integration density like silicon-based chips. Therefore, how to make the best use of their strengths and avoid their weaknesses, organically combine their respective advantages, and form complementary advantages is a problem that needs to be solved by technical personnel in this field.
[0003] To solve the above problems, technicians generally use silicon-based and silicon carbide-based materials to make chips with their respective advantages, such as using silicon materials to make control circuit chips, and using silicon carbide materials to make power device chips, and then package them separately and solder them to the printed circuit board (Printed Circuit Board, PCB) board and make corresponding connections, or further, package them and integrate them, that is, package the two processed bare chips into one package. In this way, no matter which of the above solutions is used, there will be two inevitable results. One is that the chip size is relatively large, and the other is that the connection between the two chips is relatively long. In the field of high-frequency applications, the delay will be increased, and performance deviations will occur in some application scenarios that require real-time detection and interactive control of chip status (such as temperature, etc.). Therefore, it is necessary to provide a new semiconductor device to improve the above problems. Summary of the invention
[0004] In view of this, the present disclosure provides a semiconductor integrated device and a method for manufacturing the same, which realizes the integration of silicon carbide-based devices and silicon-based devices by bonding, and realizes the electrical lead-out of multiple ends of the lower silicon carbide-based device by a first conductive column, thereby improving the chip integration, reducing the volume, and improving the chip performance and reliability.
[0005] According to one aspect of an embodiment of the present disclosure, there is provided a semiconductor integrated device, including:
[0006] A first semiconductor layer, a first device formed based on the first semiconductor layer;
[0007] A connection layer, located on the first semiconductor layer;
[0008] A second semiconductor layer, located on the connection layer, having opposite first and second surfaces, the second surface being connected to the connection layer, and a second device being formed based on the second semiconductor layer; and
[0009] A plurality of first conductive pillars, penetrating through the second semiconductor layer and the connection layer, for electrically leading out a plurality of ends of the first device from the first surface,
[0010] wherein, the material of the first semiconductor layer includes silicon carbide, and the material of the second semiconductor layer includes silicon.
[0011] Optionally, further comprising:
[0012] A second dielectric layer, located on the first surface;
[0013] A plurality of second conductive pillars, penetrating through the second dielectric layer, for electrically leading out the second device from the second dielectric layer; and
[0014] A wiring layer, located on the second dielectric layer,
[0015] wherein, the plurality of first conductive pillars also penetrate through the second dielectric layer to electrically lead out the first device onto the second dielectric layer, and a plurality of ends of the first device and a plurality of ends of the second device can be selectively electrically connected through the wiring layer, the first conductive pillars and the second conductive pillars.
[0016] Optionally, the first semiconductor layer includes a silicon carbide substrate and an epitaxial layer located on the silicon carbide substrate,
[0017] The first device includes a gate region, a source region and a drain region, located in the epitaxial layer,
[0018] wherein, the plurality of first conductive pillars are respectively connected to the gate region, the source region and the drain region.
[0019] Optionally, at least part of the gate region is located between the source region and the drain region, and the gate region, the source region and the drain region are separated from each other.
[0020] Optionally, the gate region is in an inverted "day" shape and surrounds the source region and the drain region respectively, and the gate region, the source region and the drain region are separated from each other.
[0021] Optionally, the second device includes:
[0022] A source region and a drain region, located in the second semiconductor layer; and
[0023] a gate, located on the second semiconductor layer and between the source region and the drain region,
[0024] Wherein, the plurality of second conductive pillars are respectively connected to the gate, the source region and the drain region.
[0025] Optionally, the silicon carbide substrate and the gate region are of a first conductivity type, the epitaxial layer, the source region and the drain region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.
[0026] Optionally, the source region and the drain region are of the second conductivity type; or, the source region and the drain region are of the first conductivity type.
[0027] Optionally, the connection layer includes:
[0028] A first dielectric layer, located on the first semiconductor layer;
[0029] a first bonding layer, located on the first dielectric layer; and
[0030] a second bonding layer, located on the first bonding layer,
[0031] Wherein, the second surface is adjacent to the second bonding layer.
[0032] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor integrated device, comprising:
[0033] forming a first device based on the first semiconductor layer;
[0034] Fixing a second semiconductor layer above the first semiconductor layer, wherein the second semiconductor layer is connected to the first semiconductor layer via a connecting layer, wherein the second semiconductor layer has a first surface and a second surface opposite to each other, and the second surface is connected to the connecting layer;
[0035] forming a second device based on the second semiconductor layer; and
[0036] forming a plurality of first conductive pillars penetrating the second semiconductor layer and the connection layer, wherein the plurality of first conductive pillars are used to electrically lead a plurality of ends of the first device out of the first surface,
[0037] The material of the first semiconductor layer includes silicon carbide, and the material of the second semiconductor layer includes silicon.
[0038] Optionally, it also includes:
[0039] forming a second dielectric layer on the first surface;
[0040] forming a plurality of second conductive pillars penetrating the second dielectric layer, wherein the plurality of second conductive pillars are used to electrically lead the second device out of the second dielectric layer; and
[0041] forming a wiring layer on the second dielectric layer,
[0042] The multiple first conductive pillars also penetrate the second dielectric layer to electrically lead the first device out of the second dielectric layer, and the multiple ends of the first device and the multiple ends of the second device can be selectively electrically connected through the wiring layer, the first conductive pillars and the second conductive pillars.
[0043] Optionally, it also includes:
[0044] forming a first dielectric layer on the first semiconductor layer;
[0045] forming a first bonding layer on the first dielectric layer; and
[0046] forming a second bonding layer on the second surface,
[0047] The first dielectric layer, the first bonding layer and the second bonding layer are used to form the connection layer.
[0048] The step of fixing the second semiconductor layer above the first semiconductor layer includes: bonding the first bonding layer to the second bonding layer.
[0049] Optionally, the step of forming the second device is performed after the bonding,
[0050] A process temperature for forming the first device is greater than a process temperature for forming the second device.
[0051] Optionally, the material of the first dielectric layer includes silicon oxide, the material of the first bonding layer includes polysilicon, and the material of the second bonding layer includes silicon oxide.
[0052] Optionally, before the step of forming the first dielectric layer, the manufacturing method further comprises performing a high-temperature oxidation treatment on the surface of the first semiconductor layer to reduce the surface state density of the first semiconductor layer.
[0053] Optionally, before the step of forming the first bonding layer, the manufacturing method further comprises performing chemical mechanical polishing (CMP) on the surface of the first dielectric layer.
[0054] Preferably, the second bonding layer is formed by an oxidation process.
[0055] Optionally, the step of forming the plurality of first conductive pillars includes:
[0056] Using a first etching process, a hole groove is formed which penetrates the second semiconductor layer and extends to the first dielectric layer;
[0057] Using a second etching process, the hole groove is extended to the vicinity of the surface of the first semiconductor layer adjacent to the connecting layer;
[0058] A third dielectric layer and the first conductive column are formed in the hole groove, and the first conductive column and the side wall of the hole groove are separated by the third dielectric layer.
[0059] Wherein, in the second etching step, a rate of etching the first dielectric layer is greater than a rate of etching the first semiconductor layer.
[0060] One of the above technical solutions has the following beneficial effects:
[0061] A silicon carbide-based first device is formed based on the first semiconductor layer, a silicon-based second device is formed based on the second semiconductor layer, and the integration of the silicon carbide-based first device and the silicon-based second device is realized by bonding the first semiconductor layer and the second semiconductor layer, thereby reducing the area or volume of the chip. Since the silicon carbide-based device and the silicon-based device are integrated in the same chip, the length of the interconnection line between the devices can also be reduced, and the circuit delay can be reduced, thereby improving the reliability of the chip. Furthermore, the electrical lead-out of multiple ends of the lower silicon carbide-based first device is realized through the first conductive column, providing the degree of freedom of connection between each end of the silicon carbide-based first device and the silicon-based second device, thereby increasing the flexibility of circuit design to adapt to different application scenarios.
[0062] In some embodiments, the first semiconductor layer and the second semiconductor layer are fixedly connected by bonding between the first bonding layer and the second bonding layer, wherein the material of the first bonding layer is polysilicon and the material of the second bonding layer is silicon oxide. Since a large number of devices can be formed on the two bonded semiconductor wafers, the manufacturing difficulty and cost of the devices are reduced.
[0063] In some embodiments, the surface of the first semiconductor layer is subjected to high temperature oxidation treatment to reduce the surface state density of the first semiconductor layer, and then a silicon oxide dielectric layer (first dielectric layer) is formed on the surface of the first semiconductor layer and polished, so that a high-quality polysilicon bonding layer (first bonding layer) can be deposited on the silicon oxide dielectric layer, which is more conducive to the stability of the bonding. Among them, since the polysilicon material and the silicon oxide material have strong adhesion and the stress between the two is small, growing a polysilicon bonding layer on the silicon oxide dielectric layer is also conducive to reducing the overall stress of the device and improving the fixing strength.
[0064] In some embodiments, an oxidation process is used to form a silicon oxide bonding layer (second bonding layer) on a silicon-based semiconductor layer (second semiconductor layer), which can improve the quality of the silicon oxide bonding layer and make it have a lower surface state density, which is more conducive to improving the performance of devices on the second semiconductor layer.
[0065] In some embodiments, in the step of forming the first conductive column, two etchings are used to form a hole groove penetrating the second semiconductor layer and the connecting layer, wherein the second etching rate of the first dielectric layer is much greater than the etching rate of the first semiconductor layer, which can take into account the overall etching rate of the hole groove and reduce the damage caused by etching to the surface of the first semiconductor layer.
[0066] In addition, since the process temperature for forming the silicon carbide-based device is higher than the process temperature for forming the silicon-based device, when the silicon-based device is formed after the silicon carbide-based device is formed, the process temperature for forming the silicon-based device will not affect the already formed silicon carbide-based device. Moreover, since the silicon oxide dielectric layer, the polysilicon bonding layer and the silicon oxide bonding layer are all high temperature resistant materials, the process temperature for forming the silicon-based device will not affect the structures in the first semiconductor layer and the dielectric layer.
[0067] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0068] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.
[0069] Figure 1 A schematic diagram of the three-dimensional structure of a semiconductor integrated device in an embodiment of the present disclosure is shown.
[0070] Figure 2 Shows Figure 1 Schematic diagram of the top view structure.
[0071] Figure 3 Shown along Figure 2 Cross-sectional view taken along line AA.
[0072] Figures 4 to 9 The invention shows cross-sectional views of some stages of a method for manufacturing a semiconductor integrated device according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0073] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements or parts are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps can be described in one figure.
[0074] Figure 1 shows a schematic diagram of the three-dimensional structure of a semiconductor integrated device in an embodiment of the present disclosure, Figure 2 Shows Figure 1 A top view of the structure. Figure 3 Shown along Figure 2 The cross-sectional view taken along line AA, where: Figure 1 and Figure 2 The connecting layer between the two semiconductor layers, the second dielectric layer above the second semiconductor layer, and the second conductive pillar are not shown. Figures 1 to 3 The wiring layers located on the second dielectric layer are not shown.
[0075] like Figures 1 to 3 As shown, the semiconductor integrated device in the embodiment of the present disclosure includes: a first semiconductor layer and a first device located in the first semiconductor layer, a first dielectric layer 130, a first bonding layer 140, a second bonding layer 210, a second semiconductor layer and a second device located in the second semiconductor layer, a plurality of first conductive pillars 310, a third dielectric layer 311, a plurality of second conductive pillars 320 and a wiring layer.
[0076] The first semiconductor layer is, for example, a SiC substrate or a SiC substrate and an epitaxial layer thereon, and a silicon carbide-based device (first device) is formed based on the first semiconductor layer. The second semiconductor layer is, for example, a Si substrate or a Si substrate and an epitaxial layer thereon, and a silicon-based device (second device) is formed based on the second semiconductor layer.
[0077] In the present embodiment, the first semiconductor layer includes a silicon carbide substrate 101 and an epitaxial layer 110 thereon. The second semiconductor layer includes a silicon substrate 201 having a first surface 201a and a second surface 201b opposite to each other.
[0078] The gate region 121, the source region 122 and the drain region 123 of the first device extend from the surface of the epitaxial layer 110 into the epitaxial layer 110, and the gate region 121, the source region 122 and the drain region 123 are separated from each other. Figure 2 In some specific embodiments, the gate doping region 121 is in the shape of a fallen “sun”, referred to as an inverted “sun” shape. The two rings of the inverted “sun” shape surround the source region 122 and the drain region 123 respectively. Optionally, a lead-out region 121a of the gate region 121 may be provided, close to the connection of the two rings of the inverted “sun” shape and located outside the two rings.
[0079] In this embodiment, the first device composed of the silicon carbide substrate 101, the epitaxial layer 110, the gate region 121, the source region 122 and the drain region 123 is a junction field effect transistor (JFET). In this embodiment, the silicon carbide substrate 101 and the gate region 121 are of the first conductivity type, the epitaxial layer 110, the source region 122 and the drain region 123 are of the second conductivity type, and the first conductivity type is opposite to the second conductivity type. The first conductivity type is selected from one of the P type and the N type, and the second conductivity type is selected from the other of the P type and the N type. In the following, the first conductivity type is P type and the second conductivity type is N type for example.
[0080] A groove 103 is also provided in the epitaxial layer 110, and the groove 103 serves as an alignment mark. The alignment mark is usually provided in the dicing lane of the wafer, so after the dicing step, the actual semiconductor device no longer includes the alignment mark. The first dielectric layer 130 is located on the epitaxial layer 110, covering the gate region 121, the source region 122 and the drain region 123. The first bonding layer 140 is located on the first dielectric layer 130. The second bonding layer 210 is located between the second surface 201b of the silicon substrate 201 and the first bonding layer 140, and is adjacent to the second surface 201b. The first bonding layer 140 and the second bonding layer 210 are fixedly connected by bonding. Among them, the materials of the first dielectric layer 130 and the second bonding layer 210 include silicon oxide, and the material of the first bonding layer 140 includes polysilicon. The first dielectric layer 130, the first bonding layer 140 and the second bonding layer 210 constitute a connecting layer 102, connecting the first semiconductor layer and the second semiconductor layer as a whole.
[0081] The source region 221 and the drain region 222 extend from the first surface 201a of the silicon substrate 201 into the silicon substrate 201. The gate 230 is located on the first surface 201a and between the source region 221 and the drain region 222, wherein the gate 230 includes a gate dielectric layer 231 and a gate conductor 232. The silicon substrate 201 is of the first conductivity type, and the source region 221 and the drain region 222 are of the second conductivity type. Alternatively, the silicon substrate 201 is of the second conductivity type, and the source region 221 and the drain region 222 are of the first conductivity type. In this embodiment, the second device composed of the silicon substrate 201, the source region 221, the drain region 222 and the gate 230 is a metal-oxide semiconductor field-effect transistor (MOSFET).
[0082] In this embodiment, the first device is a JFET and the second device is a MOSFET. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art can make other settings for the types of the first device and the second device according to needs.
[0083] A plurality of first conductive pillars 310 penetrate through the second dielectric layer 240, the silicon substrate 201, and the connection layer 102, and are respectively connected to the gate region 121, the source region 122, and the drain region 123, so as to electrically lead out the gate, source, and drain ends of the first device to the surface of the second dielectric layer 240. The third dielectric layer 311 wraps the side walls of the respective first conductive pillars 310 to prevent the side walls of the first conductive pillars 310 from being electrically connected to other regions of the device. A plurality of second conductive pillars 320 penetrate through the second dielectric layer 240 and are respectively connected to the gate 230, the source region 221, and the drain region 222, so as to electrically lead out the gate, source, and drain ends of the second device to the surface of the second dielectric layer 240. The wiring layer is located on the second dielectric layer 240, and the gate, source, and drain ends of the first device and the gate, source, and drain ends of the second device can be selectively electrically connected through the wiring layer, the first conductive pillars 310, and the second conductive pillars 320.
[0084] In some specific embodiments, the number of the second devices is plural. Refer to Figure 2 , a plurality of second devices are arranged in an array, and a part of the second devices correspond to being within one ring of the inverted "day"-shaped gate region 121, and another part of the second devices correspond to being within another ring of the inverted "day"-shaped gate region 121. The plurality of second devices are all close to the connection part of the two rings, and the source region 122 and the drain region 123 are both far from the connection part of the two rings. Further, the plurality of first conductive pillars 310 are respectively distributed corresponding to the lead-out region 121a, the source region 122, and the drain region 123, and the plurality of second conductive pillars 320 are respectively distributed corresponding to the plurality of gates 230, the source regions 221, and the drain regions 222, so as to make the stress distribution of the device more uniform.
[0085] The production and manufacturing of chips are generally divided into front-end processes and back-end processes. The front-end processes are mainly for processing wafers, including process steps such as wafer preparation, lithography, etching, ion implantation, metallization, etc. The back-end processes are assembly processing technologies for separately cutting and packaging the chips made on the wafers. The present disclosure provides an integrated solution for the front-end processes. Taking an N-type MOS device with a silicon-on-insulator (SOI) as the substrate in the silicon-based chip of this solution as an example, and a high-voltage N-channel JFET device with a P-type silicon carbide substrate and N-type epitaxy in the silicon carbide chip as an example. The specific technical solution is as follows:
[0086] Figures 4 to 9 Shows cross-sectional views of some stages of the method for manufacturing a semiconductor integrated device according to the embodiments of the present disclosure.
[0087] As Figure 4 As shown, a groove 103 is formed in the scribe line of the silicon carbide wafer (first semiconductor layer) by etching or other methods. The groove 103 serves as an alignment mark for photolithography positioning in subsequent processes, including photolithography of devices on the silicon carbide epitaxial layer 110, and alignment with the underlying silicon carbide-based devices after bonding the silicon-based wafer (second semiconductor layer).
[0088] Furthermore, a gate region 121 is formed in the epitaxial layer 110 .
[0089] In this step, for example, an implantation mask is first formed on the surface of the epitaxial layer 110, and then a high temperature implantation process is used to implant P-type impurities such as Al into the epitaxial layer 110 to form the gate region 121. The implantation mask is then removed.
[0090] Furthermore, a source region 122 and a drain region 123 are formed in the epitaxial layer 110 .
[0091] In this step, for example, an implantation mask is first formed on the surface of the epitaxial layer 110, and then N-type impurities are implanted into the epitaxial layer 110 using a high temperature implantation process to form the source region 122 and the drain region 123. The implantation mask is then removed.
[0092] Furthermore, the lattice defects of the first semiconductor layer are repaired by a high temperature annealing process, and the injected impurities are activated at the same time. In some preferred embodiments, the surface of the first semiconductor layer is subjected to a high temperature oxidation process, thereby reducing the surface state density of the device.
[0093] Furthermore, a first dielectric layer 130 is formed on the surface of the epitaxial layer 110, such as Figure 5 shown.
[0094] In this step, for example, a deposition process is used to form the first dielectric layer 130, wherein the thickness of the first dielectric layer 130 needs to be able to fill the groove 103 and form a certain thickness accumulation on the surface of the epitaxial layer 110. In some preferred embodiments, a chemical mechanical polishing (CMP) process is used to smooth the surface of the first dielectric layer 130 to facilitate subsequent wafer bonding. If the surface of the first dielectric layer 130 is uneven, it will affect the quality of bonding, and in severe cases, it is easy to cause the separation of the two wafers. Further, a first bonding layer 140 is formed on the first dielectric layer 130, such as Figure 6 As shown, the material of the first bonding layer 140 is polysilicon. In this step, for example, a deposition process is used to grow polysilicon of a certain thickness on the surface of the first dielectric layer 130.
[0095] Further, a high-quality second bonding layer 210 is grown on the second surface 201b of the silicon substrate 201, such as Figure 7As shown, the material of the second bonding layer 210 is silicon oxide. In this step, the second bonding layer 210 is formed by, for example, an oxidation process, so that the surface state density of the interface between the second bonding layer 210 and the second semiconductor layer is low.
[0096] Furthermore, the first bonding layer 140 is bonded to the second bonding layer 210. During bonding, the silicon wafer with silicon oxide is bonded to the silicon carbide wafer with polysilicon. 2 The interface bonding process is easier to implement, which can reduce the difficulty of the manufacturing process. Then, the silicon wafer is ground and polished according to specific needs until the required thickness is reached.
[0097] Furthermore, a conventional silicon chip processing technology is used to manufacture the required device on the silicon substrate 201, which is a MOS device in this embodiment, including a source region 221, a drain region 222 and a gate 230. Then, a second dielectric layer 240 is formed on the first surface 201a of the silicon substrate 201, and the material of the second dielectric layer 240 is, for example, silicon oxide.
[0098] In this embodiment, since the melting point of silicon carbide is 2700°C, the annealing and diffusion temperature of doped ions in silicon carbide is above 1700°C, and the melting point of silicon is 1414°C, the annealing temperature of silicon-based devices generally does not exceed 1350°C. Therefore, the processing of silicon-based devices can be carried out at normal process temperatures, such as high-temperature annealing, without worrying about affecting the silicon carbide devices below. Further, a plurality of first conductive pillars 310 are formed that penetrate the second dielectric layer 240, the silicon substrate 201, the second bonding layer 210, the first bonding layer 140, and the first dielectric layer 130, such as Fig. 9 shown.
[0099] In this step, for example, an etching process is used to form a plurality of holes extending from the second dielectric layer 240 to the surface of the epitaxial layer 110, and a first conductive column 310 and a third dielectric layer 311 are formed in the holes. In order to avoid damage to the surface of the silicon carbide epitaxial layer 110 caused by etching, in some preferred embodiments, the etching process can be carried out in two steps, that is, firstly etching to the upper surface of the first dielectric layer 130 or a certain position between the upper surface of the first dielectric layer 130 and the upper surface of the epitaxial layer 110 to form holes. In the second step, the etching process is adjusted so that the etching process has a high selectivity ratio between the first dielectric layer 130 and silicon carbide, that is, the etching rate of the first dielectric layer 130 is much higher than the etching rate of the epitaxial layer 110, so as to reduce the damage to the surface of the silicon carbide epitaxial layer 110 caused by etching, for example, this can be achieved by reducing the radio frequency power of the etching equipment and adjusting the ratio of the fluorine-containing gas to oxygen. In which, the second etching extends the holes to the vicinity of the surface adjacent to the epitaxial layer 110 and the first dielectric layer 130.
[0100] Furthermore, a plurality of second conductive pillars 320 are formed penetrating the second dielectric layer 240 , and a wiring layer is formed on the second dielectric layer 240 , thereby forming an electrical connection between the silicon-based device and the silicon carbide-based device.
[0101] The semiconductor device and the manufacturing method thereof provided by the present disclosure have at least the following advantages:
[0102] First process the silicon carbide chip, that is, first complete the high temperature process required for silicon carbide chip processing, and then form a bonded wafer by wafer bonding. Since the high temperature processing on the SOI substrate will not affect the lower silicon carbide chip, the two chips are integrated together in this way to overcome the process barriers. The two materials can not only play their own maximum advantages, but also because the two chips are integrated at a micron-level distance, the chip status can be easily detected and controlled. Among them, the JFET chip has a channel in the body, not a surface device, and its radiation resistance and other properties will be greatly improved.
[0103] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A semiconductor integrated device, comprising: A first semiconductor layer, a first device formed based on the first semiconductor layer; A connecting layer, located on the first semiconductor layer; A second semiconductor layer, located on the connection layer, having a first surface and a second surface opposite to each other, the second surface being connected to the connection layer, and a second device being formed based on the second semiconductor layer; as well as a plurality of first conductive pillars, penetrating the second semiconductor layer and the connecting layer, and used to electrically lead the plurality of ends of the first device out of the first surface, The material of the first semiconductor layer includes silicon carbide, and the material of the second semiconductor layer includes silicon.
2. The semiconductor integrated device according to claim 1, further comprising: A second dielectric layer, located on the first surface; A plurality of second conductive pillars, penetrating the second dielectric layer, and used to electrically lead the second device out of the second dielectric layer; as well as A wiring layer, located on the second dielectric layer, The multiple first conductive pillars also penetrate the second dielectric layer to electrically lead the first device out of the second dielectric layer, and the multiple ends of the first device and the multiple ends of the second device can be selectively electrically connected through the wiring layer, the first conductive pillars and the second conductive pillars.
3. The semiconductor integrated device according to claim 2, wherein: The first semiconductor layer includes a silicon carbide substrate and an epitaxial layer located on the silicon carbide substrate, The semiconductor integrated device further includes a gate region, a source region and a drain region, which are located in the epitaxial layer. Wherein, the plurality of first conductive pillars are respectively connected to the gate region, the source region and the drain region.
4. The semiconductor integrated device according to claim 3, wherein: At least a portion of the gate region is located between the source region and the drain region, and the gate region, the source region, and the drain region are separated from each other.
5. The semiconductor integrated device according to claim 3, further comprising: A source region and a drain region, located in the second semiconductor layer; as well as a gate, located on the second semiconductor layer and between the source region and the drain region, Wherein, the plurality of second conductive pillars are respectively connected to the gate, the source region and the drain region.
6. The semiconductor integrated device according to claim 5, wherein: The silicon carbide substrate and the gate region are of a first conductivity type, the epitaxial layer, the source region and the drain region are of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.
7. The semiconductor integrated device according to claim 6, wherein: The source region and the drain region are of the second conductivity type; or, the source region and the drain region are of the first conductivity type.
8. The semiconductor integrated device according to any one of claims 1 to 7, wherein: The connection layer comprises: A first dielectric layer, located on the first semiconductor layer; a first bonding layer, located on the first dielectric layer; and a second bonding layer, located on the first bonding layer, Wherein, the second surface is adjacent to the second bonding layer.
9. A method for manufacturing a semiconductor integrated device, comprising: forming a first device based on the first semiconductor layer; Fixing a second semiconductor layer above the first semiconductor layer, wherein the second semiconductor layer and the first semiconductor layer are separated by a connecting layer, the second semiconductor layer having a first surface and a second surface opposite to each other, and the second surface is connected to the connecting layer; forming a second device based on the second semiconductor layer; as well as forming a plurality of first conductive pillars penetrating the second semiconductor layer and the connection layer, wherein the plurality of first conductive pillars are used to electrically lead a plurality of ends of the first device out of the first surface, The material of the first semiconductor layer includes silicon carbide, and the material of the second semiconductor layer includes silicon.
10. The manufacturing method according to claim 9, further comprising: forming a second dielectric layer on the first surface; forming a plurality of second conductive pillars penetrating through the second dielectric layer, wherein the plurality of second conductive pillars are used to electrically lead the second device out of the second dielectric layer; as well as forming a wiring layer on the second dielectric layer, The multiple first conductive pillars also penetrate the second dielectric layer to electrically lead the first device out of the second dielectric layer, and the multiple ends of the first device and the multiple ends of the second device can be selectively electrically connected through the wiring layer, the first conductive pillars and the second conductive pillars.
11. The manufacturing method according to claim 9, further comprising: forming a first dielectric layer on the first semiconductor layer; forming a first bonding layer on the first dielectric layer; as well as forming a second bonding layer on the second surface, The first dielectric layer, the first bonding layer and the second bonding layer are used to form the connection layer. The step of fixing the second semiconductor layer above the first semiconductor layer includes: bonding the first bonding layer to the second bonding layer.
12. The manufacturing method according to claim 11, wherein: The step of forming the second device is performed after the bonding, A process temperature for forming the first device is greater than a process temperature for forming the second device.
13. The manufacturing method according to claim 11, wherein: The material of the first dielectric layer includes silicon oxide, the material of the first bonding layer includes polysilicon, and the material of the second bonding layer includes silicon oxide. 14 . The manufacturing method according to claim 11 , further comprising, before the step of forming the first dielectric layer, performing a high temperature oxidation treatment on the surface of the first semiconductor layer to reduce the surface state density of the first semiconductor layer. 15 . The manufacturing method according to claim 11 , further comprising polishing a surface of the first dielectric layer before forming the first bonding layer.
16. The manufacturing method according to any one of claims 11 to 13, wherein: The second bonding layer is formed by an oxidation process.
17. The manufacturing method according to any one of claims 11 to 13, wherein: The step of forming the plurality of first conductive pillars comprises: Using a first etching process, a hole groove is formed which penetrates the second semiconductor layer and extends to the first dielectric layer; Using a second etching process, the hole groove is extended to the vicinity of the surface of the first semiconductor layer adjacent to the connecting layer; A third dielectric layer and the first conductive column are formed in the hole groove, and the first conductive column and the side wall of the hole groove are separated by the third dielectric layer. Wherein, in the second etching step, a rate of etching the first dielectric layer is greater than a rate of etching the first semiconductor layer.