Semiconductor package and method of manufacturing the same
By designing a semiconductor packaging structure with recessed carrier plates and interposer substrates, the problem of photonic integrated circuit chips being easily damaged in the packaging process is solved, and higher packaging flexibility and integration density are achieved, diverse needs are met and packaging efficiency is improved.
Patent Information
- Application Number
- CN202410002349.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-26
- Filing Date
- 2024-01-02
- Publication Date
- 2025-03-28
AI Technical Summary
In the packaging structure production process, existing photonic integrated circuit chips are easily damaged by heating, alkaline washing and other steps, resulting in damage to the optical waveguide layer.
A semiconductor package is designed, in which the carrier plate has a notch, the photonic integrated circuit chip is arranged in the notch, and the electronic integrated circuit chip is arranged on the first side of the carrier plate, and is electrically connected through an interposer substrate. This design allows photonic integrated circuit chips to be made individually and assembled later, avoiding their involvement in the production process of other chips.
It effectively reduces the chances of contamination and/or damage to the components of the photonic integrated circuit chip, meets a small number of diversified production needs, shortens the development time of packaging modules, and takes into account chip heat dissipation, electrical properties optimization and optical coupling convenience.
Smart Images
Figure CN119725337A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a semiconductor package and a manufacturing method thereof. Background Art
[0002] Heterogenous integration is the integration of multiple electronic components of different properties into a single system-in-package (SiP) through multi-dimensional spatial design such as 2.5D and 3D. In the existing manufacturing process of a packaging structure with a photonic integrated circuit chip, the photonic integrated circuit chip participates in multiple manufacturing process steps of the packaging structure, such as heating and alkali washing. However, the optical waveguide layer of the photonic integrated circuit chip is easily damaged by these manufacturing process steps. Therefore, it is one of the goals of the industry in this technical field to propose a semiconductor package and a manufacturing method thereof that can improve the above-mentioned existing problems. Summary of the invention
[0003] One embodiment of the present invention provides a semiconductor package. The semiconductor package includes a carrier, a photonic integrated circuit chip, an electronic integrated circuit chip, and an interposer substrate. The carrier has a recess and a first surface and a second surface opposite to each other, and the recess extends from the first surface to the second surface. The photonic integrated circuit chip is disposed in the recess. The electronic integrated circuit chip is disposed on the first surface of the carrier. The photonic integrated circuit chip and the electronic integrated circuit chip are disposed on the carrier through the interposer substrate.
[0004] Another embodiment of the present invention provides a method for manufacturing a semiconductor package. The manufacturing method includes the following steps: providing a carrier, wherein the carrier has a recess and a first surface and a second surface opposite to each other, and the recess extends from the first surface to the second surface; and configuring a photonic integrated circuit chip and an electronic integrated circuit chip on the carrier through an interposer substrate, wherein the photonic integrated circuit chip is configured in the recess, and the electronic integrated circuit chip is configured on the first surface of the carrier.
[0005] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1A is a top view of a semiconductor package 100 according to an embodiment of the present invention;
[0007] Figure 1B for Figure 1A A bottom view of a semiconductor package 100;
[0008] Figure 2A for Figure 1A A cross-sectional view of the semiconductor package 100 along direction 2A-2A';
[0009] Figure 2B for Figure 1A A cross-sectional view of the semiconductor package 100 along direction 2B-2B';
[0010] Figure 3A is a top view of a semiconductor package 200 according to another embodiment of the present invention;
[0011] Figure 3B for Figure 3A A bottom view of a semiconductor package 200;
[0012] Figure 4A for Figure 3A A cross-sectional view of the semiconductor package 200 along direction 4A-4A';
[0013] Figure 4B for Figure 3A A cross-sectional view of the semiconductor package 200 along direction 4B-4B';
[0014] Figure 5A is a top view of a semiconductor package 300 according to another embodiment of the present invention;
[0015] Figure 5B for Figure 5A A bottom view of a semiconductor package 200;
[0016] Figure 6A to Figure 6F for Figure 1A FIG. 1 is a diagram showing a manufacturing process of a semiconductor package 100;
[0017] Figure 7A to Figure 7F for Figure 3A FIG. 2 is a diagram showing a manufacturing process of a semiconductor package 200;
[0018] Figure 8A to Figure 8C for Figure 5A FIG. 3 is a diagram of a manufacturing process of a semiconductor package 300 .
[0019] Explanation of symbols
[0020] 100,200,300:Semiconductor packaging
[0021] 100A, 200A, 200B: Structure
[0022] 110,310:Carrier board
[0023] 110r,310r: Notch
[0024] 110s1,310s1: Side 1
[0025] 110s2,310s2: Side 2
[0026] 110s3: Side 3
[0027] 110s4: Side 4
[0028] 120: First Electronic Integrated Circuit Chip
[0029] 120u,131u,160u,220u: upper surface
[0030] 130: Photonic integrated circuit chip
[0031] 130b: Lower surface
[0032] 131: Base material
[0033] 132: Optical waveguide
[0034] 135,137,139:Contact
[0035] 140:Intermediary substrate
[0036] 140s1: Side 5
[0037] 140s2:Sixth side
[0038] 141: Base material
[0039] 141s1: first substrate surface
[0040] 141s2: Second substrate surface
[0041] 142: First layer of cloth
[0042] 143: Second layer of cloth
[0043] 144: Conductive hole
[0044] 150,250: Passive components
[0045] 160: Encapsulation
[0046] 170: First primer
[0047] 180: Second base glue
[0048] 220: Second electronic integrated circuit chip DETAILED DESCRIPTION
[0049] Please refer to Figure 1A to Figure 2B , Figure 1A FIG. 1 is a top view of a semiconductor package 100 according to an embodiment of the present invention. Figure 1B Draw Figure 1A A bottom view of the semiconductor package 100 is shown. Figure 2A Draw Figure 1A The semiconductor package 100 is a cross-sectional view taken along the direction 2A-2A', and Figure 2B Draw Figure 1A 2B-2B′ is a cross-sectional view of the semiconductor package 100 taken along direction 2B-2B′.
[0050] like Figure 1A to Figure 1B As shown, the semiconductor package 100 includes a carrier 110, at least one first electronic integrated circuit (EIC) chip 120, at least one photonic integrated circuit (PIC) chip 130, at least one interposer substrate 140, at least one contact 135, at least one contact 137, at least one contact 139, at least one passive component 150, a package body 160, a first underfill 170 and a second underfill 180.
[0051] like Figure 1A to Figure 1B As shown, the carrier 110 has a notch 110r and a first surface 110s1 and a second surface 110s2 opposite to each other, and the notch 110r extends from the first surface 110s1 to the second surface 110s2. The first electronic integrated circuit chip 120 is disposed on the first surface 110s1 of the carrier 110. The photonic integrated circuit chip 130 is disposed in the notch 110r. Due to the notch design of the carrier 110, the photonic integrated circuit chip 130 is allowed to be assembled to the notch 110r of the carrier 110 after being manufactured separately. Since the photonic integrated circuit chip 130 can be manufactured separately, it can be avoided that the photonic integrated circuit chip 130 participates in the manufacturing process of the first electronic integrated circuit chip 120, thereby reducing the probability of the components (for example, optical waveguide) of the photonic integrated circuit chip 130 being contaminated and / or damaged (the optical waveguide remains intact, which is helpful for optical coupling). In addition, since the photonic integrated circuit chip 130 can be manufactured separately, it can meet the production needs of small quantities and diversified production and / or shorten the development time of the packaging module.
[0052] like Figure 1A to Figure 1B As shown, the carrier 110 is, for example, a U-shaped plate. Specifically, the notch 110r is a through hole extending from the first surface 110s1 to the second surface 110s2. The carrier 110 further has a third surface 110s3 and a fourth surface 110s4 opposite to each other, the third surface 110s3 and the fourth surface 110s4 extending between the first surface 110s1 and the second surface 110s2, and the notch 110r further extends from the third surface 110s3 toward the fourth surface 110s4, but does not extend to the fourth surface 110s4.
[0053] The carrier 110 may be manufactured by, for example, a printed circuit board (PCB) manufacturing process, an integrated circuit carrier manufacturing process, or a ceramic substrate manufacturing process. Although not shown, the carrier 110 may include at least one trace, at least one pad, and at least one conductive hole, etc., to electrically connect the components configured on the carrier 110, and / or to electrically connect the components configured on the carrier 110 with an external component, such as an external circuit board, etc.
[0054] The first electronic integrated circuit chip 120 is, for example, a chip with Cu pillar bumps, a chip with solder bumps, a fan-out chip scale package, or CoWoS (Chip on Wafer on Substrate). In one embodiment, the first electronic integrated circuit chip 120 may be a digital signal processor (DSP) or an application specific integrated circuit (ASIC).
[0055] like Figure 1A to Figure 1B As shown, the photonic integrated circuit chip 130 may be entirely disposed in the recess 110r. In another embodiment, a portion of the photonic integrated circuit chip 130 may be disposed in the recess 110r, but another portion may be located outside the recess 110r.
[0056] like Figure 2A and Figure 2B As shown, the photonic integrated circuit chip 130 has a lower surface 130b, and the lower surface 130b of the photonic integrated circuit chip 130 is retracted relative to the second surface 110s2. In this way, the photonic integrated circuit chip 130 can be prevented from protruding relative to the second surface 110s2 and interfering with components located therebelow, such as a circuit board (not shown).
[0057] like Figure 1A and Figure 2AAs shown, the photonic integrated circuit chip 130 also includes a substrate 131 and at least one optical waveguide 132. The substrate 131 is, for example, a silicon substrate, such as a silicon wafer. The optical waveguide 132 is formed in the substrate 131. The optical waveguide 132 is, for example, a silicon waveguide, and its material includes, for example, silicon (silicon), silicon nitride (SiN), etc. The optical waveguide 132 is exposed from the upper surface 131u of the substrate 131 to receive external optical signals. In this embodiment, since the photonic integrated circuit chip 130 does not participate in the manufacturing process of the first electronic integrated circuit chip 120, the carrier 110 and / or the interposer substrate 140, it can avoid being contaminated or damaged by these manufacturing processes.
[0058] like Figure 2A and Figure 2B As shown, the interposer substrate 140 has a fifth surface 140s1 and a sixth surface 140s2 opposite to each other. The first electronic integrated circuit chip 120 is disposed on the fifth surface 140s1 of the interposer substrate 140, and the photonic integrated circuit chip 130 is disposed on the sixth surface 140s2 of the interposer substrate 140. For example, the contact 135 is disposed between the first electronic integrated circuit chip 120 and the fifth surface 140s1 of the interposer substrate 140 to electrically connect the first electronic integrated circuit chip 120 and the interposer substrate 140. In one embodiment, the contact 135 can be pre-formed on the first electronic integrated circuit chip 120 or the interposer substrate 140, and the first electronic integrated circuit chip 120 and the interposer substrate 140 are connected to each other through the contact 135. The contact 137 is disposed between the photonic integrated circuit chip 130 and the sixth surface 140s2 of the interposer substrate 140 to electrically connect the photonic integrated circuit chip 130 and the interposer substrate 140. In one embodiment, the contact 137 may be preformed on the photonic integrated circuit chip 130 or the interposer substrate 140, and the photonic integrated circuit chip 130 and the interposer substrate 140 are connected via the contact 137. In addition, the contact 139 is disposed between the carrier 110 and the sixth surface 140s2 of the interposer substrate 140 to electrically connect the carrier 110 and the interposer substrate 140. In one embodiment, the contact 139 may be preformed on the carrier 110 or the interposer substrate 140, and the carrier 110 and the interposer substrate 140 are connected via the contact 139. The aforementioned contacts 135, 137 and 139 are, for example, conductive solder balls, conductive pillars and / or conductive bumps.
[0059] like Figure 2A and Figure 2BAs shown, the interposer substrate 140 includes a substrate 141, a first redistribution layer (RDL) 142, a second redistribution layer 143 and at least one conductive via 144. The substrate 141 is, for example, a silicon substrate, such as a silicon wafer. The substrate 141 has a first substrate surface 141s1 and a second substrate surface 141s2 opposite to each other. The first redistribution layer 142 is formed on the first substrate surface 141s1 of the substrate 141, and the second redistribution layer 143 is formed on the second substrate surface 141s2 of the substrate 141. The conductive via 144 is, for example, a through silicon via (TSV), which is formed on the substrate 141 and connects the first redistribution layer 142 and the second redistribution layer 143. Since the interposer substrate is a silicon-based substrate, the spacing between two adjacent conductive vias 144 is in the millimeter or micrometer level, which can provide high-density input / output contacts. At least two of the carrier 110 , the first electronic integrated circuit chip 120 , the photonic integrated circuit chip 130 and the passive component 150 may be electrically connected via the interposer substrate 140 .
[0060] like Figure 2A and Figure 2B As shown, each passive component 150 is, for example, a resistor, a capacitor, or an inductor. In terms of capacitor, the passive component 150 is, for example, a multi-layer ceramic capacitor (MLCC). The passive component 150 is configured on the interposer substrate 140. For example, the passive component 150 is configured and electrically connected to the first redistribution layer 142 of the interposer substrate 140. The passive component 150 can be electrically connected to the first electronic integrated circuit chip 120 and / or the photonic integrated circuit chip 130 through the first redistribution layer 142.
[0061] like Figure 2A and Figure 2B As shown, the package body 160 is formed on the interposer substrate 140 and covers the first electronic integrated circuit chip 120 and the passive component 150. The first electronic integrated circuit chip 120 has an upper surface 120u, which is exposed from the package body 160 to communicate with the outside. In this way, the heat generated by the first electronic integrated circuit chip 120 can be quickly convected to the outside through the upper surface 120u.
[0062] The package 160 is, for example, a molding compound. The package 160 may include, for example, a novolac-based resin, an epoxy-based resin, a silicone-based resin, or other suitable encapsulants. The package 160 may also include a suitable filler, such as powdered silicon dioxide. The package 160 may be formed using a number of packaging techniques, such as compression molding, liquid encapsulation, injection molding, or transfer molding.
[0063] like Figure 2A and Figure 2B As shown, the package body 160 has an upper surface 160u. The upper surface 160u of the package body 160 is substantially flush with the upper surface 120u of the first electronic integrated circuit chip 120. In terms of manufacturing process, after the package body 160 is formed to cover the upper surface 120u of the first electronic integrated circuit chip 120, a technique such as grinding may be used to flatten the package body 160 to expose the upper surface 120u of the first electronic integrated circuit chip 120, or until the flattened upper surface 160u of the package body 160 is substantially flush with the upper surface 120u of the first electronic integrated circuit chip 120. The aforementioned grinding technique is, for example, mechanical grinding or chemical polishing.
[0064] like Figure 2A and Figure 2B As shown, the first underfill 170 is formed between the interposer substrate 140 and the carrier 110, and covers the contacts 139 between the interposer substrate 140 and the carrier 110 to protect these contacts 139. The first underfill 170 also has the function of fixing the relative position between the interposer substrate 140 and the carrier 110. The second underfill 180 is formed between the interposer substrate 140 and the photonic integrated circuit chip 130, and covers the contacts 137 between the interposer substrate 140 and the photonic integrated circuit chip 130 to protect these contacts 137. The second underfill 180 also has the function of fixing the relative position between the interposer substrate 140 and the photonic integrated circuit chip 130. In another embodiment, although not shown, the semiconductor package 100 further includes an adhesive, which can be formed between the photonic integrated circuit chip 130 and the carrier 110 to fix the relative position between the photonic integrated circuit chip 130 and the carrier 110.
[0065] Please refer to Figure 3A to Figure 4B , Figure 3AFIG. 2 is a top view of a semiconductor package 200 according to another embodiment of the present invention. Figure 3B Draw Figure 3A A bottom view of the semiconductor package 200 is shown in FIG. Figure 4A Draw Figure 3A The semiconductor package 200 is a cross-sectional view taken along direction 4A-4A', and Figure 4B Draw Figure 3A 4B-4B′ is a cross-sectional view of the semiconductor package 200 .
[0066] like Figure 3A to Figure 3B As shown, the semiconductor package 200 includes a carrier 110, at least one first electronic integrated circuit chip 120, at least one contact 135, at least one contact 137, at least one contact 139, at least one second electronic integrated circuit chip 220, at least one photonic integrated circuit (PIC) chip 130, an interposer substrate 140, at least one passive component 250, a package body 160, a first base glue 170 and a second base glue 180.
[0067] The semiconductor package 200 includes the same or similar features (structure, material, connection relationship, etc.) as the aforementioned semiconductor package 100 , and one of the differences is that the semiconductor package 200 further includes a second electronic integrated circuit chip 220 .
[0068] like Figure 3A to Figure 3B As shown, the carrier 110 has a notch 110r and a first surface 110s1 and a second surface 110s2 opposite to each other, and the notch 110r extends from the first surface 110s1 to the second surface 110s2. The first electronic integrated circuit chip 120 and the second electronic integrated circuit chip 220 are disposed on the first surface 110s1 of the carrier 110. The photonic integrated circuit chip 130 is disposed in the notch 110r. Due to the notch design of the carrier 110, the photonic integrated circuit chip 130 is allowed to be assembled to the notch 110r of the carrier 110 after being manufactured separately. Since the photonic integrated circuit chip 130 can be manufactured separately, it can avoid the photonic integrated circuit chip 130 from participating in the manufacturing process of the first electronic integrated circuit chip 120, thereby reducing the probability of the components (e.g., optical waveguide) of the photonic integrated circuit chip 130 being contaminated and / or damaged. In addition, since the photonic integrated circuit chip 130 can be manufactured separately, it can meet the advantages of small-volume and diversified manufacturing requirements and / or shorten the development time of the packaging module.
[0069] like Figure 3A and Figure 4AAs shown, the type and / or structure of the second electronic integrated circuit chip 220 is, for example, the same or similar to the first electronic integrated circuit chip 120. In one embodiment, the difference between the second electronic integrated circuit chip 220 and the first electronic integrated circuit chip 120 is that the second electronic integrated circuit chip 220 may be a single-function chip such as a transimpedance amplifier (TIA) or a driver to assist the function that the first electronic integrated circuit chip 120 may lack. The second electronic integrated circuit chip 220 has an upper surface 220u, and the upper surface 220u of the second electronic integrated circuit chip 220 is substantially flush with the upper surface 160u of the package body 160. In terms of manufacturing process, after the package body 160 is formed to cover the upper surface 220u of the second electronic integrated circuit chip 220 and the upper surface 120u of the first electronic integrated circuit chip 120, the package body 160 may be planarized by, for example, grinding to expose the upper surface 220u of the second electronic integrated circuit chip 220 and the upper surface 120u of the first electronic integrated circuit chip 120, or until the planarized upper surface 160u of the package body 160 is substantially flush with the upper surface 220u of the second electronic integrated circuit chip 220 and the upper surface 120u of the first electronic integrated circuit chip 120.
[0070] like Figure 4A As shown, at least one contact 135 is disposed between the second electronic integrated circuit chip 220 and the fifth surface 140s1 of the interposer substrate 140 to electrically connect the second electronic integrated circuit chip 220 and the interposer substrate 140. In one embodiment, the contact 135 may be pre-formed on the second electronic integrated circuit chip 220 or the interposer substrate 140, and the second electronic integrated circuit chip 220 and the interposer substrate 140 are connected via the contact 135.
[0071] like Figure 4A and Figure 4B As shown, in this embodiment, the passive component 250 is embedded in the interposer substrate 140 and can be electrically connected to the first redistribution layer 142 and the second redistribution layer 143. The passive component 250 can be electrically connected to the first electronic integrated circuit chip 120 and / or the second electronic integrated circuit chip 220 through the first redistribution layer 142 and / or the second redistribution layer 143.
[0072] Please refer to Figure 5A to Figure 5B , Figure 5A FIG. 1 is a top view of a semiconductor package 300 according to another embodiment of the present invention. Figure 5B Draw Figure 5A FIG. 2 is a bottom view of a semiconductor package 200 .
[0073] like Figure 5A to Figure 5BAs shown, the semiconductor package 300 includes a carrier 310, at least one first electronic integrated circuit chip 120, at least one second electronic integrated circuit chip 220, at least one photonic integrated circuit chip 130, an interposer substrate 140, at least one passive component 150 (not shown), a package body 160, a first base glue 170 and a second base glue 180.
[0074] The semiconductor package 200 includes the same or similar features (structure, material, connection relationship, etc.) as the aforementioned semiconductor package 100 , and one of the differences is that the structure of the carrier 310 of the semiconductor package 300 is different from the structure of the carrier 110 of the semiconductor package 200 .
[0075] like Figure 5A and Figure 5B As shown, the carrier 310 has a notch 310r and a first surface 310s1 and a second surface 310s2 opposite to each other, and the notch 310r extends from the first surface 310s1 to the second surface 310s2. The first electronic integrated circuit chip 120 and the second electronic integrated circuit chip 220 are disposed on the first surface 310s1 of the carrier 310. The photonic integrated circuit chip 130 is disposed in the notch 310r. Due to the notch design of the carrier 310, the photonic integrated circuit chip 130 is allowed to be assembled to the notch 310r of the carrier 310 after being manufactured separately. Since the photonic integrated circuit chip 130 can be manufactured separately, it can avoid the photonic integrated circuit chip 130 from participating in the manufacturing process of the first electronic integrated circuit chip 120, thereby reducing the probability of the components (e.g., optical waveguide) of the photonic integrated circuit chip 130 being contaminated and / or damaged. In addition, since the photonic integrated circuit chip 130 can be manufactured separately, it can meet the advantages of small-volume and diversified manufacturing requirements and / or shorten the development time of the packaging module.
[0076] like Figure 5A to Figure 5B As shown, the notch 310r extends from the first surface 110s1 toward the second surface 110s2, but does not extend to the second surface 110s2. In other words, unlike the aforementioned carrier 110, the notch 310r of the carrier 310 of the embodiment of the present invention is a groove that does not penetrate the carrier 310. The remaining features (material, structure and / or connection relationship, etc.) of the carrier 310 are the same or similar to those of the aforementioned carrier 110, and will not be described in detail herein.
[0077] In summary, by using a carrier with a notch, multiple circuits (or chips) of different sizes and functions can be integrated into a semiconductor package. This design not only has high flexibility and high-density integration, but also takes into account the needs of chip heat dissipation, electrical optimization and optical coupling convenience.
[0078] Please refer to Figure 6A to Figure 6F , which shows Figure 1A FIG. 1 is a diagram of a manufacturing process of a semiconductor package 100 .
[0079] like Fig. 6A As shown, at least one first electronic integrated circuit chip 120 and at least one passive component 150 are disposed on the interposer substrate 140. Although not shown, the aforementioned contact 135 (the contact 135 is shown in Figure 2A ) can be pre-formed on the carrier 110 or the first electronic integrated circuit chip 120. The carrier 110 and the first electronic integrated circuit chip 120 are butted and electrically connected via the contact 135.
[0080] like Figure 6B As shown, compression molding, liquid packaging, injection molding or transfer molding can be used to form a package body 160 on the interposer substrate 140 and cover the first electronic integrated circuit chip 120 and the passive component 150. Then, a grinding technique can be used to flatten the package body 160 to expose the upper surface 120u of the first electronic integrated circuit chip 120, or until the upper surface 160u of the package body 160 is substantially flush with the upper surface 120u of the first electronic integrated circuit chip 120.
[0081] like Figure 6C As shown, the structure 100A of FIG. 6B may be disposed on the first surface 110s1 of the carrier 110 by using, for example, flip-chip technology. The structure 100A is, for example, a multi-chip heterogeneous integrated module. In addition, although not shown, the aforementioned contact 139 (the contact 139 is shown in FIG. Figure 2A ) may be pre-formed on the carrier 110 or the interposer substrate 140. The carrier 110 and the interposer substrate 140 may be butted and electrically connected via the contacts 139.
[0082] like Fig.6D As shown, a dispensing technique may be used, for example, to form a first primer 170 between the interposer substrate 140 and the carrier 110 and to cover the contact 139 (the contact 139 is shown in FIG. 1 ) between the interposer substrate 140 and the carrier 110. Figure 2A ).
[0083] like Fig. 6E As shown, at least one photonic integrated circuit chip 130 may be disposed on the Fig.6D The structure 100B has a notch 110r on the carrier board 110, and the structure after configuration is as follows Fig. 6F In one embodiment, the Fig. 6E The structure 100B has its notch 110r facing upward, so that the photonic integrated circuit chip 130 can be disposed downward in the notch 110r. In addition, although not shown, the aforementioned contact 137 (the contact 137 is shown in FIG. Figure 2A) can be pre-formed on the interposer substrate 140 or the photonic integrated circuit chip 130. The interposer substrate 140 and the photonic integrated circuit chip 130 can be connected and electrically connected via the contacts 137.
[0084] Then, a second primer 180 (shown in FIG. Figure 2A )At Fig. 6F The interposer substrate 140 (shown in FIG. Figure 2A ) and the photonic integrated circuit chip 130, and covers the contact 137 (the contact 137 is shown in FIG. 1 ) between the interposer substrate 140 and the photonic integrated circuit chip 130. Figure 2A ).
[0085] Then, although not shown, in another embodiment, a dispensing technique may be used to form a glue on the Fig. 6F The photonic integrated circuit chip 130 and the carrier 110 are connected to each other to fix the relative position between the photonic integrated circuit chip 130 and the carrier 110 .
[0086] Please refer to Figure 7A to Figure 7F , which shows Figure 3A FIG. 2 is a diagram of a manufacturing process of a semiconductor package 200 .
[0087] like Fig. 7A As shown, at least one first electronic integrated circuit chip 120 and at least one second electronic integrated circuit chip 220 may be arranged on the interposer substrate 140, wherein at least one passive component 250 may be embedded in the interposer substrate 140. In addition, although not shown, the aforementioned contact 135 may be preformed on the first electronic integrated circuit chip 120 or the interposer substrate 140, and the first electronic integrated circuit chip 120 and the interposer substrate 140 may be butted and electrically connected through the contact 135. In addition, although not shown, the aforementioned contact 135 may be preformed on the second electronic integrated circuit chip 220 or the interposer substrate 140, and the second electronic integrated circuit chip 220 and the interposer substrate 140 may be butted and electrically connected through the contact 135. In addition, the aforementioned contact 135 may be preformed on the first electronic integrated circuit chip 120 or the interposer substrate 140, and may be preformed on the second electronic integrated circuit chip 220 or the interposer substrate 140.
[0088] like Figure 7BAs shown, the package body 160 may be formed on the interposer substrate 140 and cover the first electronic integrated circuit chip 120 and the second electronic integrated circuit chip 220 by, for example, compression molding, liquid packaging, injection molding or transfer molding. Then, the package body 160 may be planarized by, for example, grinding technology to expose the upper surface 120u of the first electronic integrated circuit chip 120 and the upper surface 220u of the second electronic integrated circuit chip 220, or until the upper surface 160u of the package body 160 is substantially flush with the upper surface 120u of the first electronic integrated circuit chip 120 and the upper surface 220u of the second electronic integrated circuit chip 220.
[0089] like Figure 7C As shown, for example, flip chip technology can be used to configure Figure 7B The structure 200A is on the first surface 110s1 of the carrier 110. The structure 200A is, for example, a multi-chip heterogeneous integrated module. In addition, although not shown, the aforementioned contacts 139 can be pre-formed on the carrier 110 or the interposer substrate 140. The carrier 110 and the interposer substrate 140 can be docked and electrically connected through the contacts 139.
[0090] like Fig.7D As shown, a dispensing technique may be used, for example, to form a first primer 170 between the interposer substrate 140 and the carrier 110 and to cover the contact 139 (the contact 139 is shown in FIG. 1 ) between the interposer substrate 140 and the carrier 110. Figure 4A ).
[0091] like Fig. 7E As shown, at least one photonic integrated circuit chip 130 may be disposed on the Fig.7D The structure after configuration is as follows: Figure 7F In one embodiment, the Fig. 7E The structure 200B is formed such that the notch 110r faces upward, so that the photonic integrated circuit chip 130 can be disposed downward in the notch 110r. Although not shown, the aforementioned contact 137 can be pre-formed on the interposer substrate 140 or the photonic integrated circuit chip 130. The interposer substrate 140 and the photonic integrated circuit chip 130 can be connected and electrically connected via the contact 137.
[0092] Then, a second primer 180 (shown in FIG. Figure 4A )At Figure 7F The interposer substrate 140 and the photonic integrated circuit chip 130 are disposed between the interposer substrate 140 and the photonic integrated circuit chip 130, and the contact 137 (the contact 137 is shown in FIG. 1 ) between the interposer substrate 140 and the photonic integrated circuit chip 130 is covered. Figure 4A ).
[0093] Then, although not shown, in another embodiment, a dispensing technique may be used to form a glue on the Figure 7F The photonic integrated circuit chip 130 and the carrier 110 are connected to each other to fix the relative position between the photonic integrated circuit chip 130 and the carrier 110 .
[0094] Please refer to Figure 8A to Figure 8C , which shows Figure 5A FIG. 3 is a diagram of a manufacturing process of a semiconductor package 300 .
[0095] like Fig. 8A As shown, at least one photonic integrated circuit chip 130 is disposed in the recess 310 r of the carrier 310 .
[0096] like Figure 8B As shown, although not shown, in another embodiment, a dispensing technique, for example, may be used to form glue between the photonic integrated circuit chip 130 and the carrier 310 to fix the relative position between the photonic integrated circuit chip 130 and the carrier 310 .
[0097] like Figure 8B As shown, the aforementioned structure 200A is disposed on the carrier 310. The structure after the configuration is as follows Figure 8C Although not shown, the aforementioned contacts 139 may be preformed on the carrier 310 or the interposer substrate 140. The carrier 310 and the interposer substrate 140 may be butted and electrically connected via the contacts 139. In addition, although not shown, the aforementioned contacts 137 may be preformed on the photonic integrated circuit chip 130 or the interposer substrate 140. The photonic integrated circuit chip 130 and the interposer substrate 140 may be butted and electrically connected via the contacts 137.
[0098] like Figure 8C As shown, a dispensing technique, for example, may be used to form a first underfill 170 between the interposer substrate 140 and the carrier 310 , and to cover the contacts 139 between the interposer substrate 140 and the carrier 310 .
[0099] Then, a second primer 180 may be formed on the Figure 8C The interposer substrate 140 and the photonic integrated circuit chip 130 are disposed between the interposer substrate 140 and the photonic integrated circuit chip 130 , and covers the contact 137 between the interposer substrate 140 and the photonic integrated circuit chip 130 .
[0100] In summary, the embodiments of the present invention provide a semiconductor package and a method for manufacturing the same. Since the photonic integrated circuit chip can be manufactured separately, the photonic integrated circuit chip can be prevented from participating in the manufacturing process of the first electronic integrated circuit chip, thereby reducing the probability of the components of the photonic integrated circuit chip (e.g., optical waveguide) being contaminated and / or damaged. In one embodiment, since the photonic integrated circuit chip can be manufactured separately, it can meet the advantages of small-volume and diversified manufacturing needs and / or shorten the development time of the packaging module. In another embodiment, the photonic integrated circuit chip can be configured in the recess of the carrier. Due to the recess design, the photonic integrated circuit chip can be assembled into the recess of the carrier after the separate manufacturing is completed.
[0101] In summary, although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. A person skilled in the art in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the definition of the attached claims.
Claims
1. A semiconductor package, comprising: A carrier having a notch and a first surface and a second surface opposite to each other, wherein the notch extends from the first surface toward the second surface; A photonic integrated circuit (PIC) chip is disposed in the notch; An electronic integrated circuit (EIC) chip is disposed on the first surface of the carrier; as well as Interposer substrate; The photonic integrated circuit chip and the electronic integrated circuit chip are arranged on the carrier through the intermediate layer substrate.
2. The semiconductor package as claimed in claim 1, wherein the recess extends from the first surface to the second surface; the carrier further has a third surface and a fourth surface opposite to each other, the third surface and the fourth surface extend between the first surface and the second surface, and the recess further extends from the third surface toward the fourth surface. The semiconductor package as claimed in claim 1 , wherein the recess does not extend to the second surface. The semiconductor package as claimed in claim 1 , wherein the photonic integrated circuit chip is entirely disposed within the recess. 5 . The semiconductor package as claimed in claim 1 , wherein the photonic integrated circuit chip has a lower surface, and the lower surface of the photonic integrated circuit chip is recessed relative to the second surface. 6 . The semiconductor package as claimed in claim 1 , wherein the interposer substrate has two opposite surfaces, and the electronic integrated circuit chip and the photonic integrated circuit chip are respectively disposed on the two opposite surfaces of the interposer substrate.
7. The semiconductor package according to claim 1, further comprising: Passive components are embedded in the interposer substrate.
8. The semiconductor package according to claim 1, further comprising: A packaging body, covering the electronic integrated circuit chip; The electronic integrated circuit chip has an upper surface, and the upper surface is exposed from the packaging body. 9 . The semiconductor package as claimed in claim 8 , wherein the package body has an upper surface, and the upper surface of the package body is substantially flush with the upper surface of the electronic integrated circuit chip.
10. The semiconductor package according to claim 1, further comprising: A passive component is configured on the interposer substrate; Wherein, the packaging body covers the passive component.
11. The semiconductor package according to claim 1, further comprising: A first base glue is formed between the intermediary layer substrate and the carrier board.
12. The semiconductor package according to claim 1, further comprising: A second underfill is formed between the interposer substrate and the photonic integrated circuit chip.
13. A method for manufacturing a semiconductor package, comprising: Providing a carrier, wherein the carrier has a notch and a first surface and a second surface opposite to each other, wherein the notch extends from the first surface toward the second surface; as well as A photonic integrated circuit chip and an electronic integrated circuit chip are arranged on the carrier through an intermediate layer substrate, wherein the photonic integrated circuit chip is arranged in the recess, and the electronic integrated circuit chip is arranged on the first surface of the carrier.
14. The manufacturing method as claimed in claim 13, wherein the step of disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier comprises: The electronic integrated circuit chip is configured on the interposer substrate.
15. The manufacturing method as claimed in claim 14, wherein the step of disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier comprises: Forming a packaging body to cover the electronic integrated circuit chip to form a multi-chip heterogeneous integrated module; as well as The multi-chip heterogeneous integration module is configured on the carrier board.
16. The manufacturing method as claimed in claim 15, wherein the step of forming the package body to encapsulate the electronic integrated circuit chip comprises: The package body is planarized until the upper surface of the package body is substantially flush with the upper surface of the electronic integrated circuit chip.
17. The manufacturing method as claimed in claim 13, wherein the step of disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier comprises: A first base glue is formed between the intermediary layer substrate and the carrier board.
18. The manufacturing method as claimed in claim 13, wherein the step of disposing the photonic integrated circuit chip and the electronic integrated circuit chip on the carrier comprises: A second underfill is formed between the interposer substrate and the photonic integrated circuit chip.