Control circuit based on COT buck converter

Abstract

The invention discloses a control circuit based on a COT buck converter, and the control circuit comprises a first branch circuit which comprises a ripple extraction unit and a first gain regulator; the second branch comprises a differential unit and a second gain regulator; the control unit is connected with a feedback node of the COT step-down converter, the first branch and the second branch; and the gain adjusting unit is connected with the first gain adjuster and the second gain adjuster and is used for generating a first adjusting current for adjusting the first operation current and a second adjusting current for adjusting the second operation current according to the reference voltage VREF and the feedback voltage VFB. According to the control circuit based on the COT buck converter, different loops are adopted for ripple feedback in different states, and dynamic response and jitter performance of the COT are considered.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a control circuit based on a COT buck converter. Background Art

[0002] The buck converter includes a circuit configured to receive an input voltage V IN A pair of power switches (controlled by the HG signal and the LG signal, respectively) are alternately turned on and off to generate a switching output voltage V at the switch node SW. SW . Switch output voltage V SW is directly coupled to the output inductor L and output capacitor C OUT The LC filter circuit produces a regulated output voltage V having a substantially constant value at the output terminal. OUT . Then the output voltage V OUT To drive the load, the buck converter provides load current to make the output voltage V OUT Keep at a constant level.

[0003] Constant on-time (COT) based buck converters are widely used in industry due to some important advantages such as fast load transient response and easy control of relatively large off-time and very small constant on-time to regulate high input voltage to low output voltage.

[0004] The COT control modes in the prior art include DCAP-COT and CC-COT (Capacitor Current COT). Figure 1 As shown in the figure, DCAP-COT separates the ripple of the inductor current on the switch node SW from the output inductor L and loads it on V FB With V REF Determines the next cycle, its jitter performance is good, but the dynamic response is poor; CC-COT uses a differential circuit to separate the output capacitor C OUT The charging current ripple and reference voltage V REF Comparison is made to determine the start of the next cycle, which can achieve a fast dynamic response, but the differential circuit will introduce noise, resulting in poor jitter.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a control circuit based on a COT buck converter. Summary of the invention

[0006] In view of this, an object of the present invention is to provide a control circuit based on a COT buck converter to take into account both the dynamic response and jitter performance of the COT.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows:

[0008] A control circuit based on a COT buck converter, the control circuit comprising:

[0009] The first branch includes a ripple extraction unit and a first gain regulator, wherein the ripple extraction unit is connected to the output inductor L of the COT buck converter to obtain a first ripple of the inductor current on the switch node SW, the first gain regulator is connected to the ripple extraction unit, and the operating current of the first gain regulator is a first operating current;

[0010] The second branch includes a differential unit and a second gain regulator, wherein the differential unit and the output capacitor C of the COT buck converter are connected. OUT connected to obtain a second ripple of the charging current, the second gain regulator is connected to the differential unit, and the operating current of the second gain regulator is a second operating current;

[0011] The control unit is connected to the feedback node and the first branch and the second branch of the COT buck converter, and is used to generate a voltage signal according to the feedback voltage V FB and the first ripple or the second ripple generates a control signal for two power switches in a COT buck converter;

[0012] The gain adjustment unit is connected to the first gain adjuster and the second gain adjuster, and is used to adjust the gain according to the reference voltage V REF and feedback voltage V FB A first regulating current for regulating the first operating current and a second regulating current for regulating the second operating current are generated.

[0013] In one embodiment, the control circuit includes:

[0014] In a first state, the first branch is connected to the control unit to form a first feedback loop, and in the first state, the working weight of the first branch is greater than the working weight of the second branch;

[0015] In the second state, the second branch is connected to the control unit to form a second feedback loop, and in the second state, the working weight of the second branch is greater than the working weight of the first branch.

[0016] In one embodiment, the ripple extraction unit includes a ripple extractor connected in parallel to both ends of the output inductor L;

[0017] The differentiation unit includes a differentiator connected to an input capacitor.

[0018] In one embodiment, the output end of the ripple extraction unit is connected to the input end of the first gain adjuster, and the output end of the differentiation unit is connected to the input end of the second gain adjuster.

[0019] In one embodiment, the control unit includes a voltage adder, a comparator and an RS trigger;

[0020] The input end of the voltage adder is respectively connected to the output end of the first gain regulator, the output end of the second gain regulator and the feedback node of the COT buck converter, the output end is connected to the first input end of the comparator, the second input end of the comparator is connected to the output end of the error amplifier in the COT buck converter, the output end is connected to the S input end of the RS trigger, the R input end of the RS trigger is connected to the conduction time signal of the COT buck converter, and the Q output end and the QB output end respectively output control signals of two power switches in the COT buck converter.

[0021] In one embodiment, the first gain regulator includes a first switch tube, a control end of the first switch tube is connected to the output end of the ripple extraction unit, a first end current is a current after the first operating current is regulated by the first regulating current, and a second end is connected to the input end of the voltage adder;

[0022] The second gain regulator includes a second switch tube, a control end of the second switch tube is connected to the output end of the differential unit, a first end current is the current of the second operating current adjusted by the second adjustment current, and a second end is connected to the input end of the voltage adder.

[0023] In one embodiment, the first switch tube and the second switch tube are both NMOS tubes, the control end is a gate, the first end is a source, and the second end is a drain.

[0024] In one embodiment, the gain adjustment unit includes a first comparison unit, a second comparison unit and a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a fifth current mirror and a sixth current mirror;

[0025] The two input terminals of the first comparison unit and the second comparison unit are respectively connected to the reference voltage V REF and feedback voltage V FB connected;

[0026] The first current mirror and the second current mirror are connected to the output end of the first comparison unit and the output end of the second comparison unit respectively, and the third current mirror is connected to the first current mirror and the second current mirror respectively, and generates a first regulating current;

[0027] The fourth current mirror and the fifth current mirror are connected to the output end of the first comparison unit and the output end of the second comparison unit respectively, and the sixth current mirror is connected to the fourth current mirror and the fifth current mirror respectively, and generates a second regulating current.

[0028] In one embodiment, the first current mirror includes a first PMOS tube MP1 and a second PMOS tube MP2, the second current mirror includes a third PMOS tube MP3 and a fourth PMOS tube MP4, and the third current mirror includes a fifth NMOS tube MN5 and a sixth NMOS tube MN6;

[0029] The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2, and the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power supply voltage V DD The drain and gate of the first PMOS tube MP1 are short-circuited and connected to the output end of the first comparison unit;

[0030] The gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, and the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are respectively connected to the power supply voltage V DD The drain and gate of the third PMOS tube MP3 are short-circuited and connected to the output end of the second comparison unit;

[0031] The gate of the fifth NMOS tube MN5 is connected to the gate of the sixth NMOS tube MN6, the source of the fifth NMOS tube MN5 and the source of the sixth NMOS tube MN6 are respectively connected to the ground potential, the drain of the fifth NMOS tube MN5 is short-circuited with the gate, and is connected to the drain of the second PMOS tube MP2 and the drain of the fourth PMOS tube MP4, and the drain current of the sixth NMOS tube MN6 is the first regulating current;

[0032] The fourth current mirror includes a first NMOS tube MN1 and a second NMOS tube MN2, the fifth current mirror includes a third NMOS tube MN3 and a fourth NMOS tube MN4, and the sixth current mirror includes a fifth PMOS tube MP5 and a sixth PMOS tube MP6;

[0033] The gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are respectively connected to the ground potential, and the drain of the first NMOS transistor MN1 is short-circuited with the gate and connected to the output end of the first comparison unit;

[0034] The gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, the source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are respectively connected to the ground potential, and the drain of the third NMOS transistor MN3 is short-circuited with the gate and connected to the output end of the second comparison unit;

[0035] The gate of the fifth PMOS transistor MP5 is connected to the gate of the sixth PMOS transistor MP6. The source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 are connected to the power supply voltage V DD The drain of the fifth PMOS tube MP5 is short-circuited with the gate, and is connected to the drain of the second NMOS tube MN2 and the drain of the fourth NMOS tube MN4, and the drain current of the sixth PMOS tube MP6 is the second regulating current;

[0036] In one embodiment, the first comparison unit includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10;

[0037] The gate of the seventh PMOS tube MP7 is connected to the gate of the eighth PMOS tube MP8, and the source of the seventh PMOS tube MP7 and the source of the eighth PMOS tube MP8 are respectively connected to the power supply voltage V DD The drain of the seventh PMOS tube MP7 is connected to the gate of the seventh NMOS tube MN7 and the gate of the eighth NMOS tube MN8, the drain of the seventh NMOS tube MN7 is connected to the drain of the seventh PMOS tube MP7, the source is connected to the ground potential, the source of the eighth NMOS tube MN8 is connected to the ground potential, the drain and the gate are short-circuited, the gate of the tenth NMOS tube MN10 is connected to the gate of the ninth NMOS tube MN9, the drain of the tenth NMOS tube MN10 is connected to the drain of the eighth PMOS tube MP8, the source is connected to the ground potential, the source of the ninth NMOS tube MN9 is connected to the ground potential, the drain and the gate are short-circuited, and the gate of the ninth PMOS tube MP9 is connected to the feedback voltage V FB The drain is connected to the drain of the eighth NMOS tube MN8, the source is connected to the source of the tenth PMOS tube MP10, and the gate of the tenth PMOS tube MP10 is connected to the reference voltage V REF The drain is connected to the drain of the ninth NMOS tube MN9;

[0038] The second comparison unit includes an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, an eleventh NMOS transistor MN1, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13 and a fourteenth NMOS transistor MN14;

[0039] The gate of the eleventh PMOS transistor MP11 is connected to the gate of the twelfth PMOS transistor MP12, and the source of the eleventh PMOS transistor MP11 and the source of the twelfth PMOS transistor MP12 are connected to the power supply voltage V DDThe drain and gate of the eleventh PMOS tube MP11 are short-circuited, the gate of the eleventh NMOS tube MN11 is connected to the gate of the twelfth NMOS tube MN12, the drain of the eleventh NMOS tube MN11 is connected to the drain of the eleventh PMOS tube MP11, and the source is connected to the ground potential, the source of the twelfth NMOS tube MN12 is connected to the ground potential, and the drain and gate are short-circuited, the gate of the fourteenth NMOS tube MN14 is connected to the gate of the thirteenth NMOS tube MN13, the drain of the fourteenth NMOS tube MN14 is connected to the drain of the twelfth PMOS tube MP12, and the source is connected to the ground potential, the source of the thirteenth NMOS tube MN13 is connected to the ground potential, and the drain and gate are short-circuited, and the gate of the thirteenth PMOS tube MP13 is connected to the reference voltage V REF The drain is connected to the drain of the twelfth NMOS tube MN12, the source is connected to the source of the fourteenth PMOS tube MP14, and the gate of the fourteenth PMOS tube MP14 is connected to the feedback voltage V FB The drain is connected to the drain of the thirteenth NMOS tube MN13.

[0040] The present invention has the following beneficial effects:

[0041] The control circuit based on the COT buck converter of the present invention adopts different loops to perform ripple feedback in different states, taking into account the dynamic response and jitter performance of the COT. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 It is a timing comparison diagram under DCAP-COT and CC-COT control modes in the prior art;

[0044] Figure 2 A schematic diagram of a control circuit based on a COT buck converter in a specific embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of the gain adjustment unit in the present invention adjusting the operating current;

[0046] Figure 4 A schematic diagram of a control circuit in a balanced state in a specific embodiment of the present invention;

[0047] Figure 5 A schematic diagram of a control circuit in a fast response state in a specific embodiment of the present invention;

[0048] Figure 6 It is a working timing diagram of a gain adjuster in a specific embodiment of the present invention;

[0049] Figure 7 A schematic diagram of a module of a gain adjustment unit in a specific embodiment of the present invention;

[0050] Figure 8 A circuit diagram of a gain adjustment unit in a specific embodiment of the present invention;

[0051] Fig. 9 The gain adjustment unit in a specific embodiment of the present invention is V REF ≈V FB Schematic diagram of the time;

[0052] Fig.10 The gain adjustment unit in a specific embodiment of the present invention is V REF ≈V FB Schematic diagram of adjusting the operating current;

[0053] Fig.11 The gain adjustment unit in a specific embodiment of the present invention is V REF >V FB Schematic diagram of the time;

[0054] Fig.12 The gain adjustment unit in a specific embodiment of the present invention is V REF >V FB Schematic diagram of adjusting the operating current;

[0055] Fig.13 The gain adjustment unit in a specific embodiment of the present invention is V REF <V FB Schematic diagram of the time;

[0056] Fig.14 The gain adjustment unit in a specific embodiment of the present invention is V REF <V FB Schematic diagram of adjusting the operating current;

[0057] Fig.15 It is a timing comparison diagram under different control modes of the present invention and the prior art. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0059] In the description of this article, unless otherwise specified and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0060] The present invention discloses a control circuit based on a COT buck converter, comprising:

[0061] The first branch includes a ripple extraction unit and a first gain regulator, the ripple extraction unit is connected to the output inductor L of the COT buck converter to obtain a first ripple of the inductor current on the switch node SW, the first gain regulator is connected to the ripple extraction unit, and the operating current of the first gain regulator is a first operating current;

[0062] The second branch includes a differential unit and a second gain regulator, and the differential unit and the output capacitor C of the COT buck converter OUT connected to obtain a second ripple of the charging current, the second gain regulator is connected to the differential unit, and the operating current of the second gain regulator is a second operating current;

[0063] The control unit is connected to the feedback node and the first branch and the second branch of the COT buck converter, and is used to generate a voltage signal according to the feedback voltage V FB and the first ripple or the second ripple generates a control signal for two power switches in a COT buck converter;

[0064] The gain adjustment unit is connected to the first gain adjuster and the second gain adjuster, and is used to adjust the gain according to the reference voltage V REF and feedback voltage V FB A first regulating current for regulating the first operating current and a second regulating current for regulating the second operating current are generated.

[0065] The present invention is further described below in conjunction with specific embodiments.

[0066] Ginseng Figure 2 As shown, the control circuit based on the COT buck converter in this embodiment includes:

[0067] The first branch includes a ripple extraction unit and a first gain regulator (Gain A), the ripple extraction unit is connected to the output inductor L of the COT buck converter to obtain a first ripple of the inductor current IL on the switch node SW, the first gain regulator is connected to the ripple extraction unit, and the operating current of the first gain regulator is the first operating current IB_GainA;

[0068] The second branch includes a differential unit and a second gain regulator (Gain B), the differential unit and the output capacitor C of the COT buck converter OUT connected to obtain a second ripple of the charging current, the second gain regulator is connected to the differential unit, and the operating current of the second gain regulator is a second operating current IB_GainB;

[0069] The control unit is connected to the feedback node and the first branch and the second branch of the COT buck converter, and is used to generate a voltage signal according to the feedback voltage V FB and the first ripple or the second ripple generates control signals HG and LG for two power switches in the COT buck converter;

[0070] The gain adjustment unit (GM) is connected to the first gain adjuster (Gain A) and the second gain adjuster (Gain B) and is used to adjust the reference voltage V REF and feedback voltage V FB A first regulating current IB_GainA′ for regulating the first operating current IB_GainA and a second regulating current IB_GainB′ for regulating the second operating current IB_Gain are generated.

[0071] Among them, the ripple extraction unit in this embodiment includes a ripple extractor (Ripple Extractor) connected in parallel to both ends of the output inductor L, and the output end of the ripple extractor (Ripple Extractor) is connected to the input end of the first gain adjuster (GainA); the differential unit includes a differentiator (Differentiator) connected to the input capacitor, and the output end of the differentiator (Differentiator) is connected to the input end of the second gain adjuster (Gain B).

[0072] In this embodiment, the control unit includes a voltage adder, a comparator CMP and an RS trigger, specifically:

[0073] The input end of the voltage adder is respectively connected to the output end of the first gain regulator (Gain A), the output end of the second gain regulator (Gain B) and the feedback node (FB) of the COT buck converter, the output end is connected to the first input end of the comparator CMP, the second input end of the comparator CMP is connected to the output end of the error amplifier (Error Amp) in the COT buck converter, the output end is connected to the S input end of the RS trigger, the R input end of the RS trigger is connected to the on-time signal (ON_Time) of the COT buck converter, and the Q output end and the QB output end respectively output the control signals HG and LG of the two power switches in the COT buck converter.

[0074] Combination Figure 3 As shown, the first gain regulator (Gain A) in this embodiment includes a first switch tube S1, and the second gain regulator (Gain B) includes a second switch tube S2. Both the first switch tube and the second switch tube are NMOS tubes.

[0075] Specifically, the gate of the first switch tube S1 is connected to the output end of the ripple extractor, the gate current is the first ripple current Ripple_iL, the source current is the current after the first operating current IB_GainA is adjusted by the first regulating current IB_GainA', and the drain is connected to the input end of the voltage adder; the gate of the second switch tube S2 is connected to the output end of the differentiator, the gate current is the second ripple current Ripple_iC, the source current is the current after the second operating current IB_GainB is adjusted by the second regulating current IB_GainB', and the drain is connected to the input end of the voltage adder.

[0076] The control circuit in this embodiment includes:

[0077] The first state (Steady State, equilibrium state), reference Figure 4 Shown and combined Figure 6 , at this time the reference voltage V REF With the feedback voltage V FB The first branch is equal or approximately equal in size, the first branch is connected to the control unit to form a first feedback loop Loop A, and the working weight of the first branch is greater than the working weight of the second branch in the first state;

[0078] In a first state, the first branch is connected to the control unit to form a first feedback loop, and in the first state, the working weight of the first branch is greater than the working weight of the second branch;

[0079] The second state (Transient Response, rapid response state), see Figure 5 Shown and combined Figure 6 , at this time the reference voltage V REFGreater or less than the feedback voltage V FB The second branch is connected to the control unit to form a second feedback loop Loop B, and the working weight of the second branch is greater than the working weight of the first branch in the second state.

[0080] Ginseng Figure 7 The gain adjustment unit (GM) in this embodiment is shown as a schematic diagram. The gain adjustment unit (GM) adjusts the gain according to the reference voltage V REF and feedback voltage V FB A first regulating current IB_GainA′ for regulating the first operating current IB_GainA and a second regulating current IB_GainB′ for regulating the second operating current IB_GainB may be generated.

[0081] Ginseng Figure 8 FIG. 1 is a circuit diagram of the gain adjustment unit (GM) in this embodiment, which includes a first comparison unit, a second comparison unit, a first current mirror (Pair A1), a second current mirror (Pair A2), a third current mirror, a fourth current mirror (Pair B1), a fifth current mirror (Pair B2), and a sixth current mirror, wherein:

[0082] Two input terminals of the first comparison unit and the second comparison unit are respectively connected to a reference voltage V REF and feedback voltage V FB connected;

[0083] The first current mirror and the second current mirror are connected to the output end of the first comparison unit and the output end of the second comparison unit respectively, and the third current mirror is connected to the first current mirror and the second current mirror respectively, and generates a first regulating current;

[0084] The fourth current mirror and the fifth current mirror are connected to the output end of the first comparison unit and the output end of the second comparison unit respectively. The sixth current mirror is connected to the fourth current mirror and the fifth current mirror respectively and generates a second regulating current.

[0085] Specifically, the first current mirror in this embodiment includes a first PMOS tube MP1 and a second PMOS tube MP2, the second current mirror includes a third PMOS tube MP3 and a fourth PMOS tube MP4, and the third current mirror includes a fifth NMOS tube MN5 and a sixth NMOS tube MN6.

[0086] The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2. The source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power supply voltage V DD The drain and gate of the first PMOS tube MP1 are short-circuited and connected to the output end of the first comparison unit;

[0087] The gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4. The source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are connected to the power supply voltage V DD The drain and gate of the third PMOS tube MP3 are short-circuited and connected to the output end of the second comparison unit;

[0088] The gate of the fifth NMOS tube MN5 is connected to the gate of the sixth NMOS tube MN6, the source of the fifth NMOS tube MN5 and the source of the sixth NMOS tube MN6 are respectively connected to the ground potential, the drain of the fifth NMOS tube MN5 is short-circuited with the gate and is connected to the drain of the second PMOS tube MP2 and the drain of the fourth PMOS tube MP4, and the drain current of the sixth NMOS tube MN6 is the first regulation current IB_GainA'.

[0089] The fourth current mirror in this embodiment includes a first NMOS transistor MN1 and a second NMOS transistor MN2 , the fifth current mirror includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4 , and the sixth current mirror includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6 .

[0090] The gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are respectively connected to the ground potential, and the drain of the first NMOS transistor MN1 is short-circuited with the gate and connected to the output end of the first comparison unit;

[0091] The gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, the source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are respectively connected to the ground potential, and the drain of the third NMOS transistor MN3 is short-circuited with the gate and connected to the output end of the second comparison unit;

[0092] The gate of the fifth PMOS transistor MP5 is connected to the gate of the sixth PMOS transistor MP6, and the source of the fifth PMOS transistor MP5 and the source of the sixth PMOS transistor MP6 are connected to the power supply voltage V DD The drain of the fifth PMOS tube MP5 is short-circuited with the gate, and is connected to the drain of the second NMOS tube MN2 and the drain of the fourth NMOS tube MN4, and the drain current of the sixth PMOS tube MP6 is the second regulating current IB_GainB';

[0093] In this embodiment, the first comparison unit includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10.

[0094] The gate of the seventh PMOS tube MP7 is connected to the gate of the eighth PMOS tube MP8, and the source of the seventh PMOS tube MP7 and the source of the eighth PMOS tube MP8 are respectively connected to the power supply voltage V DD The drain of the seventh PMOS tube MP7 is connected to the gate of the seventh NMOS tube MN7 and the gate of the eighth NMOS tube MN8, the drain of the seventh NMOS tube MN7 is connected to the drain of the seventh PMOS tube MP7, the source is connected to the ground potential, the source of the eighth NMOS tube MN8 is connected to the ground potential, the drain and the gate are short-circuited, the gate of the tenth NMOS tube MN10 is connected to the gate of the ninth NMOS tube MN9, the drain of the tenth NMOS tube MN10 is connected to the drain of the eighth PMOS tube MP8, the source is connected to the ground potential, the source of the ninth NMOS tube MN9 is connected to the ground potential, the drain and the gate are short-circuited, and the gate of the ninth PMOS tube MP9 is connected to the feedback voltage V FB The drain is connected to the drain of the eighth NMOS tube MN8, the source is connected to the source of the tenth PMOS tube MP10, and the gate of the tenth PMOS tube MP10 is connected to the reference voltage V REF The drain is connected to the drain of the ninth NMOS tube MN9.

[0095] The second comparison unit in this embodiment includes an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, an eleventh NMOS transistor MN1, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13 and a fourteenth NMOS transistor MN14.

[0096] The gate of the eleventh PMOS transistor MP11 is connected to the gate of the twelfth PMOS transistor MP12. The source of the eleventh PMOS transistor MP11 and the source of the twelfth PMOS transistor MP12 are connected to the power supply voltage V DD The drain and gate of the eleventh PMOS tube MP11 are short-circuited, the gate of the eleventh NMOS tube MN11 is connected to the gate of the twelfth NMOS tube MN12, the drain of the eleventh NMOS tube MN11 is connected to the drain of the eleventh PMOS tube MP11, and the source is connected to the ground potential, the source of the twelfth NMOS tube MN12 is connected to the ground potential, and the drain and gate are short-circuited, the gate of the fourteenth NMOS tube MN14 is connected to the gate of the thirteenth NMOS tube MN13, the drain of the fourteenth NMOS tube MN14 is connected to the drain of the twelfth PMOS tube MP12, and the source is connected to the ground potential, the source of the thirteenth NMOS tube MN13 is connected to the ground potential, and the drain and gate are short-circuited, and the gate of the thirteenth PMOS tube MP13 is connected to the reference voltage V REFThe drain is connected to the drain of the twelfth NMOS tube MN12, the source is connected to the source of the fourteenth PMOS tube MP14, and the gate of the fourteenth PMOS tube MP14 is connected to the feedback voltage V FB The drain is connected to the drain of the thirteenth NMOS tube MN13.

[0097] In this embodiment, the weights of the first operating current IB_GainA and the second operating current IB_GainB can be adjusted by adjusting the input stages Gm of the first current mirror Pair A1 , the second current mirror Pair A2 , the fourth current mirror Pair B1 , and the fifth current mirror Pair B2 .

[0098] Ginseng Fig. 9 and Fig.10 As shown, V REF ≈V FB When the COT buck converter is in a balanced state (Steady State), the ratio of the inductor ripple to the capacitor ripple is 4:1. At this time, the currents input to the first comparison unit and the second comparison unit are both 2*I, the first operating current IB_GainA and the second operating current IB_GainB are 2*I and 0.5*I respectively, and the first regulating current IB_GainA' and the second regulating current IB_GainB' are both 0. Therefore, the operating currents of the first gain regulator Gain A and the second gain regulator Gain B are 2*I and 0.5*I respectively.

[0099] Ginseng Fig.11 and Fig.12 As shown, V REF >V FB , the COT buck converter is in a fast response state (Transient Response), and the ratio of the inductor ripple to the capacitor ripple is 2:3. At this time, the currents input to the first comparison unit and the second comparison unit are both 2*I, the first operating current IB_GainA and the second operating current IB_GainB are 2*I and 0.5*I respectively, the first regulating current IB_GainA' and the second regulating current IB_GainB' are -1*I and 1*I respectively, so the final operating currents of the first gain regulator Gain A and the second gain regulator Gain B are 1*I and 1.5*I respectively.

[0100] Ginseng Fig.13 and Fig.14 As shown, V REF <V FB, the COT buck converter is in a fast response state (Transient Response), and the ratio of the inductor ripple to the capacitor ripple is 2:3. At this time, the currents input to the first comparison unit and the second comparison unit are both 2*I, the first operating current IB_GainA and the second operating current IB_GainB are 2*I and 0.5*I respectively, the first regulating current IB_GainA' and the second regulating current IB_GainB' are -1*I and 1*I respectively, so the final operating currents of the first gain regulator Gain A and the second gain regulator Gain B are 1*I and 1.5*I respectively.

[0101] Ginseng Fig.15 As shown, in this embodiment, the operating currents of the two gain regulators are adjusted by the gain adjustment unit, so that different loops (Loop A / B) are used for feedback in the balanced state and the fast response state, which can take into account the dynamic response and jitter performance of COT. The dynamic response is better than CC-COT, and the jitter response is better than DCAP-COT.

[0102] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0103] The control circuit based on the COT buck converter of the present invention adopts different loops to perform ripple feedback in different states, taking into account the dynamic response and jitter performance of the COT.

[0104] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0105] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A control circuit based on a COT buck converter, characterized in that: The control circuit comprises: The first branch includes a ripple extraction unit and a first gain regulator, wherein the ripple extraction unit is connected to the output inductor L of the COT buck converter to obtain a first ripple of the inductor current on the switch node SW, the first gain regulator is connected to the ripple extraction unit, and the operating current of the first gain regulator is a first operating current; The second branch includes a differential unit and a second gain regulator, wherein the differential unit and the output capacitor C of the COT buck converter are connected. OUT connected to obtain a second ripple of the charging current, the second gain regulator is connected to the differential unit, and the operating current of the second gain regulator is a second operating current; The control unit is connected to the feedback node and the first branch and the second branch of the COT buck converter, and is used to generate a voltage signal according to the feedback voltage V FB and the first ripple or the second ripple generates a control signal for two power switches in a COT buck converter; The gain adjustment unit is connected to the first gain adjuster and the second gain adjuster, and is used to adjust the gain according to the reference voltage V REF and feedback voltage V FB A first regulating current for regulating the first operating current and a second regulating current for regulating the second operating current are generated.

2. The control circuit based on the COT buck converter according to claim 1, characterized in that: The control circuit comprises: In a first state, the first branch is connected to the control unit to form a first feedback loop, and in the first state, the working weight of the first branch is greater than the working weight of the second branch; In the second state, the second branch is connected to the control unit to form a second feedback loop, and in the second state, the working weight of the second branch is greater than the working weight of the first branch.

3. The control circuit based on the COT buck converter according to claim 1, characterized in that: The ripple extraction unit includes a ripple extractor connected in parallel to both ends of the output inductor L; The differentiation unit includes a differentiator connected to an input capacitor.

4. The control circuit based on the COT buck converter according to claim 1, characterized in that: The output end of the ripple extraction unit is connected to the input end of the first gain adjuster, and the output end of the differential unit is connected to the input end of the second gain adjuster.

5. The control circuit based on the COT buck converter according to claim 4, characterized in that: The control unit includes a voltage adder, a comparator and an RS trigger; The input end of the voltage adder is respectively connected to the output end of the first gain regulator, the output end of the second gain regulator and the feedback node of the COT buck converter, the output end is connected to the first input end of the comparator, the second input end of the comparator is connected to the output end of the error amplifier in the COT buck converter, the output end is connected to the S input end of the RS trigger, the R input end of the RS trigger is connected to the conduction time signal of the COT buck converter, and the Q output end and the QB output end respectively output control signals of two power switches in the COT buck converter.

6. The control circuit based on the COT buck converter according to claim 5, characterized in that: The first gain regulator comprises a first switch tube, a control end of the first switch tube is connected to the output end of the ripple extraction unit, a first end current is a current after the first operating current is regulated by the first regulating current, and a second end is connected to the input end of the voltage adder; The second gain regulator includes a second switch tube, a control end of the second switch tube is connected to the output end of the differential unit, a first end current is the current of the second operating current adjusted by the second adjustment current, and a second end is connected to the input end of the voltage adder.

7. The control circuit based on the COT buck converter according to claim 6, characterized in that: The first switch tube and the second switch tube are both NMOS tubes, the control end is a gate, the first end is a source, and the second end is a drain.

8. The control circuit based on the COT buck converter according to claim 2, characterized in that: The gain adjustment unit includes a first comparison unit, a second comparison unit and a first current mirror, a second current mirror, a third current mirror, a fourth current mirror, a fifth current mirror and a sixth current mirror; The two input terminals of the first comparison unit and the second comparison unit are respectively connected to the reference voltage V REF and feedback voltage V FB connected; The first current mirror and the second current mirror are connected to the output end of the first comparison unit and the output end of the second comparison unit respectively, and the third current mirror is connected to the first current mirror and the second current mirror respectively, and generates a first regulating current; The fourth current mirror and the fifth current mirror are connected to the output end of the first comparison unit and the output end of the second comparison unit respectively, and the sixth current mirror is connected to the fourth current mirror and the fifth current mirror respectively, and generates a second regulating current.

9. The control circuit based on the COT buck converter according to claim 8, characterized in that: The first current mirror includes a first PMOS tube MP1 and a second PMOS tube MP2, the second current mirror includes a third PMOS tube MP3 and a fourth PMOS tube MP4, and the third current mirror includes a fifth NMOS tube MN5 and a sixth NMOS tube MN6; The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2, and the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power supply voltage V DD The drain and gate of the first PMOS tube MP1 are short-circuited and connected to the output end of the first comparison unit; The gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, and the source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are respectively connected to the power supply voltage V DD The drain and gate of the third PMOS tube MP3 are short-circuited and connected to the output end of the second comparison unit; The gate of the fifth NMOS tube MN5 is connected to the gate of the sixth NMOS tube MN6, the source of the fifth NMOS tube MN5 and the source of the sixth NMOS tube MN6 are respectively connected to the ground potential, the drain of the fifth NMOS tube MN5 is short-circuited with the gate, and is connected to the drain of the second PMOS tube MP2 and the drain of the fourth PMOS tube MP4, and the drain current of the sixth NMOS tube MN6 is the first regulating current; The fourth current mirror includes a first NMOS tube MN1 and a second NMOS tube MN2, the fifth current mirror includes a third NMOS tube MN3 and a fourth NMOS tube MN4, and the sixth current mirror includes a fifth PMOS tube MP5 and a sixth PMOS tube MP6; The gate of the first NMOS transistor MN1 is connected to the gate of the second NMOS transistor MN2, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are respectively connected to the ground potential, and the drain of the first NMOS transistor MN1 is short-circuited with the gate and connected to the output end of the first comparison unit; The gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, the source of the third NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are respectively connected to the ground potential, and the drain of the third NMOS transistor MN3 is short-circuited with the gate and connected to the output end of the second comparison unit; The gate of the fifth PMOS tube MP5 is connected to the gate of the sixth PMOS tube MP6, and the source of the fifth PMOS tube MP5 and the source of the sixth PMOS tube MP6 are connected to the power supply voltage V DD The drain of the fifth PMOS tube MP5 is short-circuited with the gate and connected to the drain of the second NMOS tube MN2 and the drain of the fourth NMOS tube MN4. The drain current of the sixth PMOS tube MP6 is the second regulating current.

10. The control circuit based on the COT buck converter according to claim 9, characterized in that: The first comparison unit includes a seventh PMOS tube MP7, an eighth PMOS tube MP8, a ninth PMOS tube MP9, a tenth PMOS tube MP10, a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9 and a tenth NMOS tube MN10; The gate of the seventh PMOS tube MP7 is connected to the gate of the eighth PMOS tube MP8, and the source of the seventh PMOS tube MP7 and the source of the eighth PMOS tube MP8 are respectively connected to the power supply voltage V DD The drain of the seventh PMOS tube MP7 is connected to the gate of the seventh NMOS tube MN7 and the gate of the eighth NMOS tube MN8, the drain of the seventh NMOS tube MN7 is connected to the drain of the seventh PMOS tube MP7, the source is connected to the ground potential, the source of the eighth NMOS tube MN8 is connected to the ground potential, the drain and the gate are short-circuited, the gate of the tenth NMOS tube MN10 is connected to the gate of the ninth NMOS tube MN9, the drain of the tenth NMOS tube MN10 is connected to the drain of the eighth PMOS tube MP8, the source is connected to the ground potential, the source of the ninth NMOS tube MN9 is connected to the ground potential, the drain and the gate are short-circuited, and the gate of the ninth PMOS tube MP9 is connected to the feedback voltage V FB The drain is connected to the drain of the eighth NMOS tube MN8, the source is connected to the source of the tenth PMOS tube MP10, and the gate of the tenth PMOS tube MP10 is connected to the reference voltage V REF The drain is connected to the drain of the ninth NMOS tube MN9; The second comparison unit includes an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, an eleventh NMOS transistor MN1, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13 and a fourteenth NMOS transistor MN14; The gate of the eleventh PMOS transistor MP11 is connected to the gate of the twelfth PMOS transistor MP12, and the source of the eleventh PMOS transistor MP11 and the source of the twelfth PMOS transistor MP12 are connected to the power supply voltage V DD The drain and gate of the eleventh PMOS tube MP11 are short-circuited, the gate of the eleventh NMOS tube MN11 is connected to the gate of the twelfth NMOS tube MN12, the drain of the eleventh NMOS tube MN11 is connected to the drain of the eleventh PMOS tube MP11, and the source is connected to the ground potential, the source of the twelfth NMOS tube MN12 is connected to the ground potential, and the drain and gate are short-circuited, the gate of the fourteenth NMOS tube MN14 is connected to the gate of the thirteenth NMOS tube MN13, the drain of the fourteenth NMOS tube MN14 is connected to the drain of the twelfth PMOS tube MP12, and the source is connected to the ground potential, the source of the thirteenth NMOS tube MN13 is connected to the ground potential, and the drain and gate are short-circuited, and the gate of the thirteenth PMOS tube MP13 is connected to the reference voltage V REF The drain is connected to the drain of the twelfth NMOS tube MN12, the source is connected to the source of the fourteenth PMOS tube MP14, and the gate of the fourteenth PMOS tube MP14 is connected to the feedback voltage V FB The drain is connected to the drain of the thirteenth NMOS tube MN13.

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