A filter wafer level package structure and a packaging method thereof

Abstract

The application provides a filter wafer level packaging structure, which comprises a substrate, a carrier structure, the carrier structure comprising, from bottom to top, an interdigital transducer, a pad metal layer, a passivation layer, a dry film and a cover plate arranged in sequence on one side of the substrate, a metal protective layer covering the carrier structure, and a conductive connecting piece penetrating through the substrate and electrically connected with the interdigital transducer from the side away from the carrier structure, so as to achieve the technical effects of reducing the overall size of the filter wafer level packaging structure and improving the reliability and service life of the filter wafer level packaging structure.

Description

Technical Field

[0001] This application relates to the field of device packaging technology, and in particular to a filter wafer-level packaging structure and its fabrication method. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this application as set forth in the claims. The description herein is not to be construed as prior art simply because it is included in this section.

[0003] With the rapid development of 4G and 5G communications, radio frequency devices—filters—play a core role in mobile communications and automotive electronics, thus requiring increasingly higher reliability from SAW filters.

[0004] Current filters such as Figure 1 As shown, its packaging structure is as follows: the solder / gold ball is fixedly connected to the pad metal layer by setting the UBM layer, and the outermost layer is a cover plate made of polyimide (also known as the PI layer) to protect the entire filter. However, the contact area between the PI layer and the gold ball is limited, so the reliability and stability of the connection between the solder / gold ball and the PI layer are poor, which leads to the filter being easily damaged and its service life being shortened.

[0005] Therefore, there is an urgent need to propose a filter wafer-level packaging structure and packaging method that can solve the above-mentioned technical problems. Summary of the Invention

[0006] This application provides a filter wafer-level packaging structure and its fabrication method to improve the reliability and stability of the filter wafer-level packaging structure, thereby ensuring the service life of the filter.

[0007] One aspect of this application provides a filter wafer-level packaging structure, the filter wafer-level packaging structure comprising:

[0008] Substrate;

[0009] The carrier structure includes, from bottom to top, an interdigital transducer, a pad metal layer, a passivation layer, a dry film, and a cover plate disposed on one side of the substrate.

[0010] A metal protective layer is applied to the carrier structure.

[0011] A conductive connector extends through the substrate from the side opposite to the carrier structure and is electrically connected to the interdigital transducer.

[0012] Furthermore, the conductive connector includes: a conductive via extending from the side opposite to the carrier structure through the substrate to the interdigital transducer; and a conductive bump, at least partially embedded in the conductive via and electrically connected to the interdigital transducer.

[0013] Furthermore, the conductive via includes a seed layer disposed between the conductive bump and the substrate; wherein the seed layer is made of metal; and the thickness of the seed layer is 1µm to 20µm.

[0014] Furthermore, the interdigital transducer includes: a first interdigital electrode lead-out portion; a second interdigital electrode lead-out portion; and an electrode finger located between the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion.

[0015] Furthermore, the pad metal layer includes: a first pad metal layer disposed on the side of the first interdigital electrode lead-out portion away from the substrate; and a second pad metal layer disposed on the side of the second interdigital electrode lead-out portion away from the substrate.

[0016] Furthermore, the passivation layer includes: a first passivation layer covering the interdigitated electrode; and a second passivation layer covering the first interdigitated electrode lead-out portion and the second interdigitated electrode lead-out portion.

[0017] Furthermore, the dry film is coated on the second passivation layer; the dry film, the cover plate, and the first passivation layer define a cavity.

[0018] Furthermore, the cover plate and the dry film form a stepped structure.

[0019] Furthermore, the passivation layer is nitrogen oxide or silicon oxide.

[0020] Another aspect of this application provides a filter wafer-level packaging method, the filter wafer-level packaging method comprising:

[0021] Provide a substrate;

[0022] A carrier structure is formed on one side of the substrate. The carrier structure includes, from bottom to top, an interdigital transducer, a pad metal layer, a passivation layer, a dry film, and a cover plate disposed on one side of the substrate.

[0023] A metal protective layer is applied to the carrier structure;

[0024] A conductive connector is disposed on the substrate, and the conductive connector extends through the substrate from the side opposite to the carrier structure and is electrically connected to the interdigital transducer.

[0025] This application proposes a filter wafer-level packaging structure and packaging method thereof. The filter wafer-level packaging structure includes: a substrate; a carrier structure, the carrier structure including, from bottom to top, an interdigital transducer, a pad metal layer, a passivation layer, a dry film, and a cover plate disposed on one side of the substrate; a metal protective layer covering the carrier structure; and a conductive connector penetrating the substrate from the side opposite to the carrier structure and electrically connecting to the interdigital transducer. Compared with the prior art, the filter wafer-level packaging structure proposed in this application eliminates the need to form a metal thin film layer (i.e., UBM layer) and dry film openings on the front surface of the wafer, reducing the wafer fabrication cost.

[0026] On the other hand, the filter wafer-level packaging structure described in this application prevents external moisture from entering the core working area of ​​the filter by sputtering a protective layer on the entire surface of the dry film, thereby improving the reliability of the filter. Furthermore, the substrate described in this application uses through-silicon via (TSV) technology to bring out pins to form conductive bumps, which effectively reduces the size of the filter. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0029] Figure 1 This is a schematic diagram of the structure of a prior art filter as described in the background section;

[0030] Figure 2 This is a schematic diagram of a filter wafer-level packaging structure provided in an embodiment of this application;

[0031] Figure 3 A schematic flowchart of a filter wafer-level packaging method provided in another embodiment of this application;

[0032] Figures 4-7 This is a schematic diagram of the structure of each step in the carrier structure formation process of the filter wafer-level packaging method provided in an embodiment of this application;

[0033] The attached figures are labeled as follows:

[0034] 01-Substrate; 03-Dry film; 04-Cover plate; 05-Metal protective layer; 06-Conductive via; 07-Conductive bump; 08-Seed layer; 09-First interdigitated electrode lead-out; 10-Second interdigitated electrode lead-out; 11-Interdigitated electrode; 12-First pad metal layer; 13-Second pad metal layer; 14-First passivation layer; 15-Second passivation layer; 16-Cavity; 17-UBM layer.

[0035] The same or similar reference numerals in the accompanying drawings represent the same or similar parts. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] Example 1

[0038] Figure 2 This application illustrates a filter wafer-level packaging structure provided in an embodiment of the present application. The filter wafer-level packaging structure includes:

[0039] Substrate 01;

[0040] The carrier structure includes, from bottom to top, an interdigital transducer, a pad metal layer, a passivation layer, a dry film 03, and a cover plate 04 disposed on one side of the substrate 01.

[0041] Metal protective layer 05 covers the carrier structure;

[0042] A conductive connector extends through the substrate 01 from the side opposite to the carrier structure and is electrically connected to the interdigital transducer.

[0043] In this invention, a metal protective layer 05 is introduced as the bonding part of the WLP (Wafer Level Package). The interdigital electrode leads (first interdigital electrode lead 09 or second interdigital electrode lead 10), pad metal layer (first pad metal layer 12 or second pad metal layer 13), passivation layer, dry film 03 and cover plate 04 of the interdigital transducer are sequentially stacked on the substrate 01 to achieve bonding with the substrate 01.

[0044] This application uses a metal protective layer 05 to cover the carrier structure, which includes a dry film 03, based on the inherent packaging form. On the one hand, it solves the technical problem of poor filter reliability and stability caused by insufficient support of the dry film in the original single-layer dry film packaging structure. On the other hand, the metal protective layer packaging form enhances the airtightness of the entire filter device and avoids the filter being damaged by external moisture entering the filter.

[0045] In one embodiment, the substrate 01 includes a lithium tantalate (LT) substrate, a lithium lithium niobate (LN) substrate, a POI substrate (prepared using a Smart-Cut process and consisting of a thin layer of piezoelectric single crystal material (such as single crystal lithium tantalate / lithium niobate), a silicon oxide layer, and a high-resistivity silicon substrate), a Bonding substrate, etc.

[0046] In one embodiment, the conductive connector includes: a conductive via 06 extending from the side opposite to the carrier structure through the substrate 01 to the interdigital transducer; and a conductive bump 07, at least partially embedded in the conductive via 06 and electrically connected to the interdigital transducer.

[0047] Compared to the original packaging structure that sets the conductive bump 07 on the top of the pad metal layer by setting the UBM layer to improve the reliability and stability of the filter, this application uses through silicon via technology to embed the conductive connector part on the bottom of the substrate 01, which not only improves the working stability of the filter but also greatly reduces the overall size of the filter.

[0048] In one embodiment, the conductive bump 07 includes, but is not limited to, solder balls and gold balls.

[0049] In one embodiment, the conductive connector is fabricated using through-silicon via (TSV) technology.

[0050] In one embodiment, the conductive via 06 includes a seed layer 08 disposed between the conductive bump 07 and the substrate 01; wherein the seed layer is made of metal; and the thickness of the seed layer is 1µm to 20µm.

[0051] In one embodiment, the interdigital transducer includes: a first interdigital electrode lead-out portion 09; a second interdigital electrode lead-out portion 10; and an electrode finger located between the first interdigital electrode lead-out portion 09 and the second interdigital electrode lead-out portion 10.

[0052] It is necessary to understand that Figure 2The schematic diagram shown is a cross-sectional view of the filter wafer-level package structure. For ease of explanation, the interdigital electrode lead-out portion of the interdigital transducer is described as the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion. In practical applications, the number of interdigital electrode lead-out portions is one.

[0053] In one embodiment, the pad metal layer includes: a first pad metal layer 12 disposed on the side of the first interdigital electrode lead-out portion 09 away from the substrate 01; and a second pad metal layer 13 disposed on the side of the second interdigital electrode lead-out portion 10 away from the substrate 01.

[0054] It is necessary to understand that Figure 2 The schematic diagram shown is a cross-sectional view of the filter wafer-level package structure. For ease of explanation, the pad metal layer is divided into a first pad metal layer and a second pad metal layer. In practical applications, the number of interdigitated electrode leads corresponding to the pad metal layers is the same.

[0055] In one embodiment, the projected area of ​​the first pad metal layer 12 in the first direction is not greater than the projected area of ​​the first interdigital electrode lead 09 in the first direction; the projected area of ​​the second pad metal layer 13 in the first direction is not greater than the projected area of ​​the second interdigital electrode lead 10 in the first direction. The first direction is perpendicular to the plane of the substrate 01.

[0056] In one embodiment, the passivation layer includes: a first passivation layer 14 covering the interdigital electrode 11; and a second passivation layer 15 covering the first interdigital electrode lead-out portion 09 and the second interdigital electrode lead-out portion 10; the passivation layer is provided to protect the interdigital transducer.

[0057] In one embodiment, the dry film 03 covers the second passivation layer 15; the dry film 03, the cover plate 04, and the first passivation layer 14 define a cavity 16.

[0058] In one embodiment, the cover plate 04 and the dry film 03 form a stepped structure. This stepped structure results in a stepped metal protective layer 05 covering the carrier structure, including the cover plate 04 and the dry film 03, thereby improving the stability of the metal protective layer 05 and ultimately enhancing the reliability and lifespan of the entire filter.

[0059] In one embodiment, the metal protective layer 05 includes a target seed layer and a metal layer. By setting the metal protective layer 05, external moisture is prevented from entering the interior of the filter and interfering with its core working area (interdigital transducer), thereby improving the product reliability and stability of the filter.

[0060] The target seed layer includes, but is not limited to, being generated by sputtering titanium-tungsten or sputtering copper; the metal layer includes, but is not limited to, being generated by electroplating copper, nickel, or gold.

[0061] It should be understood that this application does not limit the thickness and number of the target seed layer and the metal layer. Those skilled in the art can make adaptive adjustments to the thickness and number of the target seed layer and the metal layer according to the actual application scenario.

[0062] It should also be understood that the filter wafer-level packaging structure described in this application refers to a filter fabricated based on a wafer-level packaging process; wherein the filters described in this application include, but are not limited to, surface acoustic wave filters (SAWF or SAW filters), temperature-compensated surface acoustic wave filters (TC-SAW), and thin-film surface acoustic wave filters (TF-SAW).

[0063] Example 2

[0064] Figure 3 This application illustrates a filter wafer-level packaging method, which includes:

[0065] Step S201: Provide a substrate;

[0066] Step S202: A carrier structure is generated on one side of the substrate. The carrier structure includes an interdigital transducer, a pad metal layer, a passivation layer, a dry film, and a cover plate, which are arranged sequentially from bottom to top on one side of the substrate.

[0067] Step S203: Apply a metal protective layer to the carrier structure;

[0068] Step S204: A conductive connector is disposed on the substrate, and the conductive connector passes through the substrate from the side opposite to the carrier structure and is electrically connected to the interdigital transducer.

[0069] In one embodiment, coating the carrier structure with a metal protective layer includes: sputtering titanium-tungsten and / or copper onto the carrier structure using a sputtering process to form a seed layer; electroplating copper, nickel, and gold onto the seed layer using an electroplating process to form a metal layer; the seed layer and the metal layer constitute a metal protective layer.

[0070] In one embodiment, providing a conductive connector on the substrate includes: forming a via on the substrate; forming a seed layer within the via; and forming conductive bumps within the seed layer. The conductive bumps achieve electrical connection to the interdigital transducer through the seed layer.

[0071] In one embodiment, forming a carrier structure on one side of the substrate includes:

[0072] Step S2031, as Figures 4-6 As shown, an interdigitated transducer, a pad metal layer, a passivation layer, and a dry film are formed sequentially from bottom to top on one side of the substrate.

[0073] Step S2032, as Figure 7 As shown, a cover plate is formed on the side of the dry film away from the substrate.

[0074] In one embodiment, step S2031 includes: forming an interdigital transducer on one side of the substrate; forming a passivation layer on the side of the interdigital transducer away from the substrate, the passivation layer covering the interdigital transducer; forming a dry film on the side of the passivation layer away from the substrate and then removing the dry film in a first region; wherein the first region is the region on the side of the interdigital transducer where the electrodes are away from the substrate.

[0075] In one embodiment, step S2032 includes etching the edge of the cover plate such that the cover plate and the dry film form a stepped structure.

[0076] Example 3

[0077] This application proposes a MEMS device that includes a filter wafer-level packaging structure as described in Embodiment 1.

[0078] In one embodiment, the filter wafer-level packaging structure is prepared by the filter wafer-level packaging method described in Example 2.

[0079] Example 4

[0080] Based on the same inventive concept, this application also provides an electronic device. The method corresponding to the electronic device can be the filter wafer-level packaging method in the foregoing embodiments, and its problem-solving principle is similar to that method. The electronic device provided in this application includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the methods and / or technical solutions of the various embodiments of this application.

[0081] The electronic device can be a user device, or a device formed by integrating user devices and network devices through a network, or it can be an application running on the aforementioned devices, or a mobile communication component applied in a vehicle. The user device includes, but is not limited to, various terminal devices such as computers, mobile phones, tablets, smartwatches, and wristbands. The network device includes, but is not limited to, network hosts, single network servers, multiple network server sets, or cloud computing-based computer sets, and can be used to implement some processing functions when setting an alarm clock. Here, the cloud consists of a large number of hosts or network servers based on cloud computing, where cloud computing is a type of distributed computing, consisting of a virtual computer composed of a group of loosely coupled computer sets.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

[0083] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device through software or hardware. The terms "first," "second," etc., are used to indicate names and do not indicate any specific order.

Claims

1. A filter wafer level package structure, characterized by, The filter wafer level packaging structure comprises: a substrate; a carrier structure comprising, from bottom to top, an interdigital transducer, a pad metal layer, a passivation layer, a dry film and a cover plate arranged in sequence on one side of the substrate; a metal protective layer covering the carrier structure; a conductive connecting piece electrically connected to the interdigital transducer through the substrate from the side away from the carrier structure; the conductive connecting piece comprises: a conductive via hole penetrating through the substrate to the interdigital transducer from the side away from the carrier structure; and a conductive bump at least partially embedded in the conductive via hole and electrically connected to the interdigital transducer; the conductive via hole comprises: a seed layer arranged between the conductive bump and the substrate; the seed layer is made of metal; the interdigital transducer comprises: a first interdigital electrode lead-out portion; a second interdigital electrode lead-out portion; and an electrode finger located between the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion.

2. The filter wafer level package structure of claim 1, wherein, The thickness of the seed layer is 1-20 microns.

3. The filter wafer level package structure of claim 2, wherein, The pad metal layer comprises: a first pad metal layer arranged on the side of the first interdigital electrode lead-out portion away from the substrate; and a second pad metal layer arranged on the side of the second interdigital electrode lead-out portion away from the substrate.

4. The filter wafer level package structure of claim 3, wherein, The passivation layer comprises: a first passivation layer covering the interdigital electrode; and a second passivation layer covering the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion.

5. The filter wafer level package structure of claim 4, wherein, The dry film covers the second passivation layer; the dry film, the cover plate and the first passivation layer define a cavity.

6. The filter wafer level package structure of claim 5, wherein, The cover plate and the dry film form a stepped structure.

7. The filter wafer level package structure of claim 6, wherein, The passivation layer is nitrogen oxide or silicon oxide.

8. A filter wafer level packaging method, characterized by, The filter wafer level packaging method comprises: providing a substrate; generating a carrier structure on one side of the substrate, the carrier structure comprising, from bottom to top, an interdigital transducer, a pad metal layer, a passivation layer, a dry film and a cover plate arranged in sequence on one side of the substrate; covering a metal protective layer on the carrier structure; and arranging a conductive connecting piece in the substrate, the conductive connecting piece being electrically connected to the interdigital transducer through the substrate from the side away from the carrier structure; wherein the conductive connecting piece comprises: a conductive via hole penetrating through the substrate to the interdigital transducer from the side away from the carrier structure; and a conductive bump at least partially embedded in the conductive via hole and electrically connected to the interdigital transducer; The conductive via hole comprises: a seed layer arranged between the conductive bump and the substrate; wherein the seed layer is made of metal; The interdigital transducer comprises: a first interdigital electrode lead-out portion; a second interdigital electrode lead-out portion; and an electrode finger located between the first interdigital electrode lead-out portion and the second interdigital electrode lead-out portion.

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