Input pair circuit and DC-DC circuit

Abstract

The present application discloses an input pair circuit and a DC-DC circuit, wherein the input pair circuit includes a reference voltage providing circuit, an input pair transistor, a reverse coupling circuit and an output circuit; the reference voltage providing circuit is used to provide a reference voltage to the input pair transistor according to a reference current; the input pair transistor includes a first transistor and a second transistor, the first end of the first transistor and the first end of the second transistor are connected to the reference voltage, the body end of the first transistor and the body end of the second transistor are connected, and the control end of the first transistor and the control end of the second transistor are coupled to an input signal; the reverse coupling circuit is used to provide a reverse voltage to the body end of the first transistor and the body end of the second transistor when the reference current changes, so as to at least partially offset the deviation voltage generated at the control end of the first transistor and the control end of the second transistor due to the change of the reference current; the output circuit is used to compare the voltages on the control end of the first transistor and the control end of the second transistor and output the comparison result.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and more particularly to an input pair circuit and a DC-DC circuit. Background Art

[0002] Since DC-DC systems do not always operate under high load, they usually need to maintain high efficiency when in light load and standby states to improve battery life and the life of the power supply (such as batteries). Generally speaking, light loads have low output power, and static power consumption and drive losses account for a large proportion, resulting in low efficiency.

[0003] While driving losses can be reduced by reducing the number of switching cycles, or by reducing quiescent current when no switching occurs for extended periods, this can also lead to current switching issues. For the same circuit, the current in current-saving mode may be only 1 / 1000th of that in normal operation, or even lower. This can lead to circuit output errors during current changes. For example, a traditional input-pair circuit may experience output errors when switching between current-saving and non-current-saving modes. Summary of the Invention

[0004] In response to the above situation, the embodiments of the present application propose an input pair circuit and a DC-DC circuit to overcome or at least partially overcome the shortcomings of the prior art.

[0005] In a first aspect, an input pair circuit provided by an embodiment of the present application includes a reference voltage providing circuit, an input pair transistor, a reverse coupling circuit, and an output circuit;

[0006] The reference voltage providing circuit is used to provide a reference voltage to the input transistor pair according to the reference current;

[0007] The input transistor pair includes a first transistor M3 and a second transistor M4, wherein a first terminal of the first transistor M3 and a first terminal of the second transistor M4 are connected to the reference voltage, a body terminal of the first transistor M3 and a body terminal of the second transistor M4 are connected, and a control terminal of the first transistor M3 and a control terminal of the second transistor M4 are coupled to an input signal;

[0008] The reverse coupling circuit is used to provide a reverse voltage to the body terminal of the first transistor M3 and the body terminal of the second transistor M4 when the reference current changes, so as to at least partially offset the deviation voltage generated at the control terminal of the first transistor M3 and the control terminal of the second transistor M4 due to the change of the reference current;

[0009] The output circuit is used to compare the voltages at the control end of the first transistor M3 and the control end of the second transistor M4 and output a comparison result.

[0010] In one embodiment, the reverse coupling circuit further comprises:

[0011] The bias circuit is used to obtain a bias current as a feedback current.

[0012] a switch circuit connected to the bias circuit, configured to receive an external conduction control signal and open or close a switch according to the external conduction control signal to control the on / off of the feedback current;

[0013] The voltage feedback circuit is connected to the switch circuit and generates the reverse voltage according to the provided feedback current.

[0014] In one embodiment, the bias circuit is connected between a power supply terminal VCC and ground. The bias circuit includes transistors M9-M12 and a resistor R4. Transistor M9 and transistor M10 form a current mirror. The gates of transistors M9 and M10 are connected to each other. The sources of transistors M9 and M10 are connected to the power supply terminal VCC. The gates of transistors M11 and M12 are connected. The drain and gate of transistor M11 are connected to the drain of transistor M9. The drain of transistor M12 is connected to the drain and gate of transistor M10. Resistor R4 is arranged between the source of transistor M12 and ground.

[0015] In one embodiment, the switching circuit includes transistors M7 and M8, the source of the transistor M7 is connected to the drain of the transistor M8, the transistor M8 and the transistor M11 form a current mirror, and the transistor M8 mirrors the bias current passing through the resistor R4 to generate the feedback current; the gate of the transistor M7 is connected to the external conduction control signal, and the external conduction control signal is related to the change of the reference current.

[0016] In one embodiment, the voltage feedback circuit includes a resistor R3 , a first end of which is connected to the power supply terminal VCC, and a second end of which is connected to the body terminal of the first transistor M3 and the body terminal of the second transistor M4 . The resistor R3 is used to obtain a reverse voltage.

[0017] In one embodiment, a first terminal of the reference voltage providing circuit is connected to a power supply terminal VCC, and the other terminal is connected to the source of the first transistor M3 and the second transistor M4 of the input transistor pair. The reference voltage providing circuit includes a transistor M1, a transistor M2, and a current source. A first terminal of the current source is connected to the drain of the transistor M1, and a second terminal is connected to ground. The transistors M1 and M2 form a current mirror. The current source provides a reference current to the transistor M1. The transistor M2 replicates the reference current of the transistor M1 and converts the reference current into a reference voltage.

[0018] In one embodiment, the input pair further includes a capacitor C1, a resistor R1, a capacitor C2, and a resistor R2;

[0019] The control end of the first transistor M3 is connected to the input signal VIN1, and the control end of the second transistor M4 is connected to the input signal VIN2. The capacitor C1 and the resistor R1 form an R1C1 parallel circuit, and the capacitor C2 and the resistor R2 form an R2C2 parallel circuit. One end of the R1C1 parallel circuit is coupled to the gate of the first transistor M3, and the other end is grounded. One end of the R2C2 parallel circuit is coupled to the gate of the second transistor M4, and the other end is grounded.

[0020] In one embodiment, the output circuit includes a transistor M5 and a transistor M6, wherein the gates of the transistor M5 and the transistor M6 are connected to each other, the source terminals and the body terminals of the transistor M5 and the transistor M6 are grounded, the transistor M5 and the transistor M6 form a current mirror, the drain and the gate of the transistor M5 are connected to the drain of the first transistor M3, the drain of the transistor M6 is connected to the drain of the second transistor M4, and the output node is located between the drain D of the second transistor M4 and the drain D of the transistor M6. The output node is used to output the comparison result, which is the voltage difference V_OUT between the input signals VIN1 and VIN2.

[0021] In a second aspect, an embodiment of the present application provides a DC-DC circuit, comprising the input pair circuit described above.

[0022] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:

[0023] In this embodiment, a reverse coupling circuit is provided to provide a reverse voltage to the body terminal of the first transistor and the body terminal of the second transistor when the reference current changes, so as to at least partially offset the deviation voltage generated at the control terminal of the first transistor and the control terminal of the second transistor due to the change of the reference current. This stabilizes the gate input signals VIN1 and VIN2 of the first transistor M3 and the second transistor M4, thereby avoiding output signal errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0025] Figure 1 FIG. 1 shows a schematic diagram of the input pair circuit structure according to the first embodiment of the present application;

[0026] Figure 2The waveform diagram when the input to the circuit voltage is restored according to the present application is shown.

[0027] Figure 3 FIG. 2 shows a schematic diagram of an input pair circuit structure according to a second embodiment of the present application;

[0028] Figure 4 A logic block diagram of an input pair circuit according to a second embodiment of the present application is shown.

[0029] Figure 5 This is the timing diagram of the external conduction control signal. DETAILED DESCRIPTION

[0030] Exemplary embodiments of the present disclosure will now be described in detail, examples of which are shown in the accompanying drawings. The same reference numerals are used throughout the drawings to represent the same or similar parts whenever possible. In the specification, it should be noted that similar reference numerals that have been used to represent similar components in other drawings are used for these elements whenever possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.

[0031] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0032] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the details illustrated. Like reference numerals denote like elements throughout. In the following description, when it is determined that a detailed description of related known functions or structures would inevitably obscure the key points of the present disclosure, the detailed description will be omitted.

[0033] As will be fully understood by those skilled in the art, the features of the various embodiments of the present disclosure may be combined or combined in part or in whole, and may interoperate and technically drive each other in various ways. The embodiments of the present disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0034] In this application, a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. When the MOS transistor is in the on state, current flows from the first terminal to the second terminal. The first terminal, second terminal, and control terminal of a PMOS transistor are a source electrode D, a drain electrode S, and a gate electrode G, respectively. The first terminal, second terminal, and control terminal of an NMOS transistor are a drain electrode D, a source electrode S, and a gate electrode G, respectively.

[0035] In the prior art, when a DC-DC system switches states, for example, between standby and load states, the reference current I_REF will be different, which involves the problem of current switching. For the same circuit, the reference current I_REF in the standby state (current saving state) is only 1 / 1000 of that in normal operation or even lower. This may cause circuit output errors during the current change process. The present application adopts the following solution to solve the above-mentioned defects, as follows:

[0036] like Figure 1 As shown, the input pair circuit of the first embodiment of the present application includes a reference voltage providing circuit, an input pair tube, and an output circuit. The current mirror is connected between the power supply terminal VCC and the ground, the input pair tube circuit is connected between the output end of the current mirror and the input end of the output circuit, and the output circuit is connected between the output end of the input pair tube and the ground.

[0037] The reference voltage supply circuit is used to convert a reference current into a reference voltage and provide it to the input transistor pair. A first terminal of the reference voltage supply circuit 100 is connected to the power supply terminal VCC, and another terminal is connected to the common source of the input transistor pair. Specifically, the reference voltage supply circuit comprises a transistor M1, a transistor M2, and a current source. Both transistors M1 and M2 are PMOS transistors. The first terminals of each transistor M1 and M2 are connected to the power supply terminal VCC. The first terminal of the current source is connected to the drain D and gate G of transistor M1, and the second terminal of the current source is connected to ground. The current source provides a reference current for transistor M1. Transistors M1 and M2 form a current mirror, which replicates the reference current I_REF of transistor M1. The reference current I_REF is provided to the input transistor pair via the drain of transistor M2 as the tail current of transistor M2. The drain of transistor M2 serves as a reference voltage node, and the reference voltage VS at the reference voltage node serves as the input voltage of the source S of the first transistor M3 and the second transistor M4.

[0038] Reference Figure 1As shown, the input transistor pair includes a first transistor M3 and a second transistor M4. The sources of the first transistor M3 and the second transistor M4 are connected to each other, and the source S of the first transistor M3 and the source S of the second transistor M4 are both connected to the drain of the transistor M2. The gates G of the first transistor M3 and the second transistor M4 are connected to the input signals of different load systems. When the reference voltage of the source S suddenly changes, the parasitic capacitance voltage of the input transistor pair is coupled to the gate G, causing the input signal to generate an offset voltage. The first transistor M3 and the second transistor M4 are both PMOS transistors. The first terminal and the body terminal of the first transistor M3 and the second transistor M4 are both connected to the reference voltage node.

[0039] Reference Figure 1 As shown, the input pair tubes (M3, M4) are controlled by the reference current of the current mirror. When exiting from the current saving state, the source S reference current of the input pair tubes changes. Due to the equivalent input resistance and capacitance of the gate connection of the input pair tubes and the parasitic capacitance of the transistors themselves, at the moment when the source S reference current suddenly changes, the increased source S voltage and body terminal voltage will be coupled to the gate G of the input pair tubes through the parasitic capacitance, thereby causing the input signal of the input pair tube gate G to change.

[0040] like Figure 1 As shown, there is a parasitic capacitance C_GS3 between the gate and source terminals of the first transistor M3, and a parasitic capacitance C_GB3 between the control terminal and the bulk terminal. Similarly, there is a parasitic capacitance C_GS4 between the gate and source terminals of the second transistor M4, and a parasitic capacitance C_GB4 between the control terminal and the bulk terminal. The control terminal of the first transistor M3 is connected to the input signal VIN1, and the control terminal of the second transistor M4 is connected to the input signal VIN2. The input signals VIN1 and VIN2 are output signals of different load systems respectively. Since the input signals of the input transistors are provided by different load systems, there are equivalent output capacitors and resistors that serve as inputs at the same time.

[0041] In the present application, capacitor C1 and resistor R1 are the output capacitor and resistor of input signal VIN1, and capacitor C2 and resistor R2 are the output capacitor and resistor of input signal VIN2. Capacitor C1 and resistor R1 form a parallel circuit R1C1, where the first end of the R1C1 parallel circuit is coupled to the control terminal of the first transistor M3, and the second end is grounded. Capacitor C2 and resistor R2 form a parallel circuit R2C2, where the first end of the R2C2 parallel circuit is coupled to the control terminal of the second transistor M4, and the second end is grounded. In the above scheme, since input signals VIN1 and VIN2 are output signals of different load systems, the equivalent resistance and capacitance R1 / C1 of input signal VIN1 and the equivalent resistance and capacitance R2 / C2 of input signal VIN2 are usually different. When there is no switching action under light load, the quiescent current will be reduced to improve efficiency, so that the reference current I_REF will become smaller. When switching is required, this current will return to normal, so under light load, there will be a switching between increasing and decreasing of reference current I_REF.

[0042] Taking the example of an increase in reference current I_REF, when returning from standby (current-saving) to a light-load state, the reference current I_REF is relatively low in standby. At the moment of return from standby, the tail current mirrored by transistor M2 also increases, causing the current in the source S and body terminals of the first and second transistors M3 and M4 to increase, thereby increasing the current in the first and second transistors M3 and M4. However, due to the presence of parasitic capacitance between the gate-source GS and GB, such as C_GS3 / C_GB3, the increased source S and body terminals are coupled to the control terminal of the first transistor M3 through the parasitic capacitance. Thus, at this instant, the voltage coupled to the control terminal becomes the voltage divided by the parasitic capacitance and the original input capacitance. Capacitors in series also have a voltage-dividing function, but the characteristic of capacitors is that the smaller the capacitance, the greater the voltage divided. If the input capacitance is larger, the instantaneous coupled voltage is lower. Over time, the coupled voltage will gradually decrease, and the time it takes to decrease is determined by the RC constant of the capacitor. In this case, the larger the capacitance and resistance, the larger the time constant, resulting in a longer time for the voltage to drop to normal.

[0043] like Figure 1 As shown, assuming Figure 1Capacitor C1 is smaller than capacitor C2, and resistors R1 and R2 are the same. Therefore, when reference current I_REF increases, capacitor C1 has a smaller capacitance than C2, and the characteristic of capacitors is that smaller capacitance yields larger voltages. Input signal VIN1 rises higher due to coupling, but because R1*C1 is smaller than R2*C2, it also falls faster. Although input signal VIN2 rises more slowly, it falls more slowly. This may mean that there is a time when input signal VIN2 is greater than input signal VIN1. If input signal VIN2 is less than input signal VIN1 before coupling occurs, coupling may cause the control input signal to reverse. If the input remains in an incorrect state for a long time, the output may also be erroneous.

[0044] The output circuit is used to compare the input signal and output the comparison result. Therefore, due to the defects of the above solution, the comparison result output by the output circuit is inaccurate. Figure 1 The output circuit includes a transistor M5, a transistor M6, and an output node. The transistors M5 and M6 form a current mirror, wherein the transistors M5 and M6 are NMOS transistors, wherein the source terminals / body terminals of the transistors M5 and M6 are grounded. The current flowing through the first transistor M3 is mirrored to the transistor M6 and then output to the output node. The current at the second terminal of the second transistor M4 is output to the output node. The output node is located between the drain D of the second transistor M4 and the drain D of the transistor M6, and is used to output a comparison result, which is the voltage difference VOUT between the input signal VIN1 and the input signal VIN2 of the first transistor M3 and the second transistor M4.

[0045] Since the voltage difference VOUT of the output node depends on the size of VIN1 and VIN2, such as Figure 2 If it appears Figure 2 In the waveforms of the input signals VIN1 and VIN2 shown in the figure, at the rising edge of the reference voltage VS, the peak voltage of the input signal VIN1 is greater than the peak voltage of the input signal VIN2. Later, the peak voltage of the input signal VIN1 is less than the peak voltage of the input signal VIN2. Therefore, the voltage difference V-OUT will also change accordingly. As a result, V-OUT also changes when VS changes, causing V-OUT to be unexpectedly uncontrollable, and thus the comparison result to be uncontrollable.

[0046] Therefore, in the case of this current saving and recovery structure, without any processing, the capacitance and resistance of the control terminals of the first transistors M3 and M4 need to be as similar as possible, which greatly limits the scope of the circuit that can save current.

[0047] The input pair circuit in the first embodiment described above quickly pulls down the highly coupled input signals VIN1 and VIN2 to their normal values ​​through the pull-down circuit, and then pulls them up again when in reverse (entering current saving). However, it is difficult to control the amplitude of the pull-up and pull-down. If the amplitude is too large, the input signal may deviate significantly from the original normal value, resulting in an output error. If the amplitude is too small, the effect is not obvious.

[0048] The main problem mentioned above is that the current flowing through the same MOS transistor is different when saving current and when not saving current. Assuming that the reference current I_REF is I1 when saving current and I2 when not saving current, the gate-source voltages corresponding to currents I1 and I2 flowing through the MOS are VGS1 and VGS2 respectively. When the reference current I_REF changes from I1 to I2, the gate-source voltage of the MOS transistor in the stable state needs to change from VGS1 to VGS2, where the control terminal voltage is a fixed value. This requires the source S voltage to change, and the source S voltage change is VGS2-VGS1. At this time, if a reverse voltage is generated, the amplitude of the reverse voltage is k times the increased voltage of the source S. The k value can be determined by the ratio of the influence of the source S on the control terminal and the body terminal on the control terminal, which is mainly related to parasitic capacitance, thereby offsetting the influence of the source S voltage change on the control terminal.

[0049] Based on the above analysis of the first embodiment, the second embodiment of the present application proposes an input pair circuit, see Figure 3 、 Figure 4 The input pair circuit includes a reference voltage supply circuit 100, an input pair transistor 200, a reverse coupling circuit 300, and an output circuit 400. By incorporating the reverse coupling circuit 300, the input pair circuit of the present application can more accurately and quickly restore the coupled signals (input signals VIN1 and VIN2). Compared to the first embodiment, this embodiment has the reference voltage supply circuit 100 and output circuit 400 of the first embodiment. The circuit structure and principles are the same as those of the first embodiment, and will not be further described in this embodiment.

[0050] It should be noted that the input pair of pipes 200 in this embodiment is different from the input pair of pipes in the first embodiment. Please refer to Figure 3 、 Figure 1In the first embodiment, the input transistor pair includes a first transistor M3 and a second transistor M4. The source S and body terminals of the first transistor M3 and the second transistor M4 are both coupled to a reference voltage node. This embodiment differs from the first embodiment in that, in this embodiment, the first terminal of the first transistor M3 and the first terminal of the second transistor M4 are connected to the reference voltage, the body terminals of the first transistor M3 and the second transistor M4 are connected, and the control terminals of the first transistor M3 and the second transistor M4 are coupled to an input signal. In this embodiment, the body terminals of the first transistor M3 and the second transistor M4 are no longer coupled to the reference voltage node. Aside from the aforementioned differences, the input transistor pair 200 in this embodiment has the same circuit structure as the first embodiment.

[0051] The reverse coupling circuit of this embodiment is configured to provide a reverse voltage to the body terminal of the first transistor M3 and the body terminal of the second transistor M4 when the reference current changes, so as to at least partially offset the deviation voltage generated at the control terminal of the first transistor M3 and the control terminal of the second transistor M4 due to the change in the reference current.

[0052] Specifically: The reverse coupling circuit includes a bias circuit, a switch circuit, and a voltage feedback circuit. The bias circuit is used to obtain a bias current as a feedback current. The switch circuit is connected to the bias circuit and is used to receive an external conduction control signal and open or close the switch according to the conduction control signal to control the on and off of the feedback current; the voltage feedback circuit is connected to the switch circuit and is used to generate a reverse voltage according to the provided feedback current, and the reverse voltage is used to offset the voltage change value of the gate input signal caused by the source voltage change. The reverse coupling circuit is used to adjust the offset caused by the gate-source voltage of the first transistor M3 and the second transistor M4, which is beneficial to improve the accuracy of the output result. The following content is the specific structure of the reverse coupling circuit.

[0053] like Figure 3As shown, the bias circuit is connected between the power supply terminal VCC and ground. The bias circuit includes transistors M9-M12 and a resistor R4. Transistors M9 and M10 form a current mirror, and transistor M9 is connected to the gate of transistor M10. Transistors M9-M10 are PMOS transistors, and transistors M11-M12 are NMOS transistors. There is a certain ratio between transistors M11 and M12. The gates of transistors M11 and M12 are connected. The drain and gate of transistor M11 are connected to the drain of transistor M9. The drain of transistor M12 is connected to the drain and gate of transistor M10. Resistor R4 is connected between the source of transistor M12 and ground to obtain a bias current. The bias current flowing through resistor R4 is (VGS11-VGS12) / R4. This bias current is related to the difference between VGS, where VGS11 is the gate-source voltage of transistor M11 and VGS12 is the gate-source voltage of transistor M12.

[0054] Continue to refer to Figure 3 The first end of the switch circuit is connected to the gate of the transistor M11 and the transistor M12, and the other end is connected to the common body terminal of the input pair transistor 200 (the first transistor M3 and the second transistor M4). The switch circuit includes a transistor M7 and a transistor M8. The transistor M7 and the transistor M8 are NMOS transistors. The drain of the transistor M7 is connected to the body terminal of the first transistor M3, and the drain of the transistor M7 is connected to the body terminal of the second transistor M4. The source of the transistor M7 is connected to the drain of the transistor M8. The transistor M8 and the transistor M11 form a current mirror. The transistor M8 mirrors the bias current passing through the resistor R4 to generate the feedback current. Since the transistor M8 also forms a current mirror with the transistor M11, the transistor M8 mirrors the current passing through the resistor R4 and uses the bias current as the feedback current.

[0055] Continue to refer to Figure 3 The gate of the transistor M7 is connected to an external conduction control signal, which is related to the change of the reference current. The external conduction control signal V_CTRL controls the opening or closing of the transistor M7 and thus controls the on-off of the feedback current.

[0056] See Figure 5 , Figure 5This is the timing diagram of the external conduction control signal V_CTRL. It is always open when exiting the current saving mode and is always closed after entering the current saving mode. Among them, V_M3.4S is the voltage timing diagram of the source S of the first transistor M3 and the first transistor M4, and V_M3.4B is the voltage timing diagram of the body terminal B of the first transistor M3 and the first transistor M4. The external conduction control signal V_CTRL is related to the current saving mode. When exiting the current saving mode, the external conduction control signal V_CTRL will become high, turning on the transistor M7, allowing current to flow through R3, and causing the body terminal B of the input pair tube 200 to generate a pull-down voltage to offset the upward voltage of the source S. After that, this current can continue to exist. In the steady state, the voltage of the body terminal B is lower than the power supply voltage by (VGS11-VGS12)*R3 / R4, which reduces the threshold voltage Vth of the transistor M3 / 4. When current saving is activated, the external conduction control signal V_CTRL transitions from high to low, eliminating this current and generating an upward voltage to offset the downward voltage at the source S during current saving. Therefore, the external conduction control signal V_CTRL can be synchronized with the current saving signal: when current saving goes high, the external conduction control signal V_CTRL goes low; when current saving goes low, the external conduction control signal V_CTRL goes high. Adjustments can also be made based on actual simulations, for example, the external conduction control signal V_CTRL can be set earlier or later than the current saving signal.

[0057] Continue to refer to Figure 3 The voltage feedback circuit is connected to the switching circuit and generates the reverse voltage based on the feedback current provided. The voltage feedback circuit includes a resistor R3, a first end of which is connected to the power supply terminal VCC, and a second end of which is connected to the body terminal of the first transistor M3 and the body terminal of the second transistor M4. When the current saving mode is exited, the external conduction control signal V_CTRL timely turns on the transistor M7, allowing current to flow through the resistor R3, causing the body terminal voltages of the first transistor M3 and the second transistor M4 to drop by (VGS11-VGS12)*R3 / R4. Since the rising voltage of the source of the first transistor M3 and the second transistor M4 is also related to the gate-source voltage, by adjusting R3 and R4 to control the magnitude of the falling voltage of the body terminal of the first transistor M3 and the second transistor M4, the effect of the rising source S of the first transistor M3 and the second transistor M4 can be relatively accurately reduced or even eliminated, thereby stabilizing the gate input signals VIN1 and VIN2 of the first transistor M3 and the second transistor M4.

[0058] Please refer to Figure 3The output circuit has the same structure as that of the first embodiment, including transistors M5 and M6 and an output node. The voltage difference between the gate input signals VIN1 and VIN2 of the first transistor M3 and the second transistor M4 is output through the output node. The input signals VIN1 and VIN2 input to the control terminals of the first transistor M3 and the second transistor M4 are relatively stable. For example, the input signals VIN1 and VIN2 are relatively stable within a preset range, thereby avoiding errors in the output signal.

[0059] The present application also provides a DC-DC circuit, comprising the input pair circuit.

[0060] For example, the input pair circuit can be applied to a DC-DC circuit with a constant on-time (COT) architecture and used as a comparator in the DC-DC circuit. The input signal VIN1 of the input pair circuit of the present application is the feedback voltage FB of the DC-DC circuit, and the input signal VIN2 is the reference voltage REF of the DC-DC circuit. Whether to turn on the power tube is determined by detecting the magnitude of the feedback voltage FB and the reference voltage REF. If an erroneous flip causes the power tube to be turned on by mistake or not turned on when it should be turned on, the entire loop will be faulty. Furthermore, to reduce delay, the current of the input pair circuit is usually higher when not saving current. Therefore, the current changes more when saving current, which can easily cause errors. Therefore, it is urgent for the input pair circuit to output an accurate comparison result.

[0061] It should be noted that although the device is described herein as a certain N-channel or P-channel device, or a certain N-type or P-type doped region, it will be understood by those skilled in the art that complementary devices can also be realized according to the present invention. It will be understood by those skilled in the art that the conductivity type refers to the mechanism by which conduction occurs, such as conduction by holes or electrons, and therefore the conductivity type does not refer to the doping concentration but to the doping type, such as P-type or N-type. It will be understood by those skilled in the art that the terms "during", "when", and "when..." used in this article in relation to circuit operation are not strict terms indicating an action that occurs immediately upon the start of the start-up action, but rather that there may be some small but reasonable delay or delays between the action and the reaction initiated by the start-up action, such as various transmission delays. The terms "approximately" or "substantially" are used herein to mean that the element value has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be exactly the stated value. It is well established in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the desired goal of accuracy as described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0062] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further limitations, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0063] The embodiments of the present invention are described above, but these embodiments do not describe all details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. An input pair circuit, characterized in that It includes a reference voltage providing circuit, an input pair tube, a reverse coupling circuit and an output circuit; The reference voltage providing circuit is used to provide a reference voltage to the input transistor pair according to the reference current; The input transistor pair includes a first transistor M3 and a second transistor M4, wherein a first terminal of the first transistor M3 and a first terminal of the second transistor M4 are connected to the reference voltage, a body terminal of the first transistor M3 and a body terminal of the second transistor M4 are connected, and a control terminal of the first transistor M3 and a control terminal of the second transistor M4 are coupled to an input signal; The reverse coupling circuit is used to provide a reverse voltage to the body terminal of the first transistor M3 and the body terminal of the second transistor M4 when the reference current changes, so as to at least partially offset the deviation voltage generated at the control terminal of the first transistor M3 and the control terminal of the second transistor M4 due to the change of the reference current; The output circuit is used to compare the voltages at the control end of the first transistor M3 and the control end of the second transistor M4 and output a comparison result.

2. The input pair circuit according to claim 1, wherein: The reverse coupling circuit further comprises: a bias circuit, used for obtaining a bias current as a feedback current; a switch circuit connected to the bias circuit, configured to receive an external conduction control signal and open or close a switch according to the external conduction control signal to control the on / off of the feedback current; The voltage feedback circuit is connected to the switch circuit and generates the reverse voltage according to the provided feedback current.

3. The input pair circuit according to claim 2, wherein: The bias circuit is connected between the power supply terminal VCC and the ground. The bias circuit includes transistors M9-M12 and a resistor R4. The transistor M9 and the transistor M10 form a current mirror. The gates of the transistors M9 and M10 are connected to each other. The sources of the transistors M9 and M10 are connected to the power supply terminal VCC. The gates of the transistors M11 and M12 are connected. The drain and gate of the transistor M11 are connected to the drain of the transistor M9. The drain of the transistor M12 is connected to the drain and gate of the transistor M10. The resistor R4 is arranged between the source of the transistor M12 and the ground.

4. The input pair circuit according to claim 3, wherein: The switching circuit includes transistors M7 and M8, the source of the transistor M7 is connected to the drain of the transistor M8, the transistor M8 and the transistor M11 form a current mirror, and the transistor M8 mirrors the bias current passing through the resistor R4 to generate the feedback current; the gate of the transistor M7 is connected to the external conduction control signal.

5. The input pair circuit according to claim 2, wherein: The voltage feedback circuit includes a resistor R3 , a first end of which is connected to the power supply terminal VCC, and a second end of which is connected to the body terminal of the first transistor M3 and the body terminal of the second transistor M4 . The resistor R3 is used to obtain a reverse voltage.

6. The input pair circuit according to claim 1, wherein: The first end of the reference voltage providing circuit is connected to the power supply terminal VCC, and the other end is connected to the source of the first transistor M3 and the second transistor M4 of the input transistor pair. The reference voltage providing circuit includes a transistor M1, a transistor M2, and a current source. The first end of the current source is connected to the drain and gate of the transistor M1, and the second end is connected to the ground. The transistor M1 and the transistor M2 form a current mirror. The current source provides a reference current for the transistor M1. The transistor M2 replicates the reference current of the transistor M1 and converts the reference current into a reference voltage.

7. The input pair circuit according to claim 6, wherein: The input transistor pair further includes a capacitor C1, a resistor R1, a capacitor C2, and a resistor R2; a control end of the first transistor M3 is connected to an input signal VIN1, a control end of the second transistor M4 is connected to an input signal VIN2, the capacitor C1 and the resistor R1 form an R1C1 parallel circuit, the capacitor C2 and the resistor R2 form an R2C2 parallel circuit, one end of the R1C1 parallel circuit is coupled to the gate of the first transistor M3, and the other end is grounded, and one end of the R2C2 parallel circuit is coupled to the gate of the second transistor M4, and the other end is grounded.

8. The input pair circuit according to claim 7, wherein: The output circuit includes a transistor M5 and a transistor M6, wherein the gates of the transistor M5 and the transistor M6 are connected to each other, the source terminals and the body terminals of the transistor M5 and the transistor M6 are grounded, and the transistor M5 and the transistor M6 form a current mirror. The drain and gate of the transistor M5 are connected to the drain of the first transistor M3, and the drain of the transistor M6 is connected to the drain of the second transistor M4. The output node is located between the drain D of the second transistor M4 and the drain D of the transistor M6. The output node is used to output the comparison result, which is the voltage difference V_OUT between the input signals VIN1 and VIN2.

9. A DC-DC circuit, characterized in that: The invention comprises the input pair circuit according to any one of claims 1 to 8.

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