FPGA-based ADC sampling error correction method and system

Abstract

The invention relates to an FPGA-based ADC sampling error correction method and system, and the method comprises the steps: carrying out the sampling control of an ADC chip, and obtaining sampling data; calculating a fitting error value according to the sampling data; and testing the chip to be tested to obtain test data, and calculating according to the test data and the fitting error value to obtain a corrected voltage value. According to the invention, errors caused by factors such as temperature change or chip pin parasitic capacitance can be effectively corrected, and the sampling precision of the system is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of computer equipment testing, and in particular to an ADC sampling error correction method and system based on FPGA. Background Art

[0002] In computer system research, ADC sampling is a commonly required technology in the process of equipment development, especially in computer systems in high-computing application fields, which often place higher requirements on ADC sampling accuracy.

[0003] Although the current high-speed and high-precision ADC chips have greatly improved in sampling rate and accuracy, in harsh environments such as high and low temperatures, due to factors such as temperature fluctuations and parasitic capacitance of sampling devices, the device sampling accuracy cannot meet high-precision requirements. Summary of the invention

[0004] The present invention provides an ADC sampling error correction method and system based on FPGA, which are used to solve the defects of the prior art.

[0005] The present invention provides an ADC sampling error correction method based on FPGA, comprising:

[0006] S1: Sampling control of ADC chip to obtain sampling data;

[0007] S2: Calculate and obtain a fitting error value according to the sampled data;

[0008] S3: Testing the chip to be tested to obtain test data, and calculating a corrected voltage value according to the test data and the fitting error value.

[0009] According to an ADC sampling error correction method based on FPGA provided by the present invention, step S1 further comprises:

[0010] S11: receiving a standard voltage value for testing;

[0011] S12: conditioning the standard voltage value to obtain a standard voltage signal;

[0012] S13: Perform multiple tests on the ADC chip using a standard voltage signal to obtain multiple sets of sampling data.

[0013] According to an ADC sampling error correction method based on FPGA provided by the present invention, step S2 further includes:

[0014] S21: Establish an error calculation model based on the least squares method;

[0015] S22: inputting the sampled data into the error calculation model to obtain a fitting voltage value;

[0016] S23: Calculate and obtain a fitting error value according to the standard voltage value used for testing and the fitting voltage value.

[0017] According to an ADC sampling error correction method based on FPGA provided by the present invention, the expression of the error calculation model in step S21 is:

[0018] y=β1x+β0;

[0019]

[0020] Where y is the fitted voltage value, x is the standard voltage value, β1 is the calculated linear function slope parameter, β0 is the calculated linear function intercept parameter, i is the data group index value in the sampled data, n is the total number of data groups in the sampled data, and x is the number of the linear function groups in the sampled data. i is the input value of the i-th group of data in the sampled data, y i is the output value of the i-th group of data in the sampled data, is the average value of the input values ​​in the sampled data, is the average of the output values ​​in the sampled data.

[0021] According to an ADC sampling error correction method based on FPGA provided by the present invention, step S2 further includes:

[0022] S24: storing the fitting error value into an error register.

[0023] According to an ADC sampling error correction method based on FPGA provided by the present invention, step S3 further includes:

[0024] S31: forwarding the corrected voltage value to a relay station according to an Ethernet communication protocol;

[0025] S32: The relay station uploads the corrected voltage value to the host computer via Ethernet.

[0026] The present invention also provides an ADC sampling error correction system based on FPGA, which is used to execute the ADC sampling error correction method based on FPGA as described in any one of the above items, comprising:

[0027] Sampling module: used to control the sampling of the ADC chip and obtain sampling data;

[0028] FPGA module: used to calculate the fitting error value according to the sampling data; and also used to accumulate the test data of the chip to be tested and the fitting error value to obtain a corrected voltage value;

[0029] Network communication module: used to transmit the corrected voltage value to the host computer.

[0030] According to an FPGA-based ADC sampling error correction system provided by the present invention, the sampling module includes:

[0031] Conditioning unit: used for receiving a standard voltage value, and conditioning the standard voltage value to obtain a standard voltage signal;

[0032] The first acquisition unit is used to perform multiple tests on the ADC chip through a standard voltage signal to acquire multiple sets of sampling data;

[0033] The second acquisition unit is used to test the chip to be tested and obtain test data.

[0034] According to an ADC sampling error correction system based on FPGA provided by the present invention, the FPGA module includes:

[0035] A first calculation unit: used for calculating a fitting error value according to the sampling data;

[0036] The second calculation unit is used to accumulate the test data of the chip to be tested and the fitting error value to obtain a corrected voltage value.

[0037] According to an FPGA-based ADC sampling error correction system provided by the present invention, the network communication module includes:

[0038] Receiving unit: used for receiving the corrected voltage value output by the FPGA module;

[0039] Sending unit: used for uploading the corrected voltage value to the host computer via Ethernet.

[0040] The present invention provides an ADC sampling error correction method based on FPGA, which can accurately calculate and correct the sampling error of the ADC chip, thereby significantly improving the sampling accuracy of the ADC; secondly, the method of the present invention obtains multiple groups of sampling data through multiple tests, and uses the least square method to establish an error calculation model, which can effectively reduce the influence of accidental errors, enhance the stability and reliability of the system, and ensure the continuity and accuracy of data acquisition; in addition, the present invention is not only suitable for a specific type of ADC chip, but also based on the advantages of FPGA, can adapt to different types of ADC chips by adjusting the parameters of the error calculation model, and has high flexibility and versatility; the present invention uses FPGA for error correction, which can make full use of the parallel processing capability and programmability of FPGA, realize efficient and fast data processing and error correction, and the hardware implementation of FPGA also improves the real-time and response speed of the system; after obtaining the error value, the present invention also stores the fitting error value in the error register, which is convenient for subsequent data analysis and troubleshooting. When a problem occurs, it can be quickly located and solved, thereby improving the maintainability and reliability of the system.

[0041] The present invention provides an ADC sampling error correction method and system based on FPGA. Generally speaking, FPGA is used as the main controller, and the least square method is used to fit the sampling function to correct the sampling error value. The method can effectively correct the errors caused by factors such as temperature changes or chip pin parasitic capacitance, thereby greatly improving the sampling accuracy of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 A schematic flow chart of an ADC sampling error correction method based on FPGA provided in an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of the structure of an ADC sampling error correction system based on FPGA is provided in an embodiment of the present invention.

[0045] Reference numerals:

[0046] 100, sampling module; 110, conditioning unit; 120, first collection unit; 130, second collection unit;

[0047] 200, FPGA module; 210, first computing unit; 220, second computing unit;

[0048] 300, network communication module; 310, receiving unit; 320, sending unit. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments, and they should not be understood as limitations on the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In the description of the present invention, it should be understood that the terms used are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0050] Combine the following Figure 1 to Figure 2 Embodiments of the present invention are described.

[0051] like Figure 1 As shown, the present invention provides an ADC sampling error correction method based on FPGA, comprising:

[0052] S1: Perform sampling control on the ADC chip to obtain sampling data.

[0053] Wherein, step S1 further comprises:

[0054] S11: Receive the standard voltage value for testing.

[0055] S12: Conditioning the standard voltage value to obtain a standard voltage signal.

[0056] S13: Perform multiple tests on the ADC chip using a standard voltage signal to obtain multiple sets of sampling data.

[0057] Specifically, in steps S11 to S12, a known standard voltage value is first received, which is an accurate and stable voltage used to calibrate and verify the conversion accuracy of the ADC chip. The subsequent conditioning of the voltage value usually refers to preprocessing the signal to make it suitable for the input requirements of the ADC chip, including amplification, attenuation, filtering, and offset adjustment, so that the received standard voltage value is converted into a standard voltage signal suitable for the input range of the ADC chip. This ensures that the ADC can correctly sample and convert the signal while minimizing errors.

[0058] In step S13, the ADC chip is sampled and tested multiple times using the conditioned standard voltage signal. Each test generates a set of sampling data. The above data is the result of the ADC chip converting the standard voltage signal into a digital signal. Multiple sets of data can be obtained through testing.

[0059] S2: Calculate and obtain a fitting error value according to the sampling data.

[0060] Wherein, step S2 further comprises:

[0061] S21: Establish an error calculation model based on the least squares method.

[0062] The error calculation model in step S21 is expressed as:

[0063] y=β1x+β0;

[0064]

[0065] Where y is the fitted voltage value, x is the standard voltage value, β1 is the calculated linear function slope parameter, β0 is the calculated linear function intercept parameter, i is the data group index value in the sampled data, n is the total number of data groups in the sampled data, and x is the number of the linear function groups in the sampled data. iis the input value of the i-th group of data in the sampled data, y i is the output value of the i-th group of data in the sampled data, is the average value of the input values ​​in the sampled data, is the average of the output values ​​in the sampled data.

[0066] S22: Input the sampled data into the error calculation model to obtain a fitting voltage value.

[0067] S23: Calculate and obtain a fitting error value according to the standard voltage value used for testing and the fitting voltage value.

[0068] In steps S21 to S23, the least squares method is first used to establish a linear error calculation model, and then the actual sampling data is input into the error calculation model to calculate the fitting voltage value. The fitting voltage value is obtained by fitting the model according to the least squares method, that is, the voltage value that the ADC chip should output when there is no error; then the standard voltage value used for testing is subtracted from the fitting voltage value to calculate the fitting error value, which represents the difference between the actual output of the ADC chip and the output predicted by the model.

[0069] Wherein, step S2 also includes:

[0070] S24: storing the fitting error value into an error register.

[0071] The register is a special hardware register used for storing and subsequently processing error values. By storing these error values, they can be analyzed and corrected when necessary to improve the conversion accuracy of the ADC chip.

[0072] S3: Testing the chip to be tested to obtain test data, and calculating a corrected voltage value according to the test data and the fitting error value.

[0073] After obtaining the fitting error value through FPGA calculation in step S2, the fitting error value is taken out from the error register in step S3, and then the sampled value in the third step is superimposed with the value in the error register to obtain a corrected voltage value.

[0074] Wherein, step S3 also includes:

[0075] S31: forwarding the corrected voltage value to a relay station according to an Ethernet communication protocol.

[0076] S32: The relay station uploads the corrected voltage value to the host computer via Ethernet.

[0077] like Figure 2 As shown, the present invention also provides an ADC sampling error correction system based on FPGA, comprising:

[0078] Sampling module 100: used to perform sampling control on the ADC chip to obtain sampling data.

[0079] Wherein, the sampling module 100 comprises:

[0080] The conditioning unit 110 is used for receiving a standard voltage value and conditioning the standard voltage value to obtain a standard voltage signal.

[0081] The first acquisition unit 120 is used to perform multiple tests on the ADC chip through a standard voltage signal to acquire multiple groups of sampling data.

[0082] The second acquisition unit 130 is used to test the chip to be tested and obtain test data.

[0083] FPGA module 200: used to calculate and obtain a fitting error value according to the sampled data; and also used to accumulate the test data of the chip to be tested and the fitting error value to obtain a corrected voltage value.

[0084] Wherein, the FPGA module 200 includes:

[0085] The first calculation unit 210 is used to calculate and obtain a fitting error value according to the sampling data.

[0086] The second calculation unit 220 is used to accumulate the test data of the chip to be tested and the fitting error value to obtain a corrected voltage value.

[0087] Network communication module 300: used to transmit the corrected voltage value to the host computer.

[0088] Wherein, the network communication module 300 includes:

[0089] Receiving unit 310: used for receiving the corrected voltage value output by the FPGA module.

[0090] The sending unit 320 is used to upload the corrected voltage value to the host computer via Ethernet.

[0091] Furthermore, an ADC sampling error correction method based on FPGA provided by the present invention is described below in combination with an ADC sampling error correction system based on FPGA provided by the present invention.

[0092] First, the system is powered on. After power-on, the standard test voltage value is loaded on the conditioning unit, that is, the ADC conditioning circuit. After conditioning, the voltage signal enters the ADC sampling chip; the FPGA module controls the sampling of the first acquisition unit of the sampling module according to the timing of the ADC sampling chip, obtains the initial value of the sampling data, and then loops to obtain a set of linear sampling data.

[0093] Subsequently, a set of sampled data is substituted into the least squares calculation formula to derive the coefficients of the least squares method, and then the corrected y value is substituted into the formula. The obtained y value is compared with the standard voltage value to obtain the fitted error value. The fitted error value is stored in the error register in the FPGA module.

[0094] The FPGA module superimposes the sampling value obtained by the second acquisition unit with the value in the error register to obtain a corrected voltage value. The FPGA control module forwards the sampling data to the network communication module according to the Ethernet communication protocol, and the network communication module uploads the data to the host computer according to the Ethernet protocol.

[0095] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0096] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for correcting ADC sampling errors based on FPGA, characterized in that: include: S1: Sampling control of ADC chip to obtain sampling data; S2: Calculate and obtain a fitting error value according to the sampled data; S3: Testing the chip to be tested to obtain test data, and calculating a corrected voltage value according to the test data and the fitting error value.

2. The ADC sampling error correction method based on FPGA according to claim 1, characterized in that: Step S1 further comprises: S11: receiving a standard voltage value for testing; S12: conditioning the standard voltage value to obtain a standard voltage signal; S13: Perform multiple tests on the ADC chip using a standard voltage signal to obtain multiple sets of sampling data.

3. The ADC sampling error correction method based on FPGA according to claim 1, characterized in that: Step S2 further comprises: S21: Establish an error calculation model based on the least squares method; S22: inputting the sampled data into the error calculation model to obtain a fitting voltage value; S23: Calculate and obtain a fitting error value according to the standard voltage value used for testing and the fitting voltage value.

4. The ADC sampling error correction method based on FPGA according to claim 3, characterized in that: The expression of the error calculation model in step S21 is: y=β1x+β0; Where y is the fitted voltage value, x is the standard voltage value, β1 is the calculated linear function slope parameter, β0 is the calculated linear function intercept parameter, i is the data group index value in the sampled data, n is the total number of data groups in the sampled data, and x is the number of the linear function groups in the sampled data. i is the input value of the i-th group of data in the sampled data, y i is the output value of the i-th group of data in the sampled data, is the average value of the input values ​​in the sampled data, is the average of the output values ​​in the sampled data.

5. The ADC sampling error correction method based on FPGA according to claim 1, characterized in that: Step S2 also includes: S24: storing the fitting error value into an error register.

6. The ADC sampling error correction method based on FPGA according to claim 1, characterized in that: Step S3 also includes: S31: forwarding the corrected voltage value to a relay station according to an Ethernet communication protocol; S32: The relay station uploads the corrected voltage value to the host computer via Ethernet.

7. An ADC sampling error correction system based on FPGA, used to execute the ADC sampling error correction method based on FPGA according to any one of claims 1 to 6, characterized in that: include: Sampling module: used to control the sampling of the ADC chip and obtain sampling data; FPGA module: used for calculating and obtaining a fitting error value according to the sampling data; It is also used to accumulate the test data of the chip to be tested and the fitting error value to obtain a corrected voltage value; Network communication module: used to transmit the corrected voltage value to the host computer.

8. The ADC sampling error correction system based on FPGA according to claim 7, characterized in that: The sampling module comprises: Conditioning unit: used for receiving a standard voltage value, and conditioning the standard voltage value to obtain a standard voltage signal; The first acquisition unit is used to perform multiple tests on the ADC chip through a standard voltage signal to acquire multiple groups of sampling data; The second acquisition unit is used to test the chip to be tested and obtain test data.

9. The ADC sampling error correction system based on FPGA according to claim 7, characterized in that: The FPGA module includes: A first calculation unit: used for calculating a fitting error value according to the sampling data; The second calculation unit is used to accumulate the test data of the chip to be tested and the fitting error value to obtain a corrected voltage value.

10. The ADC sampling error correction system based on FPGA according to claim 7, characterized in that: The network communication module includes: Receiving unit: used for receiving the corrected voltage value output by the FPGA module; Sending unit: used for uploading the corrected voltage value to the host computer via Ethernet.

Images