Multichannel sampling synchronization method and device of radio frequency direct sampling RFSOC system

Abstract

The invention discloses a multi-channel sampling synchronization method and device of a radio frequency direct sampling RFSOC system. The method comprises the steps that a PL end RF IP core of the system sets relevant parameter configuration; according to hardware configuration peripheral connection lines of the system, generating a bottom layer driving framework; generating register parameters on the user layer according to the set related clock, and transmitting the register parameters to the PL end by the PS end through DMA; the PL end transmits the register parameters to a clock distribution module through an SPI interface; a clock distribution module is configured through a system SPI interface, so that the clock distribution module outputs a corresponding sampling clock, a synchronous clock and a data associated clock, ADC input signals can be collected and converted into analog-to-digital conversion data with specified digits, and output analog signals of a DAC are controlled through set frequency control word parameters at a PL end; and the PS end controls the RF IP core of the PL end through an interface function so as to realize multi-channel sampling synchronization of the RFSOC system. According to the invention, low-delay and high-precision multi-channel sampling synchronization of the system is realized.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, and in particular to a multi-channel sampling synchronization method and device for a radio frequency direct sampling (RFSOC) system. Background Art

[0002] As 5G technology matures, its biggest features are big data, crowd connection and scene experience. In the deployment of 5G, large-scale MIMO (multiple transmit and receive) and DBF (digital beamforming) technologies occupy a large part of the solution. At the same time, in the field of radar detection and wireless electromagnetic spectrum monitoring, multi-channel direction finding between antenna array units is also its basic technology. In order to support these technologies, the RF unit close to the antenna-end device must be more compact, and have high sampling rate ADC / DAC (analog-to-digital / digital-to-analog) conversion functions and even RF direct sampling capabilities, as well as programmable signal processing capabilities. The latest RFSOC system integrates RF direct sampling, transceiver and signal processing functions to solve the above problems. It integrates multiple channel sampling data converters, CPU processors and FPGA programmable signal processing capabilities. The power consumption and size of the system are greatly reduced to 50% to 25% of the traditional system design. The system software and hardware functions are flexible and configurable, and have broad application prospects.

[0003] In the RFSOC (Radio Frequency System-on-Chip) system, MIMO, DBF and multi-channel direction finding technology between antenna array units must be implemented, among which multi-channel sampling synchronization is the basis and important link of technical implementation. By constructing the multi-channel sampling synchronization method of the RFSOC system, the multi-channel received and transmitted signals can meet the high-precision synchronization requirements in terms of time, frequency, phase and amplitude, and achieve the key indicators of signal MIMO reception and DBF, thereby completing the system signal multi-carrier multi-channel reception and transmission and array signal digital beam synthesis functions.

[0004] Although the RFSOC system has high integration and compact design, it integrates multi-channel sampling ADC / DAC (analog-to-digital / digital-to-analog) converters, with a maximum of 16 T / R (transmitter / receiver). However, the system itself does not have complete multi-channel sampling synchronization functions and capabilities. It is necessary to redesign the RFSOC system and construct a multi-channel sampling synchronization method to complete the multi-channel sampling synchronization capability, meet the subsequent technology development of 5G and the application requirements of various wireless communications, radar arrays, wireless electromagnetic spectrum monitoring, and digital signal beamforming, and overcome the system's functional deficiencies.

[0005] Patent application number CN202410595018.4 discloses an audio sampling synchronization method and device thereof, which mainly presets a cache area on the device side, and presets high and low cache capacity alarm lines of the cache area, caches the data information sent by the host side in the cache area, and monitors the cache capacity of the cache area in real time; when the cache capacity of the cache area reaches the high / low cache capacity alarm line, the device side feeds back the current actual playback rate to the host side, and the host side adjusts the rate of sending data information according to the actual playback rate until the data information of the host side is sent. However, the invention does not discuss the method of multi-channel sampling synchronization of the RFSOC system, and its entire method is a method for audio signal processing and cannot be applied to high-speed sampling signal processing of the RFSOC system.

[0006] Patent application number CN202311284326.7 is a multi-channel modulation and forwarding system based on RFSOC, which discloses a multi-channel ADC module for acquiring received RF signals, performing digital-to-analog conversion on received RF signals, and obtaining received baseband signals. The PS end receives identification binding information and forwarding binding information, and the PL end performs digital beamforming, signal identification modulation, and multi-channel transmit beamforming on the received baseband signal according to the identification binding information and forwarding binding information to obtain the baseband signal to be transmitted, and the multi-channel DAC module performs analog-to-digital conversion on the baseband signal to be transmitted to obtain the RF signal to be transmitted. This patent introduces a multi-channel modulation and forwarding method for the RFSOC system, but the invention does not discuss a method for constructing a multi-channel sampling synchronization, and the entire system is an introduction to a method for multi-channel modulation and forwarding that cannot be applied to the application environment of the RFSOC system that requires multi-channel sampling synchronization signal processing. Summary of the invention

[0007] In view of this, through the internal components of the RFSOC system and the peripheral clock distribution circuit, the present invention provides a multi-channel sampling synchronization method and device of the RF direct sampling RFSOC system, which cleverly controls the PL (Programmable Logic) end, PS (Processing System) end and clock distribution module in the RFSOC system, thereby realizing a low-latency, high-precision system multi-channel sampling synchronization method.

[0008] The present invention discloses a multi-channel sampling synchronization method of a radio frequency direct sampling RFSOC system, which comprises:

[0009] Step 1: Set up relevant parameter configurations for the RF IP core at the PL end of the system; the relevant parameter configurations include ADC / DAC sampling clock related parameters, input and output characteristic parameters, and data mode;

[0010] Step 2: Generate the underlying driver framework based on the peripheral connection lines of the system hardware configuration; the PS side uses the underlying driver framework as the software platform foundation, generates register parameters at the user layer according to the set related clocks, and the PS side transfers the register parameters to the PL side through DMA;

[0011] Step 3: The PL side transfers the register parameters to the clock distribution module through the SPI interface; the clock distribution module is configured through the system SPI interface to output the corresponding sampling clock, synchronization clock and data follower clock, so that the ADC input signal can be collected and converted into analog-to-digital conversion data of the specified number of bits, and the output analog signal of the DAC is controlled by the set frequency control word parameters on the PL side; the PS side controls the RF IP core on the PL side through the interface function to realize multi-channel sampling synchronization of the RFSOC system.

[0012] Furthermore, the step 1 comprises:

[0013] After the system starts, the PL terminal initializes the configured RF IP core related parameters, and the IP core configuration is key information related to signal acquisition; the ADC and DAC signal sampling modes both use the clock source of the peripheral circuit for direct RF acquisition, and enable multiple signals. The ADC input and DAC output signals are both AC coupled.

[0014] Furthermore, the step 2 comprises:

[0015] After the PS completes system initialization, it determines the parameters of the output signal of the clock distribution module according to the clock setting of the PL, and generates relevant register parameters based on the value of the parameter and the data configuration manual of the clock distribution module; the parameters of the output signal include type, frequency, channel and level;

[0016] According to the type of register parameters, the transmission data bit width and frequency are configured in the DMA transmission modules of the PS and PL ends, the DMA transmission module is enabled, and the PS end passes the register configuration parameters to the PL end.

[0017] Furthermore, the step 3 comprises:

[0018] After the PL receives the data, it sets the transmission clock and data type according to the SPI configuration mode required by the clock distribution module and transmits the register configuration parameters to the clock distribution module for configuration. After the configuration is completed, the clock distribution module writes the clock lock status into the register. The RFSOC chip reads the value of the register and determines the output clock until it is stable.

[0019] The PS end initializes and runs multi-channel synchronization, sets the initialization delay, and then initializes the data converter and the configuration information of multi-channel synchronization in turn. After calling the multi-channel synchronization function and setting the number of channels and channel numbers to be synchronized, the function writes the synchronization information to the corresponding register of the RF IP core through the data interface for data interaction between the PS end and the PL end to realize the synchronization function.

[0020] Furthermore, it also includes:

[0021] Whether the synchronization is successful is determined by detecting the value returned by calling the synchronization API function. If the ADC synchronization is successful, the multi-channel data collected by the ADC is observed in the debugging interface of the VIVADO software, and the collected spectrum is observed and multi-channel phase error analysis is performed through the MATLAB software. If the DAC synchronization is successful, the frequency control word parameters required for the DAC output are set in the data control interface of the VIVADO software, the output is enabled, and an oscilloscope is used to observe the DAC output signal and analyze the phase error of the signal.

[0022] The present invention also discloses a multi-channel sampling synchronization device of a radio frequency direct sampling RFSOC system, which is composed of an RFSOC chip, a clock distribution module and a peripheral circuit of the RFSOC chip; the RFSOC chip is respectively connected to the clock distribution module and the peripheral circuit of the RFSOC chip; the RFSOC chip includes a PL end and a PS end; the clock distribution module is connected to the PS end through the PL end.

[0023] Furthermore, the PL end includes an SPI interface module and an RF configuration module; the clock distribution module is used to transmit the sampling clock, synchronization clock and data path clock to the RF configuration module; the PS end is used to transmit the SPI configuration to the clock distribution module; the RF configuration module is used to receive external RF signals and output RF signals.

[0024] Furthermore, the PS end includes an SPI interface module and a function interface module; the SPI interface module is used to transmit the configuration clock parameters to the SPI interface module in the PL end; the function interface module is used to transmit the synchronization control to the RF configuration module.

[0025] Furthermore, the peripheral circuit includes a power module, a storage module and a memory; the power module includes a plurality of independent power chips, and the plurality of independent power chips are respectively connected to the RFSOC chip to provide different types of power supply to the RFSOC chip.

[0026] Furthermore, the clock distribution module includes a crystal oscillator, a phase-locked loop chip and a clock buffer chip; the crystal oscillator is connected to the phase-locked loop, the crystal oscillator provides a reference source for the phase-locked loop, the phase-locked loop is connected to the clock buffer chip, the phase-locked loop inputs multiple frequency-multiplied clocks to the clock buffer chip, and the clock buffer chip is connected to the RFSOC chip; the clock buffer chip provides the RFSOC chip with multiple required clock sources.

[0027] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0028] 1. In a typical MIMO multi-receive and multi-transmit and DBF digital beamforming system, in order to minimize the error of multi-channel sampling synchronization and not reduce the overall performance indicators of the system, it is generally required that the phase error between multi-channel sampling is ≤3° after each power-on. The multi-channel sampling synchronization method of the RF direct sampling RFSOC system constructed by the patent of this invention has a multi-channel sampling phase error of better than 3° after actual testing.

[0029] 2. In the case of 3GSPS high-speed sampling clock, the results of ADC multi-channel synchronization phase difference in the RFSOC system are shown in Table 1. It can be seen from the table that after testing, the change in the phase difference between each channel of the ADC is ≤±1°, which is equivalent to a multi-channel synchronization time domain error of 0.92 picoseconds. The results of DAC multi-channel synchronization phase difference in the RFSOC system are shown in Table 2. It can be seen from Table 2 that after testing, the change in the phase difference between each channel of the DAC is ≤±1°, which is equivalent to a multi-channel synchronization time domain error of 0.92 picoseconds. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0031] Figure 1 This is a schematic diagram of the architecture of a multi-channel sampling synchronous RFSOC system according to an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of hardware implementation of a multi-channel sampling synchronous RFSOC system according to an embodiment of the present invention;

[0033] Figure 3 This is the process flow of the multi-channel sampling synchronization method of the RFSOC system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention is further described in conjunction with the accompanying drawings and embodiments, and the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present invention.

[0035] See also Figure 1 The present invention provides an embodiment of a multi-channel sampling synchronization method of a radio frequency direct sampling RFSOC system, which includes:

[0036] First, the ADC / DAC (analog-to-digital / digital-to-analog) sampling clock related parameters, input and output characteristic parameters, data mode and other related configurations are set through the dedicated RF IP core on the PL side of the system, and the peripheral connection lines are configured according to the hardware of the system to generate the underlying driver framework; then the PS side uses this as the basis of the software platform, and generates control register parameters at the user layer according to the set related clocks, and transmits them to the PL side through the internal data interface; then the clock distribution module is configured through the system SPI interface to output the corresponding sampling clock, synchronization clock and data follow-up clock, so that the ADC input signal can be collected and converted into 12-bit analog-to-digital conversion data, and the output analog signal of the DAC is controlled by the set frequency control word parameters on the PL side; finally, the PS side controls the RF IP core on the PL side through the compiled dedicated myRfdcInit() interface function to realize the multi-channel sampling synchronization method of the RFSOC system.

[0037] The specific implementation steps of the signal multi-channel sampling synchronization method of the RFSOC system are as follows:

[0038] 1) After the system starts, the PL side initializes and configures the relevant parameters of the RF IP core. The IP core mainly configures key information related to signal acquisition. There are 8 RF input channels and 8 RF output channels. The ADC and DAC signal sampling modes are both to use the clock source of the peripheral circuit for direct RF sampling. The sampling rate is 3GSPS (sampling clock), the Nyquist domain is set in Zone1, and multiple signals are enabled, and the synchronization signal is set to 5MHz. Both the ADC input and DAC output signals are AC coupled. Under the same dedicated AXIS clock cycle, the ADC input data is 8 channels, the data bit width is 12 bits, and the data clock is set to 375MHz (sampling clock divided by 8). The DAC output data is 8 channels, the data bit width is 16 bits, and the data clock is set to 187.5MHz (sampling clock divided by 16).

[0039] 2) After the PS completes system initialization, the type, frequency, channel, level and other parameters of the clock distribution module output signal are determined according to the clock setting of the PL, and the relevant register parameters are generated based on these values ​​and the data configuration manual of the reference clock distribution module.

[0040] 3) Configure the transmission data bit width and frequency in the DMA (direct memory access) transmission module on the PS and PL sides according to the register parameter type. After the configuration in step 2) is completed, enable the transmission module, and the PS side passes the register configuration parameters to the PL side.

[0041] 4) After the PL receives the data, it sets the transmission clock and data type according to the SPI configuration mode required by the clock distribution module and transmits the register configuration parameters to the clock distribution module for configuration. After the configuration is completed, the clock distribution module writes the clock lock status into a dedicated register. The RFSOC chip reads the value of the system register and determines the output clock until it is stable.

[0042] 5) The PS side initializes and runs multi-channel synchronization. First, the initialization delay is set, and then the RFdc data converter and the configuration information of multi-channel synchronization are initialized in turn. Finally, the multi-channel synchronization function is called and the number of channels and channel numbers to be synchronized are set. The function writes the synchronization information to the corresponding register of the RF IP core through the axi4-lite data interface for data exchange between the PS side and the PL side to realize the synchronization function.

[0043] 6) Finally, determine whether the synchronization is successful by detecting the value returned by calling the synchronization API function. If the ADC synchronization is successful, the multi-channel data collected by the ADC can be observed in the debugging interface of the VIVADO software, and the collected spectrum can be observed and multi-channel phase error analysis can be performed through the MATLAB software; if the DAC synchronization is successful, set the frequency control word parameters required for the DAC output in the VIO data control interface of the VIVADO software, enable the output, and use an oscilloscope to observe the DAC output signal and analyze the phase error of the signal.

[0044] In summary, the RFSOC system multi-channel sampling synchronization method process is as follows Figure 3 shown.

[0045] The present invention also provides an embodiment of a multi-channel sampling synchronization device of a radio frequency direct sampling RFSOC system, which is composed of an RFSOC chip, a clock distribution module and a peripheral circuit of the RFSOC chip; the RFSOC chip is respectively connected to the clock distribution module and the peripheral circuit of the RFSOC chip; the RFSOC chip includes a PL terminal and a PS terminal; the clock distribution module is connected to the PS terminal through the PL terminal.

[0046] In one embodiment of the present application, the PL end includes an SPI interface module and an RF configuration module; the clock distribution module is used to transmit the sampling clock, synchronization clock and data path clock to the RF configuration module; the PS end is used to transmit the SPI configuration to the clock distribution module; the RF configuration module is used to receive external RF signals and output RF signals.

[0047] In one embodiment of the present application, the PS end includes an SPI interface module and a function interface module; the SPI interface module is used to transmit the configuration clock parameters to the SPI interface module in the PL end; the function interface module is used to transmit the synchronization control to the RF configuration module.

[0048] In one embodiment of the present application, the peripheral circuit includes a power module, a storage module and a memory; the power module includes multiple independent power chips, and the multiple independent power chips are respectively connected to the RFSOC chip to provide different types of power supply to the RFSOC chip.

[0049] In one embodiment of the present application, the clock distribution module includes a crystal oscillator, a phase-locked loop chip and a clock buffer chip; the crystal oscillator is connected to the phase-locked loop, the crystal oscillator provides a reference source for the phase-locked loop, the phase-locked loop is connected to the clock buffer chip, the phase-locked loop inputs multiple frequency-multiplied clocks to the clock buffer chip, and the clock buffer chip is connected to the RFSOC chip; the clock buffer chip provides the RFSOC chip with multiple required clock sources.

[0050] The clock distribution circuit is composed of a TC53NAGHC-10MHz crystal oscillator, a LMK04828 phase-locked loop, and a HMC987 clock buffer. It provides the RFSOC synchronization system with a sampling clock for collecting RF signals, a control clock (referred to as control clock) required for multi-channel synchronization, and a channel clock for monitoring and controlling data.

[0051] See also Figure 2 and Figure 3 , 8-channel RF input / output is connected to the RFSOC chip through the RF connector, the 8-channel RF input provides the RFSOC chip with the RF input signal that needs to be collected, and the 8-channel RF output outputs the analog RF signal generated by the RFSOC chip to the outside;

[0052] See also Figure 2 and Figure 3 The power circuit uses the DCDC power supply type LTM4650 chip to provide 0.85V chip voltage for the RFSOC synchronization system, and the LTM4644 provides 0.9V / 1.2V / 1.8V voltage for the digital circuit of the RFSOC synchronization system; the LDO power supply type LT3083 chip is used to provide 0.92V / 1.8V analog circuit voltage for the RFSOC synchronization system;

[0053] See also Figure 2 and Figure 3The RFSOC chip uses the XCZU28DR chip produced by Xilinx as the main chip for the synchronization system implementation. The chip includes a programmable logic end (PL end) and a processing system end (PS end). The PL end contains 4272 digital signal processors, 1080 38Mb BRAMs, 425280 logic units, 8 CMTs, 2 PCIE3.0X16s, 16 GTYs and other programmable resources; the PS end contains four Cortex-A53 ARM cores and two Cortex-R5ARM cores.

[0054] See also Figure 2 and Figure 3 The RFSOC chip is connected to two 2Gbits SPI FLASH (model MT25QU02GCBB8E12) for storing burning files; the RFSOC chip is connected to four 1GB DDR3 (model MT40A512M16) for storing and reading and writing data and payload files, with a data width of 64 bits and a rate of 2400MB / s.

[0055] When using a 3GSPS high-speed sampling clock, the results of the ADC multi-channel synchronization phase difference in the RFSOC system are shown in Table 1. As shown in Table 1, after testing, the change in the phase difference between each channel of the ADC is ≤±1°, which is equivalent to a multi-channel synchronization time domain error of 0.92 picoseconds.

[0056] Table 1 ADC multi-channel synchronization phase difference results

[0057]

[0058] The results of the DAC multi-channel synchronization phase difference in the RFSOC system are shown in Table 2. As shown in Table 2, after testing, the change in the phase difference between each channel of the DAC is ≤±1°, which is equivalent to a multi-channel synchronization time domain error of 0.92 picoseconds.

[0059] Table 2DAC multi-channel synchronization phase difference results

[0060]

[0061]

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A multi-channel sampling synchronization method for a radio frequency direct sampling RFSOC system, characterized in that: include: Step 1: Set up relevant parameters of the RF IP core on the PL side of the system; Related parameter configuration includes ADC / DAC sampling clock related parameters, input and output characteristic parameters and data mode; Step 2: Generate the underlying driver framework based on the peripheral connection lines of the system hardware configuration; the PS side uses the underlying driver framework as the software platform foundation, generates register parameters at the user layer according to the set related clocks, and the PS side transfers the register parameters to the PL side through DMA; Step 3: The PL side transmits the register parameters to the clock distribution module through the SPI interface; The clock distribution module is configured through the system SPI interface to output the corresponding sampling clock, synchronization clock and data follow-up clock, so that the ADC input signal can be collected and converted into analog-to-digital conversion data of the specified number of bits. The output analog signal of the DAC is controlled by the set frequency control word parameters on the PL side; the PS side controls the RF IP core on the PL side through the interface function to realize multi-channel sampling synchronization of the RFSOC system.

2. The method according to claim 1, characterized in that The step 1 comprises: After the system starts, the PL terminal initializes the configured RF IP core related parameters, and the IP core configuration is key information related to signal acquisition; the ADC and DAC signal sampling modes both use the clock source of the peripheral circuit for direct RF acquisition, and enable multiple signals. The ADC input and DAC output signals are both AC coupled.

3. The method according to claim 1, characterized in that The step 2 comprises: After the PS completes system initialization, it determines the parameters of the output signal of the clock distribution module according to the clock setting of the PL, and generates relevant register parameters based on the value of the parameter and the data configuration manual of the clock distribution module; the parameters of the output signal include type, frequency, channel and level; According to the type of register parameters, the transmission data bit width and frequency are configured in the DMA transmission modules of the PS and PL ends, the DMA transmission module is enabled, and the PS end passes the register configuration parameters to the PL end.

4. The method according to claim 1, characterized in that: The step 3 comprises: After the PL receives the data, it sets the transmission clock and data type according to the SPI configuration mode required by the clock distribution module and transmits the register configuration parameters to the clock distribution module for configuration. After the configuration is completed, the clock distribution module writes the clock lock status into the register. The RFSOC chip reads the value of the register and determines the output clock until it is stable. The PS end initializes and runs multi-channel synchronization, sets the initialization delay, and then initializes the data converter and the configuration information of multi-channel synchronization in turn. After calling the multi-channel synchronization function and setting the number of channels and channel numbers to be synchronized, the function writes the synchronization information to the corresponding register of the RF IP core through the data interface for data interaction between the PS end and the PL end to realize the synchronization function.

5. The method according to claim 1, characterized in that Also includes: Whether the synchronization is successful is determined by detecting the value returned by calling the synchronization API function. If the ADC synchronization is successful, the multi-channel data collected by the ADC is observed in the debugging interface of the VIVADO software, and the collected spectrum is observed and multi-channel phase error analysis is performed through the MATLAB software. If the DAC synchronization is successful, the frequency control word parameters required for the DAC output are set in the data control interface of the VIVADO software, the output is enabled, and an oscilloscope is used to observe the DAC output signal and analyze the phase error of the signal.

6. A multi-channel sampling synchronization device for a radio frequency direct sampling RFSOC system, characterized in that: It consists of an RFSOC chip, a clock distribution module and a peripheral circuit of the RFSOC chip; the RFSOC chip is connected to the clock distribution module and the peripheral circuit of the RFSOC chip respectively; the RFSOC chip includes a PL terminal and a PS terminal; the clock distribution module is connected to the PS terminal via the PL terminal.

7. The multi-channel sampling synchronization device of the radio frequency direct sampling RFSOC system according to claim 6 is characterized in that: The PL side includes an SPI interface module and an RF configuration module; the clock distribution module is used to transmit the sampling clock, synchronization clock and data path clock to the RF configuration module; The PS end is used to transmit the SPI configuration to the clock distribution module; the RF configuration module is used to receive external RF signals and output RF signals.

8. The multi-channel sampling synchronization device of the radio frequency direct sampling RFSOC system according to claim 7 is characterized in that: The PS end includes an SPI interface module and a function interface module; the SPI interface module is used to transmit the configuration clock parameters to the SPI interface module in the PL end; the function interface module is used to transmit the synchronization control to the RF configuration module.

9. The multi-channel sampling synchronization device of the radio frequency direct sampling RFSOC system according to claim 6, characterized in that: The peripheral circuit includes a power module, a storage module and a memory; the power module includes a plurality of independent power chips, and the plurality of independent power chips are respectively connected to the RFSOC chip to provide different types of power supply to the RFSOC chip.

10. The multi-channel sampling synchronization device of the radio frequency direct sampling RFSOC system according to claim 6, characterized in that: The clock distribution module includes a crystal oscillator, a phase-locked loop chip and a clock buffer chip; the crystal oscillator is connected to the phase-locked loop, the crystal oscillator provides a reference source for the phase-locked loop, the phase-locked loop is connected to the clock buffer chip, the phase-locked loop inputs multiple frequency-multiplied clocks to the clock buffer chip, the clock buffer chip is connected to the RFSOC chip; the clock buffer chip provides the RFSOC chip with multiple required clock sources.

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